IGBT power device preparation method and IGBT power device

Abstract

The invention relates to an IGBT power device preparation method and an IGBT power device, and belongs to the technical field of semiconductor power devices. Comprising the following steps: etching a plurality of grooves in a first cellular region and a second cellular region; growing a gate oxide layer and forming a first composite silicon oxide film layer in each groove, and filling first gate polycrystalline silicon; removing redundant first grid polycrystalline silicon according to a first preset depth to obtain effective grid polycrystalline silicon; removing the redundant first composite silicon oxide film layer according to a second preset depth and a preset angle to obtain an effective composite silicon oxide film layer; depositing a second composite silicon oxide film layer on the surface of the effective composite silicon oxide film layer in the second cellular area according to a preset thickness; and depositing second grid polycrystalline silicon in the residual space of each groove, and depositing a third composite silicon oxide film layer on the surface of the second grid polycrystalline silicon. The zero temperature coefficient point of the device is reduced, and the safe working area and the application reliability of the device are improved. And meanwhile, the current sharing stability is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor power devices, and in particular to an IGBT power device preparation method and an IGBT power device. Background Art

[0002] Insulated-gate bipolar transistors (IGBTs), as composite power semiconductor devices, combine the high input impedance and fast switching characteristics of MOSFETs with the low on-state voltage drop of bipolar transistors. They are widely used in frequency converters, inverters, electric vehicles, and industrial power supplies. However, existing IGBT devices still have shortcomings in some key performance indicators, limiting their adoption in higher-performance applications.

[0003] The main shortcomings of existing IGBT technology include: First, its turn-on voltage varies significantly with temperature, resulting in a high zero temperature coefficient (ZTC) point, making the device's switching characteristics unstable at low temperatures and difficult to meet the requirements of high-reliability applications. Second, the capacitance characteristics and turn-on process characteristics of existing IGBT devices are less than ideal, limiting their high-frequency switching performance and increasing switching losses. In addition, when IGBTs are used in parallel, current distribution is uneven, affecting device reliability and service life. These issues indicate that existing IGBT technology still needs to be improved in terms of zero temperature coefficient optimization, capacitance and turn-on characteristics optimization, and current sharing stability. Summary of the Invention

[0004] To this end, the technical problem to be solved by the present invention is to overcome the problems in the prior art where the turn-on voltage is affected by temperature, resulting in unstable switching characteristics at low temperatures, insufficient optimization of capacitance characteristics, and uneven current distribution when used in parallel.

[0005] In a first aspect, to solve the above technical problems, the present invention provides a method for preparing an IGBT power device, comprising:

[0006] S1. Etching a plurality of trenches in a first cell region and a second cell region, wherein the trenches pass through a carrier storage layer; the carrier storage layer is obtained by injecting carriers into a designated region;

[0007] S2, growing a gate oxide layer and forming a first composite silicon oxide film layer in each of the trenches, and filling the trench with first gate polysilicon;

[0008] S3. According to a first preset depth, removing excess first gate polysilicon to obtain effective gate polysilicon; according to a second preset depth and a preset angle, removing excess first composite silicon oxide film to obtain an effective composite silicon oxide film;

[0009] S4. Depositing a second compound on the surface of the effective composite silicon oxide film layer in the second cell region according to a preset thickness to form a second composite silicon oxide film layer; in the second cell region, depositing a second gate polysilicon in the space surrounded by the second composite silicon oxide film layer, the effective gate polysilicon, and the effective composite silicon oxide film layer; and in the first cell region, depositing a second gate polysilicon in the space surrounded by the gate oxide layer, the effective gate polysilicon, and the effective composite silicon oxide film layer.

[0010] S5. Depositing a third composite silicon oxide film layer on the surface of the second gate polysilicon, and performing body region implantation and source region implantation between each of the trenches; wherein the source region is located above the body region;

[0011] S6. Depositing an isolation oxide layer on the surface of the third composite silicon oxide film layer and the source region, and etching through the isolation oxide layer to extend to the body region to obtain a contact hole.

[0012] In one embodiment of the present invention, the step S2 is:

[0013] growing a gate oxide layer in each of the trenches; depositing a first compound on the surface of the gate oxide layer to form a first composite silicon oxide film layer;

[0014] A first gate polysilicon is deposited on the first composite silicon oxide film layer, and the first gate polysilicon completely fills the trench.

[0015] In one embodiment of the present invention, the step of designing a chip layout is performed before S1 , wherein at least one gate pad is designed in the chip layout.

[0016] In one embodiment of the present invention, the first cell region in S1 is far away from the gate pad.

[0017] In one embodiment of the present invention, the step S1 of injecting the carrier storage layer into the designated area also includes pushing the carrier storage layer; the method of pushing the carrier storage layer includes high temperature annealing and rapid thermal processing.

[0018] In one embodiment of the present invention, in S6, after etching to obtain the contact hole, the step further includes filling a tungsten plug in the contact hole.

[0019] In one embodiment of the present invention, after S6, the process further includes performing ion implantation in the field stop region and ion implantation in the collector region on the back side of the IGBT power device.

[0020] In one embodiment of the present invention, the method for performing ion implantation in the field stop region is to use an ion implanter to implant dopants into a specific region on the back side of the wafer.

[0021] In one embodiment of the present invention, before depositing the second compound on the surface of the effective composite silicon oxide film layer in the second cell region, the method further includes covering the inside of the trench in the first cell region with photoresist.

[0022] In a second aspect, in order to solve the above technical problem, the present invention provides an IGBT power device, which is prepared according to the above-mentioned method for preparing an IGBT power device.

[0023] The above technical solution of the present invention has the following beneficial effects compared with the prior art:

[0024] (1) The present invention discloses a method for preparing an IGBT power device and an IGBT power device, wherein a thick gate oxide layer is formed in a cell trench near the gate region by a process combining etching and oxide layer deposition. Under the same body region process conditions, based on the difference in gate oxide layer thickness, the turn-on voltage of the second cell region is higher than that of the first cell region, thereby reducing the zero temperature coefficient (ZTC) of the device and improving the safe operating area and application reliability of the device.

[0025] (2) The present invention forms a structure in which the area at the bottom of the trench in contact with the carrier storage layer is a thick oxide layer, and the area in contact with the body region is a thin oxide layer by combining a thermal oxide layer with a deposited oxide layer inside the overall cell trench, thereby optimizing the capacitance and turn-on process characteristic parameters of the device.

[0026] (3) In the chip layout design, the present invention coordinates the opening speed of the cells on the entire device through the design of at least one gate pad to achieve the stability of the current sharing. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to make the content of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings, wherein:

[0028] Figure 1 This is a flow chart of a method for preparing an IGBT power device in a preferred embodiment of the present invention;

[0029] Figure 2 A schematic structural diagram of an IGBT power device obtained by a method for preparing an IGBT power device according to a preferred embodiment of the present invention;

[0030] Figure 3 This is a screenshot of the IGBT power device structure in a preferred embodiment of the present invention;

[0031] Figure 4 This is the first layout of existing IGBT power devices;

[0032] Figure 5 This is the second layout of existing IGBT power devices;

[0033] Figure 6 The figure is a schematic diagram of the steps of a method for preparing an IGBT power device in a preferred embodiment of the present invention.

[0034] Explanation of the reference numerals in the accompanying drawings in the specification: 1. Groove; 2. Gate oxide layer; 3. Composite silicon oxide film layer; 31. First composite silicon oxide film layer; 32. Second composite silicon oxide film layer; 33. Third composite silicon oxide film layer; 4. Carrier storage layer; 5. Gate polysilicon; 51. First gate polysilicon; 52. Second gate polysilicon; 6. Injection region at the bottom of the contact hole; 7. Contact hole; 8. Source region; 9. Body region; 10. Isolation oxide layer; 11. Front metal layer; 12. Field stop region; 13. Collector region; 14. Back metal layer. DETAILED DESCRIPTION

[0035] The present invention will be further described below with reference to the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it. However, the embodiments are not intended to limit the present invention.

[0036] Example 1

[0037] Reference Figures 1 to 2 As shown, an embodiment of the present invention provides a method for preparing an IGBT power device, including but not limited to the following steps:

[0038] S1. Etching a plurality of trenches 1 in a first cell region and a second cell region, wherein the trenches 1 pass through a carrier storage layer 4; the carrier storage layer 4 is obtained by injecting carriers into a designated region;

[0039] S2, growing a gate oxide layer 2 and forming a first composite silicon oxide film layer 31 in each trench 1, and filling the first gate polysilicon 51;

[0040] S3, removing the excess first gate polysilicon 51 according to the first preset depth to obtain an effective gate polysilicon; removing the excess first composite silicon oxide film layer 31 according to the second preset depth and preset angle to obtain an effective composite silicon oxide film layer;

[0041] S4. Depositing a second compound on the surface of the effective composite silicon oxide film layer in the second cell region according to a preset thickness to form a second composite silicon oxide film layer 32; in the second cell region, depositing a second gate polysilicon 52 in the space surrounded by the second composite silicon oxide film layer 32, the effective gate polysilicon, and the effective composite silicon oxide film layer; and in the first cell region, depositing a second gate polysilicon 52 in the space surrounded by the gate oxide layer 2, the effective gate polysilicon, and the effective composite silicon oxide film layer.

[0042] S5, depositing a third composite silicon oxide film layer 33 on the surface of the second gate polysilicon 52, and implanting the body region 9 and the source region 8 between each trench 1; wherein the source region 8 is located above the body region 9;

[0043] S6. Deposit an isolation oxide layer 10 on the surface of the third composite silicon oxide film layer 33 and the source region 8, and etch through the isolation oxide layer 10 to extend to the body region 9 to obtain a contact hole 7.

[0044] An embodiment of the present invention provides a method for fabricating an IGBT power device. By injecting carriers into a designated area to form a carrier storage layer 4, the carrier distribution within the device can be precisely controlled, thereby optimizing the device's electrical characteristics, such as breakdown voltage and on-resistance. By growing a gate oxide layer 2 within a trench 1 and depositing a first gate polysilicon 51 to form a first composite silicon oxide film 31, the gate's ability to control carriers can be improved, enhancing the device's switching speed and efficiency. By removing excess first gate polysilicon 51 and first composite silicon oxide film 31 to obtain an effective gate structure and composite silicon oxide film, stress concentration and cracks that may occur during device operation can be reduced, thereby enhancing the device's reliability and lifespan. Furthermore, in an embodiment of the present invention, a thick gate oxide layer 2 is formed in the cell trench 1 near the gate region through a combined etching and oxide deposition process. Under the same body region process conditions, due to the difference in gate oxide layer 2 thickness, the turn-on voltage of the second cell region is higher than that of the first cell region, thereby lowering the device's zero temperature coefficient (ZTC) and improving the device's safe operating area (SOA) and application reliability. Inside the overall cell trench 1, by combining a thermal oxide layer with a deposited oxide layer, a structure is formed in which the area at the bottom of the trench 1 in contact with the carrier storage layer 4 is a gate oxide layer 2, and the area in contact with the body region 9 is a thin oxide layer, which can optimize the device's capacitance and turn-on process characteristic parameters.

[0045] Specifically, chip layout design is a key step before manufacturing IGBT power devices. It involves laying out and designing the various components of the circuit on the silicon wafer, including transistors, resistors, capacitors, wiring, etc., as well as the connection between them. Figure 3As shown, in an embodiment of the present invention, by designing at least one gate pad, not only is it ensured that the gate of each cell in the device can effectively receive the control signal, but also by optimizing the layout and size of the gate pad, accurate coordination of the cell turn-on speed is achieved. The beneficial effect of this design method is that it reduces the current unevenness and potential thermal unevenness caused by the difference in turn-on speed between cells, and can ensure that during device operation, all cells can respond to the gate signal at almost the same speed, thereby achieving uniform current distribution throughout the device. The embodiment of the present invention coordinates the turn-on speed of the cells on the entire device by introducing the design of at least one gate pad in the chip layout design, thereby achieving the stability of current sharing and improving the performance of the device in multi-parallel applications. In addition, Figure 3 What is shown is a screenshot of the IGBT power device structure of the present invention. Figures 4 and 5 There are two layouts for existing power devices. Figures 3 to 5 It can be seen that the power device obtained by the preparation method provided in the embodiment of the present invention is significantly different from the existing device. Figure 3 The A-A' mark in the figure represents a cutting surface, which is used to show the internal structure, including the active area, gate, gate oxide layer 2, and other possible functional layers. In the figure, cell region A represents the first cell region, and cell region B represents the second cell region.

[0046] Specifically, refer to Figure 6 As shown, Figure 6 Schematic diagram of the overall steps of the method described in an embodiment of the present invention. Before performing step S1 of injecting the carrier storage layer 4, the wafer is selected. The wafer is usually made of semiconductor materials such as pure silicon (Si) or gallium arsenide (GaAs). Specific areas on the surface of the wafer need to be doped to form P-type or N-type semiconductor regions. Doping is achieved by introducing impurity atoms (such as boron, phosphorus, etc.) into the surface of the wafer, and these impurity atoms will change the electrical properties of the wafer.

[0047] Furthermore, the carrier storage layer 4 is implanted and pushed in a designated area of ​​the wafer to form a high-concentration carrier storage layer 4 in the active area of ​​the device, laying the foundation for subsequent electric field modulation and device conduction characteristics. Carrier implantation is usually performed using an ion implanter, which accelerates dopant atoms and implants them into a specific area of ​​the wafer. The implanted dose (the number of dopant atoms per unit area) and energy (which determines the doping depth) can be adjusted according to the desired device characteristics.

[0048] For example, N-type dopant ions (e.g., N+ ions) are injected into the carrier storage layer 4. After the N+ ion injection, the carrier storage layer can significantly increase the electron concentration in the drift region. In devices such as IGBTs, this helps reduce the on-state voltage drop and improve the device's forward conduction performance. The dose is set to 1E12 to 9.9E13, and the energy is set to 100KeV to 5MeV, followed by a junction push-up process.

[0049] Furthermore, junction pushing refers to the change in junction depth caused by the expansion of the depletion region of the PN junction due to changes in the applied voltage during device operation. During the manufacturing process, junction pushing usually involves high-temperature annealing or rapid thermal processing (RTP) to activate the implanted dopant atoms and repair the lattice damage caused by the implantation process.

[0050] Specifically, after the injection and push-in of the carrier storage layer 4 are completed, the etching of the trench 1 in each cell area is carried out. The trench 1 passes through the area after the injection and push-in of the carrier storage layer 4. The etching accuracy of the trench 1 directly affects the electric field distribution and voltage resistance characteristics of the device, so the etching depth and opening size need to be strictly controlled. In terms of the number of trenches 1, the number and layout of the trenches 1 need to be determined through detailed electrothermal simulation and optimization to ensure that the device has good reliability and cost-effectiveness while meeting the performance requirements. During the etching process, the etching rate is controlled to achieve the required trench 1 depth and sidewall angle. Use a sidewall protection layer, such as depositing a hard mask material, to reduce sidewall damage during the etching process. In addition, it also includes optimizing the design of the trench 1, including the width, depth and spacing of the trench 1, to meet the performance requirements of the device.

[0051] Exemplarily, the depth of the etched groove 1 is 3um to 7um, and the opening size is 0.5um to 2um.

[0052] Specifically, after the trench 1 is etched, a gate oxide layer 2 is thermally grown in each trench 1. At the same time, the gate oxide layer 2 is also grown on the surface of the semiconductor substrate. This oxide layer will serve as an insulating layer for the subsequent first gate polysilicon 51 and provide good electric field isolation when the device is in operation. The gate oxide layer 2 can be grown by a thermal oxidation process, that is, placing a silicon wafer in an oxygen or water vapor environment at a high temperature so that silicon reacts with oxygen to form silicon dioxide (SiO2), or by using a chemical vapor deposition (CVD) method to grow the gate oxide layer 2, that is, by reacting a silicon source gas and an oxidant on the substrate surface to form a silicon oxide film. The thickness of the gate oxide layer 2 can be precisely controlled according to the design requirements of the device. For example, a gate oxide layer 2 with a thickness of 500 Å to 1200 Å is grown through a high-temperature oxidation process.

[0053] Furthermore, the thickness of the gate oxide layer 2 differs between the first and second cell regions. In particular, the gate oxide layer 2 is thicker in the trench 1 near the gate region (i.e., the second cell region). Under the same body process conditions, the turn-on voltage in the second cell region is higher than that in the first cell region due to the difference in gate oxide layer 2 thickness. This design helps lower the zero temperature coefficient (ZTC) of the device, significantly improving its safe operating area (SOA) and application reliability.

[0054] Specifically, on the surface of the gate oxide layer 2, a first compound is further deposited to form a first composite silicon oxide film layer 31. The first compound can be a variety of materials, such as silane, tetraethoxysilane (TEOS), tetraethyl orthosilicate, etc. In view of the advantages of tetraethoxysilane (TEOS) such as high purity and stability, good film-forming properties, low deposition temperature and high deposition rate, the first compound is preferably tetraethoxysilane (TEOS) in this embodiment. The purpose of this step is to construct a uniform and high-quality first composite silicon oxide film layer 31, which not only enhances the insulation properties of the gate oxide layer 2, but also improves its durability and reliability. During the deposition process, the deposition conditions, such as temperature, pressure and gas flow, are precisely controlled to ensure that the composite silicon oxide film layer 3 has the required thickness and excellent electrical properties. In addition, the composite layer can also effectively reduce gate leakage current and improve the overall performance of the device.

[0055] Furthermore, regarding the thickness of the first composite silicon oxide film layer 31 , illustratively, the first composite silicon oxide film layer 31 is formed to have a total thickness of 1000 Å to 2000 Å, where 1 Å=0.1 nm (nanometer).

[0056] Specifically, the first gate polysilicon 51 is deposited on the surface of the first composite silicon oxide film layer 31 , and the first gate polysilicon 51 completely fills the trench 1 .

[0057] Furthermore, the first gate polysilicon 51 is etched until reaching a first preset depth, wherein the first preset depth is the depth of the effective gate polysilicon.

[0058] Exemplarily, the first gate polysilicon 51 is etched to a first preset depth that is 0.4 to 0.7 times the depth of the trench 1 .

[0059] Specifically, the first composite silicon oxide film layer 31 is selectively removed and re-deposited. Methods for selectively removing the first composite silicon oxide film layer 31 include dry etching and wet etching. The advantage of wet etching is that it can provide highly selective and anisotropic etching characteristics, which makes it possible to precisely control the etching process to ensure that only the TEOS layer is removed without damaging the underlying thermal oxide silicon layer (i.e., the gate oxide layer 2), thereby maintaining the integrity and electrical performance of the device structure. Therefore, the embodiment of the present invention preferably wet etches the excess first composite silicon oxide film layer 31. The surface of the etched first composite silicon oxide film layer 31 is a bevel, and the bevel structure can effectively improve the electric field distribution and reduce the electric field concentration phenomenon, thereby reducing the leakage current and breakdown voltage of the device and improving the electrical performance and reliability of the device.

[0060] Furthermore, the second preset depth and angle can be optimized based on specific process requirements and device performance requirements. For example, by adjusting the preset depth and angle, the shape and size of the bevel can be precisely controlled to achieve optimal electric field distribution, optical coupling efficiency, and physical contact performance. This optimized design not only improves device performance but also enhances its stability and reliability under different operating conditions.

[0061] Furthermore, cell region A (i.e., away from the gate pad, the first cell region) is covered with photoresist, and the surface of cell region B (i.e., close to the gate pad, the second cell region) is not covered with photoresist. By covering cell region A with photoresist, the region can be protected from being affected during subsequent etching or deposition processes. Photoresist acts as a temporary protective layer that can prevent the region from being etched or covered by deposited materials in a specific process step. The surface of cell region B is not covered with photoresist, so that it can be directly exposed to the process environment during subsequent etching or deposition processes. This allows specific etching or deposition treatment to be performed on region B to achieve the desired structure or function.

[0062] It should be noted that since processing within each trench is performed simultaneously, when the trench structures in different cell regions differ, other materials can be used to protect the trenches that do not require that step. For example, cell region A can be covered with photoresist to prevent it from being accidentally processed during a specific process step. This selective protection measure ensures that each cell region can be precisely processed according to the predetermined design and process requirements, thereby achieving high performance and high reliability of the device.

[0063] Furthermore, a second compound is deposited on the portion of the sidewall of the trench 1 in the cell region B where the first composite silicon oxide film 31 is absent. The second compound may be silane, tetraethoxysilane (TEOS), or tetraethyl orthosilicate, with tetraethoxysilane being preferred in this embodiment, to form a second composite gate silicon oxide film. The thickness of the second composite gate silicon oxide film is preferably 1000 Å to 1500 Å.

[0064] Specifically, based on the above steps, a second gate polysilicon 52 is deposited in the trench 1 of the cell region A (i.e., the first cell region) and the cell region B (i.e., the second cell region). The gate polysilicon 5 (including the first gate polysilicon 51 and the second gate polysilicon 52) is finally formed with a wide top and narrow bottom. This special morphology helps to optimize the electric field distribution of the device, reduce the electric field concentration phenomenon, and thus improve the withstand voltage capability of the device. Further, a third compound is deposited on the surface of the second gate polysilicon 52. The third compound is preferably tetraethoxysilane (TEOS) to form a third composite silicon oxide film layer 33.

[0065] It should be noted that in this embodiment, the composite silicon oxide film layer 3 includes a first composite silicon oxide film layer 31, a second composite silicon oxide film layer 32, and a third composite silicon oxide film layer 33, and the effective composite silicon oxide film layer is obtained by removing the excess first composite silicon oxide film layer 31. The gate polysilicon 5 includes a first gate polysilicon 51 and a second gate polysilicon 52.

[0066] By combining the thermal oxide layer with the deposited oxide layer, a thick oxide layer is formed in the area at the bottom of the trench that contacts the carrier storage layer, while a thin oxide layer is formed in the area that contacts the body region. This optimizes the device's capacitance and turn-on characteristic parameters. The thick oxide layer in the first cell region refers to the gate oxide layer 2 and the first composite silicon oxide film layer 31 as a whole; the thick oxide layer in the second cell region refers to the gate oxide layer 2 and the first composite silicon oxide film layer 31 as a whole. The thin oxide layer in the first cell region refers to the gate oxide layer 2; the thin oxide layer in the second cell region refers to the gate oxide layer 2 and the second composite silicon oxide film layer 32 as a whole.

[0067] Specifically, ion implantation and junction drive are performed between the body region 9 and the source region 8, an isolation oxide layer 10 is deposited, contact holes 7 are etched, tungsten plugs are filled, and metal deposition is completed to form the IGBT front-side structure. These steps form the active region and source region 8 of the device, ensuring good conduction characteristics and low on-resistance during device operation.

[0068] Furthermore, ion implantation involves using an ion implanter to implant a specific type of dopant (usually boron or phosphorus) into specific areas of a semiconductor substrate with a completed gate structure, forming body regions 9 and source regions 8. Body regions 9 serve as the base of the IGBT, while source regions 8 serve as the emitter. After ion implantation, a high-temperature annealing (junction push-up) process diffuses the dopant within the substrate, forming a uniformly doped region. This process also helps repair lattice damage that may have occurred during the implantation process, thereby improving device performance and reliability.

[0069] Furthermore, a method of depositing an isolation oxide layer 10 on the substrate surface includes using thermal oxidation or chemical vapor deposition (CVD) technology. This oxide layer is used to isolate different cells, prevent current from leaking from one cell to another, and ensure the stability of the device.

[0070] Furthermore, before etching the contact hole 7, ion implantation is performed on the implantation region 6 at the bottom of the contact hole, where the implantation region 6 at the bottom of the contact hole is located in the body region 9. First, an ion implantation process is used to form implantation regions with high doping concentrations on the substrate. These regions are located at the bottom of the future contact hole 7 and are used to ensure good ohmic contact between the contact hole 7 and the semiconductor substrate. Next, a high-temperature annealing (junction push-in) process is used to activate the implanted dopants and uniformly diffuse the dopants within the substrate to form stable implantation regions.

[0071] Forming a highly doped implanted region at the bottom of contact hole 7 can significantly reduce the contact resistance between the metal and the semiconductor. This is because the highly doped region provides more carriers, thereby reducing the transmission resistance of electrons from the metal contact layer to the semiconductor substrate. By reducing contact resistance, power loss can be reduced and the efficiency and performance of the device can be improved, especially in high-frequency switching applications. The pre-formed implanted region can serve as a seed layer when filling the tungsten plug or other metal, helping to improve the adhesion between the filling material and the semiconductor substrate, thereby improving the filling quality of contact hole 7.

[0072] After the push-in of the implanted region is completed, the contact hole 7 is etched. First, a layer of photoresist is coated on the isolation oxide layer 10, and a photolithography technique is used to expose the pattern of the contact hole 7. Then, a wet or dry etching technique is used to remove the isolation oxide layer 10 in the exposed area, forming the contact hole 7 leading to the body region 9 and the source region 8.

[0073] Furthermore, for filling the tungsten plug, tungsten (W) is filled in the contact hole 7, and chemical vapor deposition (CVD) technology can be used. The tungsten plug provides a low-resistance electrical connection from the metal layer to the body region 9 and the source region 8. During the filling process, tungsten grows in the contact hole 7 until it completely fills the contact hole 7. After the filling is completed, additional steps (such as CMP, chemical mechanical polishing) can be performed to planarize the surface in preparation for the subsequent deposition of the front metal layer 11.

[0074] Furthermore, a layer of metal (such as aluminum or copper) is deposited on the tungsten plug to form the device's metallization layer (i.e., front metal layer 11). This metal layer is used to connect the various electrodes of the IGBT, achieving electrical connections. Furthermore, photolithography and etching techniques can be used to form the desired pattern on the metal layer to ensure that the metal layer only covers areas that require electrical connections.

[0075] After completing the front structure of the IGBT power device, the front structure is inspected, including electrical performance testing and visual inspection to ensure that all structures meet the design requirements.

[0076] Specifically, the preparation of the back structure of the IGBT power device includes the following steps:

[0077] Step 1: Ion implantation is performed in the field-stop region 12 to reduce leakage current and improve the device's withstand voltage. This involves using an ion implanter to implant a specific type of dopant (such as boron) into a specific area on the backside of the wafer. The implantation dose and energy are controlled to ensure that the depth and concentration of the field-stop region 12 meet design requirements.

[0078] Step 2: Perform ion implantation in the collector region 13 to collect current. The specific implantation method is: according to the device design, use an ion implanter to implant dopants (such as phosphorus) into the collector region 13 on the back of the wafer. Control the implantation dose and energy to form a collector region 13 with appropriate resistivity. It should be noted that the collector region 13 here is a P+ collector region. The main function of the P+ collector region is to collect electrons emitted by the base region. The high doping concentration of the P+ collector region helps to reduce the resistance of the region, thereby reducing power loss and improving the efficiency of the device. In addition, the P+ collector region can form a good ohmic contact with the metal layer to ensure that current can flow smoothly from the semiconductor material to the metal layer.

[0079] Step 3: Laser annealing is performed to activate the injected dopants, repair lattice damage, and promote uniform dopant distribution. The specific method involves using laser annealing equipment to rapidly heat and cool the implanted area. The laser energy and irradiation time are controlled to ensure dopant activation and lattice repair.

[0080] Step 4: Form a metal layer (i.e., back metal layer 14) on the back of the wafer to collect current and provide mechanical support. The specific method is as follows: After laser annealing, a layer of metal (such as aluminum or copper) is deposited on the back of the wafer using physical vapor deposition (PVD) or chemical vapor deposition (CVD) technology. The desired metal pattern is formed through photolithography and etching processes to ensure good electrical contact between the metal layer and the collector region 13.

[0081] Furthermore, to protect the metal layer and semiconductor material on the back of the wafer from oxidation and corrosion, a passivation layer, such as silicon nitride (SiNx) or silicon oxide (SiOx), can be coated on the metal layer and annealed to ensure the quality and adhesion of the passivation layer.

[0082] Through steps 1 to 4, ion implantation and laser annealing are performed on the back side of the wafer in the field stop region 12 and the collector region 13 to form a back side metal.

[0083] The embodiment of the present invention prepares an IGBT power device with a complete structure, which is suitable for various power electronic equipment such as frequency converters, inverters, electric vehicles, industrial power supplies and other fields, and can meet the application requirements of high performance and high reliability. Specifically, in the field of frequency converters, the IGBT power device of the present invention can efficiently adjust the speed and torque of the AC motor, significantly improving energy efficiency and the overall performance of the system. In inverter applications, the device can convert direct current into alternating current, and is suitable for solar photovoltaic systems, electric vehicle charging stations and uninterruptible power supply (UPS) systems, ensuring the efficiency and reliability of power conversion. In the field of electric vehicles (EVs), as a core component in the traction system of electric vehicles, the device is responsible for controlling the speed and torque of the motor, thereby improving the driving performance and energy efficiency of the vehicle. In the field of industrial power supplies, this IGBT power device provides a stable and efficient power supply solution for various industrial applications, such as servo drives, welding equipment and industrial robots, enhancing the accuracy and reliability of industrial systems.

[0084] Example 2

[0085] This embodiment provides an IGBT power device, which is manufactured by the IGBT power device manufacturing method described in the first embodiment.

[0086] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. A method for preparing an IGBT power device, characterized in that: include: S1. Etching a plurality of trenches in a first cell region and a second cell region, wherein the trenches pass through a carrier storage layer; the carrier storage layer is obtained by injecting carriers into a designated region; S2, growing a gate oxide layer and forming a first composite silicon oxide film layer in each of the trenches, and filling the trench with first gate polysilicon; S3. According to a first preset depth, removing excess first gate polysilicon to obtain effective gate polysilicon; according to a second preset depth and a preset angle, removing excess first composite silicon oxide film to obtain an effective composite silicon oxide film; S4. Depositing a second compound on the surface of the effective composite silicon oxide film layer in the second cell region according to a preset thickness to form a second composite silicon oxide film layer; in the second cell region, depositing a second gate polysilicon in the space surrounded by the second composite silicon oxide film layer, the effective gate polysilicon, and the effective composite silicon oxide film layer; and in the first cell region, depositing a second gate polysilicon in the space surrounded by the gate oxide layer, the effective gate polysilicon, and the effective composite silicon oxide film layer. S5. Depositing a third composite silicon oxide film layer on the surface of the second gate polysilicon, and performing body region implantation and source region implantation between each of the trenches; wherein the source region is located above the body region; S6. Depositing an isolation oxide layer on the surface of the third composite silicon oxide film layer and the source region, and etching through the isolation oxide layer to extend to the body region to obtain a contact hole.

2. The method for preparing an IGBT power device according to claim 1, wherein: The steps of S2 are: growing a gate oxide layer in each of the trenches; depositing a first compound on the surface of the gate oxide layer to form a first composite silicon oxide film layer; A first gate polysilicon is deposited on the first composite silicon oxide film layer, and the first gate polysilicon completely fills the trench.

3. The method for preparing an IGBT power device according to claim 1, wherein: The step S1 includes designing a chip layout, wherein at least one gate pad is designed in the chip layout.

4. The method for preparing an IGBT power device according to claim 3, wherein: The first cell region in the S1 is far away from the gate pad.

5. The method for preparing an IGBT power device according to claim 1, wherein: The step S1 injects the carrier storage layer into the designated area and also includes pushing the carrier storage layer; the pushing method includes high temperature annealing and rapid thermal processing.

6. The method for preparing an IGBT power device according to claim 1, wherein: In the above S6, after etching to obtain the contact hole, the step further includes filling a tungsten plug in the contact hole.

7. The method for preparing an IGBT power device according to claim 1, wherein: After S6, the process also includes performing ion implantation in the field stop region and the collector region on the back side of the IGBT power device.

8. The method for preparing an IGBT power device according to claim 7, wherein: The method for performing field stop region ion implantation is to use an ion implanter to implant dopants into a specific region on the back side of the wafer.

9. The method for preparing an IGBT power device according to claim 1, wherein: Before depositing the second compound on the surface of the effective composite silicon oxide film layer in the second cell region, the method further includes covering the inside of the trench in the first cell region with photoresist.

10. An IGBT power device, characterized in that: The power device is prepared according to the method for preparing an IGBT power device according to any one of claims 1 to 9.

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