Anti-radiation four-terminal SiC UMOSFET device and manufacturing method thereof

Abstract

The invention provides an anti-radiation four-terminal SiC UMOSFET device and a manufacturing method thereof. The anti-radiation four-terminal SiC UMOSFET device and the manufacturing method thereof can be applied to the technical field of semiconductors. The device comprises an N-type heavily doped substrate; the drain electrode is arranged on the lower surface of the N-type heavily doped substrate; the N-type epitaxial layer is arranged on the upper surface of the N-type heavily doped substrate, and a groove is formed in the N-type epitaxial layer; the P protection region is arranged at the bottom of the groove; the oxide layer is arranged on the vertical side wall of the trench on the P protection region; the control electrode is arranged on the P protection region in the groove; the first interlayer dielectric is arranged on the control electrode in the groove; the grid electrode is arranged on the first interlayer dielectric in the groove, and the control electrode and the grid electrode are surrounded by the oxide layer; the P base region is arranged in the N-type epitaxial layer and surrounds the periphery of the groove; the N-type heavily doped source region is arranged in the P base region and surrounds the periphery of the groove; and the source electrode is arranged on the N-type heavily doped source region.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor devices, and in particular to a radiation-resistant four-terminal SiC UMOSFET device and a manufacturing method thereof. Background Art

[0002] With the growing demand for applications, the electrical performance of traditional Si-based power devices has reached its physical performance limit, restricting the application and development of power semiconductor devices. Silicon carbide (SiC), especially SiC metal-oxide-semiconductor field-effect transistors (MOSFETs), as third-generation semiconductor materials, has advantages such as wide bandgap, high breakdown field strength, and high thermal conductivity, and has broad application prospects in high-frequency, high-voltage, and high-power fields.

[0003] However, with the development of SiC UMOSFET, the reliability issues of SiC UMOSFET devices under radiation and electrothermal dynamic combined stress have become increasingly prominent. Summary of the Invention

[0004] In view of this, the present disclosure provides a radiation-hardened four-terminal SiC UMOSFET device and a method for manufacturing the same.

[0005] One aspect of the present disclosure provides a radiation-hardened four-terminal SiC UMOSFET device, comprising:

[0006] N-type heavily doped substrate;

[0007] A drain electrode is provided on the lower surface of the N-type heavily doped substrate;

[0008] An N-type epitaxial layer is provided on the upper surface of the N-type heavily doped substrate, wherein a trench is formed in the N-type epitaxial layer;

[0009] P protection zone, set at the bottom of the trench;

[0010] an oxide layer disposed on the vertical sidewalls of the trench on the P protection zone;

[0011] The control electrode is arranged on the P protection zone in the trench;

[0012] a first interlayer dielectric disposed on the control electrode in the trench;

[0013] a gate, disposed in the trench on the first interlayer dielectric, wherein the control electrode and the gate are surrounded by an oxide layer;

[0014] A P-base region is provided in the N-type epitaxial layer around the periphery of the trench;

[0015] An N-type heavily doped source region is disposed in the P-base region and surrounds the periphery of the trench; and

[0016] The source is arranged on the N-type heavily doped source region.

[0017] According to an embodiment of the present disclosure, the control electrode is configured to change the electric field in the oxide layer and the electric field in the N-type epitaxial layer adjacent to the P protection zone by adjusting the voltage applied to the control electrode.

[0018] According to an embodiment of the present disclosure, the device further includes:

[0019] The second interlayer dielectric is arranged on the upper surface of the oxide layer and the gate.

[0020] According to an embodiment of the present disclosure, the thickness of the control electrode along the vertical direction is 0.1-0.5 μm, and the thickness of the first interlayer dielectric along the vertical direction is 10-500 nm.

[0021] According to an embodiment of the present disclosure, the depth of the groove along the vertical direction is 0.3-2 um.

[0022] According to the embodiment of the present disclosure, the junction depth of the P protection zone is 0.1~0.5um, and the peak doping concentration is 1e17~5e19cm -3 .

[0023] According to the embodiment of the present disclosure, the thickness of the N-type heavily doped substrate in the vertical direction is 100-500 μm, and the resistivity of the N-type heavily doped substrate is 0.01-0.03 .

[0024] According to the embodiment of the present disclosure, the thickness of the N-type epitaxial layer in the vertical direction is 8-20 μm, and the doping concentration of the N-type epitaxial layer is 5e14-5e16 cm -3 .

[0025] According to the embodiment of the present disclosure, the junction depth of the P base region is 0.2~2.5 μm, and the peak doping concentration of the P protection region is 1e17~5e19 cm -3 .

[0026] Another aspect of the present disclosure provides a method of manufacturing a radiation-hardened four-terminal SiC UMOSFET device, comprising:

[0027] forming an N-type epitaxial layer on the upper surface of the N-type heavily doped substrate;

[0028] forming a trench in the N-type epitaxial layer;

[0029] A P protection zone is formed at the bottom of the trench;

[0030] forming an oxide layer on the vertical sidewalls of the trench on the P protection area;

[0031] forming a control electrode on the P protection zone in the trench;

[0032] forming a first interlayer dielectric on the control electrode in the trench;

[0033] forming a gate on the first interlayer dielectric in the trench;

[0034] forming a P-base region on an upper portion of the N-type epitaxial layer, wherein the P-base region surrounds an outer periphery of the trench;

[0035] forming an N-type heavily doped source region in the P-base region;

[0036] forming a source electrode on the N heavily doped source region; and

[0037] A drain is formed on the lower surface of the N-type heavily doped substrate.

[0038] According to an embodiment of the present disclosure, the radiation-resistant four-terminal SiC UMOSFET device provided by the present disclosure replaces the conventional gate structure with a trench gate structure, which can fix the potential under the trench of the SiC UMOSFET device, thereby controlling the transient electric field in the oxide layer and preventing breakdown due to excessive transient electric fields. By adjusting the potential of the control electrode, the width of the depletion region between the P-protected area and the surrounding N-type epitaxial layer is controlled, thereby controlling the electric field strength directed to the P-protected area, so that minority carrier holes are extracted from the control electrode under composite stress impact processes such as radiation, electricity, heat, and dynamics. The control electrode can also attract holes, making the positive feedback generated by BJT hole injection and substrate epitaxial impact ionization more difficult to occur, thereby improving the single-event burnout threshold voltage of the SiC UMOSFET device. The control electrode potential can also be adjusted to make the SiC UMOSFET device operate in different states, making the device flexible and applicable to various scenarios. The control electrode can also attract mobile charges in the oxide layer, reducing the impact of mobile charges on the threshold and improving the gate oxide reliability of the SiC UMOSFET device. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0040] Figure 1 The cross-sectional structure diagram of a three-terminal SiC UMOSFET device in the related art is schematically shown;

[0041] Figure 2 Schematically shows a cross-sectional structural diagram of a radiation-resistant four-terminal SiC UMOSFET device according to an embodiment of the present disclosure;

[0042] Figure 3Schematically shows a flow chart of a method for manufacturing a radiation-hardened four-terminal SiC UMOSFET device according to an embodiment of the present disclosure;

[0043] Figure 4 Schematically shows a cross-sectional structural diagram of a device according to an embodiment of the present disclosure after an N-type epitaxial layer is formed on the upper surface of an N-type heavily doped substrate;

[0044] Figure 5 Schematically shows a cross-sectional structure diagram of a device after a trench is formed in an N-type epitaxial layer according to an embodiment of the present disclosure;

[0045] Figure 6 Schematically shows a cross-sectional structure diagram of a device according to an embodiment of the present disclosure after a P protection zone is formed at the bottom of the trench;

[0046] Figure 7 Schematically shows a cross-sectional structure diagram of a device according to an embodiment of the present disclosure after an oxide layer is formed on the vertical sidewalls of the trench in the P protection area;

[0047] Figure 8 Schematically shows a cross-sectional structure diagram of a device according to an embodiment of the present disclosure after a control electrode is formed on a P protection zone in a trench;

[0048] Figure 9 Schematically shows a cross-sectional structure diagram of a device according to an embodiment of the present disclosure after a first interlayer dielectric is formed on a control electrode in a trench;

[0049] Figure 10 Schematically shows a cross-sectional structure diagram of a device according to an embodiment of the present disclosure after a gate is formed on a first interlayer dielectric in a trench;

[0050] Figure 11 Schematically shows a cross-sectional structure diagram of a device according to an embodiment of the present disclosure after a P-base region is formed on an upper portion of an N-type epitaxial layer and an N-type heavily doped source region is formed in the P-base region;

[0051] Figure 12 Schematically shows a cross-sectional structure diagram of a device according to an embodiment of the present disclosure after a source electrode is formed on an N-heavily doped source region;

[0052] Figure 13 Schematic diagram showing the change of the maximum transient electric field of the gate oxide with time when the three-terminal SiC UMOSFET device and the radiation-resistant four-terminal SiC UMOSFET device of the embodiment of the present disclosure are irradiated; and

[0053] Figure 14 The diagram schematically shows the relationship between the maximum transient electric field peak of the gate oxide and the control electrode bias voltage when the radiation-resistant four-terminal SiC UMOSFET device according to the embodiment of the present disclosure is irradiated. DETAILED DESCRIPTION

[0054] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0055] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0056] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0057] When expressions such as "at least one of A, B, and C, etc." are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0058] Figure 1 The cross-sectional structure diagram of a three-terminal SiC UMOSFET device in the related art is schematically shown.

[0059] The three-terminal SiC UMOSFET device in the related art includes a first source 110, a first gate 120, and a first drain 130. Above the first drain 130 is a substrate, and above the substrate is an epitaxial layer. A trench is provided in the epitaxial layer. The bottom of the trench is a P protection area, and the vertical sidewalls of the trench are covered with an oxide layer. Above and below the first gate 120 are interlayer dielectrics. Also provided in the epitaxial layer are a P base region surrounding the trench, an N+ source region surrounding the trench on the P base region, and a P+ short-circuit region surrounding the N+ source region. Figure 1 The shading in FIG. 1 is only used to illustrate the first source 110 , the first gate 120 and the first drain 130 in the device.

[0060] In the blocking state, high-energy particle irradiation (such as protons, neutrons, and heavy ions) can trigger single-event effects (SEEs), leading to a sudden increase in the transient electric field in the gate oxide layer. Specifically, collisions between the incident particles and the crystal lattice generate a large number of electron-hole pairs. Driven by the source-drain electric field, these holes migrate toward the gate oxide interface, forming a local short-circuit current, causing the electric field strength within the gate dielectric to far exceed the breakdown threshold. This process not only causes oxide degradation and a surge in leakage current, but can also induce single-event burnout or single-event gate punchthrough through the parasitic bipolar transistor effect, causing permanent damage. Methods to mitigate electric field concentration by optimizing gate oxide thickness or doping engineering have limited controllability under dynamic stress.

[0061] In view of this, the present disclosure proposes a radiation-resistant four-terminal SiC UMOSFET device, such as Figure 2 .

[0062] Figure 2 The cross-sectional structure diagram of a radiation-resistant four-terminal SiC UMOSFET device according to an embodiment of the present disclosure is schematically shown.

[0063] like Figure 2 , radiation-hardened four-terminal SiC The UMOSFET device includes an N-type heavily doped substrate 201; a drain 202, arranged on the lower surface of the N-type heavily doped substrate 201; an N-type epitaxial layer 203, arranged on the upper surface of the N-type heavily doped substrate 201, wherein a trench is formed in the N-type epitaxial layer 203; a P protection zone 204, arranged at the bottom of the trench; an oxide layer 205, arranged on the vertical sidewall of the trench on the P protection zone 204; a control electrode 206, arranged on the P protection zone 204 in the trench; a first interlayer dielectric 207, arranged on the control electrode 206 in the trench; a gate 208, arranged on the first interlayer dielectric 207 in the trench, wherein the control electrode 206 and the gate 208 are surrounded by the oxide layer; a P base region 209, arranged in the N-type epitaxial layer 203 around the periphery of the trench 208; an N-type heavily doped source region 210, arranged in the P base region 209, surrounding the periphery of the trench; and a source 211, arranged on the N-type heavily doped source region. Figure 2 The shading in FIG. 2 is only used to illustrate the drain 202 , gate 208 , source 211 and control electrode 206 in the device.

[0064] According to the embodiments of the present disclosure, Figure 2 As shown in , the device further includes: a second interlayer dielectric 212 disposed on the upper surfaces of the oxide layer 205 and the gate 208 .

[0065] The N-type heavily doped source region 210 includes a P+ short-circuit region 2101 and an N+ source region 2102. The N+ source region 2102 is located in the P-base region 209 and surrounds the periphery of the trench. The P+ short-circuit region 2101 is located in the P-base region 209 and surrounds the periphery of the N+ source region 2102.

[0066] According to an embodiment of the present disclosure, the control electrode 206 is configured to change the electric field in the oxide layer and the electric field in the N-type epitaxial layer adjacent to the P protection zone by adjusting the voltage applied to the control electrode 206 .

[0067] According to an embodiment of the present disclosure, the radiation-resistant four-terminal SiC UMOSFET device provided by the present disclosure replaces the conventional gate structure with a trench gate structure, which can fix the potential under the trench of the SiC UMOSFET device, thereby controlling the transient electric field in the oxide layer and preventing breakdown due to excessive transient electric fields. By adjusting the potential of the control electrode, the width of the depletion region between the P-protected area and the surrounding N-type epitaxial layer is controlled, thereby controlling the electric field strength directed to the P-protected area, so that minority carrier holes are extracted from the control electrode under composite stress impact processes such as radiation, electricity, heat, and dynamics. The control electrode can also attract holes, making the positive feedback generated by BJT hole injection and substrate epitaxial impact ionization more difficult to occur, thereby improving the single-event burnout threshold voltage of the SiC UMOSFET device. The control electrode potential can also be adjusted to make the SiC UMOSFET device operate in different states, making the device flexible and applicable to various scenarios. The control electrode can also attract mobile charges in the oxide layer, reducing the impact of mobile charges on the threshold and improving the gate oxide reliability of the SiC UMOSFET device.

[0068] The following describes the relationship between the various layer structures in the radiation-hardened four-terminal SiC UMOSFET device in conjunction with a method for manufacturing the radiation-hardened four-terminal SiC UMOSFET.

[0069] Figure 3 A flow chart of a method for manufacturing a radiation-hardened four-terminal SiC UMOSFET device according to an embodiment of the present disclosure is schematically shown.

[0070] like Figure 3 As shown, the method includes operations S301 to S311.

[0071] In operation S301 , an N-type epitaxial layer is formed on an upper surface of an N-type heavily doped substrate.

[0072] In operation S302 , a trench is formed in the N-type epitaxial layer.

[0073] In operation S303 , a P protection region is formed at the bottom of the trench.

[0074] In operation S304 , an oxide layer is formed on the vertical sidewalls of the trench on the P protection region.

[0075] In operation S305 , a control electrode is formed on the P protection region within the trench.

[0076] In operation S306 , a first interlayer dielectric is formed on the control electrode in the trench.

[0077] In operation S307 , a gate is formed on the first interlayer dielectric in the trench.

[0078] In operation S308 , a P-base region is formed on an upper portion of the N-type epitaxial layer, wherein the P-base region surrounds an outer circumference of the trench.

[0079] In operation S309 , an N-type heavily doped source region is formed in the P-base region.

[0080] In operation S310 , a source is formed on an N heavily doped source region.

[0081] In operation S311 , a drain is formed on a lower surface of an N-type heavily doped substrate.

[0082] The following combination Figures 4 to 12 Explain operations S301 to S311.

[0083] Figure 4 The cross-sectional structure diagram of the device according to the embodiment of the present disclosure after an N-type epitaxial layer is formed on the upper surface of the N-type heavily doped substrate is schematically shown.

[0084] like Figure 4 As shown, an epitaxial process can be used to form an N-type epitaxial layer 203 on an N-type heavily doped substrate 201. The N-type heavily doped substrate 201 can be an N-type SiC substrate, or Si, GaN, etc., without limitation. The resistivity of the N-type heavily doped substrate 201 can be 0.01~0.03 The thickness along the vertical direction can be 100~500μm, and the doping concentration of the N-type epitaxial layer 203 can be 5e14~5e16cm -3 , the thickness along the vertical direction can be 8~20μm.

[0085] Figure 5 The cross-sectional structure diagram of the device after forming a trench in the N-type epitaxial layer according to an embodiment of the present disclosure is schematically shown.

[0086] like Figure 5 As shown, a photolithography and etching process may be used to form a trench A1 on the N-type epitaxial layer 203 . The depth of the trench A1 along the vertical direction may be 0.3-2 μm.

[0087] Figure 6 The cross-sectional structure diagram of the device after forming a P protection zone at the bottom of the trench according to an embodiment of the present disclosure is schematically shown.

[0088] like Figure 6As shown, an epitaxial process can be used to form a P protection zone 204 at the bottom of the trench A1. The junction depth of the P protection zone 204 is 0.1-0.5 μm, and the peak doping concentration is 1e17-5e19 cm -3 .

[0089] Figure 7 The cross-sectional structure diagram of the device according to the embodiment of the present disclosure is schematically shown after an oxide layer is formed on the vertical sidewalls of the trench in the P protection area.

[0090] like Figure 7 As shown, a thermal oxidation or deposition process can be used to generate a layer of oxide on the device surface, and the excess portion is removed by photolithography and etching, leaving only the oxide on the vertical sidewalls of the trench to form an oxide layer 205. The thickness of the oxide layer 205 along the horizontal direction can be 10 to 200 nm.

[0091] Figure 8 The cross-sectional structure diagram of the device according to the embodiment of the present disclosure is schematically shown after a control electrode is formed on the P protection zone in the trench.

[0092] like Figure 8 As shown, a deposition process can be used to deposit a layer of polysilicon on the P protection zone 204, and photolithography and etching processes can be used to remove excess polysilicon to form a control electrode 206. The thickness of the control electrode 206 along the vertical direction is 0.1-0.5 μm.

[0093] Figure 9 The cross-sectional structure diagram of the device according to the embodiment of the present disclosure is schematically shown after a first interlayer dielectric is formed on the control electrode in the trench.

[0094] like Figure 9 As shown, a first interlayer dielectric 207 may be formed above the control electrode 206 by using deposition, photolithography, and etching processes. The thickness of the first interlayer dielectric along the vertical direction is 10-500 nm.

[0095] Figure 10 The cross-sectional structure diagram of the device according to the embodiment of the present disclosure is schematically shown after a gate is formed on the first interlayer dielectric in the trench.

[0096] like Figure 10 As shown, a deposition process may be used to deposit a layer of polysilicon on the first interlayer dielectric 207 , and photolithography and etching processes may be used to remove excess polysilicon to form a gate 208 .

[0097] Figure 11 The cross-sectional structure diagram of the device according to the embodiment of the present disclosure is schematically shown after a P-base region is formed on the upper part of the N-type epitaxial layer and an N-type heavily doped source region is formed in the P-base region.

[0098] like Figure 11 As shown in FIG, a P base region 209 is formed on the N epitaxial layer 203 by photolithography and ion implantation, with a junction depth of 0.2 to 2.5 μm and a peak implantation concentration of 1e17 to 5e19 cm -3 The N+ source region 2102 is formed in the P base region 209 by photolithography and ion implantation. The junction depth of the N+ source region 2102 is 0.1~0.5um, and the junction depth of the N+ source region 2102 is 0.1~1.5um less than the junction depth of the P base region 209. The peak doping concentration is 5e18~5e20cm -3 The photolithography and ion implantation process is used to form a P+ short-circuit region 2101 in the P-base region 209. The junction depth of the P+ short-circuit region 211 is 0.1~0.5um, and the junction depth of the P+ short-circuit region 2101 is 0.1~1.5um less than the junction depth of the P-base region 209. The peak doping concentration is 5e18~5e20cm -3 .

[0099] According to an embodiment of the present disclosure, the layout of the P base region, the N+ source region, the P+ short circuit region, and the P+ injection region can be a square, a hexagon, a lattice array, etc.

[0100] Figure 12 The cross-sectional structure diagram of the device after forming a source electrode on the N-heavily doped source region according to an embodiment of the present disclosure is schematically shown.

[0101] like Figure 12 As shown, a second interlayer dielectric 212 is formed above the gate 208 by deposition, photolithography and etching processes. A source 211 is formed above the second interlayer dielectric 212, the P+ short circuit region 2101 and the N+ source region 2102 by deposition, photolithography and etching processes.

[0102] Laser annealing, metal thickening and deposition processes are used to form the drain electrode 202 on the back of the device and remove the protective glue on the front of the device to obtain the following: Figure 2 The radiation-hardened four-terminal SiC UMOSFET device is shown.

[0103] The preparation method provided by the present disclosure is highly compatible with the conventional SiC UMOSFET device preparation process, and mass production can be achieved without special adjustments to the SiC process.

[0104] To clarify this solution, the process flow diagram only shows the layered layout relevant to the patent. Dimensions in the diagram (including lateral dimensions, layout dimensions, dielectric thickness, metal thickness, junction depth, etc.) do not represent actual dimensions and are provided solely to illustrate the patent concept. Examples of methods that can be used to form the structures disclosed herein include, but are not limited to, planar MOSFETs, planar IGBTs, and JBSs; semiconductor materials include, but are not limited to, SiC, Si, GaN, and others.

[0105] The radiation-resistant four-terminal SiC UMOSFET device disclosed herein significantly reduces the peak gate oxide electric field when a single-particle effect occurs by controlling the control electrode potential, which can significantly reduce the maximum drain-gate leakage current spike and the gate-source leakage current spike, reducing potential damage to the gate. At the same time, it can improve the blocking voltage of the single-particle burnout resistance and enable the MOSFET power device to operate flexibly in different states and be suitable for different radiation environments. Through the new control electrode, the potential difference between the control electrode and the gate is fixed, thereby reducing the electric field in the oxide layer and preventing the electric field in the oxide layer from being too high and being broken down.

[0106] Will Figure 1 The three-terminal SiC UMOSFET device shown in FIG and the radiation-resistant four-terminal SiC UMOSFET device of the embodiment of the present disclosure are compared with the change of the maximum transient electric field of the gate oxide when they are irradiated. Figure 13 shown.

[0107] Figure 13 Schematic diagram showing the change of the maximum transient electric field of the gate oxide with time when the three-terminal SiC UMOSFET device and the radiation-resistant four-terminal SiC UMOSFET device of the embodiment of the present disclosure are irradiated.

[0108] like Figure 13 As shown, when high-energy particles bombard the device, the radiation-hardened four-terminal SiC UMOSFET device (4T-UMOSFET) of the embodiment of the present disclosure can significantly reduce the maximum peak electric field of the gate oxide layer compared to the three-terminal SiC UMOSFET device (CN-UMOSFET). When the control electrode bias voltage of the radiation-hardened four-terminal SiC UMOSFET device of the embodiment of the present disclosure is 0V, the maximum peak electric field is reduced by 89.667% compared to the three-terminal SiC UMOSFET device.

[0109] Figure 14 The diagram schematically shows the relationship between the maximum transient electric field peak of the gate oxide and the control electrode bias voltage when the radiation-resistant four-terminal SiC UMOSFET device according to the embodiment of the present disclosure is irradiated.

[0110] like Figure 14 As shown in the figure, when high-energy particles bombard the device, the maximum peak electric field in the gate oxide layer can be further reduced as the control bias voltage increases in the reverse direction. When the control bias voltage of the radiation-hardened four-terminal SiC UMOSFET device is -20V, the maximum peak electric field is reduced by 28.982% compared to the radiation-hardened four-terminal SiC UMOSFET device with a control bias of 0V, and the maximum peak electric field can be further reduced as the control bias voltage increases in the reverse direction.

[0111] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of the systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or part of the code, which contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the boxes can also occur in an order different from that marked in the accompanying drawings. For example, two boxes shown in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, as well as the combination of boxes in the block diagram or flowchart, can be implemented using a dedicated hardware-based system that performs the specified functions or operations, or can be implemented using a combination of dedicated hardware and computer instructions. It will be understood by those skilled in the art that the features described in the various embodiments of the present disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features described in the various embodiments of the present disclosure may be combined and / or coupled in various ways, and all of these combinations and / or couplings fall within the scope of the present disclosure.

[0112] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A radiation-hardened four-terminal SiC UMOSFET device, comprising: N-type heavily doped substrate; a drain electrode, arranged on the lower surface of the N-type heavily doped substrate; An N-type epitaxial layer is provided on the upper surface of the N-type heavily doped substrate, wherein a trench is formed in the N-type epitaxial layer; A P protection zone is provided at the bottom of the groove; an oxide layer, disposed on the vertical sidewalls of the trench on the P protection area; a control electrode, disposed in the trench on the P protection zone; a first interlayer dielectric disposed on the control electrode in the trench; a gate, disposed in the trench on the first interlayer dielectric, wherein the control electrode and the gate are surrounded by the oxide layer; A P-base region is provided in the N-type epitaxial layer and surrounds the outer periphery of the trench; An N-type heavily doped source region is disposed in the P-base region and surrounds the periphery of the trench; and The source is arranged on the N-type heavily doped source region.

2. The device according to claim 1, wherein The control electrode is configured to change the electric field in the oxide layer and the electric field in the N-type epitaxial layer adjacent to the P protection zone by adjusting a voltage applied to the control electrode.

3. The device according to claim 1, further comprising: A second interlayer dielectric is provided on the upper surfaces of the oxide layer and the gate.

4. The device according to claim 1, wherein The thickness of the control electrode along the vertical direction is 0.1-0.5 μm, and the thickness of the first interlayer dielectric along the vertical direction is 10-500 nm.

5. The device according to any one of claims 1 to 4, wherein The depth of the groove in the vertical direction is 0.3~2um.

6. The device according to any one of claims 1 to 4, wherein The junction depth of the P protection zone is 0.1~0.5um, and the peak doping concentration is 1e17~5e19 cm -3 .

7. The device according to any one of claims 1 to 4, wherein The thickness of the N-type heavily doped substrate in the vertical direction is 100-500 μm, and the resistivity of the N-type heavily doped substrate is 0.01-0.03 .

8. The device according to any one of claims 1 to 4, wherein The thickness of the N-type epitaxial layer in the vertical direction is 8-20 μm, and the doping concentration of the N-type epitaxial layer is 5e14-5e16 cm -3 .

9. The device according to any one of claims 1 to 4, wherein: The junction depth of the P base region is 0.2-2.5 μm, and the peak doping concentration of the P protection region is 1e17-5e19 cm -3 .

10. A method for manufacturing a radiation-hardened four-terminal SiC UMOSFET device, characterized in that: include: forming an N-type epitaxial layer on the upper surface of the N-type heavily doped substrate; forming a trench in the N-type epitaxial layer; forming a P protection zone at the bottom of the trench; forming an oxide layer on the vertical sidewalls of the trench on the P protection area; forming a control electrode in the trench on the P protection zone; forming a first interlayer dielectric on the control electrode in the trench; forming a gate on the first interlayer dielectric in the trench; forming a P-base region on an upper portion of the N-type epitaxial layer, wherein the P-base region surrounds an outer periphery of the trench; forming an N-type heavily doped source region in the P-base region; forming a source electrode on the N heavily doped source region; and A drain is formed on the lower surface of the N-type heavily doped substrate.

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