Semiconductor element

Abstract

The invention discloses a semiconductor element, which mainly comprises a metal gate arranged on a substrate, an interlayer dielectric layer surrounding the metal gate and a groove arranged between the interlayer dielectric layer and the metal gate, wherein the metal gate comprises a high dielectric constant dielectric layer arranged on the substrate, a work function metal layer arranged on the high dielectric constant dielectric layer and a low impedance metal layer arranged on the work function metal layer, and the top surface of the work function metal layer is lower than the top surface of the high dielectric constant dielectric layer; the top surface of the work function metal layer is lower than the top surface of the low impedance metal layer, and the groove is arranged in the work function metal layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor element, and in particular to a metal gate transistor with a groove provided between an interlayer dielectric layer and a metal gate. Background Art

[0002] With the advancement of science and technology, technologies such as augmented reality (AR) and virtual reality (VR) are gradually maturing. In the foreseeable future, AR and VR will be widely used in human life, for example in education, logistics, medical care, and the military.

[0003] Currently, augmented reality and virtual reality are mainly realized by head-mounted displays. Among them, current head-mounted displays usually connect display driver integrated circuits (DDICs) containing high-voltage components, medium-voltage components, and / or low-voltage components to a display module via very long wires or metal interconnects. This design usually results in a large product, which not only takes up space but also increases the difficulty of wearing. Therefore, how to improve the current manufacturing process to provide a display that can be used in AR or VR environments is an important issue. Summary of the Invention

[0004] One embodiment of the present invention discloses a semiconductor device, which mainly includes a metal gate arranged on a substrate, an interlayer dielectric layer surrounding the metal gate, and a groove arranged between the interlayer dielectric layer and the metal gate, wherein the metal gate includes a high dielectric constant dielectric layer arranged on the substrate, a work function metal layer arranged on the high dielectric constant dielectric layer, and a low impedance metal layer arranged on the work function metal layer, the top surface of the work function metal layer is lower than the top surface of the high dielectric constant dielectric layer, the top surface of the work function metal layer is lower than the top surface of the low impedance metal layer, and the groove is arranged in the work function metal layer.

[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a first gate structure and a second gate structure extending along a first direction on a substrate, a first contact plug extending along the first direction on one side of the first gate structure, a second contact plug extending along the first direction on the other side of the second gate structure, and a dummy contact plug extending along the first direction between the first gate structure and the second gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1 to 3 A schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0007] Figure 4 is a schematic structural diagram of a semiconductor element according to an embodiment of the present invention;

[0008] Figure 5 is a schematic structural diagram of a semiconductor element according to an embodiment of the present invention;

[0009] Figure 6 FIG. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.

[0010] Explanation of symbols

[0011] 12: Base

[0012] 14: Transistor area

[0013] 16: Shallow Trench Isolation

[0014] 18: Gate structure

[0015] 20: Gate structure

[0016] 22: Gate structure

[0017] 24: Gate dielectric layer

[0018] 26: Gate material layer

[0019] 28: gap wall

[0020] 30: Source / drain region

[0021] 32: epitaxial layer

[0022] 34: Interlayer dielectric layer

[0023] 36: Gate dielectric layer

[0024] 46: High dielectric constant dielectric layer

[0025] 48: Work function metal layer

[0026] 50: low impedance metal layer

[0027] 52:Metal gate

[0028] 54: Hard mask

[0029] 56: Groove

[0030] 58: interlayer dielectric layer

[0031] 60: Contact plug

[0032] 62: Silicide metal layer

[0033] 64: Intermetallic dielectric layer

[0034] 66: Contact hole conductor

[0035] 68: Groove conductor

[0036] 70:Metal interconnect

[0037] 72: Stop layer

[0038] 74: dummy contact plug DETAILED DESCRIPTION

[0039] Although specific configurations and arrangements are discussed herein, it should be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in a variety of other applications.

[0040] It should be noted that references in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc. indicate that the described embodiments may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such terms do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of those skilled in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0041] Generally, terms can be understood at least in part based on usage in context. For example, as used herein, the term "one or more" (depending at least in part on the context) can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a plural combination of features, structures or characteristics. Similarly, terms such as "a", "an" or "the" can again be understood to express singular usage or to convey plural usage, depending at least in part on the context. In addition, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, and can instead allow for the presence of additional factors that are not necessarily explicitly described and depend at least in part on the context.

[0042] It should be readily understood that the meanings of “on,” “over,” and “above” in the disclosure of this case should be interpreted in the broadest manner, so that “on” means not only “directly” on something, but also includes being on something with intervening features or layers therebetween, and that “on” or “above” means not only being on or above something, but also includes having no intervening features or layers (i.e., directly on something).

[0043] Furthermore, for ease of description, as illustrated in the accompanying drawings, spatially relative terms such as "below," "beneath," "lower," "above," "higher," etc. may be used to describe the relationship of one element or feature to another element(s) or feature(s). Spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0044] As used herein, the term "substrate" refers to the material onto which a layer of material is subsequently added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. Additionally, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0045] As used herein, the term "layer" refers to a portion of a material that includes an area having a thickness. A layer may extend over the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes between the top and bottom surfaces. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer that may include one or more layers and / or may have one or more layers above and / or below it. A layer may contain multiple layers. For example, an interconnect layer may include one or more conductors and contact layers (in which contacts, interconnects and / or vias are formed) and one or more dielectric layers.

[0046] Please refer to Figures 1 to 3 , Figures 1 to 3 A schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein Figure 1 The upper left part is a top view of a semiconductor device manufactured according to an embodiment of the present invention. Figure 1 The upper right part is a circuit diagram of a semiconductor device according to an embodiment of the present invention. Figure 1 The lower half is along Figure 1 The cross-sectional view of the semiconductor device is shown in the upper left corner along the tangent line AA'. Figure 1As shown, a substrate 12 is first provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate. Preferably, the substrate 12 has a planar transistor region 14 or an active region, such as a high-voltage region or a medium-voltage region, for fabricating a high-voltage or medium-voltage device. It should be noted that while this embodiment uses the fabrication of a planar field-effect transistor as an example, the present invention is not limited thereto. The present invention can also be applied to general non-planar field-effect transistors, such as fin-structured field-effect transistors, which also fall within the scope of the present invention.

[0047] According to one embodiment of the present invention, the fin structure is preferably manufactured by sidewall pattern transfer (SIT) and other technologies, and the procedure generally includes: providing a layout pattern to a computer system, and defining the corresponding pattern in a photomask through appropriate calculations. Subsequently, a plurality of equidistant and equal-width patterned sacrificial layers can be formed on the substrate through photolithography and etching processes, so that their individual appearances are strip-shaped. Thereafter, deposition and etching processes are sequentially performed to form spacers on each sidewall of the patterned sacrificial layer. The patterned sacrificial layer is then removed, and an etching process is performed under the coverage of the spacers, so that the pattern formed by the spacers is transferred to the substrate, and then the desired patterned structure, such as a strip-shaped patterned fin structure, is obtained by a fin cut process.

[0048] In addition, the fin structure can be formed by first forming a patterned mask (not shown) on the substrate 12, and then performing an etching process to transfer the pattern of the patterned mask to the substrate 12 to form the fin structure. Alternatively, the fin structure can be formed by first forming a patterned hard mask layer (not shown) on the substrate 12, and then using an epitaxial process to grow a semiconductor layer, such as silicon germanium, on the substrate 12 exposed by the patterned hard mask layer. This semiconductor layer can serve as the corresponding fin structure. These embodiments of forming the fin structure are all within the scope of the present invention.

[0049] A shallow trench isolation (STI) 16 is then formed surrounding the transistor region 14. In this embodiment, the STI 16 is formed by first forming a silicon oxide layer within the substrate 12 surrounding the transistor region using a flowable chemical vapor deposition (FCVD) process. A chemical mechanical polishing (CMP) process is then used in conjunction with an etching process to remove a portion of the silicon oxide layer, leaving the remaining silicon oxide layer slightly higher than the substrate 12 surface in the transistor region 14 to form the STI 16. While the top surface of the STI 16 in this embodiment is slightly higher than the substrate 12 surface in the transistor region 14, this is not limiting. According to other embodiments of the present invention, the top surface of the STI 16 may be flush with or slightly higher than the substrate 12 surface, and these variations are within the scope of the present invention.

[0050] Next, gate structures 18, 20 or dummy gates are formed on the substrate 12. In this embodiment, the gate structures 18, 20 can be fabricated using a gate-first process, a gate-last process (a high-k first process), or a gate-last process (a high-k last process) depending on the manufacturing process requirements. Taking the high-k last process of this embodiment as an example, a gate dielectric layer 24 or dielectric layer, a gate material layer 26 made of polysilicon, and a selective hard mask (not shown) can be sequentially formed on the substrate 12. A pattern transfer process is then performed using a patterned photoresist (not shown) as a mask. A portion of the gate material layer 26 is removed by a single etch or sequential etch steps. The patterned photoresist is then stripped to form gate structures 18, 20 each formed of the patterned gate material layer 26 on the substrate 12.

[0051] Then, at least one spacer 28 is formed on the sidewalls of each of the gate structures 18 and 20, and a source / drain region 30 and / or an epitaxial layer 32 are formed in the substrate 12 on both sides of the spacer 28. It should be noted that although the source / drain regions 30 are formed in the substrate 12 on both sides of the gate structures 18 and 20 and between the gate structures 18 and 20, respectively, in this embodiment, only the source / drain regions 30 on the left side of the gate structure 18 and the right side of the gate structure 20 will be connected to external devices in subsequent fabrication processes, while the source / drain region 30 between the gate structures 18 and 20 will not be connected to external devices. In other words, even if contact plugs are formed on the left side of the gate structure 18, the right side of the gate structure 20, and the source / drain region 30 between the two gate structures 18 and 20 in the subsequent manufacturing process, only the source / drain region 30 on the left side of the gate structure 18 and the right side of the gate structure 20 will be connected to the external components through the contact plugs and the upper metal interconnects. Only contact plugs will be formed on the source / drain region 30 between the gate structures 18 and 20 in the subsequent manufacturing process, but no metal interconnects will be formed or connected directly above the contact plugs.

[0052] In this embodiment, the spacer 28 can be a single spacer or a composite spacer, for example, including an offset spacer and a main spacer. The offset spacer and the main spacer can be made of the same or different materials, and both can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride. The source / drain region 30 can include different dopants depending on the conductivity type of the transistor being prepared, for example, P-type dopants or N-type dopants.

[0053] In a preferred embodiment of the present invention, epitaxial layer 32 can be made of different materials depending on the type of metal oxide semiconductor (MOS) transistor. For example, if the MOS transistor is a P-type transistor (PMOS), epitaxial layer 32 can optionally include silicon germanium (SiGe), silicon germanium boron (SiGeB), or silicon germanium tin (SiGeSn). In another embodiment of the present invention, if the MOS transistor is an N-type transistor (NMOS), epitaxial layer 32 can optionally include silicon carbide (SiC), silicon carbon phosphide (SiCP), or silicon phosphide (SiP). Furthermore, the selective epitaxial growth process can be performed using a single layer or multiple layers, and the heterogeneous atoms (e.g., germanium atoms or carbon atoms) can be varied in a gradual manner. However, it is preferred that the surface of epitaxial layer 32 be lighter or free of germanium atoms to facilitate the subsequent formation of a metal silicide layer.

[0054] According to one embodiment of the present invention, the source / drain region 30 can be selectively formed on a portion or all of the epitaxial layer 32. In one embodiment, the formation of the source / drain region 30 can also be performed in-situ during the selective epitaxial growth process. For example, when the metal oxide semiconductor conductor is a PMOS, a germanium silicide epitaxial layer, a germanium boron silicide epitaxial layer, or a germanium tin silicide epitaxial layer is formed, which can be accompanied by the implantation of P-type dopants; or when the metal oxide semiconductor conductor is an NMOS, a carbon silicide epitaxial layer, a carbon phosphorus silicide epitaxial layer, or a phosphorus silicide epitaxial layer is formed, which can be accompanied by the implantation of N-type dopants. This can omit the subsequent use of additional ion implantation steps to form the source / drain region 30 of the P-type / N-type transistor. In another embodiment, the dopants in the source / drain region 30 can also be formed in a gradual manner.

[0055] A contact etch stop layer (not shown) is then optionally formed to cover the surfaces of the gate structures 18, 20 and the shallow trench isolation 16, and an interlayer dielectric layer 34 is then formed on the gate structures 18, 20. A planarization process is then performed, such as using chemical mechanical polishing (CMP) to remove portions of the interlayer dielectric layer 34 and the contact etch stop layer and expose the gate material layer 26 made of polysilicon material, so that the upper surface of the gate material layer 26 is flush with the upper surface of the interlayer dielectric layer 34.

[0056] Please continue to refer to Figure 2 , Figure 2 To continue Figure 1 Schematic diagram of a method for manufacturing a semiconductor element, wherein Figure 2 The upper left part is a top view of a semiconductor device manufactured according to an embodiment of the present invention. Figure 2 The upper right part is a circuit diagram of semiconductor components, and Figure 2 The lower half is along Figure 2 The cross-sectional view of the semiconductor device is shown in the upper left corner along the BB' direction. Figure 2 As shown, a replacement metal gate (RMG) process is then performed to convert each gate structure 18 , 20 into a metal gate. For example, a selective dry etching or wet etching process, such as using an etching solution such as ammonium hydroxide (NH 4 OH) or tetramethylammonium hydroxide (TMAH), can be performed to remove the gate material layer 26 in the gate structures 18 , 20 to form a recess (not shown) in the interlayer dielectric layer 34 .

[0057] Next, another optional dielectric layer (not shown) or gate dielectric layer 36, a high-k dielectric layer 46, a work function metal layer 48, and a low-resistance metal layer 50 are sequentially formed in the recesses. A planarization process is then performed, such as using CMP to remove portions of the low-resistance metal layer 50, the work function metal layer 48, and the high-k dielectric layer 46 to form metal gates 52. Taking the gate structure fabricated using the high-k dielectric layer last fabrication process in this embodiment as an example, each metal gate 52 preferably includes a dielectric layer or gate dielectric layer 36, a U-shaped high-k dielectric layer 46, a U-shaped work function metal layer 48, and a low-resistance metal layer 50.

[0058] In this embodiment, the gate dielectric layer 24 and the gate dielectric layer 36 may include the same material or different materials. For example, both may include silicon oxide. The high-k dielectric layer 46 includes a dielectric material having a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalum oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalum oxide (SrTiO3), and strontium bismuth tantalum oxide (SrTiO3). tantalate,SrBi2Ta2O9,SBT), lead zirconate titanate (leadzirconate titanate,PbZr x Ti 1-x O3, PZT), barium strontium titanate (barium strontium titanate, Ba x Sr 1- x TiO3, BST), or a combination thereof.

[0059] The work function metal layer 48 is preferably used to adjust the work function of the metal gate so that it is suitable for an N-type transistor (NMOS) or a P-type transistor (PMOS). If the transistor is an N-type transistor, the work function metal layer 48 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as, but not limited to, titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide). If the transistor is a P-type transistor, the work function metal layer 48 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC). Another barrier layer (not shown) may be included between the work function metal layer 48 and the low resistance metal layer 50. The barrier layer may be made of materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The low resistance metal layer 50 may be made of low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or a combination thereof.

[0060] Next, a portion of the high-k dielectric layer 46, a portion of the work function metal layer 48, and a portion of the low-resistance metal layer 50 may be removed to form a recess (not shown). A hard mask 54 may then be filled into the recess and aligned with the surface of the interlayer dielectric layer 34. The hard mask 54 may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride. It should be noted that, in this stage, due to the different material selection ratios used to remove the portion of the high-k dielectric layer 46, the portion of the work function metal layer 48, and the portion of the low-resistance metal layer 50 by etching to form the recess, the top surface of the low-resistance metal layer 50 is preferably slightly higher than the top surfaces of the high-k dielectric layer 46 and the work function metal layer 48.

[0061] More specifically, in this embodiment, when removing a portion of the high-k dielectric layer 46, a portion of the work function metal layer 48, and a portion of the low-resistance metal layer 50 by etching, the material selectivity is preferably adjusted to remove more of the high-k dielectric layer 46 and the work function metal layer 48 and less of the low-resistance metal layer 50, so that the top surface of the work function metal layer 48 is lower than the top surfaces of the high-k dielectric layer 46 and the low-resistance metal layer 50, and the top surface of the high-k dielectric layer 46 is also lower than the top surface of the low-resistance metal layer 50, and a groove 56 is simultaneously formed between the interlayer dielectric layer 34 and the metal gate 52. In detail, the groove 56 is preferably disposed within the work function metal layer 48, or the groove 56 is preferably formed by the sidewalls of the high-k dielectric layer 46, the top surface of the work function metal layer 48, and the sidewalls of the low-resistance metal layer 50.

[0062] Please continue to refer to Figure 3 , Figure 3 To continue Figure 2 Schematic diagram of a method for manufacturing a semiconductor element, wherein Figure 3 The upper left part is a top view of a semiconductor device manufactured according to an embodiment of the present invention. Figure 3 The upper right part is a circuit diagram of semiconductor components, and Figure 3 The lower half is along Figure 3 The cross-sectional view of the semiconductor device is shown in the upper left tangent line CC' direction. Figure 3 As shown, another interlayer dielectric layer 58 may then be formed on the interlayer dielectric layer 34, and a contact plug fabrication process may be performed to form contact plugs 60 electrically connected to the source / drain regions 30 adjacent to the gate structures 18 and 20, respectively. In this embodiment, the contact plugs 60 may be formed by first removing portions of the interlayer dielectric layers 34 and 58 to form contact holes (not shown), and then sequentially depositing a barrier layer (not shown) and a metal layer (not shown) on the substrate 12 to fill the contact holes. A planarization process, such as CMP, is then performed to remove portions of the metal layer, the barrier layer, and even portions of the interlayer dielectric layers 34 and 58 to form contact plugs 60 in the contact holes. The top surface of the contact plugs 60 is preferably flush with the top surface of the interlayer dielectric layer 58. In this embodiment, the interlayer dielectric layers 34 and 58 may include silicon oxide, the barrier layer is preferably selected from the group consisting of titanium, tantalum, titanium nitride, tantalum nitride and tungsten nitride, and the metal layer is preferably selected from the group consisting of aluminum, titanium, tantalum, tungsten, niobium, molybdenum and copper.

[0063] It should be noted that, in this embodiment, after depositing the barrier layer and metal layer in the contact holes, a metal silicide process may be simultaneously performed according to process requirements. For example, a thermal annealing process may be performed to react a portion of the barrier layer with the substrate to form a metal silicide layer 62 between the substrate 12 and the contact plug 60. A back-end metal interconnect fabrication process may then be performed. For example, an inter-metal dielectric (IMD) layer 64 may be formed on the interlayer dielectric layer 58. A photolithography and etching process may be performed to remove a portion of the IMD layer 64 and expose the contact plugs 60 on the left side of the gate structure 18 and the right side of the gate structure 20 to form contact holes (not shown). The contact holes are then filled with metal or a conductive material and planarized to form metal interconnects 70 consisting of contact hole conductors 66 and trench conductors 68. The metal interconnects 70 are connected to the contact plugs 60 on the left side of the gate structure 18 and the right side of the gate structure 20, respectively, but are preferably not connected to or disposed directly above the contact plug 60 between the two gate structures 18 and 20. It should be noted that the metal interconnect 70 formed by the contact hole conductor 66 and the trench conductor 68 is Figure 3 From the bottom half, although only the contact plugs 60 on both sides of the gate structures 18 and 20 are connected, Figure 3From the top view in the upper left part, the tail ends of the gate structures 18 and 20 can be simultaneously connected through the contact plugs 60 directly above the gate structures 18 and 20 .

[0064] Because the contact plug 60 between the two gate structures 18 and 20 is not connected to external devices via an upper metal interconnect, the contact plug 60 between the gate structures 18 and 20 is preferably a dummy contact plug 74, compared to the contact plugs 60 on the left side of gate structure 18 and the right side of gate structure 20, which are active contact plugs. A stop layer 72 can then be formed on the intermetallic dielectric layer 64. In this embodiment, the intermetallic dielectric layer 64 preferably comprises silicon oxide or an ultra-low-k dielectric layer such as a porous dielectric material, such as, but not limited to, silicon oxycarbide (SiOC) or silicon oxycarbide hydrogen (SiOCH). The metal interconnect 70 preferably comprises copper, and the stop layer 72 comprises, but is not limited to, nitrogen-doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN). This completes the fabrication of a semiconductor device according to one embodiment of the present invention.

[0065] Please refer to Figure 3 , Figure 3 The following also discloses a schematic structural diagram of a semiconductor device according to an embodiment of the present invention. Figure 3 As shown in the lower half, the semiconductor device mainly includes two gate structures 18 and 20 composed of metal gates 52 arranged on the substrate 12, an interlayer dielectric layer 34 surrounding the metal gates 52, a groove 56 arranged between the interlayer dielectric layer 34 and the metal gates 52, contact plugs 60 arranged on both sides of the metal gates 52, and dummy contact plugs 74 arranged in the interlayer dielectric layer 34 between the metal gates 52 and connected to the source / drain regions 30, wherein each metal gate 52 includes a high dielectric constant dielectric layer 46 arranged on the substrate 12, a work function metal layer 48 arranged on the high dielectric constant dielectric layer 46 and a low resistance metal layer 50 arranged on the work function metal layer 48, each contact plug 60 and the dummy contact plug 74 includes a silicide metal layer 62, and the groove 56 is arranged in the work function metal layer 48.

[0066] From a detailed perspective, the top surface of the work function metal layer 48 is preferably lower than the top surface of the high-k dielectric layer 46 and the top surface of the low-resistance metal layer 50, and the top surface of the high-k dielectric layer 46 is in turn lower than the top surface of the low-resistance metal layer 50. The recess 56 extends from the sidewalls of the high-k dielectric layer 46 to the top surface of the work function metal layer 48 and the sidewalls of the low-resistance metal layer 50. Looking at the left side of the recess 56 in the gate structure 18, the left sidewall of the recess 56 or the sidewall of the high-k dielectric layer 46 is preferably lower than the right sidewall of the recess 56 or the sidewall of the low-resistance metal layer 50. Looking at the right side of the recess 56, the right sidewall of the recess 56 or the sidewall of the high-k dielectric layer 46 is preferably lower than the left sidewall of the recess 56 or the sidewall of the low-resistance metal layer 50. Furthermore, the overall shape of the recess 56 can vary depending on the actual manufacturing process or product requirements, for example, it can include a roughly V-shaped or U-shaped cross-section.

[0067] like Figure 3 As shown in the upper left portion, the semiconductor device, viewed from a top view, primarily includes a gate structure 18 and a gate structure 20 extending along a first direction, such as the Y direction, on the substrate 12; source / drain regions 30 extending along a second direction, such as the X direction, on both sides of the gate structure 18 and the gate structure 20; a contact plug 60, also in a rectangular shape, extending along the Y direction on one side of the gate structure 18, such as the source / drain region 30 on the left side; the contact plug 60 extending along the Y direction on the other side of the gate structure 20, such as the source / drain region 30 on the right side; and a dummy contact plug 74 extending along the Y direction on the source / drain region 30 between the two gate structures 18 and 20. It should be noted that compared to the contact plugs 60 on the left side of the gate structure 18 and the right side of the gate structure 20, which are both provided with metal interconnects 70 composed of contact hole conductors 66 and trench conductors 68 and connected to external circuits through the metal interconnects 70, it is preferred that no metal interconnects 70 composed of contact hole conductors 66 and / or trench conductors 68 are formed or connected to external circuits directly above the dummy contact plug 74 between the gate structures 18 and 20.

[0068] Please continue to refer to Figure 4 , Figure 4 FIG. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention, wherein Figure 4 The upper left portion is a top view of a semiconductor device according to an embodiment of the present invention. Figure 4 The upper right part is a circuit diagram of semiconductor components, and Figure 4 The lower half is along Figure 4 The cross-sectional view of the semiconductor element is shown in the upper left tangent line DD'. Figure 4 As shown, compared with the above embodiment, only two gate structures 18 and 20 are provided in the transistor region 14 and according to Figure 3The upper right half connects the two gate structures 18 and 20 in parallel to a circuit. In this embodiment, three gate structures 18, 20, and 22 can be set in the transistor area 14 and based on Figure 4 The upper right portion connects the three gate structures 18, 20, and 22 in parallel to a circuit. As in the previous embodiment, each gate structure 18, 20, and 22 can be converted from a polysilicon gate into a metal gate 52 using a metal gate transistor fabrication process. Each gate structure 18, 20, and 22 includes components such as a high-k dielectric layer 46, a work function metal layer 48, and a low-resistance metal layer 50. Furthermore, contact plugs 60 are provided on both sides of the gate structures 18, 20, and 22. Metal interconnects 70, consisting of contact hole conductors 66 and trench conductors 68, are preferably formed directly above the contact plugs 60 on the left side of gate structure 18 and the right side of gate structure 20. These metal interconnects 70 connect to external circuitry. The contact plugs 60 between the gate structures 18 and 22 and between the gate structures 20 and 22 are preferably dummy contact plugs 74 , that is, any metal interconnects 70 composed of contact hole conductors 66 and trench conductors 68 are preferably not formed directly above the dummy contact plugs 74 and connected thereto.

[0069] Please continue to refer to Figure 5 , Figure 5 FIG. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention, wherein Figure 5 The upper left portion is a top view of a semiconductor device according to an embodiment of the present invention. Figure 5 The upper right part is a circuit diagram of semiconductor components, and Figure 5 The lower half is along Figure 5 The cross-sectional view of the semiconductor element is shown in the upper left tangent line EE' direction. Figure 5 As shown in the lower half, compared with Figure 3 In this embodiment, each gate dielectric layer 36 of the dual-gate structure has a uniform thickness. In this embodiment, a metal gate replacement process is used to hollow out the polysilicon gate material layer 26 and fill it with the gate dielectric layer 36. An additional etching process is then performed to remove a portion of the gate dielectric layer 36, resulting in different thicknesses on the left and right sides of the gate dielectric layer 36. A high-k dielectric layer 46, a work function metal layer 48, and a low-resistance metal layer 50 are then sequentially formed on the gate dielectric layer 36 to form a metal gate 52.

[0070] In this embodiment, the gate dielectric layer 36 in each gate structure 18 , 20 preferably has a non-uniform thickness, wherein the gate dielectric layer 36 closer to the adjacent gate structure 18 , 20 preferably has a thinner thickness. For example, the thickness of the gate dielectric layer 36 closer to the right side of the left gate structure 18 is preferably slightly thinner than the thickness of the gate dielectric layer 36 closer to the left side, and the thickness of the gate dielectric layer 36 closer to the left side of the right gate structure 20 is slightly thinner than the thickness of the gate dielectric layer 36 closer to the right side. Furthermore, a step is preferably formed between the left and right gate dielectric layers 36 due to the height difference. Furthermore, the lower and upper portions of each gate dielectric layer 36 can have the same or different widths or lengths depending on product requirements. For example, the width or length of the left half of each gate dielectric layer 36 can be less than, greater than, or equal to the width or length of the right half. These variations are all within the scope of the present invention.

[0071] Please continue to refer to Figure 6 , Figure 6 FIG. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention, wherein Figure 6 The upper left portion is a top view of a semiconductor device according to an embodiment of the present invention. Figure 6 The upper right part is a circuit diagram of semiconductor components, and Figure 6 The lower half is along Figure 6 The cross-sectional view of the semiconductor device is shown in the upper left tangent line FF'. Figure 6 As shown in the lower half, compared with Figure 4 In this embodiment, each gate dielectric layer 36 of the three gate structures 18, 20, and 22 has a uniform thickness. In this embodiment, a metal gate replacement process is used to hollow out the polysilicon gate material layer 26 and fill it with the gate dielectric layer 36. An additional etching process is then performed to remove portions of the gate dielectric layer 36 in the left and right gate structures 18 and 20. This results in different thicknesses of the gate dielectric layer 36 on the left and right gate structures 18 and 20, while maintaining a uniform thickness of the gate dielectric layer 36 in the middle gate structure 22. A high-k dielectric layer 46, a work function metal layer 48, and a low-resistance metal layer 50 are then sequentially formed on the gate dielectric layer 36 to form a metal gate 52.

[0072] In this embodiment, each gate dielectric layer 36 in the left gate structure 18 and the right gate structure 20 preferably has a non-uniform thickness, while the gate dielectric layer 36 in the middle gate structure 22 has a uniform thickness, wherein the gate dielectric layer 36 close to the adjacent gate structures 18, 20, 22 preferably has a lower thickness. For example, the thickness of the gate dielectric layer 36 close to the right side of the left gate structure 18 is preferably slightly lower than the thickness of the gate dielectric layer 36 close to the left side, and the thickness of the gate dielectric layer 36 close to the left side of the right gate structure 20 is slightly lower than the thickness of the gate dielectric layer 36 close to the right side, and a step is preferably formed between the left gate dielectric layer 36 and the right gate dielectric layer 36 due to the height difference. Figure 5 In an embodiment, the lower portion and the upper portion of each gate dielectric layer 36 may have the same or different widths or lengths according to product requirements. For example, the width of the left half of each gate dielectric layer 36 may be less than, greater than, or equal to the width or length of the right half. These variations are all within the scope of the present invention.

[0073] In summary, compared to conventional display driver integrated circuit (DDIC) fabrication processes that merely dispose a single gate structure and a set of source / drain regions on either side of a single planar transistor region or active region, the present embodiment preferably divides the space originally occupied by the single gate structure into two or more gate structures. Active contact plugs are formed on either side of the two outermost gate structures in subsequent fabrication processes, and dummy plugs are formed between the remaining gate structures. In other words, the total length of the conventional single gate structure is approximately equal to the total length of the two or more gate structures of the present invention, where the length of the gate structure is preferably equal to the length of the gate structure extending along the X-direction in the aforementioned embodiment. According to preferred embodiments of the present invention, the gate structure of the aforementioned embodiment is preferably applied to planar transistor devices with larger line widths. Therefore, the length of each divided gate structure is preferably greater than 0.25 microns, or more preferably greater than 0.4 microns, 0.6 microns, or even 1 micron or greater, all of which are within the scope of the present invention.

[0074] In addition, the present invention can also be based on Figures 5 and 6 In one embodiment, an additional etching process is used during the metal gate replacement process to adjust the thickness of a portion of the gate dielectric layer, resulting in a non-uniform thickness of the gate dielectric layer 36. The gate dielectric layer 36 preferably has a lower thickness on a side closer to the adjacent gate structure and a higher thickness on a side farther from the adjacent gate structure. According to a preferred embodiment of the present invention, connecting multiple gate structures in parallel to form a stacked gate structure and / or forming a height difference in the gate dielectric layer can help alleviate undercutting of the work function metal layer caused by over-etching during the metal gate replacement process.

[0075] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor element, characterized in that: Include: A metal gate is provided on the substrate; an interlayer dielectric layer surrounding the metal gate; and The groove is arranged between the interlayer dielectric layer and the metal gate.

2. The semiconductor device according to claim 1, wherein the metal gate comprises: a high-k dielectric layer disposed on the substrate; a work function metal layer disposed on the high-k dielectric layer; and The low-resistance metal layer is disposed on the work function metal layer. 3 . The semiconductor device as claimed in claim 2 , wherein a top surface of the work function metal layer is lower than a top surface of the high-k dielectric layer. 4 . The semiconductor device as claimed in claim 2 , wherein a top surface of the work function metal layer is lower than a top surface of the low resistance metal layer. The semiconductor device as claimed in claim 2 , wherein the groove is disposed in the work function metal layer. The semiconductor device as claimed in claim 2 , wherein the groove comprises a U-shape. The semiconductor device as claimed in claim 1 , wherein the metal gate has a length greater than 0.25 μm.

8. A semiconductor device, characterized in that: Include: A first gate structure and a second gate structure extend on the substrate along a first direction; A first contact plug extending along the first direction to one side of the first gate structure; a second contact plug extending along the first direction to the other side of the second gate structure; as well as The dummy contact plug extends along the first direction between the first gate structure and the second gate structure.

9. The semiconductor device according to claim 8, further comprising: The source / drain region extends along the second direction on both sides of the first gate structure and the second gate structure. 10 . The semiconductor device as claimed in claim 9 , wherein the first contact plug is disposed on the source / drain region. 11 . The semiconductor device as claimed in claim 9 , wherein the second contact plug is disposed on the source / drain region. 12 . The semiconductor device as claimed in claim 8 , further comprising a metal interconnection connected to the first contact plug. 13 . The semiconductor device as claimed in claim 8 , further comprising a metal interconnection connected to the second contact plug.

14. The semiconductor device as claimed in claim 8, wherein the first contact plug comprises a metal silicide layer. 15 . The semiconductor device as claimed in claim 8 , wherein the second contact plug comprises a metal silicide layer. 16 . The semiconductor device as claimed in claim 8 , wherein the dummy contact plug comprises a metal silicide layer.

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