Hybrid pixel and hybrid sensor

Abstract

There is provided a hybrid pixel including a semiconductor substrate, a pixel circuit including at least one transfer transistor, a sensing circuit configured to detect movement of an object, and at least one photodiode having one end connected to the pixel circuit and the other end connected to the sensing circuit, the semiconductor substrate has a first conductivity type, the semiconductor substrate comprises a photoelectric conversion region corresponding to at least one photodiode, the photoelectric conversion region comprises a first region of a second conductivity type and a second region, and the second region is physically separated from a second region of an adjacent mixed pixel by a deep trench isolation region; and the semiconductor substrate includes a deep trench isolation region.

Description

Technical Field

[0001] The present inventive concept relates to a hybrid pixel and a hybrid sensor. More particularly, the present inventive concept relates to a hybrid pixel and a hybrid sensor capable of performing both image sensor functions and dynamic vision sensor functions. Background Art

[0002] Image sensors are semiconductor devices that convert incident light signals into electrical signals and generate image information corresponding to the incident light signals. With the recent development of the computer and communications industries, demand for image sensors has increased in various fields, such as digital cameras, video cameras, mobile phones, surveillance cameras, and medical cameras. While image sensors are capable of producing images with excellent image quality, they also consume a large amount of power.

[0003] A vision sensor (e.g., a dynamic vision sensor) generates information about an event (e.g., a change in light intensity) when it occurs, such as an event signal, and transmits the event signal to a processor. Vision sensors have low power consumption because the result is output only in pixels where a signal change has occurred, but only information about the event can be output.

[0004] Recently, attempts have been made to achieve fast frame rates with high image quality by combining images from an image sensor and images from a dynamic vision sensor. When part of the pixel area is used as a dynamic vision sensor, signal-to-noise ratio (SNR) deterioration may occur due to the reduction in the amount of light, and pixel design may become difficult. Summary of the Invention

[0005] The present inventive concept provides a hybrid sensor capable of using holes and electrons of a photodiode.

[0006] According to some aspects of the present inventive concept, a hybrid pixel is provided.

[0007] A hybrid pixel includes a semiconductor substrate, a pixel circuit including at least one transfer transistor, a sensing circuit configured to detect movement of an object, and at least one photodiode connected to the pixel circuit at one end and to the sensing circuit at the other end, the semiconductor substrate has a first conductivity type, the semiconductor substrate includes a photoelectric conversion region corresponding to the at least one photodiode, the photoelectric conversion region includes a first region of a second conductivity type and a second region surrounding the first region, the second region is physically separated from the second region of an adjacent hybrid pixel by a deep trench isolation region, and the semiconductor substrate includes a deep trench isolation region.

[0008] According to some aspects of the present inventive concept, a hybrid pixel is provided.

[0009] A hybrid pixel includes a semiconductor substrate, a pixel circuit including at least one transfer transistor, a sensing circuit configured to detect movement of an object, and at least one photodiode connected to the pixel circuit at one end and to the sensing circuit at the other end, the semiconductor substrate having a first conductivity type, the semiconductor substrate including a photoelectric conversion region corresponding to the at least one photodiode, the photoelectric conversion region including a first region of a second conductivity type and a second region, the second region being physically separated from the second region of an adjacent hybrid pixel by a deep trench isolation region, and the first layer including the pixel circuit and the at least one photodiode is different from the second layer including the sensing circuit.

[0010] According to some aspects of the present inventive concept, a hybrid sensor is provided.

[0011] The hybrid sensor includes a pixel array including a plurality of hybrid pixels, the plurality of hybrid pixels including a photodiode, a pixel circuit connected to one end of the photodiode, a sensing circuit connected to the other end of the photodiode, and a noise removal circuit connected between the sensing circuit and the other end of the photodiode, and each of the plurality of hybrid pixels is physically separated from adjacent hybrid pixels by a deep trench isolation region. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram of an image processing apparatus according to some example embodiments; Figure 2 is a block diagram of a hybrid sensor according to some example embodiments; Figure 3A 、 Figure 3B and Figure 3C is a diagram illustrating an implementation example of a pixel array corresponding to a color filter array according to some example embodiments; Figure 4A is a diagram for describing a circuit diagram of a hybrid pixel according to some example embodiments; Figure 4B Shown Figure 4A Some example embodiments of circuit diagrams of hybrid pixels; Figure 5A is with Figure 4B A cross-sectional view of the layout area corresponding to area A; Figure 5B is used to describe Figure 5A Diagram of charge flow in a cross-sectional view of ; Figure 6A is a diagram for describing a circuit diagram of a hybrid pixel according to some example embodiments; Figure 6B It shows Figure 6AA top view of the layout of some components of a hybrid pixel; Figure 6C It is along Figure 6B A cross-sectional view taken along line AA'; Figure 7 is a circuit diagram of a hybrid pixel according to some example embodiments; Figure 8 shows a stacked structure of a hybrid sensor according to some example embodiments; Figure 9 shows a stacked structure of a hybrid sensor according to some example embodiments; Figure 10A illustrates a stacked structure of components of a hybrid pixel included in a hybrid sensor according to some example embodiments; Figure 10B illustrates a stacked structure of components of a hybrid pixel included in a hybrid sensor according to some example embodiments; Figure 11 is a block diagram of the structure of a hybrid pixel according to some example embodiments; Figure 12 is a circuit diagram of a hybrid pixel according to some example embodiments; Figure 13 is used to describe Figure 12 A timing diagram showing a turn-on timing of a transistor included in a noise removal circuit; Figure 14 is a timing diagram for describing turn-on timing of transistors included in a noise removal circuit according to some example embodiments; and Figure 15 is a timing diagram for describing turn-on timing of transistors included in a noise removal circuit according to some example embodiments. DETAILED DESCRIPTION

[0013] Hereinafter, various embodiments will be described with reference to the accompanying drawings.

[0014] Figure 1 is a block diagram of an image processing apparatus 10 according to some example embodiments.

[0015] Reference Figure 1The image processing device 10 may include a hybrid sensor 100 and a processor 300. The image processing device 10 according to some example embodiments may be installed on an electronic device having an image or optical sensing function. For example, the image processing device 10 may be installed on an electronic device such as a camera, a smartphone, a wearable device, an Internet of Things (IoT) device, a tablet computer (PC), a personal digital assistant (PDA), a portable multimedia player (PMP), a navigation device, a drone, or an advanced driver assistance system (ADAS). Furthermore, the image processing device 10 may be included as a component in a vehicle, furniture, manufacturing equipment, a door, or any type of measurement device.

[0016] The hybrid sensor 100 can be a sensor capable of performing both visual sensor and image sensor functions. The visual sensor function can output an event signal by detecting changes in the intensity of incident light. The visual sensor function provided by the hybrid sensor 100 can be a dynamic visual sensor function that outputs an event signal for pixels where a change in light intensity has been detected (e.g., pixels where an event has occurred). Changes in light intensity can be caused by movement of an object captured by the hybrid sensor 100, or by movement of the hybrid sensor 100 or the image processing device 10 itself. The hybrid sensor 100 can periodically or irregularly transmit multiple pieces of visual sensor data VDT, including event signals, to the processor 300.

[0017] An image sensor functions by converting light signals from an object incident through an optical lens into electrical signals, generating image data (IDT) based on the electrical signals, and outputting the image data (IDT). The hybrid sensor 100 may include, for example, a readout circuit and a pixel array. The pixel array comprises a plurality of pixels arranged two-dimensionally, and the pixel array converts the received light signals into electrical signals. The pixel array may be implemented using photoelectric conversion elements (e.g., a charge-coupled device (CCD) or a complementary metal-oxide semiconductor (CMOS)), or any other type of photoelectric conversion element. The readout circuit generates raw data based on the electrical signals provided by the pixel array, and outputs the raw data, or the raw data after pre-processing such as bad pixel removal, as image data (IDT). The hybrid sensor 100 may be implemented using a semiconductor chip or package that includes the pixel array and readout circuit.

[0018] According to the present inventive concept, the hybrid sensor 100 can perform both image sensor functions and visual sensor functions based on multiple pieces of information (e.g., electrons and holes) obtained from at least one photodiode included in the hybrid pixel. A hybrid pixel included in the pixel array included in the hybrid sensor 100 may include at least one photodiode, a pixel circuit connected to one end of the photodiode, and a sensing circuit connected to the other end of the photodiode.

[0019] The processor 300 may perform image processing on the image data IDT provided by the hybrid sensor 100. For example, the processor 300 may perform image processing to change the data format of the image data IDT (e.g., changing the image data of a Bayer pattern to a YUV or RGB format), image processing to improve image quality, such as noise removal, brightness adjustment, or sharpness adjustment, and / or similar processing. The processor 300 may process the visual sensor data VDT received from the hybrid sensor 100 and detect the movement of an object (or the movement of an object in an image recognized by the image processing device 10) based on an event signal in the visual sensor data VDT.

[0020] Furthermore, the processor 300 may match the image frame included in the image data IDT provided from the hybrid sensor 100 with the visual sensor data VDT received from the hybrid sensor 100 based on the timestamp and the plurality of synchronization signal information. The processor 300 may include an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a dedicated microprocessor, a microprocessor, or a general-purpose processor. According to some example embodiments, the processor 300 may be an application processor or an image signal processor.

[0021] The hybrid sensor 100 and the processor 300 may each be implemented as an integrated circuit (IC). For example, the hybrid sensor 100 and the processor 300 may be implemented as separate semiconductor chips. Alternatively, the hybrid sensor 100 and the processor 300 may be implemented as a single chip. For example, the hybrid sensor 100 and the processor 300 may be implemented as a system on a chip (SoC).

[0022] The image processing apparatus 10 may control the external device 400 and collect data. The device 400 may include an acceleration sensor, an inertial measurement unit (IMU), a gyro sensor, an infrared (IR) photodiode (LED), and a flash light.

[0023] An accelerometer is a sensor configured to measure the acceleration of a moving object or the intensity of an impact. It can measure dynamic forces on an object, such as acceleration, vibration, or impact, by processing the output signal. A gyroscope is a sensor that uses the dynamic motion of a rotating object to measure position and orientation. IR LEDs are used to capture images in the absence of light and are used in closed-circuit television (CCTV) and similar devices.

[0024] IMUs use a combination of accelerometers, gyroscopes, and sometimes magnetometers, and have recently been used as orientation sensors in many consumer products, such as mobile phones and cameras. IMUs operate by detecting linear acceleration using one or more accelerometers and rotational velocity using one or more gyroscopes, and in some cases may also include a magnetometer. In a typical configuration, an IMU may include one accelerometer, one gyroscope, and one magnetometer for each of the three axes of pitch, roll, and yaw.

[0025] Figure 2 is a block diagram of a hybrid sensor 100 according to some example embodiments.

[0026] The hybrid sensor 100 may include a pixel array 110 , a row driver 120 , a readout circuit 130 , a ramp signal generator 140 , a timing controller 150 , an event detection circuit 160 , and an interface circuit 170 , and the readout circuit 130 may include an analog-to-digital conversion (ADC) circuit 131 and a data bus 132 .

[0027] The pixel array 110 includes a plurality of row lines RL, a plurality of column lines CL, and a plurality of pixels PX, which access the plurality of row lines RL and the plurality of column lines CL and are arranged in a matrix. The plurality of pixels PX may be hybrid pixels. According to some example embodiments, each of the plurality of pixels PX may include a pixel circuit configured to output an image signal and a sensing circuit configured to sense whether an event has occurred. According to some example embodiments, the sensing circuit may detect the motion of an object by detecting the motion as an event. The pixel circuit and the sensing circuit included in each of the plurality of pixels PX may share a photodiode included in each of the plurality of pixels PX. According to some example embodiments, the pixel circuit may operate based on the electrons of the photodiode, and the sensing circuit may operate based on the holes of the photodiode. The following will refer to Figure 4A A structure corresponding to a plurality of pixels PX is described.

[0028] Each pixel PX may include at least one photoelectric conversion element. The pixel PX may detect light using the photoelectric conversion element and output an image signal as an electrical signal based on the detected light. For example, the photoelectric conversion element may be a light detection element including an organic or inorganic material, such as an inorganic photodiode, an organic photodiode, a perovskite photodiode, a photodiode, a grating, and / or a pinned photodiode. According to some example embodiments, each pixel PX may include multiple photoelectric conversion elements.

[0029] A microlens (not shown) for focusing light may be arranged above each pixel PX or above each pixel group including adjacent pixels PX. Each of the plurality of pixels PX may detect light in a specific spectral domain from the light received through the microlens arranged thereover. For example, the pixel array 110 may include red (R) pixels that convert light in a red spectral domain into electrical signals, green (G) pixels that convert light in a green spectral domain into electrical signals, blue (B) pixels that convert light in a blue spectral domain into electrical signals, and white (W) pixels for noise adjustment. A color filter array CF for transmitting light in a specific spectral domain may be arranged above each of the plurality of pixels PX. This will be described below with reference to Figures 3A to 3C However, some example embodiments are not limited thereto, and the pixel array 110 may include pixels that convert light in spectral domains other than red, green, and blue into electrical signals. According to some example embodiments, the pixels PX included in the pixel array 110 may be RGBW pixels.

[0030] Charge generated by a photoelectric conversion element (e.g., a photodiode) in each pixel PX can be accumulated in a floating diffusion node, and the accumulated charge in the floating diffusion node can be converted into a voltage. The ratio at which the charge accumulated in the floating diffusion node is converted into a voltage can be referred to as a conversion gain. The conversion gain can vary depending on the capacitance of the floating diffusion node.

[0031] The row driver 120 can drive the pixel array 110 in units of row lines RL. The row driver 120 can select at least one row line RL from the row lines RL configuring the pixel array 110. For example, the row driver 120 can generate a selection signal that selects one row line from the plurality of row lines RL. The pixel array 110 can output a pixel signal from the row line RL selected by the selection signal. The pixel signal can include a reset signal and an image signal.

[0032] The row driver 120 may generate control signals for controlling the pixel array 110. For example, the row driver 120 may generate control signals for controlling transistors included in the sensing circuit and the pixel circuit included in the pixel PX. The row driver 120 may independently (e.g., independently or without direction or interference from another element / feature) provide control signals for controlling the sensing circuit included in the pixel PX and the transistors included in the pixel circuit. The row driver 120 may provide control signals to the plurality of pixels PX in response to timing control signals provided by the timing controller 150.

[0033] The timing controller 150 can control the timing of the row driver 120, the readout circuit 130, and the ramp signal generator 140. The timing controller 150 can provide control signals for controlling the operation timing of the row driver 120, the readout circuit 130, and the ramp signal generator 140, respectively. The timing controller 150 can adjust the timing of the multiple control line signals generated by the row driver 120 to determine the activation and deactivation timing of the signals applied to the control lines. A detailed timing control method of the timing controller 150 will be described below.

[0034] The ramp signal generator 140 may generate a ramp signal RAMP that increases or decreases with a specific slope and provide the ramp signal RAMP to the ADC circuit 131 of the readout circuit 130 .

[0035] The readout circuit 130 can read out pixel signals of the pixels PX of the row line RL selected by the row driver 120 from among the plurality of pixels PX. The readout circuit 130 can convert the pixel signals received from the pixel array 110 through the plurality of column lines CL into digital data based on the ramp signal RAMP provided from the ramp signal generator 140, and generate and output pixel values ​​corresponding to the plurality of pixels PX in units of rows.

[0036] The ADC circuit 131 compares each pixel signal received via the column line CL with the ramp signal RAMP and generates a pixel value as a digital signal based on the comparison result. For example, the reset signal can be removed from the image signal to generate a pixel value indicating the amount of light detected in the pixel PX. The ADC circuit 131 can sample and hold the pixel signal using the correlated double sampling (CDS) method, sampling both the level of specific noise (e.g., the reset signal) and the level of the image signal, generating a comparison signal based on the level corresponding to the difference between them. The ADC circuit 131 can first read out the image signal and then sample the pixel signal provided by the readout reset signal using the delta reset sampling (DRS) method.

[0037] The plurality of pixel values ​​generated by the ADC circuit 131 may be output as image data IDT through the data bus 132. The image data IDT may be provided to an image signal processor inside or outside the hybrid sensor 100.

[0038] The data bus 132 can temporarily store the pixel values ​​output from the ADC circuit 131 and then output the pixel values. The data bus 132 can include multiple column memories and a column decoder. Under the control of the column decoder, the multiple pixel values ​​stored in the multiple column memories can be output as image data IDT.

[0039] According to some example embodiments, each of the plurality of pixels PX may detect an event in which the intensity of received light increases or decreases. For example, each of the plurality of pixels PX may be connected to the event detection circuit 160 via a column line extending in the column direction and a row line extending in the row direction. A signal indicating that an event has occurred and polarity information of the event (e.g., whether the event is a turn-on event in which light intensity increases or a turn-off event in which light intensity decreases) may be output from the pixel PX in which the event occurred to the event detection circuit 160. In the present inventive concept, the signal output from the pixel PX to the event detection circuit 160 is referred to as an event detection signal.

[0040] Event detection circuit 160 can read events from pixel array 110 and process these events. Event detection circuit 160 can generate event data EDT including polarity information of the event, the address of the pixel where the event occurred, and a timestamp. Event detection circuit 160 can process events occurring in pixel array 110 on a pixel basis, on a pixel group basis including a plurality of pixels, on a column basis, or on a frame basis.

[0041] The interface circuit 170 can receive the event data EDT and the timestamp and send the visual sensor data VDT to the processor 300 according to the set protocol. The interface circuit 170 can package the event data EDT and the timestamp in a single signal unit, a packet unit, or a frame unit according to the set protocol to generate the visual sensor data VDT and transmit the visual sensor data VDT to the processor 300 (see Figure 1 For example, the interface circuit 170 may include at least one of an Address Event Representation (AER) interface, a Mobile Industry Processor Interface (MIPI), and / or a parallel interface.

[0042] According to the present invention, image signals and event detection signals can be output simultaneously (e.g., at the same or approximately the same time) from pixels PX included in pixel array 110. In other words, according to the present invention, pixels PX included in pixel array 110 can be hybrid pixels capable of outputting both image signals and event detection signals. Therefore, desired image data can be combined, and data availability can be improved.

[0043] Figure 3A 、 Figure 3B and Figure 3C is a diagram illustrating an implementation example of a pixel array corresponding to a color filter array according to some example embodiments.

[0044] Reference Figure 3A, the pixel array 110a includes a plurality of pixels arranged in multiple rows and columns, and for example, a shared pixel defined in a unit including pixels arranged in two rows and two columns may include four sub-pixels. The pixel array 110a may include a first shared pixel SP0 to a sixteenth shared pixel SP15. The pixel array 110a may also include a color filter array CF for the first shared pixels SP0 to the sixteenth shared pixels SP15 to sense various colors. For example, the color filter array CF includes color filters for sensing red (R), green (G), and blue (B), and each of the first shared pixels SP0 to the sixteenth shared pixels SP15 may include sub-pixels arranged with the same color filters. For example, the first shared pixel SP0, the third shared pixel SP2, the ninth shared pixel SP8 and the eleventh shared pixel SP10 may include sub-pixels including a blue color filter, the second shared pixel SP1, the fourth shared pixel SP3, the fifth shared pixel SP4, the seventh shared pixel SP6, the tenth shared pixel SP9, the twelfth shared pixel SP11, the thirteenth shared pixel SP12 and the fifteenth shared pixel SP14 may include sub-pixels including a green color filter, and the sixth shared pixel SP5, the eighth shared pixel SP7, the fourteenth shared pixel SP13 and the sixteenth shared pixel SP15 may include sub-pixels including a red color filter. In addition, a group including a first shared pixel SP0, a second shared pixel SP1, a fifth shared pixel SP4 and a sixth shared pixel SP5, a group including a third shared pixel SP2, a fourth shared pixel SP3, a seventh shared pixel SP6 and an eighth shared pixel SP7, a group including a ninth shared pixel SP8, a tenth shared pixel SP9, a thirteenth shared pixel SP12 and a fourteenth shared pixel SP13, and a group including an eleventh shared pixel SP10, a twelfth shared pixel SP11, a fifteenth shared pixel SP14 and a sixteenth shared pixel SP15 can each be arranged in the pixel array 110a to correspond to a Bayer pattern. According to some example embodiments, a group including the first shared pixel SP0, the second shared pixel SP1, the fifth shared pixel SP4 and the sixth shared pixel SP5, a group including the third shared pixel SP2, the fourth shared pixel SP3, the seventh shared pixel SP6 and the eighth shared pixel SP7, a group including the ninth shared pixel SP8, the tenth shared pixel SP9, the thirteenth shared pixel SP12 and the fourteenth shared pixel SP13, and a group including the eleventh shared pixel SP10, the twelfth shared pixel SP11, the fifteenth shared pixel SP14 and the sixteenth shared pixel SP15 may each correspond to a block of the color filter array CF.

[0045] However, this is merely an example, and the pixel array 110a according to some example embodiments may include various types of color filters. For example, the color filter array CF may include color filters that sense not only red, green, and blue, but also yellow, cyan, magenta, and white. In addition, the pixel array 110a may include more shared pixels, and the arrangement of the first shared pixel SP0 to the sixteenth shared pixel SP15 may vary.

[0046] Reference Figure 3B In the pixel array 110b, each of the first shared pixel SP0, the second shared pixel SP1, the fifth shared pixel SP4, and the sixth shared pixel SP5 may include nine sub-pixels. The first shared pixel SP0 may include nine sub-pixels including a blue (B) color filter, and the second shared pixel SP1 and the fifth shared pixel SP4 may each include nine sub-pixels including a green (G) color filter. The sixth shared pixel SP5 may include nine sub-pixels including a red (R) color filter. According to some embodiments, the first shared pixel SP0, the second shared pixel SP1, the fifth shared pixel SP4, and the sixth shared pixel SP5 may be referred to as a nine-in-one (nona) unit.

[0047] Reference Figure 3C In the pixel array 110c, each of the first shared pixel SP0, the second shared pixel SP1, the fifth shared pixel SP4, and the sixth shared pixel SP5 may include sixteen sub-pixels. The first shared pixel SP0 may include sixteen sub-pixels including a blue (B) color filter, and the second shared pixel SP1 and the fifth shared pixel SP4 may each include sixteen sub-pixels including a green (G) filter. The sixth shared pixel SP5 may include sixteen sub-pixels including a red (R) color filter. According to some embodiments, the first shared pixel SP0, the second shared pixel SP1, the fifth shared pixel SP4, and the sixth shared pixel SP5 may be referred to as a hexadeca unit.

[0048] The shared pixel may include sub-pixels that are adjacent to each other while including the same color filter. Figures 3A to 3C The shared pixel is shown as an example including sub-pixels having an N*N arrangement, but the arrangement of sub-pixels included in the shared pixel is not limited to N*N. N may be a natural number equal to or greater than 2.

[0049] Figure 4A is a diagram for describing a circuit diagram of a hybrid pixel PXa according to some example embodiments.

[0050] Reference Figure 4A, the hybrid pixel PXa may include a photodiode 3000, a pixel circuit 1000 connected to one end of the photodiode 3000, and a sensing circuit 2000 connected to the other end of the photodiode 3000. According to some example embodiments, a cathode of the photodiode 3000 may be connected to the pixel circuit 1000, and an anode of the photodiode 3000 may be connected to the sensing circuit 2000.

[0051] The pixel circuit 1000 can generate a pixel signal of voltage based on the amount of charge generated in the photodiode 3000. The sensing circuit 2000 can generate an event detection signal by detecting whether the change in the amount of charge generated in the photodiode 3000 has exceeded a specific threshold. The pixel circuit 1000 included in the hybrid pixel PXa according to the present inventive concept can generate a pixel signal based on electrons generated in the photodiode 3000, and the sensing circuit 2000 can generate an event detection signal based on holes generated in the photodiode 3000. Therefore, the pixel circuit 1000 can use an electron-based current, while the sensing circuit 2000 can use a hole-based current. In this case, even when electrons accumulate in the photodiode 3000, the hole-based current can continue to flow. Therefore, the pixel circuit 1000 can maintain 4T operation, operate as a circuit separate from the sensing circuit 2000, and have various shared structures. In some example embodiments, the pixel signal generated from electrons may have less noise than when the pixel signal is generated from holes, and thus the signal quality of the pixel signal can be improved. In some example embodiments, the sensing circuit 2000 uses a hole current, and thus, the hybrid pixel PXa may be implemented to have improved performance and reliability in terms of light loss or pixel operation.

[0052] Figure 4B Shown Figure 4A Some example embodiments of circuit diagrams of hybrid pixels PXa.

[0053] Reference Figure 4B , the hybrid pixel PXa may include a photodiode 3000a, a pixel circuit 1000a, and a sensing circuit 2000a. The pixel circuit 1000a may include a transfer transistor TX, a reset transistor RX, a drive transistor DX, and a selection transistor SX. The description of the operation method of the pixel circuit 1000a is omitted. Figure 4B, one end of the transfer transistor TX included in the pixel circuit 1000a can be connected to the cathode of the photodiode 3000a. The sensing circuit 2000a may include a transimpedance amplifier (TIA). According to some example embodiments, the transimpedance amplifier (TIA) may amplify a current value corresponding to holes output from the anode of the photodiode 3000a and output the current value (or an approximate current value) as a voltage. Although omitted in the present inventive concept for ease of description, the sensing circuit 2000a may also include a comparator configured to compare the amplified hole current value with a reference value. According to some example embodiments, the sensing circuit 2000a may be a circuit corresponding to a dynamic vision sensor configured to output an event detection signal. The description of the operating method of the sensing circuit 2000a will be omitted.

[0054] Figure 4B The circuit structures of the pixel circuit 1000a and the sensing circuit 2000a are merely examples, and the pixel circuit 1000a and the sensing circuit 2000a may each be modified in various ways within the scope of a circuit structure capable of performing a readout of a pixel signal and a circuit structure capable of comparing a charge change amount with a threshold value and outputting an event detection signal. For example, according to some example embodiments, based on the above-described method, the speed, accuracy, and / or power efficiency of an image processing device may be improved. Thus, the improved device and method overcome the shortcomings of conventional devices and methods while reducing resource consumption and improving data accuracy and resource allocation (e.g., latency).

[0055] According to some example embodiments, the pixel circuit 1000a and the sensing circuit 2000a included in the hybrid pixel PXa may share a photodiode 3000a. Therefore, the functions of an image sensor and a dynamic vision sensor may be performed based on at least one photodiode 3000a included in one hybrid pixel PXa.

[0056] Figure 5A is with Figure 4B The A area corresponds to the cross-sectional view of the layout area. Figure 5A The hybrid pixel PXa may include a semiconductor substrate 2110 , a photoelectric conversion region 2120 , a vertical transfer gate VTG, a microlens 2130 , a color filter 2140 , deep trench isolation (DTI) regions 2150 and 2160 , and a contact region 2180 .

[0057] The semiconductor substrate 2110 may include a first surface SUF1 and a second surface SUF2 facing the first surface SUF1. Impurities of a first conductivity type (e.g., p-type) (e.g., boron (B)) may be implanted into the semiconductor substrate 2110, and impurities of a second conductivity type (e.g., n-type) opposite to the first conductivity type (e.g., phosphorus (p) or arsenic (As)) may be implanted into the floating diffusion region. Although not shown, a p-type epitaxial layer may be grown or a separate well region may be formed over the semiconductor substrate 2110 to form the photoelectric conversion region 2120 and the vertical transfer gate VTG on the p-type epitaxial film and / or well region.

[0058] The photoelectric conversion region 2120 may be formed inside the semiconductor substrate 2110, and incident light may reach the photoelectric conversion region 2120 through the second surface SUF2 of the semiconductor substrate 2110. The photoelectric conversion region 2120 may be a region corresponding to the photodiode 3000. The photoelectric conversion region 2120 may generate charges (e.g., photocharges or holes) in the PN junction region according to photoelectric conversion based on the incident light. The number of generated electrons may increase as the brightness increases. The number of generated holes may be the same as the number of electrons. According to some example embodiments, the photoelectric conversion region 2120 may be a region formed when the second conductive type (e.g., n-type) is injected. The area and shape of the photoelectric conversion region 2120 are not limited to Figure 5A Those shown.

[0059] Reference Figure 5A , the semiconductor substrate 2110 may include a first region 2120a and a second region 2120b. According to some example embodiments, the first region 2120a may be a region corresponding to the photoelectric conversion region 2120. According to some example embodiments, the second region 2120b may be a region surrounding the first region 2120a in the semiconductor substrate 2110. According to some example embodiments, the second region 2120b may be a remaining region obtained by excluding the region of the photoelectric conversion region 2120 from the semiconductor substrate 2110. According to some example embodiments, the second region 2120b may be a region in the semiconductor substrate 2110 where holes may transfer between regions where holes are accumulated.

[0060] According to some example embodiments, a contact region 2180 may be formed on the first surface SUF1 of the semiconductor substrate 2110. According to some example embodiments, the contact region 2180 may be formed in the semiconductor substrate 2110 and provide a transfer path for holes formed in the second region 2120b. According to some example embodiments, the holes formed in the second region 2120b may be transferred to the sensing circuit 2000a along the contact region 2180.

[0061] The vertical transfer gate VTG may be formed on the first surface SUF1 of the semiconductor substrate 2110. A portion of the vertical transfer gate VTG may extend from the first surface SUF1 of the semiconductor substrate 2110 into the semiconductor substrate 2110 toward the photoelectric conversion region 2120. The vertical transfer gate VTG may allow electrons generated in the first region 2120a of the photoelectric conversion region 2120 to be transferred to the floating diffusion region.

[0062] According to the inventive concept, electrons generated in the first region 2120 a may be transferred to the pixel circuit 1000 a through the vertical transfer gate VTG, and holes generated in the second region 2120 b may be transferred to the sensing circuit 2000 a through the contact region 2180 .

[0063] The hybrid pixel PXa may include DTI regions 2150 and 2160. According to some example embodiments, the DTI regions 2150 and 2160 may extend from the first surface SUF1 of the semiconductor substrate 2110 to a depth spaced apart from the first surface SUF1, or may completely (e.g., completely) penetrate the semiconductor substrate 2110 from the first surface SUF1 to the second surface SUF2 of the semiconductor substrate 2110. The DTI regions 2150 and 2160 may contact the first surface SUF1 and / or the second surface SUF2 of the semiconductor substrate 2110. According to some example embodiments, the surfaces of the DTI regions 2150 and 2160 contacting the semiconductor substrate 2110 may not be parallel to each other. According to some example embodiments, the DTI regions 2150 and 2160 may form isolation regions by contacting shallow trench isolation (STI) regions formed in the first surface SUF1 or the second surface SUF2. According to some example embodiments, the DTI regions 2150 and 2160 may be isolation regions formed by front DTI (FDTI). The DTI regions 2150 and 2160 may include an insulating layer and / or a conductive layer. For example, the DTI regions 2150 and 2160 may include a silicon oxide layer formed along the inner wall of the trench and a silicon layer filling the remaining portion of the trench. According to some example embodiments, the thickness of the DTI regions 2150 and 2160 may be non-uniform.

[0064] According to the present invention, DTI regions 2150 and 2160 can be formed to isolate the first region 2120a and the second region 2120b included in a hybrid pixel PXa from the first region and the second region included in an adjacent hybrid pixel PXa. According to the present invention, the first region 2120a and the second region 2120b are formed within the semiconductor substrate 2110, and the contact region 2180 is formed above the semiconductor substrate 2110. To ensure a complete hole transport path, the second region 2120b and its corresponding contact region 2180 need to be completely (e.g., completely) isolated from the contact regions arranged in adjacent pixels. Therefore, DTI regions 2150 and 2160 can be formed on both sides of the first region 2120a and the second region 2120b to configure a single pixel of the sensing circuit 2000a (e.g., other sides not shown). According to the present invention, the sensing circuit 2000a can be configured by using the hole current classified by the DTI regions 2150 and 2160 for each hybrid pixel.

[0065] The hybrid pixel PXa may further include a color filter array CF and a microlens 2130 located on the second surface SUF2 of the semiconductor substrate 2110. In some example embodiments, the order of the color filter array CF and the microlens 2130 may be different. According to some example embodiments, a nanostructure may be located on the second surface SUF2 of the semiconductor substrate 2110 instead of the color filter array CF and / or the microlens 2130, and may isolate and / or guide light according to wavelength.

[0066] Figure 5B is used to describe Figure 5A Diagram of the charge flow in a cross-sectional view. Figure 5B 2120 is a diagram for describing the flow of charges from the first region 2120 a and the second region 2120 b included in the photoelectric conversion region 2120 .

[0067] Reference Figure 5B , light L transmitted through the microlens 2130 can be transmitted to the photoelectric conversion region 2120. When a voltage is applied to the vertical transfer gate VTG, electrons e- formed in the first region 2120a by the light L can flow toward the vertical transfer gate VTC and be transferred to the floating diffusion region of the pixel circuit 1000a. Holes h+ formed in the second region 2120b by the light L can be transferred through the contact region 2180, and the hole current transferred through the contact region 2180 can be transferred to the sensing circuit 2000a.

[0068] According to some example embodiments, electrons may be used to generate pixel signals, and holes may be used to detect events. Compared to the case of using only electrons according to the comparative example, the level of the pixel signal may be increased at the same or similar brightness, thereby improving the accuracy of detecting events and improving image quality in dark places with low brightness.

[0069] Figure 6A is a diagram for describing a circuit diagram of a hybrid pixel PXb according to some example embodiments.

[0070] Reference Figure 6A The hybrid pixel PXb may include a pixel circuit 1000b, a sensing circuit 2000b, and a plurality of photodiodes 3000b. The pixel circuit 1000b according to some example embodiments may include a first transfer transistor TX1, a second transfer transistor TX2, a third transfer transistor TX3, and a fourth transfer transistor TX4, a first floating diffusion node FD1, a source follower transistor SF1, a first select transistor SX1, and first and second reset transistors RX1 and RX2. First, second, third, and fourth control signals TG1, TG2, TG3, and TG4 for driving the first, second, third, and fourth transfer transistors TX1, TX2, TX3, and TX4 may be applied to the gates of the first, second, third, and fourth transfer transistors TX1, TX2, TX3, and TX4, respectively, and first and second reset signals RS1 and RS2 may be applied to the gates of the first and second reset transistors RX1 and RX2, respectively. The operation method of the pixel circuit 1000b may be similar to the operation method of the pixel circuit 1000, and thus, a description thereof is omitted.

[0071] Reference Figure 6A , the plurality of photodiodes 3000b may include a first photodiode PD1, a second photodiode PD2, a third photodiode PD3, and a fourth photodiode PD4. Charge corresponding to light incident on the hybrid pixel PXb through the first photodiode PD1, the second photodiode PD2, the third photodiode PD3, and the fourth photodiode PD4 may be accumulated. The amount of charge accumulated in the first photodiode PD1, the second photodiode PD2, the third photodiode PD3, and the fourth photodiode PD4 may be referred to as light amount data.

[0072] The pixel circuit 1000b may be connected to the cathodes of the first photodiode PD1, the second photodiode PD2, the third photodiode PD3, and the fourth photodiode PD4. The sensing circuit 2000b may be connected to the anodes of the first photodiode PD1, the second photodiode PD2, the third photodiode PD3, and the fourth photodiode PD4. According to some example embodiments, the pixel circuit 1000b and the sensing circuit 2000b may share the first photodiode PD1, the second photodiode PD2, the third photodiode PD3, and the fourth photodiode PD4. Figure 6A In some example embodiments, the pixel circuit 1000b and the sensing circuit 2000b share four photodiodes, but the present inventive concept is not limited thereto, and the pixel circuit 1000b and the sensing circuit 2000b may share N photodiodes. N may be a natural number equal to or greater than 2. According to some example embodiments, the number of transfer transistors included in the pixel circuit 1000b and the number of photodiodes 3000b connected to the pixel circuit 1000a may be the same. Figure 6A , the number of transfer transistors included in the pixel circuit 1000 b may be four, and the number of photodiodes 3000 b connected to the pixel circuit 1000 a may be four.

[0073] Figure 6B It shows Figure 6A A top view of the layout of some components of the hybrid pixel PXb. Figure 6C It is along Figure 6B A cross-sectional view taken along line AA'.

[0074] Reference Figure 6B , Figure 6A The four photodiodes included in the CMOS (eg, the first photodiode PD1 , the second photodiode PD2 , the third photodiode PD3 , and the fourth photodiode PD4 ) may be disposed in a 2×2 pixel structure based on central symmetry.

[0075] Figure 6B The hybrid pixel PXb may include a semiconductor substrate 510 , a plurality of photoelectric conversion regions 520 , a floating diffusion region 530 , four vertical transfer gates 540 , a DTI region 560 , a transistor 590 , and a contact region 591 . Figure 6B The hybrid pixel PXb may have a 4PD structure in which the semiconductor substrate 510 is shared since the central portion of the DTI region 560 is partially deleted.

[0076] according to Figure 6BIn some example embodiments, the plurality of photoelectric conversion regions 520 may include first regions 520a, 520b, 520c, and 520d. According to some example embodiments, the first regions 520a, 520b, 520c, and 520d may be regions doped with a second conductive type (eg, n-type). Figure 6B , the number of the first regions 520a, 520b, 520c, and 520d may correspond to the number of photodiodes shared by the pixel circuit 1000b. Figure 6B , four photodiodes are shared by the pixel circuit 1000b, and therefore, the number of the first regions 520a, 520b, 520c, and 520d may be four. Figure 6B In some example embodiments, the semiconductor substrate 510 may include a second region 520e surrounding the first regions 520a, 520b, 520c, and 520d. According to some example embodiments, the second region 520e surrounding the plurality of first regions 520a, 520b, 520c, and 520d is shown. In addition, a contact region 591 may be formed over the semiconductor substrate 510. According to some example embodiments, one contact region 591 may correspond to one second region 520e. In other words, the number of second regions 520e and the number of contact regions 591 may be the same. Figure 6B , the plurality of first regions 520a, 520b, 520c, and 520d share the second region 520e and the contact region 591. Therefore, the number of contact regions 591 and the number of second regions 520 may be equal to or less than the number of first regions 520a, 520b, 520c, and 520d. The position where the contact region 591 is arranged may vary within a range where it contacts the second region 520e over the semiconductor substrate 510.

[0077] Reference Figure 6C , the hybrid pixel PXb includes a semiconductor substrate 510, first regions 520c and 520d, a second region 520e, a contact region 591, a vertical transfer gate 540, a color filter 2140, a microlens 2130, and a DTI region 560. Details regarding the semiconductor substrate 510, the vertical transfer gate 540, the color filter 2140, and the microlens 2130 correspond to those in reference Figure 5A Details about the respective components are described, and thus redundant descriptions will be omitted.

[0078] Reference Figure 6C , the second region 520e is formed in a range surrounding the first regions 520c and 520d, and the contact region 591 is formed in the second region 520e, and therefore, holes generated in the second region 520e can be transferred to the sensing circuit. According to some example embodiments, the first regions 520c and 520d may share the second region 520e.

[0079] According to the present inventive concept, in a hybrid pixel sharing 4PDs, one second region 520e may be formed to surround the four first regions 520a, 520b, 520c, and 520d, and thus, the second region 520e may be shared. According to some example embodiments, it should be noted that in a hybrid pixel sharing 4PDs, the four first regions 520a, 520b, 520c, and 520d are regarded as one pixel, and thus, a DTI region 560 may be formed for distinguishing from adjacent hybrid pixels.

[0080] and Figure 5A In contrast, when the first region 2120a and the second region 2120b included in the photoelectric conversion region 2120 are Figure 5A When the DTI regions 2150 and 2160 correspond to each other in a 1:1 manner, the photoelectric conversion region 2120 can be isolated from the adjacent photoelectric conversion regions. Figure 6C In the embodiment, when the first regions 520a, 520b, 520c, and 520d included in the photoelectric conversion region 520 do not correspond 1:1 with the second region 520e, the plurality of first regions 520a, 520b, 520c, and 520d may share the second region 520e. In this case, the DTI region 560 may be formed to isolate the second region 520e from adjacent second regions. In other words, it should be noted that the DTI region may be formed to completely (e.g., completely) isolate the second region of the photoelectric conversion region having the same conductivity type as the substrate from the second region of the adjacent photoelectric conversion region.

[0081] Figure 7 is a circuit diagram of a hybrid pixel PXc according to some example embodiments.

[0082] Reference Figure 7 , the hybrid pixel PXc may include a photodiode 3000c, a pixel circuit 1000c connected to one end of the photodiode 3000c, and a sensing circuit 2000c connected to the other end of the photodiode 3000c. According to some example embodiments, an anode of the photodiode 3000c may be connected to the pixel circuit 1000c, and a cathode of the photodiode 3000 may be connected to the sensing circuit 2000c.

[0083] The pixel circuit 1000c can generate a pixel signal of voltage based on the amount of charge generated in the photodiode 3000c. The sensing circuit 2000c can generate an event detection signal by detecting whether the change in the amount of charge generated in the photodiode 3000c has exceeded a specific threshold. The pixel circuit 1000c included in the hybrid pixel PXc according to the present invention can generate a pixel signal based on the holes generated in the photodiode 3000c, and the sensing circuit 2000c can generate an event detection signal based on the electrons generated in the photodiode 3000c. Therefore, the pixel circuit 1000c can use a current based on holes, and the sensing circuit 2000c can use a current based on electrons. In this case, the pixel circuit 1000c can also operate as a circuit separated from the sensing circuit 2000c.

[0084] It should be noted that Figure 7 , the inventive concepts of some example embodiments applied to a pixel circuit using electrons and a sensing circuit using holes may also be applied to a pixel circuit using holes and a sensing circuit using electrons.

[0085] Figure 8 A stacked structure of a hybrid sensor 1 according to some example embodiments is shown.

[0086] Reference Figure 8 The hybrid sensor 1 may include an upper chip 40 and a lower chip 50. The upper chip 40 may include a sensing area SA in which circuits for a plurality of pixels PX are provided, and a pad area PA1 surrounding the sensing area SA. A plurality of upper pads PAD are arranged in the pad area PA1, and the plurality of upper pads PAD may be connected to elements provided in the lower chip 50 through vias and / or the like.

[0087] The lower chip 50 includes a circuit region LC, and peripheral circuits of the pixel array (e.g., a row driver 120, a readout circuit 130, a ramp signal generator 140, a timing controller 150, and an event detection circuit 160) may be formed in the circuit region LC. The lower chip 50 includes a pad region PA2 surrounding the circuit region LC. According to some example embodiments, sensing circuits included in the plurality of pixels PX may be formed in the circuit region LC. This will be referred to below. Figure 10A and Figure 10B According to some example embodiments, the lower chip 50 may include a storage area and a dummy area. Storage elements (e.g., dynamic random access memory (DRAM) elements or static random access memory (SRAM) elements) may be arranged in the storage area. However, the storage elements arranged in the storage area are not limited to DRAM elements or SRAM elements. The dummy area may perform functions such as supporting the upper chip 40 and dissipating heat, rather than storing data.

[0088] Figure 9 A stacked structure of a hybrid sensor according to some example embodiments is shown.

[0089] Reference Figure 9 , the hybrid sensor 2 may include multiple stacked chips. For example, the pixel array may be formed in the upper chip 40 and the middle chip 51, and the peripheral circuit or memory of the pixel array may be formed in the lower chip 60. According to some example embodiments, a plurality of photodiodes, pixel circuits, and wires corresponding to the pixel circuits included in the hybrid pixel may be formed in the upper chip 40, and the sensing circuit and wires corresponding to the sensing circuit may be formed in the middle chip 51.

[0090] The lower chip 60 may include a circuit region LC, and a peripheral circuit of the pixel array may be formed in the circuit region LC. According to some example embodiments, the lower chip 60 may include a storage region and a dummy region.

[0091] According to some example embodiments, the upper chip 40 and the middle chip 51 may be stacked on each other at a wafer level, and the lower chip 60 may be attached below the middle chip 51 at a chip level.

[0092] Figure 10A A stacked structure of components of a hybrid pixel included in a hybrid sensor according to some example embodiments is illustrated.

[0093] For ease of description, some example embodiments are shown in which a wiring structure of the first photodiode PD1 , the second photodiode PD2 , the third photodiode PD3 , and the fourth photodiode PD4 , a pixel circuit, and a sensing circuit included in one hybrid pixel 11 is applied to a stack structure.

[0094] Reference Figure 10A , the hybrid pixel 11 may include an upper chip 41 and a lower chip 42. The upper chip 41 may include a first region 41a in which a first photodiode PD1, a second photodiode PD2, a third photodiode PD3, and a fourth photodiode PD4 are formed, and a second region 41b below the first region 41a in which a pixel circuit and wires corresponding to the pixel circuit are formed. A sensing circuit and wires corresponding to the sensing circuit may be formed in the lower chip 42. An objective lens 46 for applying light to the first photodiode PD1, the second photodiode PD2, the third photodiode PD3, and the fourth photodiode PD4 included in the upper chip 41 may be arranged on the upper region of the upper chip 41.

[0095] According to some example embodiments, the upper chip 41 of the hybrid pixel 11 may correspond to Figure 8 The upper chip 40 of the hybrid pixel 11 and the lower chip 42 may correspond to Figure 8 According to some example embodiments, the upper chip 41 of the hybrid pixel 11 may correspond to Figure 9 The upper chip 40 of the hybrid pixel 11 and the lower chip 42 may correspond to Figure 9 The middle chip 51.

[0096] According to some example embodiments, the pixel circuit uses electrons and thus may include an n-channel metal oxide semiconductor (NMOS) transistor, and the sensing circuit may include both an NMOS transistor and a p-channel metal oxide semiconductor (PMOS) transistor. Therefore, an efficient stacked structure may be formed by forming the sensing circuit including both the NMOS transistor and the PMOS transistor on a layer separate from the pixel circuit and the photodiode.

[0097] According to some example embodiments, a plurality of first photodiodes PD1, second photodiodes PD2, third photodiodes PD3, and fourth photodiodes PD4 may be shared with each other and correspond to one hybrid pixel. According to some example embodiments, a hybrid pixel 11 including a plurality of first photodiodes PD1, second photodiodes PD2, third photodiodes PD3, and fourth photodiodes PD4 may be isolated from adjacent hybrid pixels by a DTI region 41c. According to some example embodiments, the DTI region 41c may be formed according to the depth of the first region 41a in which the plurality of first photodiodes PD1, second photodiodes PD2, third photodiodes PD3, and fourth photodiodes PD4 are formed. Figure 10A , the DTI region 41c is formed only on the right side of the first region 41a in which the first, second, third, and fourth photodiodes PD1, PD2, PD3, and PD4 are formed. However, this is for ease of description, and it should be noted that the DTI region 41c is formed to surround all four sides of the first region 41a in which the first, second, third, and fourth photodiodes PD1, PD2, PD3, and PD4 are formed. According to the present inventive concept, by using the DTI region 41c that is physically separated from adjacent hybrid pixels, individual sensing pixels corresponding to sensing circuits can be formed.

[0098] Despite Figure 10A , but the plurality of first photodiodes PD1, second photodiodes PD2, third photodiodes PD3, and fourth photodiodes PD4 may include a first region and a second region, and may share the second region. Figures 6A to 6C The details of the description are omitted, and therefore redundant description will be omitted.

[0099] According to some example embodiments, the upper chip 41 and the lower chip 42 may be electrically connected to each other through a vertical region 45. The vertical region 45 extends in the Z-axis direction and may be in contact with each of the upper chip 41 and the lower chip 42. According to some example embodiments, the vertical region 45 may be a path for connecting charges generated in the first photodiode PD1, the second photodiode PD2, the third photodiode PD3, and the fourth photodiode PD4 to a sensing circuit. According to some example embodiments, the vertical region 45 may be a through silicon via (TSV) or a chip-to-chip (C2C) path for connecting the charges of the first photodiode PD1, the second photodiode PD2, the third photodiode PD3, and the fourth photodiode PD4 to a sensing circuit.

[0100] Figure 10B A stacked structure of components of a hybrid pixel 21 included in a hybrid sensor according to some example embodiments is shown.

[0101] For ease of description, some example embodiments are shown in which the wiring structure of the photodiodes, pixel circuits, and sensing circuits included in a plurality of hybrid pixels is applied to a stacked structure. According to some example embodiments, the upper chip 61 of the hybrid pixel 21 may correspond to Figure 8 The upper chip 40 of the hybrid pixel 21 and the lower chip 62 may correspond to Figure 8 According to some example embodiments, the upper chip 61 of the hybrid pixel 21 may correspond to Figure 9 The upper chip 40 of the hybrid pixel 21 and the lower chip 62 may correspond to Figure 9 The middle chip 51.

[0102] Reference Figure 10B , the hybrid pixel 21 may include an upper chip 61 and a lower chip 62. The upper chip 61 may include a first region 61a in which the first photodiode PD1, the second photodiode PD2, the third photodiode PD3, and the fourth photodiode PD4 are formed, and a second region 61b below the first region 61a in which the pixel circuit and the wires corresponding to the pixel circuit are formed. The sensing circuit and the wires corresponding to the pixel circuit may be formed in the lower chip 62. An objective lens 66 for applying light to the first photodiode PD1, the second photodiode PD2, the third photodiode PD3, and the fourth photodiode PD4 included in the upper chip 61 may be arranged on the upper region of the upper chip 61.

[0103] Figure 10B It shows that Figure 10A The stacked structure of sixteen hybrid pixels 11. Figure 10B The B region corresponds to the Figure 10AThe first region 41 a and the second region 41 b in the upper chip 41 are shown in FIG. 4 , and thus a redundant description thereof is omitted.

[0104] Reference Figure 10B , multiple hybrid pixels can be physically separated by the DTI region 61c. Figure 10A and Figure 10B In some example embodiments, a hybrid pixel may refer to a pixel corresponding to one unit sharing a plurality of first photodiodes PD1, second photodiodes PD2, third photodiodes PD3, and fourth photodiodes PD4. According to some example embodiments, the DTI region 61c may be formed according to the depth of the first region 61a in which the plurality of first photodiodes PD1, second photodiodes PD2, third photodiodes PD3, and fourth photodiodes PD4 are formed. Figure 10B , some example embodiments are shown in which the DTI region 61c is formed only between four hybrid pixels in front of the first region 61a where the first photodiode PD1, the second photodiode PD2, the third photodiode PD3 and the fourth photodiode PD4 are formed, but this is only for ease of description, and it should be noted that the DTI region 61c is formed to surround each hybrid pixel that shares the first photodiode PD1, the second photodiode PD2, the third photodiode PD3 and the fourth photodiode PD4 to prevent or reduce crosstalk with adjacent hybrid pixels.

[0105] although Figure 10B , but the plurality of first photodiodes PD1, second photodiodes PD2, third photodiodes PD3, and fourth photodiodes PD4 may include a first region and a second region, and may share the second region. Figures 6A to 6C The details of the description are omitted, so redundant description will be omitted.

[0106] Reference Figure 10B , the upper chip 61 and the lower chip 62 may be electrically connected to each other through the vertical region 65. The vertical region 65 extends in the Z-axis direction and may be in contact with each of the upper chip 61 and the lower chip 62. According to some example embodiments, the vertical region 65 may be a path for connecting the charge of the first photodiode PD1, the second photodiode PD2, the third photodiode PD3, and the fourth photodiode PD4 to the sensing circuit. According to some example embodiments, the vertical region 65 may be a TSV or C2C for connecting the charge of the first photodiode PD1, the second photodiode PD2, the third photodiode PD3, and the fourth photodiode PD4 to the sensing circuit.

[0107] Reference Figure 10B, a vertical region 65 for connecting the holes of multiple hybrid pixels to one sensing circuit can be provided, instead of Figure 10A As shown, a vertical region 65 is provided for connecting the pixel circuit and the sensing circuit included in one hybrid pixel.

[0108] Reference Figure 10B In order to connect the output of the photodiode included in each of the plurality of hybrid pixels together, a plurality of first vertical regions 65b vertically connected to the output of each hybrid pixel (e.g., electrically connected), a plurality of first planar regions 65c connecting the plurality of first vertical regions 65b on the XY plane (e.g., electrically connected), and at least one second vertical region 65a connecting the plurality of first vertical regions 65b and the plurality of first planar regions 65c to a sensing circuit (e.g., electrically connected) may be provided. According to some example embodiments, each of the plurality of first vertical regions 65b may be a vertical region for connecting charges respectively corresponding to contact regions included in the hybrid pixel, that is, each of the plurality of first vertical regions 65b may be electrically connected to a corresponding contact region included in the hybrid pixel.

[0109] Reference Figure 10B , only one second vertical region 65a is shown, but this is only an example, and it should be noted that a plurality of second vertical regions 65a may be provided. Figure 10B The contact regions separated by the DTI region in the upper chip 61 can be connected to a sensing circuit by combining conductive lines such as metal or polysilicon included in the vertical region 65 into one conductive line.

[0110] refer to Figure 10B In some example embodiments, when the sensing circuit performs event detection by mixing the outputs of sixteen mixed pixels, a 16-fold larger signal can be connected, and thus, operation under low illumination can be facilitated. According to some example embodiments, the output of the hole signal of the plurality of mixed pixels can be as follows: Figure 10B According to some example embodiments, when color information is not required in the sensing circuit, a conductive line may be formed by connecting hole signals of photodiodes corresponding to RGB.

[0111] Figure 11 is a block diagram of a structure of a hybrid pixel PXd according to some example embodiments.

[0112] Reference Figure 11 , the hybrid pixel PXd may include a photodiode 3000d, a pixel circuit 1000d, a sensing circuit 2000d and a noise removal circuit 4000d. Figure 11 When Figure 4AAccording to some example embodiments, in the sensing circuit 2000d using holes, noise caused by TIA may occur, and when the noise interferes with the ground level, the signal-to-noise ratio (SNR) of the pixel signal may be affected. Figure 11 The noise removal circuit 4000d can be connected between the photodiode 3000d and the sensing circuit 2000d. The noise removal circuit 4000d can be connected between the anode of the photodiode 3000d and the sensing circuit 2000d. The noise removal circuit 4000d can include multiple transistors, and the noise generated by the sensing circuit 2000d can be removed by adjusting the on and off of the multiple transistors.

[0113] Figure 12 is a circuit diagram of a hybrid pixel PXe according to some example embodiments.

[0114] Reference Figure 12 , the hybrid pixel PXe may include a pixel circuit 1000e, a sensing circuit 2000e, a photodiode 3000e and a noise removal circuit 4000e. The pixel circuit 1000e may include a transfer transistor TX, a reset transistor RX, a drive transistor DX and a selection transistor SX. The structure of the sensing circuit 2000e may correspond to Figure 4A According to some example embodiments, details regarding the pixel circuit 1000e, the sensing circuit 2000e, and the photodiode 3000e correspond to those of reference 1000e. Figures 4A to 10B Details regarding the pixel circuit, sensing circuit, and photodiode are described, and therefore, redundant descriptions will be omitted.

[0115] The noise removal circuit 4000e may include a first transistor NRB and a second transistor NR. According to some example embodiments, the first transistor NRB may be connected between the anode of the photodiode 3000e and the sensing circuit 2000e. The second transistor NR may be connected between the anode of the photodiode 3000e and the ground. According to some example embodiments, the first transistor NRB and the second transistor NR may be connected in parallel with each other. The noise removal circuit 4000e may configure a circuit that connects or releases the sensing circuit 2000e by using the first transistor NRB and the second transistor NR. According to some example embodiments, the first transistor NRB of the noise removal circuit 4000e may be a transistor configured to control the connection between the contact region of the photodiode 3000e and the sensing circuit 2000e, and the second transistor NR may be a transistor configured to control the connection between the contact region of the photodiode 3000e and the ground or between different specific voltages.

[0116] When the first transistor NRB is turned on and the second transistor NR is turned off, the photodiode 3000e and the sensing circuit 2000e can be connected to each other. In this case, the holes generated in the photodiode 3000e can be transferred to the sensing circuit 2000e. When the first transistor NRB is turned off and the second transistor NR is turned on, the photodiode 3000e and the ground can be connected to each other, and the holes generated in the photodiode 3000e can flow to the ground, and thus, the hole current can be depleted. Therefore, by controlling the on and off of the first transistor NRB and the second transistor NR, the connection between the sensing circuit 2000e and the photodiode 3000e can be adjusted.

[0117] Figure 13 is used to describe Figure 12 A timing diagram showing the turn-on timing of transistors included in the noise removal circuit 4000e.

[0118] Figure 13 A timing diagram of a selection control signal SEL applied to the selection transistor SX, a reset control signal RG applied to the reset transistor RX, a transmission control signal TG applied to the transmission transistor TX, a first control signal NRBS applied to the first transistor NRB, and a second control signal NRS applied to the second transistor NR is shown.

[0119] Reference Figure 13 , showing a period corresponding to one frame. During one frame FRM, a reset time RST, an exposure time IT, a read time RO, and a non-integration time NIT can be allocated to each of the multiple rows. The reset time RST corresponding to the period t1 to t3, the exposure time IT corresponding to the period t3 to t4, the read time RO corresponding to the period t4 to t6, and the non-integration time NIT corresponding to the period t6 to t7 are shown.

[0120] During reset time RST, corresponding to the period from t1 to t3, the pixel can be reset. At time t2, the transfer transistor TX included in the pixel can be turned on and transfer the charge generated in the photodiode during the non-integration time NIT to the floating diffusion node, thereby removing the charge. During reset time RST, the reset control signal RG applied to the reset transistor RX maintains the second level. Therefore, while the reset voltage is applied to the floating diffusion node, the transfer transistor TX of the pixel is turned on. Therefore, the floating diffusion node and the pixel can be reset together.

[0121] During the exposure time IT corresponding to the period t3 to t4, charges corresponding to the light signal may be generated and accumulated in the photodiode included in the pixel. The pixel may be read during the read time RO corresponding to the period t4 to t6. At time point t5, the transfer transistor TX included in the pixel is turned on and the charges accumulated in the photodiode during the exposure time IT are transferred to the floating diffusion node and may be read by the floating diffusion node. Figure 1 The column line CL outputs a pixel voltage corresponding to the transferred charge. During read time RO before time point t5, sampling of a signal corresponding to the reset voltage (reset sampling) can be performed, and during read time RO after time point t5, sampling of data corresponding to the image voltage (signal sampling) can be performed. At time point t4, which is the start time point of read time RO, the select control signal SEL applied to the select transistor SX can change from the first level to the second level, and the reset control signal RG applied to the reset transistor RX can change from the second level to the first level. At time point t6, which is the end time point of read time RO, the select control signal SEL applied to the select transistor SX can change from the second level to the first level, and the reset control signal RG applied to the reset transistor RX can change from the first level to the second level. In the present inventive concept, the first level can be a low level, and the second level can be a high level.

[0122] According to some example embodiments, during the reset time RST, the exposure time IT, and the non-integration time NIT, the second control signal NRS applied to the second transistor NR may maintain a first level, and during the read time RO, the second control signal NRS applied to the second transistor NR may maintain a second level. According to some example embodiments, during the reset time RST, the exposure time IT, and the non-integration time NIT, the first control signal NRBS applied to the first transistor NRB may maintain a second level, and during the read time RO, the first control signal NRBS applied to the first transistor NRB may maintain a first level. According to some example embodiments, at time point t4, which is the start time point of the read time RO, the second control signal NRS may change from the first level to the second level, and the first control signal NRBS may change from the second level to the first level. According to some example embodiments, at time point t6, which is the end time point of the read time RO, the second control signal NRS may change from the second level to the first level, and the first control signal NRBS may change from the first level to the second level. According to some example embodiments, the first transistor NRB and the second transistor NR may be complementary. When the first transistor NRB is turned on, the second transistor NR may be turned off, and when the first transistor NR is turned off, the second transistor NR may be turned on.

[0123] According to some example embodiments, the first control signal NRBS applied to the first transistor NRB may be changed from the second level to the first level before the CDS sampling time ST, and may be changed from the first level to the second level after the CDS sampling time ST. According to some example embodiments, the second control signal NRS applied to the second transistor NR may be changed from the first level to the second level before the CDS sampling time ST, and may be changed from the second level to the first level after the CDS sampling time ST. The CDS sampling time ST may be a period included in the read time RO.

[0124] In other words, during the read time RO, the first transistor NRB is turned off and the second transistor NR is turned on to block a path that may be connected to the sensing circuit 2000e during the read time RO and block noise that may occur in the sensing circuit 2000e during the read time RO. According to some example embodiments, the read time RO may be most susceptible to noise, and therefore, according to the present inventive concept, noise may be removed by controlling signals applied to transistors included in the noise removal circuit 4000e.

[0125] Figure 14 and Figure 15 is a timing diagram for describing the turn-on timing of transistors included in the noise removal circuit according to some example embodiments. Figure 14 and Figure 15 When the reference Figure 13 The details described overlap the details.

[0126] Reference Figure 14 During the reset time RST corresponding to the period from t1 to t3, the second control signal NRS applied to the second transistor NR may maintain the second level, and the first control signal NRBS applied to the first transistor NRB may maintain the first level. According to some example embodiments, at time point t1, which is the start time point of the reset time RST, the second control signal NRS may change from the first level to the second level, and the first control signal NRBS may change from the second level to the first level. According to some example embodiments, at time point t3, which is the end time point of the reset time RST, the second control signal NRS may change from the second level to the first level, and the first control signal NRBS may change from the first level to the second level.

[0127] Reference Figure 14 In some example embodiments, by controlling the second transistor NR to be turned on and the first transistor NRB to be turned off during the reset time RST corresponding to the period from t1 to t3, noise that may occur in the sensing circuit 2000e may have little effect even during a reset operation.

[0128] exist Figure 13 and Figure 14 , some example embodiments are shown in which the second transistor NR is turned on and the first transistor NRB is turned off during the entire period of the reset time RST and / or the read time RO, but the present inventive concept is not limited thereto, and the second transistor NR may be turned on and the first transistor NRB may be turned off during a period corresponding to 90% or more of the entire period of the reset time RST and / or the read time RO. According to some example embodiments, the second transistor NR may be turned on and the first transistor NRB may be turned off during a portion of the reset time RST and / or the read time RO. According to some example embodiments, during the reset time RST, the second control signal NRS may be changed from a first level to a second level, such that the first control signal NRBS is changed from the second level to the first level before the time point (time point t2) at which the transmission control signal TG applied to the transmission transistor TX is changed from the first level to the second level, and the second control signal NRS may be changed from the second level to the first level, such that the first control signal NRBS is changed from the first level to the second level after the time point at which the transmission control signal TG applied to the transmission transistor TX is changed from the second level to the first level.

[0129] Reference Figure 15 In some example embodiments, the first control signal NRBS may maintain a first level during a portion of the exposure time IT and the non-integration time NIT, and the second control signal NRS may maintain a second level during a portion of the exposure time IT and the non-integration time NIT. According to some example embodiments, during the exposure time IT and the non-integration time NIT corresponding to the periods before and after the read time RO of the photodiode, the second transistor NR may be turned on during a portion of the period, and the first transistor NRB may be turned off. Therefore, noise that may occur during periods other than the reset time RST and the read time RO can be intermittently eliminated or reduced.

[0130] exist Figures 13 to 15 In the description of the timing diagram, the multiple control signals SEL, RG, TG, NRS and NRBS described in the timing diagram can be Figure 2 The row driver 120 generates the timing control of the plurality of control signals SEL, RG, TG, NRS and NRBS described in the timing diagram. Figure 2 The timing controller 150 controls the timing.

[0131] Any or all elements described with reference to the accompanying drawings may communicate with any or all other elements described with reference to the accompanying drawings. For example, any element may communicate with any or all other elements in the drawings in a unidirectional and / or bidirectional and / or broadcast manner to transmit and / or exchange and / or receive information, such as, but not limited to, data and / or commands, in a serial and / or parallel manner via a bus, such as a wireless and / or wired bus (not shown). The information may be encoded in various formats, such as analog and / or digital formats.

[0132] When the terms "approximately" or "substantially" are used in connection with a numerical value in this specification, it is intended that the numerical value include a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. Furthermore, when the terms "generally" and "substantially" are used in connection with a geometric shape, it is intended that the geometric shape is not required to be precise, but that the degree of freedom of the shape is within the scope of this disclosure. Furthermore, regardless of whether a numerical value or shape is modified by "approximately" or "substantially," it should be understood that these numerical values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the numerical value or shape.

[0133] As described herein, any electronic device and / or portion thereof according to any example embodiment may include, be included in, and / or be implemented by one or more instances of processing circuitry, such as hardware including logic circuitry; a hardware / software combination, such as a processor that executes software; or any combination thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA) and a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), a neural network processing unit (NPU), an electronic control unit (ECU), an image signal processor (ISP), and the like. In some example embodiments, the processing circuitry may include a non-transitory computer-readable storage device (e.g., memory), such as a DRAM device, that stores a program of instructions, and a processor (e.g., a CPU) configured to execute the program of instructions to implement some or all of the functions and / or methods performed by any device, system, module, unit, controller, circuit, architecture, and / or portion thereof according to any example embodiment.

[0134] Some exemplary embodiments have been described above in the drawings and the specification. Although specific terms have been used to describe the exemplary embodiments in this specification, these terms are used for descriptive purposes only and are not intended to limit the meaning or scope of the inventive concept described in the claims. Therefore, those skilled in the art will understand that other modifications and equivalents may be made herein. Therefore, the scope of the inventive concept is to be defined by the appended claims.

Claims

1. A hybrid pixel, comprising: semiconductor substrates; a pixel circuit comprising at least one transfer transistor; a sensing circuit configured to detect motion of an object; as well as at least one photodiode, one end of the at least one photodiode being connected to the pixel circuit and the other end being connected to the sensing circuit, The semiconductor substrate has a first conductivity type, the semiconductor substrate includes a photoelectric conversion region corresponding to the at least one photodiode, and the semiconductor substrate includes a first region of a second conductivity type and a second region surrounding the first region. The second region is physically separated from the second region of the adjacent hybrid pixel by a deep trench isolation region, and The semiconductor substrate includes the deep trench isolation region.

2. The hybrid pixel according to claim 1, wherein: The first conductivity type is p-type, and the second conductivity type is n-type.

3. The hybrid pixel according to claim 1, wherein: The deep trench isolation region is a front deep trench isolation.

4. The hybrid pixel according to claim 1, wherein: The number of the at least one photodiode and the number of the at least one transfer transistor are the same number.

5. The hybrid pixel according to claim 4, wherein: The number of the first regions corresponds to the number of the at least one photodiode, and the number of the second regions is less than or equal to the number of the first regions.

6. The hybrid pixel according to claim 1, wherein: The pixel circuit is connected to a cathode of the at least one photodiode, and the sensing circuit is connected to an anode of the at least one photodiode.

7. The hybrid pixel according to claim 1, wherein: The pixel circuit is connected to an anode of the at least one photodiode, and the sensing circuit is connected to a cathode of the at least one photodiode.

8. A hybrid pixel, comprising: semiconductor substrates; a pixel circuit comprising at least one transfer transistor; a sensing circuit configured to detect motion of an object; as well as at least one photodiode, one end of the at least one photodiode being connected to the pixel circuit and the other end being connected to the sensing circuit, The semiconductor substrate has a first conductivity type, the semiconductor substrate includes a photoelectric conversion region corresponding to the at least one photodiode, and the semiconductor substrate includes a first region of a second conductivity type and a second region surrounding the first region. The second region is physically separated from the second region of the adjacent hybrid pixel by a deep trench isolation region, and The first layer including the pixel circuitry and the at least one photodiode is different from the second layer including the sensing circuitry.

9. The hybrid pixel according to claim 8, wherein: The first layer is above the second layer, and The hybrid pixel further includes a vertical region to electrically connect the first layer and the second layer to each other.

10. The hybrid pixel according to claim 9, wherein: The vertical regions are silicon vias or chip-to-chip.

11. The hybrid pixel according to claim 9, wherein: The vertical area includes: a plurality of first vertical regions, the plurality of first vertical regions being electrically connected to each other and corresponding to the plurality of second regions in the first layer; a planar region connecting the plurality of first vertical regions on a plane; and A second vertical region connects the plurality of first vertical regions and the planar region to the sensing circuit.

12. The hybrid pixel according to claim 9, wherein: The deep trench isolation region is a front deep trench isolation.

13. A hybrid sensor, comprising: a pixel array comprising a plurality of hybrid pixels, The plurality of mixed pixels include: Photodiode; a pixel circuit connected to one end of the photodiode; a sensing circuit connected to the other end of the photodiode; and a noise removal circuit connected between the sensing circuit and the other end of the photodiode, and Each hybrid pixel of the plurality of hybrid pixels is physically separated from an adjacent hybrid pixel by a deep trench isolation region.

14. The hybrid sensor according to claim 13, wherein The noise removal circuit comprises: a first transistor connected between the other end of the photodiode and the sensing circuit; and A second transistor is connected between the other end of the photodiode and a ground.

15. The hybrid sensor according to claim 14, further comprising: a row driver configured to generate a signal applied to the pixel array; as well as a timing controller configured to control the timing of signals generated by the row driver, The timing controller is further configured to control the timing of a first control signal and a second control signal applied to the first transistor and the second transistor respectively.

16. The hybrid sensor according to claim 15, wherein: The timing controller is further configured to control timings of the first control signal and the second control signal so that at a start point of a read time of the photodiode, the first transistor is turned off and the second transistor is turned on.

17. The hybrid sensor according to claim 15, wherein: The timing controller is further configured to control timing of the first control signal and the second control signal so that at an end point of a read time of the photodiode, the first transistor is turned on and the second transistor is turned off.

18. The hybrid sensor according to claim 15, wherein The timing controller is further configured to control timings of the first control signal and the second control signal so that the first transistor is turned on and the second transistor is turned off in periods before and after a read time of the photodiode.

19. The hybrid sensor according to claim 18, wherein The timing controller is further configured to control the timing of the first control signal and the second control signal so that the period before and after the reading time of the photodiode includes a portion of the period in which the first transistor is turned off, and so that the period before and after the reading time of the photodiode includes a portion of the period in which the second transistor is turned on.

20. The hybrid sensor according to claim 15, wherein The timing controller is further configured to control timing of the first control signal and the second control signal such that during a reset time of the photodiode, the first transistor is turned off and the second transistor is turned on.

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