Preparation method of quantum chip and quantum chip

Abstract

The invention relates to the technical field of chips, in particular to a preparation method of a quantum chip and the quantum chip. Comprising the steps that a first chip structure is provided, and a first superconducting metal layer and a quantum chip circuit formed on the first superconducting metal layer are formed on a first substrate; providing a second chip structure, including; providing a second substrate; growing a second superconducting metal layer on the second substrate; generating an isolating layer and a connecting layer on the second superconducting metal layer; and connecting the first chip structure with the second chip structure, so that the connecting layer and the isolation layer are both connected with the first superconducting metal layer, and the isolation layer forms independent isolation on devices of the quantum chip circuit. By arranging the isolating layer and the connecting layer in the chip structure, crosstalk signals between bits are effectively isolated and shielded, and the performance of the chip is remarkably improved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a method for preparing a quantum chip and the quantum chip. Background Art

[0002] The field of quantum computing is steadily moving toward practical application. Superconducting quantum computing, with its unique advantages, has become one of the most promising paths to its realization. However, as the number of qubits increases, crosstalk between them becomes increasingly prominent, hindering the accurate reading and efficient manipulation of bit information and becoming a significant technical bottleneck.

[0003] In the current planar chip process, in order to effectively alleviate the crosstalk problem between adjacent bits, the air bridge solution has become the mainstream technical choice. The implementation process of this solution is sophisticated and complex, and the cumbersome operation process inevitably has a negative impact on the performance of the prepared device, resulting in a decrease in its overall performance. In addition, a large number of bridge structures are arranged on both sides of the resonant cavity, read line and control line to balance the potential difference, but this layout cannot completely block the crosstalk between adjacent signals. Signals may still be transmitted through the air and cause crosstalk, thereby affecting the precise operation of quantum bits and information reading. At the same time, the mechanical strength of the air bridge and tunnel bridge structures is low, and there is a high risk of collapse. The air bridge solution still has certain limitations and cannot solve the problem of signal crosstalk between adjacent bits.

[0004] Chinese invention patent application CN116600630A discloses a method for manufacturing a quantum chip and a flip chip, wherein a first interconnecting column and a second interconnecting column are used to form an interconnection structure to realize the connection between the two chips. The flip-chip interconnection part is, for example, an indium column, and an isolation material such as titanium nitride is configured between the indium column and the aluminum. This technology ensures the quality of the line connection when the pad is subsequently used for wire bonding by configuring the pad for wire bonding inside the chip substrate. Chinese invention patent application CN119136646 A discloses a superconducting quantum flip chip and a preparation method, wherein a metal part is prepared on the lower substrate, a TiN layer is used to contact the metal part, and a groove design of the lower substrate is used without a separate limiting layer, thereby realizing high-precision pressure welding connection between the upper and lower chips and improving the comprehensive performance of the superconducting quantum flip chip. However, these technologies have not solved the technical problem of signal crosstalk between adjacent quantum chips.

[0005] In this context, how to prepare a quantum chip that can effectively reduce crosstalk between adjacent signals, optimize the electromagnetic environment inside the chip, and improve the stability and accuracy of signal transmission has become a technical problem that needs to be urgently solved in this field. Summary of the Invention

[0006] In response to the technical problems of signal crosstalk between adjacent bits in existing quantum chips and the complex implementation of solutions such as air bridges, the present invention aims to provide a quantum chip structure and its preparation method that can effectively reduce the signal crosstalk between adjacent bits, optimize the electromagnetic environment inside the chip, and improve the stability and accuracy of signal transmission.

[0007] In order to solve the above technical problems, the first aspect of the present invention provides a method for preparing a quantum chip, comprising:

[0008] Providing a first chip structure, the first chip structure comprising a first substrate, a first superconducting metal layer formed on the first substrate, and a quantum chip circuit formed on the first superconducting metal layer;

[0009] A second chip structure is provided, and the steps of preparing the second chip structure include:

[0010] providing a second substrate;

[0011] growing a second superconducting metal layer on the second substrate;

[0012] performing photolithographic patterning on the second superconducting metal layer and forming an isolation layer on the second superconducting metal layer;

[0013] Continue to perform photolithographic patterning on the isolation layer and the exposed second superconducting metal layer, and generate a connection layer in the area of ​​the second superconducting metal layer other than the isolation layer;

[0014] The first chip structure is connected to the second chip structure, so that the connection layer and the isolation layer are both connected to the first superconducting metal layer, and the isolation layer independently isolates the devices of the quantum chip circuit.

[0015] Optionally, a pressure welding operation is used to connect the first chip structure and the second chip structure.

[0016] Optionally, the photolithographic patterning of the second superconducting metal layer and the generation of an isolation layer on the second superconducting metal layer include coating a photoresist on the second superconducting metal layer, photolithographic development to define an isolation layer area; and evaporating the first superconducting metal and removing the photoresist in areas other than the isolation layer to obtain the isolation layer.

[0017] Optionally, continuing to perform photolithographic patterning on the isolation layer and the exposed second superconducting metal layer, and generating a connecting layer in the area of ​​the second superconducting metal layer other than the isolation layer, includes: after obtaining the isolation layer, coating photoresist on the isolation layer and the exposed part of the second superconducting metal layer, and performing photolithographic development to define the connecting layer area; evaporating the second superconducting metal, removing the photoresist in the area other than the connecting layer, and obtaining the connecting layer.

[0018] Optionally, the first superconducting metal and the second superconducting metal are made of the same or different materials.

[0019] A second aspect of the present invention provides a method for preparing a quantum chip, comprising:

[0020] Providing a first chip structure, the first chip structure comprising a first substrate, a first superconducting metal layer formed on the first substrate, and a quantum chip circuit formed on the first superconducting metal layer;

[0021] A second chip structure is provided, and the steps of preparing the second chip structure include:

[0022] providing a second substrate;

[0023] growing a second superconducting metal layer on the second substrate;

[0024] performing photolithographic patterning on the second superconducting metal layer, and forming an isolation layer and a connection layer on the second superconducting metal layer;

[0025] The first chip structure is connected to the second chip structure, so that the connection layer and the isolation layer are both connected to the first superconducting metal layer, and the isolation layer independently isolates the devices of the quantum chip circuit.

[0026] Optionally, the photolithographic patterning of the second superconducting metal layer and the generation of an isolation layer and a connection layer on the second superconducting metal layer include coating a photoresist on the second superconducting metal layer, photolithographic development to define the isolation layer and connection layer areas; evaporating a superconducting metal, removing the photoresist in the non-isolation layer and connection layer areas on the second superconducting metal layer, and obtaining the isolation layer and the connection layer.

[0027] A third aspect of the present invention provides a method for preparing a quantum chip, comprising:

[0028] Providing a first chip structure, the first chip structure comprising a first substrate, a first superconducting metal layer formed on the first substrate, and a quantum chip circuit formed on the first superconducting metal layer;

[0029] A second chip structure is provided, and the steps of preparing the second chip structure include:

[0030] providing a second substrate;

[0031] growing a second superconducting metal layer on the second substrate;

[0032] performing photolithographic patterning on the second superconducting metal layer, and etching the second superconducting metal layer to obtain an isolation layer;

[0033] Continue to perform photolithographic patterning on the isolation layer and the exposed second superconducting metal layer, and generate a connection layer in the area of ​​the second superconducting metal layer other than the isolation layer;

[0034] The first chip structure is connected to the second chip structure, so that the connection layer and the isolation layer are both connected to the first superconducting metal layer, and the isolation layer independently isolates the devices of the quantum chip circuit.

[0035] Optionally, the photolithographic patterning of the second superconducting metal layer and the etching of the second superconducting metal layer to obtain the isolation layer include coating a photoresist on the second superconducting metal layer, photolithographic development to define an isolation layer area; and etching a portion of the second superconducting metal layer corresponding to the isolation layer area to obtain the isolation layer.

[0036] Optionally, the step of continuing to perform photolithographic patterning on the isolation layer and the exposed second superconducting metal layer to generate a connecting layer in the area of ​​the second superconducting metal layer other than the isolation layer includes: after obtaining the isolation layer, coating photoresist on the isolation layer and the exposed partial area of ​​the second superconducting metal layer, performing photolithographic development to define the connecting layer area; and evaporating superconducting metal, removing the photoresist in the area other than the connecting layer, and obtaining the connecting layer.

[0037] Optionally, the second superconducting metal layer and the superconducting metal are made of different materials.

[0038] A fourth aspect of the present invention provides a quantum chip, comprising:

[0039] A first substrate comprising a first superconducting metal layer and a quantum chip circuit formed on the first superconducting metal layer;

[0040] A second substrate includes a second superconducting metal layer, and a connecting layer and an isolation layer formed on the second superconducting metal layer, the connecting layer is connected to the first superconducting metal layer, and the isolation layer is connected to the first superconducting metal layer at one end facing away from the second superconducting metal layer. The isolation layer is arranged corresponding to the quantum chip circuit to independently isolate the devices of the quantum chip circuit.

[0041] Optionally, when the connecting layer and the isolation layer are made of the same material, the thickness of the isolation layer is greater than or equal to the thickness of the connecting layer.

[0042] Beneficial effects:

[0043] The present invention provides a quantum chip and a preparation method thereof, which have the following advantages:

[0044] (1) The present invention introduces an isolation layer and a connection layer into the chip structure, realizes the electrical connection between the first chip and the second chip through the connection layer, and plays a limiting support role. The isolation layer separates different circuit areas to prevent interference between bit signals and ensure the stability and reliability of the circuit.

[0045] (2) The present invention further adopts a flip-chip structure design, where the superconducting circuit layer and the Josephson junction are arranged on the first chip, the isolation layer and the connection layer are arranged on the second chip, and the first chip and the second chip are fixedly connected by using flip-chip welding technology. The method of independently preparing the isolation layer and the connection layer on the second chip avoids the negative impact of the processing process on the bits and other devices on the quantum chip, thereby improving the stability and accuracy of signal transmission.

[0046] (3) The present invention can isolate key components such as the resonant cavity, control line, transmission line, and bit in the quantum chip in three-dimensional space by designing the isolation layer and the connection layer in conjunction with the pressure welding process, forming independent entities and shielding crosstalk information. At the same time, it retains the normal coupling, reading, and manipulation capabilities between circuit components, providing a guarantee for efficient and stable circuit operation.

[0047] (4) The present invention is flexible in its implementation. The superconducting metal materials for the isolation layer and the connecting layer can be flexibly selected based on design requirements, and the preparation methods of the isolation layer and the connecting layer can be adaptively adjusted. When the isolation layer and the connecting layer are made of the same material and have the same thickness, the pattern structures of the isolation layer and the connecting layer can be simultaneously defined on the surface of the second superconducting metal layer, thereby simultaneously preparing the isolation layer and the connecting layer, simplifying the operation process.

[0048] (5) When the thickness of the second superconducting metal layer is relatively large, different methods can be selected to evaporate or etch the surface of the second superconducting metal layer to obtain an isolation layer. In particular, the second superconducting metal layer can be directly etched to form a "convex" shape, thereby obtaining an isolation layer. This not only simplifies the operation process but also ensures the isolation and shielding effects of the signal, thereby improving chip performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 . Schematic diagram of the quantum chip preparation process provided by the present invention;

[0050] Figure 2 .Schematic diagram of the quantum chip structure provided by the present invention;

[0051] Figure 3 . Schematic diagram of the quantum chip preparation process provided by the present invention;

[0052] Figure 4 . Schematic diagram of the quantum chip preparation process provided by the present invention;

[0053] In the figure: 1. First superconducting metal layer, 2. Second superconducting metal layer, 3. Isolation layer, 4. Connection layer, 5. Superconducting circuit layer, 6. Josephson junction. DETAILED DESCRIPTION

[0054] In order to solve the above technical problems, the first aspect of the present invention provides a method for preparing a quantum chip, comprising:

[0055] Providing a first chip structure, the first chip structure comprising a first substrate, a first superconducting metal layer formed on the first substrate, and a quantum chip circuit formed on the first superconducting metal layer;

[0056] A second chip structure is provided, and the steps of preparing the second chip structure include:

[0057] providing a second substrate;

[0058] growing a second superconducting metal layer on the second substrate;

[0059] performing photolithographic patterning on the second superconducting metal layer and forming an isolation layer on the second superconducting metal layer;

[0060] Continue to perform photolithographic patterning on the isolation layer and the exposed second superconducting metal layer, and generate a connection layer in the area of ​​the second superconducting metal layer other than the isolation layer;

[0061] The first chip structure is connected to the second chip structure, so that the connection layer and the isolation layer are both connected to the first superconducting metal layer, and the isolation layer independently isolates the devices of the quantum chip circuit.

[0062] In some embodiments, the photolithographic patterning of the second superconducting metal layer and the generation of an isolation layer on the second superconducting metal layer include coating a photoresist on the second superconducting metal layer, photolithographically developing to define an isolation layer area; and evaporating a first superconducting metal and removing the photoresist in areas other than the isolation layer to obtain the isolation layer.

[0063] In some embodiments, the continuing to perform photolithographic patterning on the isolation layer and the exposed second superconducting metal layer and generating a connecting layer in the area of ​​the second superconducting metal layer other than the isolation layer includes: after obtaining the isolation layer, coating photoresist on the isolation layer and the exposed partial area of ​​the second superconducting metal layer, and photolithographic development to define the connecting layer area; evaporating the second superconducting metal, removing the photoresist in the area other than the connecting layer, and obtaining the connecting layer.

[0064] In some embodiments, the first superconducting metal and the second superconducting metal are made of the same or different materials and are independently selected from any one of Al (aluminum), Nb (niobium), Ta (tantalum), TiN (titanium nitride), and In (indium).

[0065] According to some embodiments of the present invention, when the isolation layer and the connection layer are made of the same material, both may be selected from In.

[0066] According to some embodiments of the present invention, when the isolation layer and the connection layer are made of different materials, the isolation layer (corresponding to the first superconducting metal) is made of Al, and the connection layer (corresponding to the second superconducting metal) is made of In.

[0067] A second aspect of the present invention provides a method for preparing a quantum chip, comprising:

[0068] Providing a first chip structure, the first chip structure comprising a first substrate, a first superconducting metal layer formed on the first substrate, and a quantum chip circuit formed on the first superconducting metal layer;

[0069] A second chip structure is provided, and the steps of preparing the second chip structure include:

[0070] providing a second substrate;

[0071] growing a second superconducting metal layer on the second substrate;

[0072] performing photolithographic patterning on the second superconducting metal layer, and forming an isolation layer and a connection layer on the second superconducting metal layer;

[0073] The first chip structure is connected to the second chip structure, so that the connection layer and the isolation layer are both connected to the first superconducting metal layer, and the isolation layer independently isolates the devices of the quantum chip circuit.

[0074] In some embodiments, the photolithographic patterning of the second superconducting metal layer and the generation of an isolation layer and a connection layer on the second superconducting metal layer include coating a photoresist on the second superconducting metal layer, photolithographic development to define the isolation layer and connection layer areas; evaporating a superconducting metal, removing the photoresist in the non-isolation layer and connection layer areas on the second superconducting metal layer, and obtaining the isolation layer and the connection layer.

[0075] Optionally, the superconducting metal is selected from any one of Al (aluminum), Nb (niobium), Ta (tantalum), TiN (titanium nitride), and In (indium).

[0076] According to some embodiments of the present invention, the materials of the isolation layer and the connection layer (corresponding to superconducting metal) are both In.

[0077] A third aspect of the present invention provides a method for preparing a quantum chip, comprising:

[0078] Providing a first chip structure, the first chip structure comprising a first substrate, a first superconducting metal layer formed on the first substrate, and a quantum chip circuit formed on the first superconducting metal layer;

[0079] A second chip structure is provided, and the steps of preparing the second chip structure include:

[0080] providing a second substrate;

[0081] growing a second superconducting metal layer on the second substrate;

[0082] performing photolithographic patterning on the second superconducting metal layer, and etching the second superconducting metal layer to obtain an isolation layer;

[0083] Continue to perform photolithographic patterning on the isolation layer and the exposed second superconducting metal layer, and generate a connection layer in the area of ​​the second superconducting metal layer other than the isolation layer;

[0084] The first chip structure is connected to the second chip structure, so that the connection layer and the isolation layer are both connected to the first superconducting metal layer, and the isolation layer independently isolates the devices of the quantum chip circuit.

[0085] In some embodiments, the photolithographic patterning of the second superconducting metal layer and etching the second superconducting metal layer to obtain an isolation layer include coating a photoresist on the second superconducting metal layer, photolithographically developing to define an isolation layer area; and etching a portion of the second superconducting metal layer corresponding to the isolation layer area to obtain the isolation layer.

[0086] In some embodiments, the continuing to perform photolithographic patterning on the isolation layer and the exposed second superconducting metal layer to generate a connecting layer in the area of ​​the second superconducting metal layer other than the isolation layer includes: after obtaining the isolation layer, coating photoresist on the isolation layer and the exposed partial area of ​​the second superconducting metal layer, and photolithographic development to define the connecting layer area; evaporating superconducting metal, removing the photoresist in the area other than the connecting layer, and obtaining the connecting layer.

[0087] In some embodiments, the second superconducting metal layer and the superconducting metal are independently made of any one of Al (aluminum), Nb (niobium), Ta (tantalum), TiN (titanium nitride), and In (indium), and the two materials are different.

[0088] According to some embodiments of the present invention, the material of the isolation layer (corresponding to the second superconducting metal layer) is Al, and the material of the connection layer (corresponding to the superconducting metal) is In.

[0089] According to some embodiments of the present invention, the steps of preparing the superconducting metal layer (e.g., the first superconducting metal layer and the second superconducting metal layer) include:

[0090] Place the substrate in a magnetron sputtering device, heat it to 700-900°C, and wait until the vacuum degree is ≤1e -9 A superconducting metal film of appropriate thickness is grown at torr to obtain a superconducting metal layer.

[0091] The materials of the superconducting metal layers (e.g., the first superconducting metal layer and the second superconducting metal layer) include but are not limited to Al (aluminum), Nb (niobium), Ta (tantalum), TiN (titanium nitride), In (indium), etc.; according to some embodiments of the present invention, the materials of the first superconducting metal layer and the second superconducting metal layer are both Ta.

[0092] In some embodiments, the thickness of the second superconducting metal layer is 0.1-2 μm, which can be 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 1 μm, 1.5 μm, or 2 μm.

[0093] According to some embodiments of the present invention, when an isolation layer is formed on the second superconducting metal layer, the thickness of the second superconducting metal layer may be 0.1-0.5 μm, and further may be 0.2 μm.

[0094] According to some embodiments of the present invention, when the second superconducting metal layer is etched to obtain an isolation layer, the thickness of the second superconducting metal layer before etching can be selected to be 0.8-2 μm; after etching, the thickness of the non-isolation layer region of the second superconducting metal layer is 0.1-0.5 μm, and can further be selected to be 0.2 μm.

[0095] The present invention does not impose any special restrictions on the shape and structure of the isolation layer and the connection layer, as long as they can isolate each bit and control line, and can be adaptively adjusted according to the circuit structure of the quantum chip.

[0096] In some embodiments, the thickness of the isolation layer is 0.5-5 μm, which can be 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm.

[0097] According to some embodiments of the present invention, when an isolation layer is generated on the second superconducting metal layer, the thickness of the isolation layer can be further selected to be 2 μm or 3 μm; for example, when the materials of the isolation layer and the connecting layer are different, the thickness of the isolation layer can be selected to be 2 μm, and when the materials of the isolation layer and the connecting layer are the same, the thickness of the isolation layer can be selected to be 3 μm.

[0098] In some embodiments, the thickness of the connecting layer is 0.5-10 μm (before the first chip and the second chip are fixedly connected), which can be 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm.

[0099] According to some embodiments of the present invention, when an isolation layer is formed on the second superconducting metal layer and the isolation layer and the connection layer are made of the same material, the thickness of the connection layer before the first chip and the second chip are fixedly connected can be selected to be 3 μm.

[0100] In some embodiments, when the isolation layer and the connection layer are made of the same material but have different thicknesses, multiple photolithography and coating operations can be used to prepare isolation layers and connection layers of different thicknesses.

[0101] According to some embodiments of the present invention, when the second superconducting metal layer is etched to obtain the isolation layer, the thickness of the isolation layer is 0.3-2 μm, and may further be 1 μm.

[0102] The present invention does not impose any special restrictions on the selection of photoresist, photolithography equipment, and photolithography process, as long as the purpose of photolithography patterning can be achieved.

[0103] According to some embodiments of the present invention, the photoresist includes a positive photoresist; the positive photoresist may include AZ6130, AZ6112, etc.

[0104] In some embodiments, when forming an isolation layer or a connection layer, a layer of pre-coating glue may be applied before applying the photoresist to optimize the development effect; further optionally, the pre-coating glue may include LOR10A and LOR20A.

[0105] According to some embodiments of the present invention, the present invention uses a developer to develop the sample, and the developer can be a 1-5 wt % TMAH (tetramethylammonium hydroxide) aqueous solution.

[0106] According to some embodiments of the present invention, the steps of preparing the first chip structure include:

[0107] growing a first superconducting metal layer on a first substrate;

[0108] performing photolithographic patterning on the first superconducting metal layer to obtain a superconducting circuit layer;

[0109] Continue with the photolithography process to obtain a Josephson junction, forming a quantum chip circuit, and thus obtain the first chip.

[0110] According to some embodiments of the present invention, the step of preparing the superconducting metal layer at least includes: defining the graphic structure of the superconducting circuit layer by photolithography and development operations, and then etching to obtain the superconducting circuit layer structure.

[0111] According to some embodiments of the present invention, the preparation steps of the Josephson junction include at least: defining the Josephson junction pattern by electron beam lithography (EBL) processing, evaporating a superconducting metal film of appropriate thickness along direction 1 in the target area of ​​the Josephson junction, and stabilizing it in a pure O2 gas pressure environment; then evaporating a superconducting metal film of appropriate thickness along direction 2, and stabilizing it in a pure O2 gas pressure environment to obtain a Josephson junction.

[0112] The present invention does not impose any special restrictions on Direction 1 and Direction 2, as long as they can achieve the purpose of preparing the Josephson junction. They can be specifically set according to the chip structure; for example, Direction 1 is the horizontal direction, and Direction 2 is the vertical direction.

[0113] In some embodiments, the thickness of the first superconducting metal layer is 0.1-0.5 μm, which can be 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, or 0.5 μm; further, 0.2 μm can be selected.

[0114] The present invention does not impose any particular limitation on the growth method and growth equipment of the superconducting metal, as long as the growth purpose can be achieved; for example, a multi-cavity evaporation device or a multi-cavity magnetron device.

[0115] In some embodiments, a pressure welding operation is used to connect the first chip structure and the second chip structure. According to some embodiments of the present invention, the step of connecting the first chip structure and the second chip structure by pressure welding includes:

[0116] The second chip is flipped vertically and aligned horizontally with the first chip, so that the connection layer and the isolation layer are both connected to the first superconducting metal layer, and the isolation layer independently isolates the devices of the quantum chip circuit; the first chip and the second chip are fixedly connected to obtain a finished superconducting quantum flip chip.

[0117] The height of the isolation layer is recorded as h1, the height of the connection layer is recorded as h2, and the distance between the first superconducting metal layer and the second superconducting metal layer is recorded as h3.

[0118] In some embodiments, before the first chip and the second chip are fixedly connected, the condition h1≤h2 is satisfied.

[0119] In some embodiments, after the first chip and the second chip are fixedly connected, the following conditions are satisfied: h1 = h2 = h3.

[0120] The present invention does not impose any special limitation on the fixed connection method and implementation approach of the first chip and the second chip, such as pressure welding.

[0121] According to some embodiments of the present invention, the first chip structure and the second chip structure are fixedly connected by pressure welding, and the height of the isolation layer is used to control the bonding distance between the first chip and the second chip after pressure welding, that is, h 3＝ h1.

[0122] In some embodiments, the pressure during pressure welding is 5-15 kg and the temperature is 110-130°C.

[0123] In some embodiments, the first chip and the second chip are plasma cleaned before being fixedly connected to each other, so as to remove the surface oxide layer of the first chip and the second chip, protect the metal surface, and inhibit metal oxidation.

[0124] The present invention does not impose any special restrictions on the material of the substrate. Any substrate commonly used in the art that can achieve the processing purpose (mechanical support, providing a growth interface) can be used; for example, intrinsic silicon, sapphire (the main component is aluminum oxide), high-resistance silicon, amorphous silicon, silicon carbide, etc. can be selected according to actual design needs.

[0125] In some embodiments, cleaning can be selected after each step to remove metal surface oxides, excess photoresist, excess metal, impurities, etc.; the cleaning method is not particularly limited as long as it can achieve the cleaning purpose, such as Ar ion cleaning, H2 plasma cleaning, ultrasonic cleaning, solvent cleaning, etc.; the solvent can be NMP (N-methylpyrrolidone), isopropyl alcohol, etc.

[0126] This invention addresses the problem of crosstalk between quantum bits in a quantum chip and proposes a novel quantum chip fabrication method. This method introduces an isolation layer and a connection layer into the chip structure. The connection layer enables electrical connection between the first and second chips, and acts as a limiting support. The isolation layer separates different circuit areas, preventing interference between bit signals and ensuring circuit stability and reliability. Furthermore, a flip-chip design is employed, with the superconducting circuit layer and Josephson junction positioned on the first chip and the isolation layer and connection layer positioned on the second chip. Pressure welding is then used to securely connect the first and second chips. This method avoids the negative impact of the processing on the bits and other devices on the quantum chip, maximizes the internal electromagnetic environment of the chip, and improves the stability and accuracy of signal transmission.

[0127] A fourth aspect of the present invention provides a quantum chip, comprising:

[0128] A first substrate comprising a first superconducting metal layer and a quantum chip circuit formed on the first superconducting metal layer;

[0129] A second substrate includes a second superconducting metal layer, and a connecting layer and an isolation layer formed on the second superconducting metal layer, the connecting layer is connected to the first superconducting metal layer, and the isolation layer is connected to the first superconducting metal layer at one end facing away from the second superconducting metal layer. The isolation layer is arranged corresponding to the quantum chip circuit to independently isolate the devices of the quantum chip circuit.

[0130] Optionally, the device includes a resonant cavity, a control line, a transmission line and a quantum bit.

[0131] Optionally, both the connecting layer and the isolation layer are made of superconducting metal material.

[0132] Optionally, the connecting layer and the isolation layer are made of the same or different materials.

[0133] Optionally, when the connecting layer and the isolation layer are made of the same material, the thickness of the isolation layer is greater than or equal to the thickness of the connecting layer.

[0134] In quantum chips, quantum bits (qubits) control their quantum states through Josephson junctions (composed of a superconductor, insulator, and superconductor). These bits typically operate under microwave signals in the GHz frequency band, and electromagnetic coupling between adjacent bits (such as capacitive coupling, inductive coupling, or microwave leakage) can lead to signal crosstalk. The present invention provides a connecting layer and an isolation layer made of superconducting metal on the second superconducting metal layer. By leveraging the near-zero resistance of superconducting metal, the high-frequency alternating electromagnetic field induces eddy currents on the surface of the superconducting isolation layer, further attenuating the signal penetration depth. Furthermore, the isolation layer, located between the first and second superconducting metal layers, covers the devices on the quantum chip circuit, providing independent, three-dimensional protection for each device and repelling external magnetic fields, forming a completely antimagnetic shielding layer to avoid signal crosstalk. When the electromagnetic field (such as microwaves or magnetic flux) of an adjacent bit attempts to penetrate the isolation layer, the superconducting current induces an opposing magnetic field, counteracting the effects of the external field. By setting up an isolation layer and utilizing the quantum properties of superconducting materials and their adaptability to low-temperature environments, signal crosstalk caused by factors such as microwaves, magnetic flux or capacitive coupling can be suppressed at the source, achieving independent isolation and shielding effects at the source, effectively avoiding the signal crosstalk problem when the number of quantum bits is large.

[0135] Furthermore, the present invention sets the connection layer and the isolation layer to work together to construct a multi-dimensional signal crosstalk suppression system. The isolation layer blocks the crosstalk caused by capacitance, inductance or magnetic flux leakage between quantum bits through the electromagnetic shielding characteristics of superconducting materials, and the connection layer forms an electromagnetic shielding cavity or a low-impedance path through the conductivity and geometric design of superconducting metals to solve the problem of external signal coupling. The closed area constructed by the connection layer in the quantum chip structure limits the external electromagnetic field to the periphery of the cavity, and the isolation layer further attenuates the residual field to below the sensitivity threshold of the quantum bit. Through the coordination of material properties, electromagnetic shielding mechanism and three-dimensional integration process, signal crosstalk is suppressed from two dimensions: internal near-field coupling and external far-field interference.

[0136] Unless otherwise specified, the raw materials and equipment used in the present invention are commercially available.

[0137] Example 1

[0138] like Figure 1 As shown, the first aspect of this embodiment provides a method for preparing a quantum chip, comprising: S1. providing a first chip structure

[0139] The first chip structure includes a first substrate, on which a first superconducting metal layer and a quantum chip circuit formed on the first superconducting metal layer are formed.

[0140] In some embodiments, the step of preparing the first chip structure includes:

[0141] S1.1 Place the first substrate (clean sapphire substrate) in a magnetron sputtering device, heat to 800°C, and wait until the vacuum degree is ≤1e -9 A Ta film with a thickness of 0.2 μm was grown at torr to obtain the first superconducting metal layer;

[0142] S1.2 Coat the surface of the first superconducting metal layer with a thickness of 1.2 μm of positive photoresist (AZ6112) at a controlled rotation speed of 4000 rpm; after coating, transfer to a hot plate and bake at 100°C for 2 minutes; place a mask on the surface of the first superconducting metal layer coated with the positive photoresist, use a stepper photolithography machine to expose for 0.2 seconds, then use a developer (2.38 wt% TMAH aqueous solution) for 40 seconds, remove and transfer to a hot plate and bake at 100°C for 2 minutes to complete the graphic structure definition of the superconducting circuit layer;

[0143] S1.3 etching the non-superconducting circuit layer region of the first superconducting metal layer, cleaning and removing excess photoresist, and preparing a superconducting circuit layer;

[0144] S1.4 Perform EBL lithography on the first superconducting metal layer to define the Josephson junction pattern; transfer to a dual-angle evaporation device for Ar ion cleaning to remove the metal oxide layer; evaporate an Al film with a thickness of 50nm along direction 1 in the target area of ​​the Josephson junction, place it in a pure O2 pressure environment of 10Torr and keep it for 10 minutes, then evaporate an Al film with a thickness of 100nm along direction 2, place it in a pure O2 pressure environment of 20Torr and keep it for 20 minutes; remove the photoresist and excess metal, and obtain the first chip structure containing the quantum chip circuit after cleaning.

[0145] In step S2.4 of this embodiment, direction 1 is the horizontal direction and direction 2 is the vertical direction.

[0146] S2. Providing a second chip structure. The steps of preparing the second chip structure include:

[0147] S2.1 providing a second substrate, and growing a second superconducting metal layer on the second substrate;

[0148] In some embodiments, the second superconducting metal layer is grown on the second substrate by evaporation. For example, the second substrate (clean sapphire substrate) is placed in a magnetron sputtering device, heated to 800°C, and then the vacuum degree is ≤1e - 9 A Ta film with a thickness of 0.2 μm is grown at torr to obtain the second superconducting metal layer:

[0149] S2.2 performing photolithographic patterning on the second superconducting metal layer and forming an isolation layer on the second superconducting metal layer;

[0150] In some embodiments, the photolithographic patterning of the second superconducting metal layer and the generation of an isolation layer on the second superconducting metal layer include coating a photoresist on the second superconducting metal layer, photolithographically developing to define an isolation layer area; and evaporating a first superconducting metal and removing the photoresist in areas other than the isolation layer to obtain the isolation layer.

[0151] In some embodiments, a positive photoresist is used for photolithography patterning to construct a pattern structure of the isolation layer. For example, a pre-coated glue (LOR10A) with a thickness of 2 μm is coated on the surface of the second superconducting metal layer, which is transferred to a hot plate and baked at 120°C for 2 minutes, and then a positive photoresist (AZ6130) with a thickness of 3 μm is coated, a mask is placed on the surface of the second superconducting metal layer coated with the positive photoresist, a stepper photolithography machine is used to expose for 0.5 seconds, and then a developer (2.38 wt% TMAH aqueous solution) is used to treat for 45 seconds, and after being taken out, it is transferred to a hot plate and baked at 100°C for 2 minutes to complete the graphic structure definition of the isolation layer; after baking, it is transferred to an electron beam coating device, and the metal surface oxide layer is removed by Ar ion cleaning, and then an Al film with a thickness of 2 μm (corresponding to the first superconducting metal) is evaporated; after evaporation, it is transferred to NMP at 90°C and allowed to stand for 4 hours to remove the glue and strip off the photoresist and excess metal, and then ultrasonically cleaned with isopropyl alcohol for 3 minutes, replaced with isopropyl alcohol and cleaned again, taken out and blown dry with N2 to complete the preparation of the isolation layer;

[0152] S2.3 continuing to perform photolithographic patterning on the isolation layer and the exposed second superconducting metal layer, and forming a connection layer in the region of the second superconducting metal layer other than the isolation layer;

[0153] In some embodiments, the continuing to perform photolithographic patterning on the isolation layer and the exposed second superconducting metal layer and generating a connecting layer in the area of ​​the second superconducting metal layer other than the isolation layer includes: after obtaining the isolation layer, coating photoresist on the isolation layer and the exposed partial area of ​​the second superconducting metal layer, and photolithographic development to define the connecting layer area; evaporating the second superconducting metal, removing the photoresist in the area other than the connecting layer, and obtaining the connecting layer.

[0154] In some embodiments, a positive photoresist is used for photolithography patterning to construct a pattern structure of the connection layer. For example, a pre-coated glue (LOR20A) with a thickness of 4 μm is coated on the surface of the second superconducting metal layer, transferred to a hot plate and baked at 120°C for 2 minutes, and then a positive photoresist (AZ6130) with a thickness of 3 μm is coated. A mask is placed on the surface of the second superconducting metal layer coated with the positive photoresist, exposed for 0.5 seconds using a stepper lithography machine, and then treated with a developer (2.38 wt% TMAH aqueous solution) for 45 seconds. After being taken out, it is transferred to a hot plate and baked at 100°C for 2 minutes to complete the graphic structure definition of the connection layer; after baking, it is transferred to an electron beam coating device, and the metal surface oxide layer is removed by Ar ion cleaning, and then an In film with a thickness of 3 μm (corresponding to the second superconducting metal) is evaporated; after evaporation, it is transferred to NMP at 90°C and allowed to stand for 4 hours to remove the glue and strip off the photoresist and excess metal, and then ultrasonically cleaned with isopropyl alcohol for 3 minutes, replaced with isopropyl alcohol for cleaning again, taken out and blown dry with N2 to complete the preparation of the connection layer; a second chip structure containing an isolation layer and a connection layer is obtained.

[0155] In this embodiment, the first superconducting metal is Al, and the second superconducting metal is In, that is, the isolation layer and the connection layer are made of different materials.

[0156] S3. Connecting the first chip structure to the second chip structure, so that the connecting layer and the isolation layer are both connected to the first superconducting metal layer, and the isolation layer independently isolates the devices of the quantum chip circuit.

[0157] In some embodiments, a bonding operation is used to connect the first chip structure to the second chip structure. For example:

[0158] The first chip structure and the second chip structure are cleaned with H2 plasma for 10 minutes under normal pressure; then, the second chip is flipped vertically under the protection of N2 atmosphere and horizontally aligned with the second chip, so that the connecting layer and the isolation layer are connected to the first superconducting metal layer, and the isolation layer forms an independent isolation for the devices of the quantum chip circuit; the first chip and the second chip are pressure-welded using a flip-chip welding device, with a pressure of 10 kg and a temperature of 120°C during pressure welding, and maintained for 5 minutes to obtain a finished superconducting quantum flip-chip product.

[0159] After pressure welding, the bonding distance between the first chip and the second chip is 2 μm.

[0160] A second aspect of this embodiment provides a quantum chip, including:

[0161] A first substrate comprising a first superconducting metal layer and a quantum chip circuit formed on the first superconducting metal layer;

[0162] A second substrate includes a second superconducting metal layer, and a connecting layer and an isolation layer formed on the second superconducting metal layer, the connecting layer is connected to the first superconducting metal layer, and the isolation layer is connected to the first superconducting metal layer at one end facing away from the second superconducting metal layer. The isolation layer is arranged corresponding to the quantum chip circuit to independently isolate the devices of the quantum chip circuit.

[0163] The device includes a resonant cavity, a control line, a transmission line and a quantum bit.

[0164] The connection layer is made of superconducting metal In, and the isolation layer is made of superconducting metal Al.

[0165] The height of the isolation layer is denoted as h1, the height of the connection layer is denoted as h2, and the distance between the second superconducting metal layer and the first superconducting metal layer is denoted as h3.

[0166] After the first chip and the second chip are fixedly connected, the following conditions are satisfied: h1 = h2 = h3.

[0167] The schematic diagram of the structure of the quantum chip is shown in Figure 2 (In the figure, 1, first superconducting metal layer, 2, second superconducting metal layer, 3, isolation layer, 4, connection layer, 5, superconducting circuit layer, 6, Josephson junction).

[0168] The preparation method provided in this embodiment adopts the method of first evaporating an Al film on the surface of the second superconducting metal layer to prepare an isolation layer, and then evaporating an In film on the non-isolation layer area of ​​the second superconducting metal layer to prepare a connection layer, which effectively avoids bit signal crosstalk. By selectively forming a composite structure of an Al-based isolation layer and an In-based connection layer on the surface of the second superconducting metal layer, the Al-based isolation layer suppresses the near-field coupling between adjacent quantum bits through superconducting anti-magnetism, and the In-based connection layer constructs a low-impedance interconnection channel through plastic deformation bonding, achieving omnidirectional anti-crosstalk coverage to ensure normal coupling, reading, and manipulation capabilities between circuit devices. At the same time, the isolation layer and the connection layer are independently prepared on the second chip, the quantum circuit is constructed on the first chip, and the architecture design for connection is then connected using pressure welding technology. This can avoid the negative impact of the processing operations of the isolation layer and the connection layer on the device to the greatest extent, and ensure the performance of the chip.

[0169] Example 2

[0170] like Figure 3 As shown, the first aspect of this embodiment provides a method for preparing a quantum chip, comprising:

[0171] S1. Providing a first chip structure

[0172] The first chip structure includes a first substrate, on which a first superconducting metal layer and a quantum chip circuit formed on the first superconducting metal layer are formed.

[0173] In some embodiments, the step of preparing the first chip structure is the same as step S1 in Example 1.

[0174] S2. Providing a second chip structure. The steps of preparing the second chip structure include:

[0175] S2.1 providing a second substrate, and growing a second superconducting metal layer on the second substrate;

[0176] In some embodiments, the second superconducting metal layer is grown on the second substrate by evaporation. For example, the second substrate (clean sapphire substrate) is placed in a magnetron sputtering device, heated to 800°C, and then the vacuum degree is ≤1e - 9 A Ta film with a thickness of 0.2 μm is grown at torr to obtain the second superconducting metal layer:

[0177] S2.2 performing photolithographic patterning on the second superconducting metal layer, and forming an isolation layer and a connection layer on the second superconducting metal layer;

[0178] In some embodiments, the photolithographic patterning of the second superconducting metal layer and the generation of an isolation layer and a connection layer on the second superconducting metal layer include coating a photoresist on the second superconducting metal layer, photolithographic development to define the isolation layer and connection layer areas; evaporating a superconducting metal, removing the photoresist in the non-isolation layer and connection layer areas on the second superconducting metal layer, and obtaining the isolation layer and the connection layer.

[0179] In some embodiments, a positive photoresist is used for photolithographic patterning to construct a graphic structure of the isolation layer and the connection layer. For example, a pre-coated glue (LOR20A) with a thickness of 4 μm is coated on the surface of the second superconducting metal layer, transferred to a hot plate at 120°C and baked for 2 minutes, and then a positive photoresist (AZ6130) with a thickness of 3 μm is coated. A mask is placed on the surface of the second superconducting metal layer coated with the positive photoresist, and a stepper lithography machine is used to expose for 0.5 seconds, and then a developer (2.38 wt% TMAH aqueous solution) is used for 45 seconds. After being taken out, it is transferred to a hot plate at 100°C and baked for 2 minutes to complete the graphic structure of the isolation layer and the connection layer. Structure definition; after baking, transfer to electron beam coating equipment, remove the metal surface oxide layer by Ar ion cleaning, and then evaporate a 3μm thick In film (corresponding to superconducting metal); after evaporation, transfer to 90℃ NMP and let it stand for 4h to remove the photoresist and excess metal, then use isopropyl alcohol ultrasonic cleaning for 3min, replace isopropyl alcohol and clean again, take out and blow dry with N2 to complete the preparation of isolation layer and connection layer (that is, the preparation operations of isolation layer and formation of connection layer are carried out simultaneously); obtain the second chip structure containing isolation layer and connection layer.

[0180] In this embodiment, the material of the superconducting metal is In, that is, the isolation layer and the connection layer are made of the same material.

[0181] S3. Connecting the first chip structure to the second chip structure, so that the connecting layer and the isolation layer are both connected to the first superconducting metal layer, and the isolation layer independently isolates the devices of the quantum chip circuit.

[0182] In some embodiments, a pressure welding operation is used to connect the first chip and the second chip, and the preparation steps are the same as step S3 of Example 1.

[0183] After pressure welding, the bonding distance between the first chip and the second chip is 2 μm.

[0184] A second aspect of this embodiment provides a quantum chip, and the chip structure is the same as that of embodiment 1.

[0185] The preparation method provided in this embodiment prepares the isolation layer and the connection layer at the same time, and is mainly applicable to the case where the material and thickness requirements of the isolation layer and the connection layer are the same. During operation, photolithography patterning is performed on the surface of the second superconducting metal layer, and the graphic structure of the isolation layer and the connection layer is constructed at the same time, and then the In film is evaporated to obtain the isolation layer and the connection layer. The In film of this scheme plays the dual role of isolation layer and connection layer, which can not only isolate and shield the signal crosstalk between independent components, but also construct a low-impedance interconnection channel. The use of a simple second chip preparation process combined with pressure welding technology can avoid the negative impact of the processing operations of the isolation layer and the connection layer on the device to the greatest extent, effectively avoid bit signal crosstalk while improving processing efficiency, improve chip performance, and facilitate implementation.

[0186] Example 3

[0187] like Figure 4 As shown, the first aspect of this embodiment provides a method for preparing a quantum chip, comprising:

[0188] S1. Providing a first chip structure

[0189] The first chip structure includes a first substrate, on which a first superconducting metal layer and a quantum chip circuit formed on the first superconducting metal layer are formed.

[0190] In some embodiments, the step of preparing the first chip structure is the same as step S1 in Example 1.

[0191] S2. Providing a second chip structure. The steps of preparing the second chip structure include:

[0192] S2.1 providing a second substrate, and growing a second superconducting metal layer on the second substrate;

[0193] In some embodiments, the second superconducting metal layer is grown on the second substrate by evaporation. For example, the second substrate (clean sapphire substrate) is placed in a magnetron sputtering device, heated to 800°C, and then the vacuum degree is ≤1e - 9 A Ta film with a thickness of 1.2 μm was grown at torr to obtain the second superconducting metal layer:

[0194] S2.2 performing photolithographic patterning on the second superconducting metal layer, and etching the second superconducting metal layer to obtain an isolation layer;

[0195] In some embodiments, the photolithographic patterning of the second superconducting metal layer and etching the second superconducting metal layer to obtain an isolation layer include coating a photoresist on the second superconducting metal layer, photolithographically developing to define an isolation layer area; and etching a portion of the second superconducting metal layer corresponding to the isolation layer area to obtain the isolation layer.

[0196] In some embodiments, a positive photoresist is used for photolithographic patterning to construct a graphic structure of the isolation layer. For example, a positive photoresist (AZ6112) with a thickness of 1.2 μm is coated on the surface of the second superconducting metal layer, transferred to a hot plate and baked at 100°C for 2 minutes, a mask is placed on the surface of the second superconducting metal layer coated with the positive photoresist, exposed for 0.2 seconds using a stepper photolithography machine, and then treated with a developer (2.38 wt% TMAH aqueous solution) for 40 seconds. After being removed, the mask is transferred to a hot plate and baked at 100°C for 2 minutes to complete the graphic structure definition of the isolation layer; the non-isolation layer area of ​​the second superconducting metal layer is partially etched to make the bottom thickness of the second superconducting metal layer 0.2 μm, completing the preparation of the isolation layer (the thickness of the isolation layer is 1 μm); the photoresist is cleaned and removed;

[0197] S2.3: Continue to perform photolithographic patterning on the isolation layer and the exposed second superconducting metal layer, and generate a connection layer in the area of ​​the second superconducting metal layer other than the isolation layer.

[0198] In some embodiments, the continuing to perform photolithographic patterning on the isolation layer and the exposed second superconducting metal layer to generate a connecting layer in the area of ​​the second superconducting metal layer other than the isolation layer includes: after obtaining the isolation layer, coating photoresist on the isolation layer and the exposed partial area of ​​the second superconducting metal layer, and photolithographic development to define the connecting layer area; evaporating superconducting metal, removing the photoresist in the area other than the connecting layer, and obtaining the connecting layer.

[0199] In some embodiments, a positive photoresist is used for photolithography patterning to construct a pattern structure of the connection layer. For example, a pre-coated glue (LOR10A) with a thickness of 2 μm is coated on the surface of the second superconducting metal layer, transferred to a hot plate and baked at 120°C for 2 minutes, and then a positive photoresist (AZ6130) with a thickness of 3 μm is coated, and a mask is placed on the surface of the second superconducting metal layer coated with the positive photoresist. A stepper lithography machine is used to expose for 0.5 seconds, and then a developer (2.38 wt% TMAH aqueous solution) is used to treat for 45 seconds. After being taken out, it is transferred to a hot plate and baked at 100°C for 2 minutes to complete the graphic structure definition of the connection layer; after baking, it is transferred to an electron beam coating device, and the metal surface oxide layer is removed by Ar ion cleaning, and then an In film with a thickness of 2 μm (corresponding to the superconducting metal) is evaporated; after evaporation, it is transferred to NMP at 90°C and allowed to stand for 4 hours to remove the glue and strip off the photoresist and excess metal, and then ultrasonically cleaned with isopropyl alcohol for 3 minutes, replaced with isopropyl alcohol for cleaning again, taken out and blown dry with N2 to complete the preparation of the connection layer; a second chip structure containing an isolation layer and a connection layer is obtained.

[0200] In this embodiment, the first superconducting metal is Al, and the second superconducting metal is In, that is, the isolation layer and the connection layer are made of different materials.

[0201] S3. Connecting the first chip structure to the second chip structure, so that the connecting layer and the isolation layer are both connected to the first superconducting metal layer, and the isolation layer independently isolates the devices of the quantum chip circuit.

[0202] In some embodiments, a pressure welding operation is used to connect the first chip and the second chip, which is the same as step S3 of Example 1.

[0203] After pressure welding, the bonding distance between the first chip and the second chip is 2 μm.

[0204] A second aspect of this embodiment provides a quantum chip, and the chip structure is the same as that of embodiment 1.

[0205] The quantum chips prepared in Examples 1-3 are all 20-bit superconducting quantum chips.

[0206] The preparation method provided in this embodiment adopts a method of first etching the second superconducting metal layer to form an isolation layer, and then vapor-depositing an In film in the non-isolation layer area of ​​the second superconducting metal layer to prepare a connection layer, which effectively avoids bit signal crosstalk. In this solution, there is no need to perform the isolation layer and the connection layer vapor deposition operations in sequence, and it is suitable for situations where the thickness of the second superconducting metal layer is relatively large. During operation, the second superconducting metal layer is directly etched to form a convex structure to generate an isolation layer structure, that is, the second superconducting metal layer plays a dual role of conductive foundation and isolation shielding. This solution can also effectively avoid bit signal crosstalk, and the process has a large operating space, which is convenient for flexibly adjusting the formation method of the isolation layer according to the thickness requirements of the component, and has strong operability.

[0207] The series of detailed descriptions listed in this invention are merely specific descriptions of feasible implementation methods of this technology and are not intended to limit the scope of protection of this application. Any equivalent implementation methods or modifications that do not depart from the technical spirit of this application should be included in the scope of protection of this application. In addition, the relational terms in this article (such as the first superconducting metal layer and the second superconducting metal layer, step S1 and step S2) are only used to distinguish one entity / operation from another entity / operation, and do not necessarily require or imply that there is an actual relationship or order between these entities / operations; in specific implementations, operations can be performed based on the principle of meeting actual usage requirements.

Claims

1. A method for preparing a quantum chip, characterized in that: include: Providing a first chip structure, the first chip structure comprising a first substrate, a first superconducting metal layer formed on the first substrate, and a quantum chip circuit formed on the first superconducting metal layer; A second chip structure is provided, and the steps of preparing the second chip structure include: providing a second substrate; growing a second superconducting metal layer on the second substrate; performing photolithographic patterning on the second superconducting metal layer and forming an isolation layer on the second superconducting metal layer; Continue to perform photolithographic patterning on the isolation layer and the exposed second superconducting metal layer, and generate a connection layer in the area of ​​the second superconducting metal layer other than the isolation layer; The first chip structure is connected to the second chip structure, so that the connection layer and the isolation layer are both connected to the first superconducting metal layer, and the isolation layer independently isolates the devices of the quantum chip circuit.

2. The method for preparing a quantum chip according to claim 1, wherein: The first chip structure and the second chip structure are connected by a pressure welding operation.

3. The method for preparing a quantum chip according to claim 1, wherein: The performing of photolithographic patterning on the second superconducting metal layer and forming an isolation layer on the second superconducting metal layer comprises coating a photoresist on the second superconducting metal layer and performing photolithographic development to define an isolation layer region; A first superconducting metal is evaporated, and the photoresist in the area other than the isolation layer is removed to obtain the isolation layer.

4. The method for preparing a quantum chip according to claim 3, wherein: Continuing to perform photolithographic patterning on the isolation layer and the exposed second superconducting metal layer and generating a connection layer in a region of the second superconducting metal layer other than the isolation layer comprises, after obtaining the isolation layer, coating a photoresist on the isolation layer and a portion of the exposed second superconducting metal layer, and performing photolithographic development to define a connection layer region; A second superconducting metal is evaporated, and the photoresist in the area other than the connecting layer is removed to obtain the connecting layer.

5. The method for preparing a quantum chip according to claim 4, characterized in that: The first superconducting metal and the second superconducting metal are made of the same or different materials.

6. A method for preparing a quantum chip, characterized in that: include: Providing a first chip structure, the first chip structure comprising a first substrate, a first superconducting metal layer formed on the first substrate, and a quantum chip circuit formed on the first superconducting metal layer; A second chip structure is provided, and the steps of preparing the second chip structure include: providing a second substrate; growing a second superconducting metal layer on the second substrate; performing photolithographic patterning on the second superconducting metal layer, and forming an isolation layer and a connection layer on the second superconducting metal layer; The first chip structure is connected to the second chip structure, so that the connection layer and the isolation layer are both connected to the first superconducting metal layer, and the isolation layer independently isolates the devices of the quantum chip circuit.

7. The method for preparing a quantum chip according to claim 6, wherein: The performing photolithographic patterning on the second superconducting metal layer and forming the isolation layer and the connection layer on the second superconducting metal layer comprises coating photoresist on the second superconducting metal layer and performing photolithographic development to define the isolation layer and the connection layer regions; The superconducting metal is evaporated, and the photoresist in the non-isolation layer and connection layer regions on the second superconducting metal layer is removed to obtain the isolation layer and the connection layer.

8. A method for preparing a quantum chip, characterized in that: include: Providing a first chip structure, the first chip structure comprising a first substrate, a first superconducting metal layer formed on the first substrate, and a quantum chip circuit formed on the first superconducting metal layer; A second chip structure is provided, and the steps of preparing the second chip structure include: providing a second substrate; growing a second superconducting metal layer on the second substrate; performing photolithographic patterning on the second superconducting metal layer, and etching the second superconducting metal layer to obtain an isolation layer; Continue to perform photolithographic patterning on the isolation layer and the exposed second superconducting metal layer, and generate a connection layer in the area of ​​the second superconducting metal layer other than the isolation layer; The first chip structure is connected to the second chip structure, so that the connection layer and the isolation layer are both connected to the first superconducting metal layer, and the isolation layer independently isolates the devices of the quantum chip circuit.

9. The method for preparing a quantum chip according to claim 8, wherein: The performing photolithographic patterning on the second superconducting metal layer and etching the second superconducting metal layer to obtain the isolation layer comprises coating photoresist on the second superconducting metal layer and performing photolithographic development to define an isolation layer region; A portion of the second superconducting metal layer is etched corresponding to the isolation layer region to obtain an isolation layer.

10. The method for preparing a quantum chip according to claim 9, wherein: Continuing to perform photolithographic patterning on the isolation layer and the exposed second superconducting metal layer to generate a connection layer in the region of the second superconducting metal layer other than the isolation layer includes coating photoresist on the isolation layer and the exposed region of the second superconducting metal layer after obtaining the isolation layer, and performing photolithographic development to define a connection layer region; The superconducting metal is evaporated, and the photoresist in the area other than the connecting layer is removed to obtain the connecting layer.

11. The method for preparing a quantum chip according to claim 9, wherein: The second superconducting metal layer and the superconducting metal are made of different materials.

12. A quantum chip, characterized in that: include: A first substrate comprising a first superconducting metal layer and a quantum chip circuit formed on the first superconducting metal layer; A second substrate includes a second superconducting metal layer, and a connecting layer and an isolation layer formed on the second superconducting metal layer, the connecting layer is connected to the first superconducting metal layer, and the isolation layer is connected to the first superconducting metal layer at one end facing away from the second superconducting metal layer. The isolation layer is arranged corresponding to the quantum chip circuit to independently isolate the devices of the quantum chip circuit.

13. The quantum chip according to claim 12, characterized in that When the connecting layer and the isolation layer are made of the same material, the thickness of the isolation layer is greater than or equal to the thickness of the connecting layer.

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