Gate drive circuit, display substrate and display device

Abstract

The invention discloses a gate drive circuit, a display substrate and a display device. The gate drive circuit comprises an output circuit (300) disposed on a silicon substrate, the output circuit (300) comprising at least one level shifter configured to perform voltage domain conversion on a target timing and at least one row drive intensifier configured to perform voltage domain conversion on the target timing, the row driving intensifier is configured to enhance the converted signal and then output the signal to a scanning signal line of the display area, at least one input signal of the row driving intensifier is provided by the level converter, and the row driving intensifier is arranged on the side, close to the display area, of the level converter.

Description

Gate driving circuit, display substrate and display device

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a gate driving circuit, a display substrate, and a display device.

[0002] Micro-OLEDs (Micro Organic Light-Emitting Diodes) are a type of microdisplay that has been developed in recent years, with silicon-based OLEDs being one of them. Silicon-based OLEDs are a novel display technology that combines semiconductor manufacturing processes with OLED display technology, using wafers as substrates to manufacture OLED devices. By combining the advantages of both semiconductor manufacturing processes and OLED display technology, silicon-based OLEDs not only offer high pixel density (PPI), but also high brightness, low power consumption, fast response time, wide color gamut, and excellent thermal stability.

[0003]

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, an embodiment of the present disclosure provides a gate drive circuit, including an output circuit arranged on a silicon substrate, the output circuit including at least one level converter and at least one row driver enhancer, the level converter being configured to perform voltage domain conversion on a target timing, the row driver enhancer being configured to enhance the converted signal and output it to a scan signal line of a display area, at least one input signal of the row driver enhancer being provided by the level converter, and the row driver enhancer being arranged on a side of the level converter close to the display area.

[0006] In an exemplary embodiment, the level converter includes at least a first inverter, a first level conversion unit, and a second level conversion unit; an input end of the first level conversion unit is connected to an input end of the first inverter, and an output end of the first level conversion unit is connected to the row driver enhancer; an input end of the second level conversion unit is connected to an output end of the first inverter, and an output end of the second level conversion unit is connected to the row driver enhancer; the first level conversion unit is arranged on a side of the first inverter close to the display area, and the second level conversion unit is arranged on a side of the first level conversion unit close to the display area.

[0007] In an exemplary embodiment, the level converter further includes a selection output unit, which is connected to the output end of the first level conversion unit and the output end of the second level conversion unit, respectively, and the selection output unit is configured to select and output the output signal of the first level conversion unit or the output signal of the second level conversion unit under the control of a selection input signal.

[0008] In an exemplary embodiment, the first inverter includes a first P-type transistor and a first N-type transistor arranged on the second direction side of the first P-type transistor; the first level conversion unit includes a first P-type transistor unit arranged on the first direction side of the first P-type transistor and a first N-type transistor unit arranged on the second direction side of the first P-type transistor unit, and the second level conversion unit includes a second P-type transistor unit arranged on the first direction side of the first P-type transistor unit and a second N-type transistor unit arranged on the second direction side of the second P-type transistor unit, and the first direction and the second direction intersect; the first P-type transistor unit includes a second P-type transistor to a seventh P-type transistor arranged on the first direction side of the first P-type transistor and arranged in sequence along the first direction; the second P-type transistor unit includes a second P-type transistor to a seventh P-type transistor arranged on the first direction side of the seventh P-type transistor and arranged in sequence along the first direction The eighth P-type transistor to the thirteenth P-type transistor are arranged in sequence in the direction; the first N-type transistor unit includes a second N-type transistor arranged on the second direction side of the seventh P-type transistor, and the second N-type transistor unit includes a third N-type transistor arranged on the second direction side of the eighth P-type transistor; at least one P-type transistor includes at least a P-type active layer, and at least one N-type transistor includes at least an N-type active layer, and the P-type active layers of the second P-type transistor to the thirteenth P-type transistor are an integrated structure connected to each other; the second P-type transistor to the seventh P-type transistor and the eighth P-type transistor to the thirteenth P-type transistor are symmetrical with respect to the active center line, and the second N-type transistor and the third N-type transistor are symmetrical with respect to the active center line, and the active center line is a straight line that bisects the P-type active layers of the second P-type transistor to the thirteenth P-type transistor in the first direction and extends along the second direction.

[0009] In an exemplary embodiment, at least one P-type transistor further includes a P-type gate electrode, and at least one N-type transistor further includes an N-type gate electrode; the P-type gate electrodes of the second P-type transistor to the seventh P-type transistor and the P-type gate electrodes of the eighth P-type transistor to the thirteenth P-type transistor are symmetrical with respect to the active center line, and the N-type gate electrode of the second N-type transistor and the N-type gate electrode of the third N-type transistor are symmetrical with respect to the active center line.

[0010] In an exemplary embodiment, at least one P-type transistor further includes a P-type source electrode and a P-type drain electrode, and at least one N-type transistor further includes an N-type source electrode and an N-type drain electrode; the P-type source electrodes of the second P-type transistor to the seventh P-type transistor and the P-type source electrodes of the eighth P-type transistor to the thirteenth P-type transistor are symmetrical with respect to the active center line, and the P-type drain electrodes of the second P-type transistor to the seventh P-type transistor and the P-type drain electrodes of the eighth P-type transistor to the thirteenth P-type transistor are symmetrical with respect to the active center line; the N-type source electrode of the second N-type transistor and the N-type source electrode of the third N-type transistor are symmetrical with respect to the active center line, and the N-type drain electrode of the second N-type transistor and the N-type drain electrode of the third N-type transistor are symmetrical with respect to the active center line.

[0011] In an exemplary embodiment, in the first direction, there is a voltage domain distance between an edge of the P-type drain electrode of the first P-type transistor close to a side of the second P-type transistor and an edge of the P-type source electrode of the second P-type transistor close to a side of the first P-type transistor, and the voltage domain distance is greater than or equal to 3.67 μm.

[0012] In an exemplary embodiment, the level converter further includes a first power line, a second power line, and a ground line, and the shapes of the first power line, the second power line, and the ground line are line-shaped or broken line-shaped extending along the first direction; the first power line is arranged on a side of the first P-type transistor to the thirteenth P-type transistor away from the first N-type transistor to the third N-type transistor, the second power line is arranged on a side of the second N-type transistor to the third N-type transistor away from the second P-type transistor to the thirteenth P-type transistor, and the ground line is arranged on a side of the first N-type transistor away from the first P-type transistor; a voltage line distance is provided between an edge of the second power line close to the ground line and an edge of the ground line close to the second power line, and the voltage line distance is greater than or equal to 5 μm.

[0013] In an exemplary embodiment, the row driver enhancer includes a plurality of transistor groups arranged in sequence along a first direction, at least one transistor group includes a P-type transistor and an N-type transistor arranged on one side of the P-type transistor in a second direction, and the first direction and the second direction intersect; the plurality of transistor groups form a first NAND gate, a first transmission gate, a second NAND gate, a second inverter, and an output unit arranged in sequence along a direction close to the display area, a first distance is provided between the transistor group in the second inverter and the transistor group in the output unit, a second distance is provided between two adjacent transistor groups in the first NAND gate, the first transmission gate, the second NAND gate, and the second inverter, the first distance is greater than the second distance, and the first distance and the second distance are both dimensions in the first direction.

[0014] In an exemplary embodiment, a first distance exists between the P-type transistor in the second inverter and the P-type transistor in the output unit, and a second distance exists between the first NAND gate, the first transmission gate, the second NAND gate, and two adjacent P-type transistors in the second inverter; and / or a first distance exists between the N-type transistor in the second inverter and the N-type transistor in the output unit, and a second distance exists between the first NAND gate, the first transmission gate, the second NAND gate, and two adjacent N-type transistors in the second inverter.

[0015] In an exemplary embodiment, a ratio of the first distance to the second distance is 0.7 to 0.8.

[0016] In an exemplary embodiment, the first distance is greater than or equal to 0.5 μm, and the second distance is greater than or equal to 0.36 μm.

[0017] In an exemplary embodiment, at least one P-type transistor includes a P-type active area, and at least one N-type transistor includes an N-type active area; a first distance exists between the P-type active area in the second inverter and the P-type active area in the output unit, and a second distance exists between two adjacent P-type active areas in the first NAND gate, the first transmission gate, the second NAND gate, and the second inverter; and / or a first distance exists between the N-type active area in the second inverter and the N-type active area in the output unit, and a second distance exists between two adjacent N-type active areas in the first NAND gate, the first transmission gate, the second NAND gate, and the second inverter.

[0018] In an exemplary embodiment, the gate driving circuit further includes a shift register circuit and a logic operation circuit disposed on a silicon substrate, wherein the shift register circuit is configured to generate a row-by-row shift timing according to a timing signal, and the logic operation circuit is configured to generate a target timing through a logic operation.

[0019] On the other hand, an embodiment of the present disclosure provides a display substrate, including a display area and a non-display area; the display area includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and at least one scanning signal line, and the scanning signal line is configured to provide a scanning signal to the connected pixel driving circuit; the non-display area includes a plurality of cascaded gate driving circuits, at least one gate driving circuit is connected to the scanning signal line in the display area, and at least one gate driving circuit includes the aforementioned gate driving circuit.

[0020] On the other hand, embodiments of the present disclosure provide a display device including the aforementioned display substrate.

[0021] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0022] The accompanying drawings are intended to facilitate understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of each component in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0023] FIG1 is a schematic structural diagram of a silicon-based OLED display device;

[0024] FIG2 is a schematic diagram of a planar structure of a display area in a silicon-based OLED display device;

[0025] FIG3 is a schematic diagram of the cross-sectional structure of a display area in a silicon-based OLED display device;

[0026] FIG4 is an equivalent circuit diagram of a pixel driving circuit;

[0027] FIG5 is a driving timing diagram of the pixel driving circuit shown in FIG4 ;

[0028] FIG6 is a schematic structural diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure;

[0029] FIG7 is a working principle diagram of a level converter according to an exemplary embodiment of the present disclosure;

[0030] FIG8 is a working principle diagram of a row drive enhancer according to an exemplary embodiment of the present disclosure;

[0031] FIG9 is an equivalent circuit diagram of a level converter according to an exemplary embodiment of the present disclosure;

[0032] FIG10 is an equivalent circuit diagram of a row driver enhancer according to an exemplary embodiment of the present disclosure;

[0033] FIG11 is an equivalent circuit diagram of an output circuit according to an exemplary embodiment of the present disclosure;

[0034] FIG12 is a schematic structural diagram of an output circuit according to an exemplary embodiment of the present disclosure;

[0035] 13A and 13B are schematic diagrams of the embodiment of the present disclosure after forming patterns of a deep N-well, an N-well region, and an active region;

[0036] 14A and 14B are schematic diagrams of an embodiment of the present disclosure after a gate conductive layer pattern is formed;

[0037] 15A and 15B are schematic diagrams of a P-type doping region pattern formed according to an embodiment of the present disclosure;

[0038] 16A and 16B are schematic diagrams of an embodiment of the present disclosure after forming an N-type doping region pattern;

[0039] FIG17 is a schematic diagram of an embodiment of the present disclosure after forming a second insulating layer pattern;

[0040] 18A and 18B are schematic diagrams of an embodiment of the present disclosure after forming a first conductive layer pattern;

[0041] FIG19 is a schematic diagram of an embodiment of the present disclosure after forming a third insulating layer pattern;

[0042] 20A and 20B are schematic diagrams of an embodiment of the present disclosure after forming a second conductive layer pattern;

[0043] FIG. 21 is an equivalent circuit diagram of another level shifter according to an exemplary embodiment of the present disclosure.

[0044] DESCRIPTION OF NUMERALS: 10—deep N-well region; 20—N-well region; 31—first P-type doping region; 32—second P-type doping region; 33—third P-type doping region; 34—fourth P-type doping region; 41—first N-type doping region; 42—second N-type doping region; 43—third N-type doping region; 44—fourth N-type doping region; 51—first power line; 52—second power line; 53—ground line; 100—shift register circuit; 101—silicon substrate; 102—driving circuit layer; 103—light-emitting structure layer; 104—first packaging layer; 105—color filter structure layer; 106—second packaging layer; 107—cover layer; 200—logic operation circuit; 201—first transmission gate; 300—output circuit; 301—first NAND gate; 302—second NAND gate; 401—first inverter; 402—second inverter; 500—select output unit; 501P—first P-type transistor unit; 501N—first N-type transistor unit; 502P—second P-type transistor unit; 502N—second N-type transistor unit; 503P—third P-type transistor unit; 503N—third N-type transistor unit.

[0045] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0046] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display device and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0047] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0048] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0049] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0050] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0051] In this specification, in order to distinguish the two electrodes of a transistor other than the gate electrode, one of the electrodes is directly described as the first electrode and the other as the second electrode. The first electrode can be the drain electrode and the second electrode can be the source electrode, or the first electrode can be the source electrode and the second electrode can be the drain electrode. In cases where transistors with opposite polarity are used or where the direction of current changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchangeable. Therefore, in this specification, the terms "source electrode" and "drain electrode" can be interchanged.

[0052] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0053] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0054] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0055] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0056] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0057] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0058] FIG1 is a schematic diagram of the structure of a silicon-based OLED display device. As shown in FIG1 , the silicon-based OLED display device may include a display area and a non-display area. The display area may include multiple scan signal lines, multiple data signal lines, and multiple sub-pixels Pxij forming multiple pixel rows and multiple pixel columns. The multiple scan signal lines are respectively arranged in the multiple pixel rows, and the multiple data signal lines are respectively arranged in the multiple pixel columns. Each sub-pixel Pxij may include at least a pixel driving circuit and a light-emitting device. The pixel driving circuit is configured to provide the current required for light emission to the connected light-emitting device. The pixel driving circuit of each sub-pixel Pxij may be connected to the scan signal line of the corresponding pixel row and the data signal line of the corresponding pixel column. The sub-pixel Pxij may refer to the sub-pixel in the i-th pixel row and the j-th pixel column. The pixel driving circuit of the sub-pixel Pxij is respectively connected to the i-th scan signal line and the j-th data signal line, where i and j may be natural numbers. The non-display area may include a display driver integrated circuit (DDIC), a gate driver (GD), and a data driver (SD). The display driver circuit may include at least a timing controller (TCON). The timing controller is configured to generate timing signals required by the gate driver, such as a start signal (STV) and a clock signal (CKV), and send the timing signals to the gate driver. The gate driver is respectively connected to a plurality of scan signal lines in the display area, and the gate driver is configured to provide the required timing signals (timing) to the connected pixel driver circuit to realize the display progressive scanning function. The data driver is respectively connected to a plurality of data signal lines in the display area, and the data driver is configured to provide the required data signals (data) to the connected pixel driver circuit to realize the switching and control of the display screen.

[0059] In one exemplary embodiment, a silicon-based OLED display device may utilize a single-chip display architecture ("One Chip"), integrating a gate driver, data driver, clock control unit, image processing unit, and storage unit on a single chip. A chip with a One Chip architecture includes both digital and analog components, making it a mixed-signal chip.

[0060] In another exemplary embodiment, the silicon-based OLED display device can be a dual-chip display architecture (Two Chip), in which the gate driving device and the data driving device are integrated in the display substrate, and the clock control unit, the image processing unit, the mobile industry processor interface (MIPI) and the storage unit are integrated in one chip, which is bonded to the display substrate through the COC process.

[0061] Figure 2 is a schematic diagram of the planar structure of a display area in a silicon-based OLED display device. As shown in Figure 2, the display area may include multiple pixel units P arranged in a matrix on a plane parallel to the display device. At least one pixel unit P may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 that emits a third color light. Each of the three sub-pixels may include a pixel driving circuit and a light-emitting device. The pixel driving circuit in the sub-pixel is respectively connected to a scan signal line and a data signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the display light-emitting device. The light-emitting device in the sub-pixel is connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0062] In an exemplary embodiment, the first subpixel P1 may be a red (R) subpixel emitting red light, the second subpixel P2 may be a blue (B) subpixel emitting blue light, and the third subpixel P3 may be a green (G) subpixel emitting green light.

[0063] In an exemplary embodiment, the shape of the sub-pixels can be any one or more of a triangle, square, rectangle, rhombus, trapezoid, parallelogram, pentagon, hexagon, and other polygons. The three sub-pixels can be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, a herringbone arrangement, etc., which is not limited in this disclosure. In other possible embodiments, the pixel unit can include four sub-pixels, which is not limited in this disclosure.

[0064] FIG3 is a schematic diagram of the cross-sectional structure of the display area in a silicon-based OLED display device, illustrating a structure that uses white light + color filter to achieve full color. As shown in FIG3 , in a direction perpendicular to the display device, the silicon-based OLED display device may include: a silicon substrate 101, a driving circuit layer 102 disposed on the silicon substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the silicon substrate 101, a first encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 away from the silicon substrate 101, a color filter structure layer 105 disposed on the side of the first encapsulation layer 104 away from the silicon substrate 101, a second encapsulation layer 106 disposed on the side of the color filter structure layer 105 away from the silicon substrate 101, and a cover layer 107 disposed on the side of the second encapsulation layer 106 away from the silicon substrate 101. In some possible implementations, the silicon-based OLED display device may include other film layers, which are not limited in this disclosure.

[0065] In an exemplary embodiment, the silicon substrate 101 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The driving circuit layer 102 may be prepared on the silicon substrate 101 by a silicon semiconductor process. The driving circuit layer 102 may include a plurality of circuit units. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is connected to a scanning signal line and a data signal line, respectively. The pixel driving circuit may include a plurality of transistors and a storage capacitor. FIG3 shows only one transistor as an example. The transistor may include a gate electrode G, a source electrode S, and a drain electrode D. The gate electrode G, the source electrode S, and the drain electrode D may be connected to corresponding connection electrodes through tungsten metal-filled vias (i.e., tungsten vias, W-vias), respectively, and may be connected to other electrical structures (such as traces, etc.) through the connection electrodes.

[0066] In an exemplary embodiment, the light-emitting structure layer 103 may include a plurality of light-emitting devices, each of which may include at least an anode, an organic light-emitting layer, and a cathode. The anode may be connected to the drain electrode D of the transistor via a connecting electrode, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the cathode is connected to the second power line. The organic light-emitting layer emits light under the drive of the anode and the cathode. In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, for a light-emitting device that emits white light, the organic light-emitting layers of all sub-pixels may be a common layer connected together.

[0067] In an exemplary embodiment, the first encapsulation layer 104 and the second encapsulation layer 106 can be encapsulated using a thin film encapsulation (TFE) method to ensure that external moisture cannot enter the light-emitting structure layer. The color filter structure layer 105 can include at least a red filter unit, a blue filter unit, and a green filter unit. The red filter unit is set in the red sub-pixel to filter the white light emitted by the light-emitting device into red light. The blue filter unit is set in the blue sub-pixel to filter the white light emitted by the light-emitting device into blue light. The green filter unit is set in the green sub-pixel to filter the white light emitted by the light-emitting device into green light. The cover layer 107 can be made of glass or a flexible plastic material such as colorless polyimide.

[0068] Figure 4 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 4, the pixel driving circuit has a 4T2C structure, which can include four transistors (a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4) and two storage capacitors (a first capacitor C1 and a second capacitor C2). The pixel driving circuit is connected to six signal lines (a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a data signal line DATA, a first power line VDD, and a second power line VSS).

[0069] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the third transistor T3, and the first end of the first capacitor C1, respectively. The second node N2 is connected to the second electrode of the second transistor T2, the first electrode of the third transistor T3, the second end of the first capacitor C1, and the first end of the second capacitor C2, respectively. The third node N3 is connected to the second electrode of the third transistor T3 and the second electrode of the fourth transistor T4, respectively.

[0070] In an exemplary embodiment, the first transistor T1 can be referred to as a write switch transistor, a gate electrode of the first transistor T1 is connected to the first scan signal line S1, a first electrode of the first transistor T1 is connected to the data signal line DATA, and a second electrode of the first transistor T1 is connected to the first node N1.

[0071] In an exemplary embodiment, the second transistor T2 is called a display switch transistor, a gate electrode of the second transistor T2 is connected to the second scan signal line S2, a first electrode of the second transistor T2 is connected to the first power line VDD, and a second electrode of the second transistor T2 is connected to the second node N2.

[0072] In an exemplary embodiment, the third transistor T3 may be referred to as a driver transistor, a gate electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to the second node N2, and a second electrode of the third transistor T3 is connected to the third node N3.

[0073] In an exemplary embodiment, the fourth transistor T4 can be referred to as a reset (Auto Zero) transistor, a gate electrode of the fourth transistor T4 is connected to the third scan signal line S3, a first electrode of the fourth transistor T4 is connected to the second power line VSS, and a second electrode of the fourth transistor T4 is connected to the third node N3.

[0074] In an exemplary embodiment, a first end of the first capacitor C1 is connected to the first node N1, a second end of the first capacitor C1 is connected to the second node N2, a first end of the second capacitor C2 is connected to the second node N2, and a second end of the second capacitor C2 is connected to the first power line VDD.

[0075] In an exemplary embodiment, the light emitting device XL may be an organic light emitting diode (OLED) including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode). The first electrode of the light emitting device XL is connected to the third node N3, and the second electrode of the light emitting device XL is connected to the common voltage line VCOM.

[0076] In an exemplary embodiment, the signal of the first power line VDD may be a continuously provided high level signal, and the signals of the second power line VSS and the common voltage line VCOM may be continuously provided low level signals.

[0077] In an exemplary embodiment, the first to fourth transistors T1 to T4 may be P-type transistors (PMOS) or N-type transistors (NMOS). For example, the first to fourth transistors T1 to T4 are all P-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the difficulty of manufacturing the display substrate, and improve the product yield.

[0078] In an exemplary embodiment, the first to fourth transistors T1 to T4 may include P-type transistors and N-type transistors. For example, the first to third transistors T1 to T3 may be P-type transistors, and the fourth transistor T4 may be an N-type transistor, as shown in FIG4 .

[0079] FIG5 is a driving timing diagram of the pixel driving circuit shown in FIG4. As shown in FIG5, in an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0080] The first phase A1 can be called the initialization phase. The signals of the first scan signal line S1 and the second scan signal line S2 are low-level signals, and the signal of the third scan signal line S3 is a high-level signal, so that the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned on. The first transistor T1 is turned on so that the bias voltage Vofs output by the data signal line DATA is written into the first capacitor C1, and the potential Vs of the first node N1 (i.e., the gate electrode of the third transistor T3) is Vofs. The second transistor T2 is turned on so that the first power supply voltage ELVDD output by the first power line VDD is written into the second node N2, and the potential Vg of the second node N2 (i.e., the first electrode of the third transistor T3) is ELVDD. At this time, the gate-source voltage Vgs of the third transistor T3 is ELVDD-Vofs, and the storage voltage V of the first capacitor C1 is V cs =ELVDD-Vofs, the potential Vd of the third node N3 (ie, the second electrode of the third transistor T3) = Vg+Vth, preparing for the next stage of discharge. ofs >|Vth|, where Vth is the threshold voltage of the third transistor T3.

[0081] The second stage A2 can be called the self-discharge stage. The signal of the third scanning signal line S3 is a high-level signal, and the fourth transistor T4 is continuously turned on. The signal of the first scanning signal line S13 changes from a low-level signal to a high-level signal, causing the first transistor T1 to be disconnected first, and the first node N1 to float. Subsequently, the signal of the second scanning signal line S2 changes from a low-level signal to a high-level signal, causing the second transistor T2 to be disconnected, and the second node N2 forms a loop through the turned-on third transistor T3, the third node N3 and the turned-on fourth transistor T4, and begins to discharge, and the potential of the second node N2 drops. Because the first node N1 is floating, the voltage difference across the first capacitor C1 remains unchanged, and thus the potential of the first node N1 drops as the potential of the second node N2 drops. Due to the back-gate effect of the third transistor T3, the gate-source voltage Vgs of the third transistor T3 remains unchanged, and thus the equivalent threshold voltage |V th_EF |As the potential of the second node N2 decreases, the equivalent threshold voltage of the third transistor T3 gradually increases. th_EF |=α(ELVDD-Vs)+|Vth|, α is the back gate coefficient. When the equivalent threshold voltage of the third transistor T3 |V th_EF When Vgs increases to the gate-source voltage Vgs of the third transistor T3, the third transistor T3 is turned off and the second node N2 stops discharging.

[0082] The third stage A3 can be called the data writing stage and the threshold compensation stage. The signal of the second scan signal line S2 is a high-level signal, and the second transistor T2 is continuously off. The signal of the third scan signal line S3 is a high-level signal, and the fourth transistor T4 is continuously on. The signal of the first scan signal line S13 changes from a high-level signal to a low-level signal, turning on the first transistor T1. Turning on the first transistor T1 causes the data voltage Vdata output by the data signal line DATA to be written to the first node N1, and the potential of the first node N1 changes from Vofs to Vdata. Because the second node N2 is floating, threshold compensation can be achieved in this stage.

[0083] The fourth phase A4 can be referred to as the light-emitting phase. The signals on the second and third scan signal lines S2 and S3 are low-level signals, while the signal on the first scan signal line S1 is high-level. This turns on the second transistor T2, while the first and fourth transistors T1 and T4 are off. Turning on the second transistor T2 causes the power supply voltage output from the first power line VDD to provide a driving voltage to the first electrode of the light-emitting device EL through the turned-on second and third transistors T2 and T3, driving the light-emitting device EL to emit light.

[0084] In the light-emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3, eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0085] An exemplary embodiment of the present disclosure provides a display substrate, comprising a display area and a non-display area; the display area comprises a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns, at least one sub-pixel comprising a pixel driving circuit and at least one scan signal line, the scan signal line being configured to provide a scan signal to the pixel driving circuit; the non-display area comprises a plurality of cascaded gate driving circuits, at least one gate driving circuit being connected to a scan signal line in a pixel row in the display area; at least one gate driving circuit comprises a shift register circuit, a logic operation circuit, and an output circuit sequentially arranged in a direction close to the display area, the shift register circuit The circuit is configured to generate a row-by-row shifted timing according to a timing signal, the logic operation circuit is configured to generate a target timing through logic operation, and the output circuit is configured to perform voltage domain conversion and signal enhancement; the output circuit includes at least one level converter and at least one row drive enhancer, the level converter is configured to perform voltage domain conversion on the target timing, the row drive enhancer is configured to enhance the converted signal and output it to the scan signal line of the display area, at least one input signal of the row drive enhancer is provided by the level converter, and the row drive enhancer is arranged on the side of the level converter close to the display area.

[0086] In an exemplary embodiment, the level converter includes at least a first inverter, a first level conversion unit, and a second level conversion unit; an input end of the first level conversion unit is connected to an input end of the first inverter, and an output end of the first level conversion unit is connected to the row driver enhancer; an input end of the second level conversion unit is connected to an output end of the first inverter, and an output end of the second level conversion unit is connected to the row driver enhancer; the first level conversion unit is arranged on a side of the first inverter close to the display area, and the second level conversion unit is arranged on a side of the first level conversion unit close to the display area.

[0087] In an exemplary embodiment, the level converter further includes a selection output unit, which is connected to the output end of the first level conversion unit and the output end of the second level conversion unit, respectively, and the selection output unit is configured to select and output the output signal of the first level conversion unit or the output signal of the second level conversion unit under the control of a selection input signal.

[0088] In an exemplary embodiment, the first inverter includes a first P-type transistor and a first N-type transistor arranged on a second direction side of the first P-type transistor; the first level conversion unit includes a first P-type transistor unit arranged on a first direction side of the first P-type transistor and a first N-type transistor unit arranged on a second direction side of the first P-type transistor unit, and the second level conversion unit includes a second P-type transistor unit arranged on a first direction side of the first P-type transistor unit and a second N-type transistor unit arranged on a second direction side of the second P-type transistor unit, and the first direction and the second direction intersect; the first P-type transistor unit includes a second P-type transistor to a seventh P-type transistor arranged on a first direction side of the first P-type transistor and arranged sequentially along the first direction; the second P-type transistor unit includes an eighth P-type transistor to a thirteenth P-type transistor arranged on a first direction side of the seventh P-type transistor and arranged sequentially along the first direction; the first N-type transistor unit includes a second N-type transistor arranged on a second direction side of the seventh P-type transistor, and the second N-type transistor unit includes a third N-type transistor arranged on a second direction side of the eighth P-type transistor.

[0089] In an exemplary embodiment, the row driver booster includes multiple transistor groups arranged sequentially along a first direction, at least one transistor group including a P-type transistor and an N-type transistor arranged to one side of the P-type transistor in a second direction, with the first and second directions intersecting. The multiple transistor groups form a first NAND gate, a first transmission gate, a second NAND gate, a second inverter, and an output unit, arranged sequentially along a direction close to the display area. A first distance exists between the transistor group in the second inverter and the transistor group in the output unit, and a second distance exists between adjacent transistor groups in the first NAND gate, the first transmission gate, the second NAND gate, and the second inverter. The first distance is greater than the second distance, and both the first and second distances are dimensions in the first direction.

[0090] The technical solution of the display substrate disclosed herein is described below through exemplary embodiments.

[0091] Figure 6 is a schematic structural diagram of a gate drive circuit of an exemplary embodiment of the present disclosure. In an exemplary embodiment, the gate drive device can be arranged in a non-display area, can be located on one side of the pixel row direction of the display area, or can be located on both sides of the pixel row direction of the display area. The gate drive device can include a plurality of cascaded gate drive circuits, at least one gate drive circuit is connected to a scan signal line in a pixel row in the display area, and provides a scan signal to the connected scan signal line. When the gate drive device is arranged on both sides of the pixel row direction of the display area, the scan signal line in the pixel row is driven by two gate drive circuits to form a bilateral drive structure, which can ensure the driving capability of high pixel density and avoid distortion of the drive signal. As shown in Figure 6, the gate drive circuit may include a shift register circuit 100, a logical operation circuit (Logical Transition Unit) 200 and an output circuit 300.

[0092] In an exemplary embodiment, the shift register circuit 100 may be a shift register circuit composed of flip-flops (D Flip Flops). The shift register circuit 100 is connected to the display driver circuit and receives timing signals generated by the display driver circuit. The timing signals may include a start signal STV and a clock signal CKV. The shift register circuit 100 is configured to shift and register the received timing signals to initially generate a timing sequence that can be shifted row by row. The logic operation circuit 200 is connected to the shift register circuit 100 and is configured to perform a logic operation on the shifted signals to generate a plurality of target timing sequences with different waveforms. The output circuit 300 is connected to the logic operation circuit 200 and is configured to perform voltage domain conversion on the target timing sequence, amplify the converted signal, and output a scan signal to the display area.

[0093] In an exemplary embodiment, for the pixel driving circuit in the display area including a first scan signal line S1, a second scan signal line S2 and a third scan signal line S3, the output circuit 300 may include three output sub-circuits, one output sub-circuit is connected to the first scan signal line S1 of a pixel row in the display area, and is configured to output a first scan signal to the display area, another output sub-circuit is connected to the second scan signal line S2 of a pixel row in the display area, and is configured to output a second scan signal to the display area, and yet another output sub-circuit is connected to the third scan signal line S3 of a pixel row in the display area, and is configured to output a third scan signal to the display area.

[0094] In an exemplary embodiment, the first scan signal may be referred to as a write switch (WS) signal, configured to control the on / off switching of a first transistor T1 in a pixel driving circuit. The second scan signal may be referred to as a display switch (DS) signal, configured to control the on / off switching of a second transistor T2 in the pixel driving circuit. The third scan signal may be referred to as a display reset (Auto Zero, AZ) signal, configured to control the on / off switching of a fourth transistor T4 in the pixel driving circuit.

[0095] In an exemplary embodiment, each output subcircuit may include a level shifter and a line driver. The level shifter is connected to the logic operation circuit 200 and is configured to perform voltage domain conversion for the target timing. The line driver enhancer is connected to the level shifter and is configured to enhance the converted signal, thereby increasing the output capability and outputting the scan signal to the display area.

[0096] In an exemplary embodiment, since signals such as the start signal and the clock signal are output by the display driver circuit, their voltage domains are inconsistent with the voltage domains of the pixel driver circuit. By converting the voltage through a level converter, the required voltage (0V to -2V & -5V) is introduced to ensure that the voltage of the output gate drive signal matches the pixel driver circuit.

[0097] In an exemplary embodiment, the start signal STV may be referred to as a frame start signal, with a period of one frame, and the clock signal CKV may be referred to as a row driving clock signal, with a period of one row.

[0098] Figure 7 is a working principle diagram of a level shifter according to an exemplary embodiment of the present disclosure. As shown in Figure 7, the level shifter may include a first inverter 401, a first P-type transistor unit 501P, a second P-type transistor unit 502P, a first N-type transistor unit 501N, and a second N-type transistor unit 502N.

[0099] In an exemplary embodiment, the input terminal IN_shifter of the level converter is respectively connected to the input terminal of the first inverter 401 and the gate electrode of the first P-type transistor unit 501P, the output terminal of the first inverter 401 is connected to the gate electrode of the second P-type transistor unit 502P, the first electrode of the first P-type transistor unit 501P and the first electrode of the second P-type transistor unit 502P are both connected to the first power line VDD, the second electrode of the first P-type transistor unit 501P is respectively connected to the second electrode of the first N-type transistor unit 501N, the gate electrode of the second N-type transistor unit 502N, and the second output terminal OUT_B_shifter of the level converter, the second electrode of the second P-type transistor unit 502P is respectively connected to the gate electrode of the first N-type transistor unit 501N, the second electrode of the second N-type transistor unit 502N, and the first output terminal OUT_shifter of the level converter, and the first electrode of the first N-type transistor unit 501N and the first electrode of the second N-type transistor unit 502N are both connected to the second power line VSS.

[0100] In an exemplary embodiment, the operating principle of the level shifter is as follows: when the input signal at the input terminal IN_shifter of the level shifter is at a low level, the first P-type transistor unit 501P is turned on, the second P-type transistor unit 502P is turned off, and the output signal at the second output terminal OUT_B_shifter of the level shifter is the signal of the first power line VDD. The first N-type transistor unit 501N is turned off, the second N-type transistor unit 502N is turned on, and the output signal at the first output terminal OUT_shifter of the level shifter is the signal of the second power line VSS. When the input signal at the input terminal IN_shifter of the level shifter is at a high level, the first P-type transistor unit 501P is turned off, the second P-type transistor unit 502P is turned on, the output signal at the first output terminal OUT_shifter of the level shifter is the signal of the first power line VDD. The first N-type transistor unit 501N is turned on, the second N-type transistor unit 502N is turned off, and the output signal at the second output terminal OUT_B_shifter of the level shifter is the signal of the second power line VSS.

[0101] FIG8 is a diagram illustrating the operating principle of a row driver booster according to an exemplary embodiment of the present disclosure. As shown in FIG8 , the row driver booster may include a first NAND gate 301, a second NAND gate 302, a first transmission gate 201, a second inverter 402, a third P-type transistor unit 503P, and a third N-type transistor unit 503N. The third P-type transistor unit 503P and the third N-type transistor unit 503N have a relatively large width-to-length ratio to improve driving capability.

[0102] In an exemplary embodiment, a first input terminal IN_driver and an enable signal terminal EN of the row driver booster are connected to an input terminal of a first NAND gate 301. An output terminal of the first NAND gate 301 is connected to an input terminal of a first transmission gate 201. An output terminal of the first transmission gate 201 is connected to a gate electrode of a third P-type transistor unit 503P. A first electrode of the third P-type transistor unit 503P is connected to a first power supply line VDD. A second input terminal IN_B_driver and an enable signal terminal EN of the row driver booster are connected to an input terminal of a second NAND gate 302. An output terminal of the second NAND gate 302 is connected to an input terminal of a second inverter 402. An output terminal of the second inverter 402 is connected to a gate electrode of a third N-type transistor unit 503N. A first electrode of the third N-type transistor unit 503N is connected to a second power supply line VSS. The second electrode of the third P-type transistor unit 503P and the second electrode of the third N-type transistor unit 503N are connected to the output terminal OUT_driver of the row driver enhancer, the high-level active enable terminal of the first transmission gate 201 and the second inverter 402 are connected to the first power line VDD, and the low-level active enable terminal is connected to the second power line VSS, the high-level active enable terminal of the first NAND gate 301 and the second NAND gate 302 are connected to the first power line VDD, and the low-level active enable terminal is connected to the ground line GND.

[0103] In an exemplary embodiment, the row driver booster operates as follows:

[0104] When the enable signal at the enable signal terminal EN is 0, the first NAND gate 301 and the second NAND gate 302 output 1 (high level). The output of the first NAND gate 301 outputs 1 (high level) after passing through the first transmission gate 201, the third P-type transistor unit 503P is disconnected, and the output of the second NAND gate 302 outputs 0 (low level) after passing through the second inverter 402, the third N-type transistor unit 503N is disconnected, and the entire circuit state is high-impedance.

[0105] When the enable signal at the enable signal terminal EN is 1, the circuit output is determined by the input signals at the first input terminal IN_driver of the row driver enhancer and the second input terminal IN_B_driver of the row driver enhancer. The input signals at the first input terminal IN_driver of the row driver enhancer and the input signals at the second input terminal IN_B_driver of the row driver enhancer are direction signals to each other.

[0106] When the input signal at the first input terminal IN_driver of the row driver booster is 1 and the input signal at the second input terminal IN_B_driver is 0, the first NAND gate 301 outputs 0. The output of the first NAND gate 301 outputs 0 after passing through the first transmission gate 201, and the third P-type transistor unit 503P is turned on. The second NAND gate 302 outputs 1. The output of the second NAND gate 302 outputs 0 after passing through the second inverter 402, and the third N-type transistor unit 503N is turned off. The output signal at the output terminal OUT_driver of the row driver booster is the signal of the first power line VDD (high level).

[0107] When the input signal at the first input terminal IN_driver of the row driver booster is 0 and the input signal at the second input terminal IN_B_driver is 1, the first NAND gate 301 outputs 1. The output of the first NAND gate 301 outputs 1 after passing through the first transmission gate 201, and the third P-type transistor unit 503P is turned off. The second NAND gate 302 outputs 0. The output of the second NAND gate 302 outputs 1 after passing through the second inverter 402, and the third N-type transistor unit 503N is turned on. The output signal at the output terminal OUT_driver of the row driver booster is the signal of the second power line VSS (low level).

[0108] In an exemplary embodiment, when the enable signal at the enable signal terminal EN is 0, the circuit output is in a high-impedance state. When the enable signal at the enable signal terminal EN is 1, the circuit output does not change the logical relationship between the high and low inputs and outputs; the enable signal at the enable signal terminal EN is a high-configuration control signal. In principle, the row driver booster is a buffer with a large width-to-length ratio, resulting in high output current and drive capability. Furthermore, the row driver booster has low output impedance, high output impedance, and strong drive capability.

[0109] In an exemplary embodiment, the input terminal IN_shifter of the level converter can be connected to the output terminal of the logic operation circuit 200, the first output terminal OUT_shifter of the level converter can be connected to the first input terminal IN_driver of the row driver enhancer, the second output terminal OUT_B_shifter of the level converter can be connected to the second input terminal IN_B_driver of the row driver enhancer, and the output terminal OUT_driver of the row driver enhancer can be connected to the scan signal line of the display area.

[0110] Figure 9 is an equivalent circuit diagram of a level shifter according to an exemplary embodiment of the present disclosure. As shown in Figure 9, the level shifter of the gate drive circuit in the display substrate of the present embodiment may include 16 transistors. Specifically, the first inverter 401 includes one P-type transistor and one N-type transistor, the first P-type transistor unit 501P includes six P-type transistors, the second P-type transistor unit 502P includes six P-type transistors, the first N-type transistor unit 501N includes one N-type transistor, and the second N-type transistor unit 502N includes one N-type transistor.

[0111] In an exemplary embodiment, a first P-type transistor P1 and a first N-type transistor N1 form a first inverter 401. A gate electrode of the first P-type transistor P1 and a gate electrode of the first N-type transistor N1 are both connected to the converter input terminal IN_shifter, a first electrode of the first P-type transistor P1 is connected to a first power supply line VDD, a first electrode of the first N-type transistor N1 is connected to a ground line GND, and a second electrode of the first P-type transistor P1 is connected to a second electrode of the first N-type transistor N1.

[0112] In an exemplary embodiment, the first P-type transistor unit 501P and the first N-type transistor unit 501N may be referred to as a first level conversion unit, and the second P-type transistor unit 502P and the second N-type transistor unit 502N may be referred to as a second level conversion unit.

[0113] In an exemplary embodiment, a second P-type transistor P2, a third P-type transistor P3, a fourth P-type transistor P4, a fifth P-type transistor P5, a sixth P-type transistor P6 and a seventh P-type transistor P7 connected in parallel constitute a first P-type transistor unit 501P, gate electrodes of the second P-type transistor P2 to the seventh P-type transistor P7 are all connected to the converter input terminal IN_shifter, first electrodes of the second P-type transistor P2 to the seventh P-type transistor P7 are all connected to the first power line VDD, and second electrodes of the second P-type transistor P2 to the seventh P-type transistor P7 are respectively connected to the gate electrode of the third N-type transistor N3 and the converter second output terminal OUT_B_shifter.

[0114] In an exemplary embodiment, an eighth P-type transistor P8, a ninth P-type transistor P9, a tenth P-type transistor P10, an eleventh P-type transistor P11, a twelfth P-type transistor P12, and a thirteenth P-type transistor P13 connected in parallel constitute a second P-type transistor unit 502P, gate electrodes of the eighth P-type transistor P8 to the thirteenth P-type transistor P13 are all connected to the second electrode of the first P-type transistor P1 and the second electrode of the first N-type transistor N1, first electrodes of the eighth P-type transistor P8 to the thirteenth P-type transistor P13 are all connected to the first power line VDD, and second electrodes of the eighth P-type transistor P8 to the thirteenth P-type transistor P13 are respectively connected to the gate electrode of the second N-type transistor N2 and the first output terminal OUT_shifter of the converter.

[0115] In the exemplary embodiment, the second N-type transistor N2 serves as the first N-type transistor unit 501N. The gate electrode of the second N-type transistor N2 is respectively connected to the first output terminal OUT_shifter of the converter and the second electrodes of the eighth through thirteenth P-type transistors P8 through P13. The first electrode of the second N-type transistor N2 is connected to the second power supply line VSS, and the second electrode of the second N-type transistor N2 is respectively connected to the second output terminal OUT_B_shifter of the converter and the second electrodes of the second through seventh P-type transistors P2 through P7.

[0116] In an exemplary embodiment, the third N-type transistor N3 serves as the second N-type transistor unit 502N, the gate electrode of the third N-type transistor N3 is respectively connected to the second output terminal OUT_B_shifter of the converter and the second electrodes of the second P-type transistor P2 to the seventh P-type transistor P7, the first electrode of the third N-type transistor N3 is connected to the second power line VSS, and the second electrode of the third N-type transistor N3 is respectively connected to the first output terminal OUT_shifter of the converter and the second electrodes of the eighth P-type transistor P8 to the thirteenth P-type transistor P13.

[0117] In some possible implementations, the first P-type transistor unit 501P may include 1, 2, 3, 4 or 5 P-type transistors, and the second P-type transistor unit 502P may include 1, 2, 3, 4 or 5 P-type transistors, which is not limited in the present disclosure.

[0118] Figure 10 is an equivalent circuit diagram of a row driver booster according to an exemplary embodiment of the present disclosure. As shown in Figure 10, the row driver booster of the gate driver circuit in the display substrate of the present embodiment may include 20 transistors. Specifically, the first NAND gate 301 includes two P-type transistors and two N-type transistors, the second NAND gate 302 includes two P-type transistors and two N-type transistors, the first transmission gate 201 includes one P-type transistor and one N-type transistor, the second inverter 402 includes one P-type transistor and one N-type transistor, the third P-type transistor unit 503P includes four P-type transistors, and the third N-type transistor unit 503N includes four N-type transistors.

[0119] In an exemplary embodiment, the first NAND gate 301, the first transmission gate 201, the second NAND gate 302 and the second inverter 402 can be arranged in sequence along the first direction X (the direction close to the display area), the third P-type transistor unit 503P and the third N-type transistor unit 503N can be arranged on one side of the second inverter 402 in the first direction X, and the third N-type transistor unit 503N can be arranged on one side of the third P-type transistor unit 503P in the second direction Y.

[0120] In an exemplary embodiment, the twenty-first P-type transistor P21 , the twenty-second P-type transistor P22 , the twenty-first N-type transistor N21 , and the twenty-second N-type transistor N22 constitute a first NAND gate 301 . The gate electrode of the twenty-first P-type transistor P21 and the gate electrode of the twenty-first N-type transistor N21 are connected to each other and to the first input terminal IN_driver of the enhancer. The gate electrode of the twenty-second P-type transistor P22 and the gate electrode of the twenty-second N-type transistor N22 are connected to each other and to the enable signal terminal EN. The first electrode of the twenty-first P-type transistor P21 and the first electrode of the twenty-second P-type transistor P22 are both connected to the first power line VDD, the first electrode of the twenty-second N-type transistor N22 is connected to the second power line VSS, the second electrode of the twenty-second N-type transistor N22 is connected to the first electrode of the twenty-first N-type transistor N21, the second electrode of the twenty-first P-type transistor P21 and the second electrode of the twenty-second P-type transistor P22 are connected to each other and are respectively connected to the second electrode of the twenty-first N-type transistor N21, the first electrode of the twenty-third P-type transistor P23, and the first electrode of the twenty-third N-type transistor N23.

[0121] In the exemplary embodiment, the twenty-third P-type transistor P23 and the twenty-third N-type transistor N23 constitute the first transmission gate 201. The gate electrode of the twenty-third P-type transistor P23 is connected to the second power supply line VSS, the gate electrode of the twenty-third N-type transistor N23 is connected to the first power supply line VDD, the first electrode of the twenty-third P-type transistor P23 and the first electrode of the second-third N-type transistor N23 are connected to each other and are respectively connected to the second electrode of the twenty-first P-type transistor P21, the second electrode of the twenty-first N-type transistor N21, and the second electrode of the twenty-second P-type transistor P22, the second electrode of the twenty-third P-type transistor P23 and the second electrode of the second-third N-type transistor N23 are connected to each other and are respectively connected to the gate electrodes of the twenty-seventh P-type transistor P27 to the thirtieth P-type transistor P30.

[0122] In an exemplary embodiment, the twenty-fourth P-type transistor P24 , the twenty-fifth P-type transistor P25 , the twenty-fourth N-type transistor N24 , and the twenty-fifth N-type transistor N25 constitute a second NAND gate 302 . The gate electrode of the twenty-fourth P-type transistor P24 and the gate electrode of the twenty-fourth N-type transistor N24 are connected to each other and to the second input terminal IN_B_driver of the enhancer. The gate electrode of the twenty-fifth P-type transistor P25 and the gate electrode of the twenty-fifth N-type transistor N25 are connected to each other and to the enable signal terminal EN. The first electrode of the twenty-fourth P-type transistor P24 and the first electrode of the twenty-fifth P-type transistor P25 are both connected to the first power line VDD, the first electrode of the twenty-fifth N-type transistor N25 is connected to the second power line VSS, the second electrode of the twenty-fifth N-type transistor N25 is connected to the first electrode of the twenty-fourth N-type transistor N24, the second electrode of the twenty-fourth P-type transistor P24 and the second electrode of the twenty-fifth P-type transistor P25 are connected to each other and are respectively connected to the second electrode of the twenty-fourth N-type transistor N24 and the gate electrode of the twenty-sixth P-type transistor P26 and the gate electrode of the twenty-sixth N-type transistor N26.

[0123] In the exemplary embodiment, the twenty-sixth P-type transistor P26 and the twenty-sixth N-type transistor N26 constitute the second inverter 402. The gate electrode of the twenty-sixth P-type transistor P26 and the gate electrode of the twenty-sixth N-type transistor N26 are connected to each other and are respectively connected to the second electrode of the twenty-fourth P-type transistor P24, the second electrode of the twenty-fourth N-type transistor N24, and the second electrode of the twenty-fifth P-type transistor P25. A first electrode of the twenty-sixth P-type transistor P26 is connected to the first power supply line VDD, a first electrode of the twenty-sixth N-type transistor N26 is connected to the second power supply line VSS, a second electrode of the twenty-sixth P-type transistor P26 and the second electrode of the twenty-sixth N-type transistor N26 are connected to each other and are respectively connected to the gate electrodes of the twenty-seventh N-type transistor N27 to the thirtieth N-type transistor N30.

[0124] In an exemplary embodiment, the third P-type transistor unit 503P and the third N-type transistor unit 503N may be referred to as output units of a row driver booster.

[0125] In the exemplary embodiment, a twenty-seventh P-type transistor P27, a twenty-eighth P-type transistor P28, a twenty-ninth P-type transistor P29, and a thirtieth P-type transistor P30 connected in parallel form a third P-type transistor unit 503P. Gate electrodes of the twenty-seventh to thirtieth P-type transistors P27 to P30 are connected to one another and to the second electrode of the twenty-third P-type transistor P23 and the second electrode of the twenty-third N-type transistor N23, respectively. First electrodes of the twenty-seventh to thirtieth P-type transistors P27 to P30 are all connected to the first power supply line VDD, and second electrodes of the twenty-seventh to thirtieth P-type transistors P27 to P30 are all connected to the booster output terminal OUT_driver.

[0126] In the exemplary embodiment, a twenty-seventh N-type transistor N27, a twenty-eighth N-type transistor N28, a twenty-ninth N-type transistor N29, and a thirtieth N-type transistor N30 connected in parallel form a third N-type transistor unit 503N. Gate electrodes of the twenty-seventh to thirtieth N-type transistors N27 to N30 are connected to one another and to the second electrode of the twenty-sixth P-type transistor P26 and the second electrode of the twenty-sixth N-type transistor N26, respectively. First electrodes of the twenty-seventh to thirtieth N-type transistors N27 to N30 are all connected to the second power supply line VSS, and second electrodes of the twenty-seventh to thirtieth N-type transistors N27 to N30 are all connected to the booster output terminal OUT_driver.

[0127] In some possible implementations, the third P-type transistor unit 503P may include 1, 2, 3 or more than 5 P-type transistors, and the third N-type transistor unit 503N may include 1, 2, 3 or more than 5 N-type transistors, which is not limited in the present disclosure.

[0128] Figure 11 is an equivalent circuit diagram of an output circuit according to an exemplary embodiment of the present disclosure. As shown in Figures 9, 10, and 11, the output circuit includes the level shifter shown in Figure 9 and the row driver booster shown in Figure 10. The first output terminal OUT_shifter of the shifter is connected to the first input terminal IN_driver of the booster, and the second output terminal OUT_B_shifter of the shifter is connected to the second input terminal IN_B_driver of the booster.

[0129] Figure 12 is a schematic diagram of the structure of an output circuit of an exemplary embodiment of the present disclosure. In an exemplary embodiment, the display substrate of the exemplary embodiment of the present disclosure may include at least a display area and a non-display area. The display area may include a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns, at least one sub-pixel including a pixel driving circuit and at least one scan signal line, and the scan signal line is configured to provide a scan signal to the connected pixel driving circuit. The non-display area may include a plurality of cascaded gate driving circuits, at least one gate driving circuit being connected to a scan signal line in a pixel row in the display area. At least one gate driving circuit may include a shift register circuit, a logic operation circuit, and an output circuit arranged on a silicon substrate, the shift register circuit being configured to generate a row-by-row shift timing according to a timing signal, the logic operation circuit being configured to generate a target timing through a logic operation, and the output circuit being configured to output to the scan signal line of the display area after performing voltage domain conversion and signal enhancement.

[0130] As shown in Figure 12, the silicon substrate of the output circuit may include at least a first region LS and a second region LD. The second region LD may be located on one side of the first region LS in a first direction X (the direction closer to the display area). The first region LS is configured to house a level shifter, and the second region LD is configured to house a row driver booster, such that the row driver booster is located on the side of the level shifter closer to the display area. In an exemplary embodiment, the level shifter is configured to perform voltage domain conversion on a target timing, and the row driver booster is configured to boost the converted signal before outputting it to the scan signal lines of the display area.

[0131] In an exemplary embodiment, the level converter may include a first inverter 401, a first level conversion unit, and a second level conversion unit sequentially arranged along a first direction X (a pixel row direction in a display area), the first level conversion unit may include a first P-type transistor unit 501P and a first N-type transistor unit 501N, and the second level conversion unit may include a second P-type transistor unit 502P and a second N-type transistor unit 502N.

[0132] In an exemplary embodiment, the row driver booster may include a first NAND gate 301, a first transmission gate 201, a second NAND gate 302, a second inverter 402, and an output unit sequentially arranged along the first direction X, and the output unit may include a third P-type transistor unit 503P and a third N-type transistor unit 503N.

[0133] In an exemplary embodiment, the first inverter 401 may include a first P-type transistor P1 and a first N-type transistor N1 disposed on the side of the first P-type transistor P1 in the second direction Y (the pixel column direction in the display area). The first P-type transistor unit 501P includes a second P-type transistor P2 to a seventh P-type transistor P7 disposed on the side of the first P-type transistor P1 close to the display area and sequentially arranged along the direction close to the display area. The second P-type transistor unit 502P includes an eighth P-type transistor P8 to a thirteenth P-type transistor P13 disposed on the side of the seventh P-type transistor P7 close to the display area and sequentially arranged along the direction close to the display area. The first N-type transistor unit 501N includes a second N-type transistor N2 disposed on the side of the seventh P-type transistor P7 in the second direction Y, and the second N-type transistor unit 502N includes a third N-type transistor N3 disposed on the side of the eighth P-type transistor P8 in the second direction Y.

[0134] In an exemplary embodiment, each of the first to thirteenth P-type transistors P1 to P13 may include a P-type active layer, and the second P-type active layer of the second P-type transistor P2 to the thirteenth P-type active layer of the thirteenth P-type transistor P13 may be an integrated structure connected to each other. Each of the first to third N-type transistors N1 to N3 may include an N-type active layer, and the second N-type active layer of the second N-type transistor N2 and the third N-type active layer of the third N-type transistor N3 may be an integrated structure connected to each other.

[0135] In an exemplary embodiment, the second to thirteenth P-type active regions of the integrated structure may have an active center line O, which may be a straight line bisecting the second to thirteenth P-type active regions of the integrated structure in the first direction X and extending along the second direction Y. The second to seventh P-type transistors P2 to P7 in the first P-type transistor unit 501P and the eighth to thirteenth P-type transistors P8 to P13 in the second P-type transistor unit 502P may be mirror-symmetrical with respect to the active center line O, and the second N-type transistor N2 in the first N-type transistor unit 501N and the third N-type transistor N3 in the second N-type transistor unit 502N may be mirror-symmetrical with respect to the active center line O.

[0136] In an exemplary embodiment, the second P-type gate electrode of the second P-type transistor P2 to the seventh P-type gate electrode of the seventh P-type transistor P7 and the eighth P-type gate electrode of the eighth P-type transistor P8 to the thirteenth P-type gate electrode of the thirteenth P-type transistor P13 can be mirror-symmetrical relative to the active center line O.

[0137] In an exemplary embodiment, a first length L1 is provided between an edge of the second P-type gate electrode of the second P-type transistor P2 on a side away from the active center line O and the active center line O, and a second length L2 is provided between an edge of the thirteenth P-type gate electrode of the thirteenth P-type transistor P13 on a side away from the active center line O and the active center line O. The ratio of the first length L1 to the second length L2 may be approximately 0.95 to 1.05.

[0138] In an exemplary embodiment, the second N-type gate electrode of the second N-type transistor N2 and the third N-type gate electrode of the third N-type transistor N3 may be mirror-symmetrical with respect to the active center line O.

[0139] In an exemplary embodiment, a third length L3 is provided between an edge of the second N-type gate electrode of the second N-type transistor N2 on a side away from the active center line O and the active center line O, and a fourth length L4 is provided between an edge of the third N-type gate electrode of the third N-type transistor N3 on a side away from the active center line O and the active center line O. The ratio of the third length L3 to the fourth length L4 may be approximately 0.95 to 1.05.

[0140] In an exemplary embodiment, the second P-type source electrode and the second P-type drain electrode of the second P-type transistor P2 to the seventh P-type source electrode and the seventh P-type drain electrode of the seventh P-type transistor P7 and the eighth P-type source electrode and the eighth P-type drain electrode of the eighth P-type transistor P8 to the thirteenth P-type source electrode and the thirteenth P-type drain electrode of the thirteenth P-type transistor P13 can be mirror-symmetrical relative to the active center line O.

[0141] In an exemplary embodiment, an eleventh length L11 is provided between an edge of the second P-type source electrode of the second P-type transistor P2 on a side away from the active center line O and the active center line O, and a twelfth length L12 is provided between an edge of the thirteenth P-type source electrode of the thirteenth P-type transistor P13 on a side away from the active center line O and the active center line O, and a ratio of the eleventh length L11 to the twelfth length L12 may be approximately 0.95 to 1.05.

[0142] In an exemplary embodiment, the second N-type drain electrode of the second N-type transistor N2 and the third N-type drain electrode of the third N-type transistor N3 may be mirror-symmetrical with respect to the active center line O.

[0143] In an exemplary embodiment, a thirteenth length L13 is provided between an edge of the second N-type drain electrode of the second N-type transistor N2 on a side away from the active center line O and the active center line O, and a fourteenth length L14 is provided between an edge of the third N-type drain electrode of the third N-type transistor N3 on a side away from the active center line O and the active center line O. The ratio of the thirteenth length L13 to the fourteenth length L14 may be approximately 0.95 to 1.05.

[0144] In an exemplary embodiment, a voltage domain distance LY is provided between an edge of the first P-type drain electrode of the first P-type transistor P1 on a side close to the second P-type transistor P2 and an edge of the second P-type source electrode of the second P-type transistor P2 on a side close to the first P-type transistor P1. The voltage domain distance LY may be greater than or equal to 3.67 μm.

[0145] In an exemplary embodiment, the output circuit may further include a first power line 51, a second power line 52, and a ground line 53. The first power line 51, the second power line 52, and the ground line 53 may be linearly shaped and extend along a first direction X. The first power line 51 may be disposed on a side of the plurality of P-type transistors away from the N-type transistors, the second power line 52 may be disposed on a side of the plurality of N-type transistors away from the P-type transistors, and the ground line 53 may be disposed on a side of the first N-type transistor N1 away from the first P-type transistor P1. In an exemplary embodiment, the first power line 51 is configured to transmit a first power signal, the second power line 52 is configured to transmit a second power signal, and the ground line 53 is configured to transmit a ground signal.

[0146] In an exemplary embodiment, a voltage line distance LX is provided between an edge of the second power line 52 close to the ground line 53 and an edge of the ground line 53 close to the second power line 52 . The voltage line distance LX may be greater than or equal to 5 μm.

[0147] In an exemplary embodiment, the row driver booster may include a plurality of transistor groups sequentially arranged along a first direction X, at least one transistor group including a P-type transistor and an N-type transistor arranged on one side of the P-type transistor in a second direction Y, and the first direction X and the second direction Y intersect; the plurality of transistor groups form a first NAND gate 301, a first transmission gate 201, a second NAND gate 302, a second inverter 402, and an output unit sequentially arranged along a direction close to the display area, a first distance S1 being provided between the transistor group in the second inverter 402 and the transistor group in the output unit, a second distance S2 being provided between two adjacent transistor groups in the first NAND gate 301, the first transmission gate 201, the second NAND gate 302, and the second inverter 402, the first distance S1 being greater than the second distance S2, and the first distance S1 and the second distance S2 being the dimensions in the first direction X.

[0148] In an exemplary embodiment, a ratio of the first distance S1 to the second distance S2 may be approximately 0.7 to 0.8.

[0149] In an exemplary embodiment, the first distance S1 may be greater than or equal to 0.5 μm, and the second distance S2 may be greater than or equal to 0.36 μm.

[0150] The following is an illustrative explanation through the preparation process of the display device. The "patterning process" mentioned in the present disclosure includes the deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes the coating of organic materials, mask exposure and development and other processes for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display device. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0151] In an exemplary embodiment, a process of preparing a display substrate may include the following steps.

[0152] (1) Provide a silicon substrate. In an exemplary embodiment, the silicon substrate may be a P-type silicon substrate. In an exemplary embodiment, the P-type silicon substrate may serve as a channel region of an N-type transistor.

[0153] In an exemplary embodiment, the P-type silicon substrate may include a first region LS and a second region LD, the second region LD may be disposed on one side of the first region LS in a first direction X (close to the display region direction), the first region LS is configured as a device for disposing a level converter, and the second region LD is configured as a device for disposing a row driver booster.

[0154] In some possible implementations, the silicon substrate may be an N-type silicon material, which may serve as a channel region of a P-type transistor, and this disclosure does not limit this.

[0155] (2) A deep N type well (DNW), an N type well (NW) region, and an active area (AA) pattern are sequentially formed. In an exemplary embodiment, a photoresist pattern including an opening region can be formed by coating a photoresist on a P-type silicon substrate, exposing, and developing. The photoresist in the opening region is removed to expose the surface of the P-type silicon substrate. N-type dopant ions are implanted in the opening region by ion implantation, and the remaining photoresist is stripped off to form a deep N well region 10 pattern on the P-type silicon substrate. Subsequently, an N well region 20 and an active area pattern are sequentially formed on the silicon substrate on which the aforementioned pattern is formed, as shown in FIG13A and FIG13B , FIG13B being a schematic diagram of the active area in FIG13A .

[0156] In an exemplary embodiment, the deep N-well region 10 of the first region LS and the deep N-well region 20 of the second region LD may be an interconnected integral structure, and the N-well region 20 of the first region LS and the N-well region 20 of the second region LD may be an interconnected integral structure.

[0157] In an exemplary embodiment, n-type dopant ions may be implanted using ion implanters such as phosphorus or arsenic. The depth and doping concentration of the ion implantation can be controlled by controlling the implantation energy and dose. The process for forming the deep N-well region may also include annealing and other processes to allow the ion implanter to diffuse into the P-type silicon substrate, forming a stable deep N-well structure.

[0158] In an exemplary embodiment, the deep N-well region 10 is configured to electrically isolate different regions to effectively limit the path of current flow, thereby reducing leakage and energy loss. The N-well region 20 is configured to form P-type transistors and P-type devices, and the regions outside the N-well region are configured to form N-type transistors and N-type devices.

[0159] In an exemplary embodiment, the active area pattern may include at least a first P-type active region 101P to a thirteenth P-type active region 113P, a twenty-first P-type active region 121P to a thirtieth P-type active region 130P, a first N-type active region 101N to a third N-type active region 103N, a twenty-first N-type active region 121N to a thirtieth N-type active region 130N, a first power supply active region 100P, a second power supply active region 100N1, and a ground active region 100N2.

[0160] In an exemplary embodiment, the first P-type active region 101P to the thirteenth P-type active region 113P, and the first N-type active region 101N to the third N-type active region 103N can be set in the first region LS, and the twenty-first P-type active region 121P to the thirtieth P-type active region 130P, and the twenty-first N-type active region 121N to the thirtieth N-type active region 130N can be set in the second region LD.

[0161] In an exemplary embodiment, the shape of the first P-type active region 101P can be a block (such as a rectangle), and the first P-type active region 101P can be located outside the area where the deep N-well region 10 is located, but within the area where the N-well region 20 is located. The orthographic projection of the first P-type active region 101P on the silicon substrate does not overlap with the orthographic projection of the deep N-well region 10N on the silicon substrate. The orthographic projection of the first P-type active region 101P on the silicon substrate is located within the range of the orthographic projection of the N-well region 20 on the silicon substrate. The first P-type active region 101P can serve as the active region of the first P-type transistor P1.

[0162] In an exemplary embodiment, the first N-type active region 101N may be block-shaped (e.g., rectangular) and may be located on one side of the first P-type active region 101P in the second direction Y. The first N-type active region 101N may be located outside the region where the deep N-well region 10 and the N-well region 20 are located. The orthographic projection of the first N-type active region 101N on the silicon substrate does not overlap with the orthographic projection of the deep N-well region 10N on the silicon substrate. The orthographic projection of the first N-type active region 101N on the silicon substrate does not overlap with the orthographic projection of the N-well region 20 on the silicon substrate. The first N-type active region 101N may serve as the active region of the first N-type transistor N1.

[0163] In an exemplary embodiment, the shape of the second P-type active region 102P can be block-shaped (such as a rectangle), and the second P-type active region 102P can be located within the area where the deep N-well region 10 and the N-well region 20 are located. The orthographic projection of the second P-type active region 102P on the silicon substrate is located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate. The second P-type active region 102P can serve as the active region of the second P-type transistor P2.

[0164] In an exemplary embodiment, the shape of the third P-type active region 103P can be block-shaped (such as rectangular), and the third P-type active region 103P can be located within the area where the deep N-well region 10 and the N-well region 20 are located. The orthographic projection of the third P-type active region 103P on the silicon substrate is located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate. The third P-type active region 103P can serve as the active region of the third P-type transistor P3.

[0165] In an exemplary embodiment, the shape of the fourth P-type active region 104P can be block-shaped (such as a rectangle), the fourth P-type active region 104P can be located within the area where the deep N-well region 10 and the N-well region 20 are located, the orthographic projection of the fourth P-type active region 104P on the silicon substrate is located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate, and the fourth P-type active region 104P can serve as the active region of the fourth P-type transistor P4.

[0166] In an exemplary embodiment, the shape of the fifth P-type active region 105P can be block-shaped (such as a rectangle), and the fifth P-type active region 105P can be located within the area where the deep N-well region 10 and the N-well region 20 are located. The orthographic projection of the fifth P-type active region 105P on the silicon substrate is located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate. The fifth P-type active region 105P can serve as the active region of the fifth P-type transistor P5.

[0167] In an exemplary embodiment, the shape of the sixth P-type active region 106P can be block-shaped (such as a rectangle), and the sixth P-type active region 106P can be located within the area where the deep N-well region 10 and the N-well region 20 are located. The orthographic projection of the sixth P-type active region 106P on the silicon substrate is located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate. The sixth P-type active region 106P can serve as the active region of the sixth P-type transistor P6.

[0168] In an exemplary embodiment, the shape of the seventh P-type active region 107P can be block-shaped (such as rectangular), the seventh P-type active region 107P can be located within the area where the deep N-well region 10 and the N-well region 20 are located, the orthographic projection of the seventh P-type active region 107P on the silicon substrate is located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate, and the seventh P-type active region 107P can serve as the active region of the seventh P-type transistor P7.

[0169] In an exemplary embodiment, the shape of the eighth P-type active region 108P can be block-shaped (such as rectangular), the eighth P-type active region 108P can be located within the area where the deep N-well region 10 and the N-well region 20 are located, the orthographic projection of the eighth P-type active region 108P on the silicon substrate is located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate, and the eighth P-type active region 108P can serve as the active region of the eighth P-type transistor P8.

[0170] In an exemplary embodiment, the shape of the ninth P-type active region 109P can be block-shaped (such as rectangular), the ninth P-type active region 109P can be located within the area where the deep N-well region 10 and the N-well region 20 are located, the orthographic projection of the ninth P-type active region 109P on the silicon substrate is located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate, and the ninth P-type active region 109P can serve as the active region of the ninth P-type transistor P9.

[0171] In an exemplary embodiment, the shape of the tenth P-type active region 110P can be block-shaped (such as rectangular), the tenth P-type active region 110P can be located within the area where the deep N-well region 10 and the N-well region 20 are located, the orthographic projection of the tenth P-type active region 110P on the silicon substrate is located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate, and the tenth P-type active region 110P can serve as the active region of the tenth P-type transistor P10.

[0172] In an exemplary embodiment, the shape of the eleventh P-type active region 111P can be block-shaped (such as rectangular), the eleventh P-type active region 111P can be located within the area where the deep N-well region 10 and the N-well region 20 are located, the orthographic projection of the eleventh P-type active region 111P on the silicon substrate is located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate, and the eleventh P-type active region 111P can serve as the active region of the eleventh P-type transistor P11.

[0173] In an exemplary embodiment, the shape of the twelfth P-type active region 112P can be block-shaped (such as rectangular), the twelfth P-type active region 112P can be located within the area where the deep N-well region 10 and the N-well region 20 are located, the orthographic projection of the twelfth P-type active region 112P on the silicon substrate is located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate, and the twelfth P-type active region 112P can serve as the active region of the twelfth P-type transistor P12.

[0174] In an exemplary embodiment, the shape of the thirteenth P-type active region 113P can be block-shaped (such as rectangular), the thirteenth P-type active region 113P can be located within the area where the deep N-well region 10 and the N-well region 20 are located, the orthographic projection of the thirteenth P-type active region 113P on the silicon substrate is located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate, and the thirteenth P-type active region 113P can serve as the active region of the thirteenth P-type transistor P13.

[0175] In an exemplary embodiment, the second to thirteenth P-type active regions 102P to 113P may be an integral structure connected to each other.

[0176] In an exemplary embodiment, the second N-type active region 102N may be block-shaped (e.g., rectangular) and may be located on one side of the seventh P-type active region 107P in the second direction Y. The second N-type active region 102N is located within the region where the deep N-well region 10 is located, but outside the region where the N-well region 20 is located. The orthographic projection of the second N-type active region 102N on the silicon substrate is within the range of the orthographic projection of the deep N-well region 10 on the silicon substrate. The orthographic projection of the second N-type active region 102N on the silicon substrate does not overlap with the orthographic projection of the N-well region 20 on the silicon substrate. The second N-type active region 102N may serve as the active region of the second N-type transistor N2.

[0177] In an exemplary embodiment, the third N-type active region 103N may be block-shaped (e.g., rectangular) and may be located on one side of the eighth P-type active region 108P in the second direction Y. The third N-type active region 103N is located within the region where the deep N-well region 10 is located, but outside the region where the N-well region 20 is located. The orthographic projection of the third N-type active region 103N on the silicon substrate is within the range of the orthographic projection of the deep N-well region 10 on the silicon substrate. The orthographic projection of the third N-type active region 103N on the silicon substrate does not overlap with the orthographic projection of the N-well region 20 on the silicon substrate. The third N-type active region 103N may serve as the active region of the third N-type transistor N3.

[0178] In an exemplary embodiment, the second N-type active region 102N and the third N-type active region 103N may be an integral structure connected to each other.

[0179] In an exemplary embodiment, the second to thirteenth P-type active regions 102P to 113P of the integrated structure may have an active center line O, which may be a straight line that bisects the second to thirteenth P-type active regions 102P to 113P of the integrated structure in the first direction X and extends along the second direction Y.

[0180] In an exemplary embodiment, the second to seventh P-type active regions 102P to 107P and the eighth to 113P P-type active regions 108P to 113P may be symmetrically disposed with respect to the active center line O. Specifically, the second P-type active region 102P and the thirteenth P-type active region 113P can be symmetrically arranged relative to the active center line O, the third P-type active region 103P and the twelfth P-type active region 112P can be symmetrically arranged relative to the active center line O, the fourth P-type active region 104P and the eleventh P-type active region 111P can be symmetrically arranged relative to the active center line O, the fifth P-type active region 105P and the tenth P-type active region 110P can be symmetrically arranged relative to the active center line O, the sixth P-type active region 106P and the ninth P-type active region 109P can be symmetrically arranged relative to the active center line O, and the seventh P-type active region 107P and the eighth P-type active region 108P can be symmetrically arranged relative to the active center line O.

[0181] In an exemplary embodiment, the second N-type active region 102N and the third N-type active region 103N may be symmetrically disposed with respect to the active center line O.

[0182] In an exemplary embodiment, the shape of the twenty-first P-type active region 121P can be block-shaped (such as a rectangle), the twenty-first P-type active region 121P can be located within the area where the deep N-well region 10 and the N-well region 20 are located, the orthographic projection of the twenty-first P-type active region 121P on the silicon substrate is located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate, and the twenty-first P-type active region 121P can serve as the active region of the twenty-first P-type transistor P21.

[0183] In an exemplary embodiment, the shape of the twenty-second P-type active region 122P can be block-shaped (such as rectangular), the twenty-second P-type active region 122P can be located within the area where the deep N-well region 10 and the N-well region 20 are located, the orthographic projection of the twenty-second P-type active region 122P on the silicon substrate is located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate, and the twenty-second P-type active region 122P can serve as the active region of the twenty-second P-type transistor P22.

[0184] In exemplary embodiments, the twenty-first P-type active region 121P and the twenty-second P-type active region 122P may be an integral structure connected to each other.

[0185] In an exemplary embodiment, the shape of the twenty-third P-type active region 123P can be block-shaped (such as rectangular), the twenty-third P-type active region 123P can be located within the area where the deep N-well region 10 and the N-well region 20 are located, the orthographic projection of the twenty-third P-type active region 123P on the silicon substrate is located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate, and the twenty-third P-type active region 123P can serve as the active region of the twenty-third P-type transistor P23.

[0186] In an exemplary embodiment, the shape of the twenty-fourth P-type active region 124P can be block-shaped (such as rectangular), the twenty-fourth P-type active region 124P can be located within the area where the deep N-well region 10 and the N-well region 20 are located, the orthographic projection of the twenty-fourth P-type active region 124P on the silicon substrate is located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate, and the twenty-fourth P-type active region 124P can serve as the active region of the twenty-fourth P-type transistor P24.

[0187] In an exemplary embodiment, the shape of the twenty-fifth P-type active region 125P can be block-shaped (such as rectangular), the twenty-fifth P-type active region 125P can be located within the area where the deep N-well region 10 and the N-well region 20 are located, the orthographic projection of the twenty-fifth P-type active region 125P on the silicon substrate is located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate, and the twenty-fifth P-type active region 125P can serve as the active region of the twenty-fifth P-type transistor P25.

[0188] In exemplary embodiments, the twenty-fourth P-type active region 124P and the twenty-fifth P-type active region 125P may be an integral structure connected to each other.

[0189] In an exemplary embodiment, the shape of the twenty-sixth P-type active region 126P can be block-shaped (such as a rectangle), the twenty-sixth P-type active region 126P can be located within the area where the deep N-well region 10 and the N-well region 20 are located, the orthographic projection of the twenty-sixth P-type active region 126P on the silicon substrate is located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate, and the twenty-sixth P-type active region 126P can serve as the active region of the twenty-sixth P-type transistor P26.

[0190] In an exemplary embodiment, the shape of the twenty-seventh P-type active region 127P can be block-shaped (such as rectangular), the twenty-seventh P-type active region 127P can be located within the area where the deep N-well region 10 and the N-well region 20 are located, the orthographic projection of the twenty-seventh P-type active region 127P on the silicon substrate is located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate, and the twenty-seventh P-type active region 127P can serve as the active region of the twenty-seventh P-type transistor P27.

[0191] In an exemplary embodiment, the shape of the twenty-eighth P-type active region 128P can be block-shaped (such as rectangular), the twenty-eighth P-type active region 128P can be located within the area where the deep N-well region 10 and the N-well region 20 are located, the orthographic projection of the twenty-eighth P-type active region 128P on the silicon substrate is located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate, and the twenty-eighth P-type active region 128P can serve as the active region of the twenty-eighth P-type transistor P28.

[0192] In an exemplary embodiment, the shape of the twenty-ninth P-type active region 129P can be block-shaped (such as a rectangle), the twenty-ninth P-type active region 129P can be located within the area where the deep N-well region 10 and the N-well region 20 are located, the orthographic projection of the twenty-ninth P-type active region 129P on the silicon substrate is located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate, and the twenty-ninth P-type active region 129P can serve as the active region of the twenty-ninth P-type transistor P29.

[0193] In an exemplary embodiment, the shape of the thirtieth P-type active region 130P can be block-shaped (such as rectangular), the thirtieth P-type active region 130P can be located within the area where the deep N-well region 10 and the N-well region 20 are located, the orthographic projection of the thirtieth P-type active region 130P on the silicon substrate is located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate, and the thirtieth P-type active region 130P can serve as the active region of the thirtieth P-type transistor P30.

[0194] In an exemplary embodiment, the twenty-seventh to thirtieth P-type active regions 127P to 130P may be an integral structure connected to each other.

[0195] In an exemplary embodiment, the twenty-first N-type active region 121N may be block-shaped (e.g., rectangular) and may be located on one side of the twenty-first P-type active region 121P in the second direction Y. The twenty-first N-type active region 121N may be located within the region where the deep N-well region 10 and the N-well region 20 are located. The orthographic projection of the twenty-first N-type active region 121N on the silicon substrate may be located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate. The twenty-first N-type active region 121N may serve as the active region of the twenty-first N-type transistor N21.

[0196] In an exemplary embodiment, the twenty-second N-type active region 122N may be block-shaped (e.g., rectangular) and may be located on one side of the twenty-second P-type active region 122P in the second direction Y. The twenty-second N-type active region 122N may be located within the region where the deep N-well region 10 and the N-well region 20 are located. The orthographic projection of the twenty-second N-type active region 122N on the silicon substrate may be located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate. The twenty-second N-type active region 122N may serve as the active region of the twenty-second N-type transistor N22.

[0197] In exemplary embodiments, the twenty-first N-type active region 121N and the twenty-second N-type active region 122N may be an integral structure connected to each other.

[0198] In an exemplary embodiment, the twenty-third N-type active region 123N may be block-shaped (e.g., rectangular) and may be located on one side of the twenty-third P-type active region 123P in the second direction Y. The twenty-third N-type active region 123N may be located within the region where the deep N-well region 10 and the N-well region 20 are located. The orthographic projection of the twenty-third N-type active region 123N on the silicon substrate may be located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate. The twenty-third N-type active region 123N may serve as the active region of the twenty-third N-type transistor N23.

[0199] In an exemplary embodiment, the twenty-fourth N-type active region 124N may be block-shaped (e.g., rectangular) and may be located on one side of the twenty-fourth P-type active region 124P in the second direction Y. The twenty-fourth N-type active region 124N may be located within the region where the deep N-well region 10 and the N-well region 20 are located. The orthographic projection of the twenty-fourth N-type active region 124N on the silicon substrate may be located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate. The twenty-fourth N-type active region 124N may serve as the active region of the twenty-fourth N-type transistor N24.

[0200] In an exemplary embodiment, the twenty-fifth N-type active region 125N may be block-shaped (e.g., rectangular) and may be located on one side of the twenty-fifth P-type active region 125P in the second direction Y. The twenty-fifth N-type active region 125N may be located within the region where the deep N-well region 10 and the N-well region 20 are located. The orthographic projection of the twenty-fifth N-type active region 125N on the silicon substrate may be located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate. The twenty-fifth N-type active region 125N may serve as the active region of the twenty-fifth N-type transistor N25.

[0201] In exemplary embodiments, the twenty-fourth N-type active region 124N and the twenty-fifth N-type active region 125N may be an integral structure connected to each other.

[0202] In an exemplary embodiment, the twenty-sixth N-type active region 126N may be block-shaped (e.g., rectangular) and may be located on one side of the twenty-sixth P-type active region 126P in the second direction Y. The twenty-sixth N-type active region 126N may be located within the region where the deep N-well region 10 and the N-well region 20 are located. The orthographic projection of the twenty-sixth N-type active region 126N on the silicon substrate may be located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate. The twenty-sixth N-type active region 126N may serve as the active region of the twenty-sixth N-type transistor N26.

[0203] In an exemplary embodiment, the twenty-seventh N-type active region 127N may be block-shaped (e.g., rectangular) and may be located on one side of the twenty-seventh P-type active region 127P in the second direction Y. The twenty-seventh N-type active region 127N may be located within the region where the deep N-well region 10 and the N-well region 20 are located. The orthographic projection of the twenty-seventh N-type active region 127N on the silicon substrate may be located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate. The twenty-seventh N-type active region 127N may serve as the active region of the twenty-seventh N-type transistor N27.

[0204] In an exemplary embodiment, the twenty-eighth N-type active region 128N may be block-shaped (e.g., rectangular) and may be located on one side of the twenty-eighth P-type active region 128P in the second direction Y. The twenty-eighth N-type active region 128N may be located within the region where the deep N-well region 10 and the N-well region 20 are located. The orthographic projection of the twenty-eighth N-type active region 128N on the silicon substrate may be located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate. The twenty-eighth N-type active region 128N may serve as the active region of the twenty-eighth N-type transistor N28.

[0205] In an exemplary embodiment, the twenty-ninth N-type active region 129N may be block-shaped (e.g., rectangular) and may be located on one side of the twenty-ninth P-type active region 129P in the second direction Y. The twenty-ninth N-type active region 129N may be located within the region where the deep N-well region 10 and the N-well region 20 are located. The orthographic projection of the twenty-ninth N-type active region 129N on the silicon substrate may be located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate. The twenty-ninth N-type active region 129N may serve as the active region of the twenty-ninth N-type transistor N29.

[0206] In an exemplary embodiment, the 30th N-type active region 130N may be block-shaped (e.g., rectangular) and may be located on one side of the 30th P-type active region 130P in the second direction Y. The 30th N-type active region 130N may be located within the region where the deep N-well region 10 and the N-well region 20 are located. The orthographic projection of the 30th N-type active region 130N on the silicon substrate may be located within the range of the orthographic projections of the deep N-well region 10 and the N-well region 20 on the silicon substrate. The 30th N-type active region 130N may serve as the active region of the 30th N-type transistor N30.

[0207] In exemplary embodiments, the twenty-seventh to thirtieth N-type active regions 127N to 130N may be an integral structure connected to each other.

[0208] In an exemplary embodiment, the shape of the first power active region 100P can be a line shape extending along the first direction X, and can be arranged in the first region LS and the second region LD, that is, the first power active region 100P extends from the first region LS to the second region LD, and is located on a side of the multiple P-type active regions away from the multiple N-type active regions. The first power active region 100P is configured to be connected to a first power line formed subsequently.

[0209] In an exemplary embodiment, the first power active region 100P may be located outside the area where the deep N-well region 10 is located, but within the area where the N-well region 20 is located. The orthographic projection of the first power active region 100P on the silicon substrate does not overlap with the orthographic projection of the deep N-well region 10N on the silicon substrate. The orthographic projection of the first power active region 100P on the silicon substrate is within the range of the orthographic projection of the N-well region 20 on the silicon substrate.

[0210] In an exemplary embodiment, the second power active region 100N1 may be in the shape of a strip extending along the first direction X and may be disposed in the first region LS and the second region LD, i.e., the second power active region 100N1 extends from the first region LS to the second region LD and is located on a side of the plurality of N-type active regions away from the plurality of P-type active regions. The second power active region 100N1 is configured to be connected to a second power line formed subsequently.

[0211] In an exemplary embodiment, the second power active region 100N1 may be located within the region where the deep N-well region 10 is located, but outside the region where the N-well region 20 is located. The orthographic projection of the second power active region 100N1 on the silicon substrate is within the range of the orthographic projection of the deep N-well region 10 on the silicon substrate, and the orthographic projection of the second power active region 100N1 on the silicon substrate does not overlap with the orthographic projection of the N-well region 20 on the silicon substrate.

[0212] In an exemplary embodiment, the grounding active region 100N2 may be in the shape of a strip extending along the first direction X, may be disposed in the first region LS, and may be located on a side of the first N-type active region 101N away from the first P-type active region 101P. The grounding active region 100N2 is configured to be connected to a ground line formed subsequently.

[0213] In an exemplary embodiment, the grounding active region 100N2 may be located outside the region where the deep N-well region 10 and the N-well region 20 are located, and the orthographic projection of the grounding active region 100N2 on the silicon substrate does not overlap with the orthographic projection of the deep N-well region 10N on the silicon substrate, and the orthographic projection of the grounding active region 100N2 and the N-well region 20 on the silicon substrate do not overlap.

[0214] In example embodiments, in the first region LS, the first to thirteenth P-type active regions 101P to 113P may be sequentially disposed along the first direction X, and the first to third N-type active regions 101N to 103N may be sequentially disposed along the first direction X.

[0215] In example embodiments, in the second region LD, the twenty-first to thirtieth P-type active regions 121P to 130P may be sequentially disposed along the first direction X, and the twenty-first to thirtieth N-type active regions 121N to 130N may be sequentially disposed along the first direction X.

[0216] In an exemplary embodiment, a fourth distance S4 is present between an edge of the twenty-second P-type active region 122P on a side close to the twenty-third P-type active region 123P and an edge of the twenty-third P-type active region 123P on a side close to the twenty-second P-type active region 122P, and a fourth distance S4 is present between an edge of the twenty-second N-type active region 122N on a side close to the twenty-third N-type active region 123N and an edge of the twenty-third N-type active region 123N on a side close to the twenty-second N-type active region 122N. The fourth distance S4 may be greater than or equal to 0.36 μm.

[0217] In an exemplary embodiment, a third distance S3 is present between an edge of the twenty-third P-type active region 123P on a side close to the twenty-fourth P-type active region 124P and an edge of the twenty-fourth P-type active region 124P on a side close to the twenty-third P-type active region 123P, and a third distance S3 is present between an edge of the twenty-third N-type active region 123N on a side close to the twenty-fourth N-type active region 124N and an edge of the twenty-fourth N-type active region 124N on a side close to the twenty-third N-type active region 123N. The third distance S3 may be greater than or equal to 0.36 μm.

[0218] In an exemplary embodiment, a second distance S2 is present between an edge of the twenty-fifth P-type active region 125P on a side close to the twenty-sixth P-type active region 126P and an edge of the twenty-sixth P-type active region 126P on a side close to the twenty-fifth P-type active region 125P, and a second distance S2 is present between an edge of the twenty-fifth N-type active region 125N on a side close to the twenty-sixth N-type active region 126N and an edge of the twenty-sixth N-type active region 126N on a side close to the twenty-fifth N-type active region 125N. The second distance S2 may be greater than or equal to 0.36 μm.

[0219] In an exemplary embodiment, the second distance S2 may be equal to the third distance S3, and the third distance S3 may be equal to the fourth distance S4.

[0220] In an exemplary embodiment, a first distance S1 is provided between an edge of the twenty-sixth P-type active region 126P on a side close to the twenty-seventh P-type active region 127P and an edge of the twenty-seventh P-type active region 127P on a side close to the twenty-sixth P-type active region 126P, and a first distance S1 is provided between an edge of the twenty-sixth N-type active region 126N on a side close to the twenty-seventh N-type active region 127N and an edge of the twenty-seventh N-type active region 127N on a side close to the twenty-sixth N-type active region 126N. The first distance S1 may be greater than the second distance S2, the first distance S1 may be greater than the third distance S3, and the first distance S1 may be greater than the fourth distance S4.

[0221] In an exemplary embodiment, a ratio of the second distance S2 to the first distance S1 may be approximately 0.7 to 0.8.

[0222] In an exemplary embodiment, the first distance S1 may be greater than or equal to 0.5 μm.

[0223] In this exemplary embodiment, the twenty-first P-type active region 121P through the twenty-sixth P-type active region 126P and the twenty-first N-type active region 121N through the twenty-sixth N-type active region 126N respectively serve as the active layers of the transistors in the first NAND gate 301, the second NAND gate 302, the first transmission gate 201, and the second inverter 402. These regions form the signal control circuit portion of the row driver booster, and the current flowing through these circuits is relatively low. By setting minimum distances between the active regions of the first NAND gate 301 and the first transmission gate 201, between the first transmission gate 201 and the second NAND gate 302, and between the second NAND gate 302 and the second inverter 402, the present disclosure can effectively reduce the occupied space of the row driver booster, shorten signal lines, and minimize input impedance.

[0224] In this exemplary embodiment, the twenty-seventh P-type active region 127P through the thirtieth P-type active region 130P, and the twenty-seventh N-type active region 127N through the thirtieth N-type active region 130N, respectively, constitute the transistors of the third P-type transistor unit 503P and the third N-type transistor unit 503N. These transistors belong to the signal output circuit portion of the row driver booster and require high current output. By setting a minimum distance between the active regions of transistors in the signal control circuit portion and the active regions of transistors in the signal output circuit portion, the present disclosure effectively reduces the mutual influence between transistors in the signal control circuit portion and transistors in the signal output circuit portion, thereby improving operational reliability and ensuring signal control and signal output.

[0225] In example embodiments, the distance between the P-type active regions may correspond to the distance between the P-type transistors, and / or the distance between the N-type active regions may correspond to the distance between the N-type transistors.

[0226] In example embodiments, the distance between P-type transistors and / or the distance between N-type transistors may be equivalent to the distance between transistor groups.

[0227] In an exemplary embodiment, multiple N-type active regions can be located on one side of the multiple P-type active regions in the second direction Y, forming a compact arrangement layout that is separated in the second direction Y (separated up and down) and arranged sequentially in the first direction X (in a long strip shape).

[0228] In an exemplary embodiment, in the second direction Y, a gap region 50 may be provided between the P-type active region and the N-type active region in a transistor group. The gap region 50 is configured to serve as an isolation region between the P-type transistor and the N-type transistor on the one hand, and is configured to accommodate a gate via connecting the gate conductive layer and the first conductive layer on the other hand, thereby optimizing the structural layout of the gate drive circuit.

[0229] In an exemplary embodiment, the widths of the gap regions 50 in some transistor groups may be substantially the same, and the widths of the gap regions 50 in other transistor groups may be different. The width of the gap region may be a dimension in the second direction Y.

[0230] In the embodiment of the present disclosure, the widths of the plurality of gap regions 50 may be substantially the same, the edges of the plurality of P-type active regions close to the gap region 50 may be substantially located on the same straight line extending along the first direction X, and the edges of the plurality of N-type active regions close to the gap region 50 may be substantially located on the same straight line extending along the first direction X.

[0231] In an exemplary embodiment, the distance between the P-type active region and the N-type active region in a transistor group may be equivalent to the distance between the P-type transistor and the N-type transistor in the transistor group, that is, the gap region 50 may be the gap between the P-type transistor and the N-type transistor.

[0232] In an exemplary embodiment, the P-type active region in a transistor group may have a P-type active region width WP, and the N-type active region may have an N-type active region width WN. The P-type active region width WP may be the distance between an edge of the second P-type active region 102P on a side close to the power active region 100P and an edge of the second P-type active region 102P on a side away from the power active region 100P. The N-type active region width WN may be the distance between an edge of the second N-type active region 102N on a side close to the ground active region 100N2 (the second power active region 100N1) and an edge of the second N-type active region 102N on a side away from the ground active region 100N2 (the second power active region 100N1). The P-type active region width WP and the N-type active region width WN may be dimensions in the second direction Y.

[0233] In an exemplary embodiment, the widths of the P-type active regions in the first NAND gate and the second NAND gate may be substantially the same, and the widths of the P-type active regions in the first inverter and the second inverter may be substantially the same. The widths of the N-type active regions in the first NAND gate and the second NAND gate may be substantially the same, and the widths of the N-type active regions in the first inverter and the second inverter may be substantially the same.

[0234] In an exemplary embodiment, the widths of the P-type active regions in the first NAND gate and the first inverter may be different, and the widths of the N-type active regions in the first NAND gate and the first inverter may be different.

[0235] In an exemplary embodiment, the widths of the P-type active regions in the first P-type transistor unit and the second P-type transistor unit may be substantially the same, but different from the width of the P-type active region in the third P-type transistor unit. The widths of the N-type active regions in the first N-type transistor unit and the second N-type transistor unit may be substantially the same, but different from the width of the N-type active region in the third N-type transistor unit.

[0236] In an exemplary embodiment, the width of the P-type active area in the first P-type transistor unit and the second P-type transistor unit may be greater than the width of the P-type active area in the first NAND gate and the second NAND gate, the width of the P-type active area in the first NAND gate and the second NAND gate may be greater than the width of the P-type active area in the first transmission gate, the width of the P-type active area in the first transmission gate may be greater than the width of the P-type active area in the first inverter and the second inverter, and the width of the P-type active area in the first inverter and the second inverter may be equal to the width of the P-type active area in the third P-type transistor unit.

[0237] In an exemplary embodiment, the width of the N-type active area in the first transmission gate may be equal to the width of the N-type active area in the third N-type transistor unit, the width of the N-type active area in the first transmission gate may be greater than the width of the N-type active area in the first NAND gate and the second NAND gate, the width of the N-type active area in the first NAND gate and the second NAND gate may be greater than the width of the N-type active area in the first N-type transistor unit and the second N-type transistor unit, and the width of the N-type active area in the first N-type transistor unit and the second N-type transistor unit may be greater than the width of the N-type active area in the first inverter and the second inverter.

[0238] In an exemplary embodiment, in the second direction Y, the size of the P-type active area in the first P-type transistor unit may be larger than the length of the P-type active area in the first inverter, that is, the size of the P-type transistor in the first P-type transistor unit may be larger than the size of the P-type transistor in the first inverter.

[0239] In an exemplary embodiment, in the second direction Y, the size of the P-type active area in the second P-type transistor unit may be greater than the length of the P-type active area in the first inverter, that is, the size of the P-type transistor in the second P-type transistor unit may be greater than the size of the P-type transistor in the first inverter.

[0240] In an exemplary embodiment, in the first NAND gate and the second NAND gate, in the second direction Y, a distance between the P-type active region and the power active region may be substantially equal to a distance between the N-type active region and the second power active region.

[0241] By setting the positions of the P-type active area and the N-type active area, the present disclosure can effectively ensure the shortest connection lines between devices, optimize the layout design space, ensure that the resistance and capacitance loading (RC loading) of the gate electrodes of the P-type transistor and the N-type transistor are basically consistent, and improve uniformity.

[0242] (3) Forming a gate conductive layer pattern. In an exemplary embodiment, forming the gate conductive layer pattern may include: sequentially depositing a first insulating film and a polysilicon film on the silicon substrate on which the aforementioned pattern is formed, first patterning the polysilicon film through a patterning process to form a first insulating layer covering the silicon substrate and a polysilicon layer disposed on the first insulating layer, and then doping the polysilicon layer to form a gate conductive layer pattern, as shown in FIG14A and FIG14B , where FIG14B is a schematic diagram of the gate conductive layer in FIG14A .

[0243] In an exemplary embodiment, the gate conductive layer pattern may include at least first to thirteenth P-type gate electrodes 201P to 213P, twenty-first to thirtieth P-type gate electrodes 221P to 230P, first to third N-type gate electrodes 201N to 203N, and twenty-first to thirtieth N-type gate electrodes 221N to 230N.

[0244] In an exemplary embodiment, the first P-type gate electrode 201P to the thirteenth P-type gate electrode 213P, and the first N-type gate electrode 201N to the third N-type gate electrode 203N can be set in the first region LS, and the twenty-first P-type gate electrode 221P to the thirtieth P-type gate electrode 230P, and the twenty-first N-type gate electrode 221N to the thirtieth N-type gate electrode 230N can be set in the second region LD.

[0245] In an exemplary embodiment, the shape of the first P-type gate electrode 201P can be a strip shape extending along the second direction Y, the orthographic projection of the first P-type gate electrode 201P on the silicon substrate at least partially overlaps with the orthographic projection of the first P-type active region 101P on the silicon substrate, and the first P-type gate electrode 201P can serve as the gate electrode of the first P-type transistor P1.

[0246] In an exemplary embodiment, the shape of the first N-type gate electrode 201N can be a strip shape extending along the second direction Y, the orthographic projection of the first N-type gate electrode 201N on the silicon substrate at least partially overlaps with the orthographic projection of the first N-type active region 101N on the silicon substrate, and the first N-type gate electrode 201N can serve as the gate electrode of the first N-type transistor N1.

[0247] In an exemplary embodiment, the first P-type gate electrode 201P and the first N-type gate electrode 201N may be an integral structure connected to each other.

[0248] In an exemplary embodiment, the shape of the second P-type gate electrode 202P can be a strip shape extending along the second direction Y, and the orthographic projection of the second P-type gate electrode 202P on the silicon substrate at least partially overlaps with the orthographic projection of the second P-type active region 102P on the silicon substrate. The second P-type gate electrode 202P can serve as the gate electrode of the second P-type transistor P2.

[0249] In an exemplary embodiment, the shape of the third P-type gate electrode 203P can be a strip shape extending along the second direction Y, and the orthographic projection of the third P-type gate electrode 203P on the silicon substrate at least partially overlaps with the orthographic projection of the third P-type active area 103P on the silicon substrate, and the third P-type gate electrode 203P can serve as the gate electrode of the third P-type transistor P3.

[0250] In an exemplary embodiment, the shape of the fourth P-type gate electrode 204P can be a strip shape extending along the second direction Y, and the orthographic projection of the fourth P-type gate electrode 204P on the silicon substrate at least partially overlaps with the orthographic projection of the fourth P-type active region 104P on the silicon substrate, and the fourth P-type gate electrode 204P can serve as the gate electrode of the fourth P-type transistor P4.

[0251] In an exemplary embodiment, the shape of the fifth P-type gate electrode 205P can be a strip shape extending along the second direction Y, and the orthographic projection of the fifth P-type gate electrode 205P on the silicon substrate at least partially overlaps with the orthographic projection of the fifth P-type active region 105P on the silicon substrate, and the fifth P-type gate electrode 205P can serve as the gate electrode of the fifth P-type transistor P5.

[0252] In an exemplary embodiment, the shape of the sixth P-type gate electrode 206P can be a strip shape extending along the second direction Y, the orthographic projection of the sixth P-type gate electrode 206P on the silicon substrate at least partially overlaps with the orthographic projection of the sixth P-type active region 106P on the silicon substrate, and the sixth P-type gate electrode 206P can serve as the gate electrode of the sixth P-type transistor P6.

[0253] In an exemplary embodiment, the shape of the seventh P-type gate electrode 207P can be a strip shape extending along the second direction Y, and the orthographic projection of the seventh P-type gate electrode 207P on the silicon substrate at least partially overlaps with the orthographic projection of the seventh P-type active region 107P on the silicon substrate, and the seventh P-type gate electrode 207P can serve as the gate electrode of the seventh P-type transistor P7.

[0254] In an exemplary embodiment, the eighth P-type gate electrode 208P may be in the shape of a strip extending along the second direction Y. The orthographic projection of the eighth P-type gate electrode 208P on the silicon substrate at least partially overlaps with the orthographic projection of the eighth P-type active region 108P on the silicon substrate. The eighth P-type gate electrode 208P may serve as the gate electrode of the eighth P-type transistor P8.

[0255] In an exemplary embodiment, the ninth P-type gate electrode 209P may be in the shape of a strip extending along the second direction Y. The orthographic projection of the ninth P-type gate electrode 209P on the silicon substrate at least partially overlaps with the orthographic projection of the ninth P-type active region 108P on the silicon substrate. The ninth P-type gate electrode 209P may serve as the gate electrode of the ninth P-type transistor P9.

[0256] In an exemplary embodiment, the shape of the tenth P-type gate electrode 210P can be a strip shape extending along the second direction Y, and the orthographic projection of the tenth P-type gate electrode 210P on the silicon substrate at least partially overlaps with the orthographic projection of the tenth P-type active region 110P on the silicon substrate, and the tenth P-type gate electrode 210P can serve as the gate electrode of the tenth P-type transistor P10.

[0257] In an exemplary embodiment, the shape of the eleventh P-type gate electrode 211P can be a strip shape extending along the second direction Y, the orthographic projection of the eleventh P-type gate electrode 211P on the silicon substrate at least partially overlaps with the orthographic projection of the eleventh P-type active region 111P on the silicon substrate, and the eleventh P-type gate electrode 211P can serve as the gate electrode of the eleventh P-type transistor P11.

[0258] In an exemplary embodiment, the shape of the twelfth P-type gate electrode 212P can be a strip shape extending along the second direction Y, the orthographic projection of the twelfth P-type gate electrode 212P on the silicon substrate at least partially overlaps with the orthographic projection of the twelfth P-type active region 112P on the silicon substrate, and the twelfth P-type gate electrode 212P can serve as the gate electrode of the twelfth P-type transistor P12.

[0259] In an exemplary embodiment, the shape of the thirteenth P-type gate electrode 213P can be a strip shape extending along the second direction Y, the orthographic projection of the thirteenth P-type gate electrode 213P on the silicon substrate at least partially overlaps with the orthographic projection of the thirteenth P-type active region 113P on the silicon substrate, and the thirteenth P-type gate electrode 213P can serve as the gate electrode of the thirteenth P-type transistor P13.

[0260] In an exemplary embodiment, the second to thirteenth P-type gate electrodes 202P to 213P may be sequentially disposed along the first direction X, and positions and shapes of the plurality of gate electrodes may be symmetrically disposed with respect to the active center line O.

[0261] In an exemplary embodiment, the gate electrode of the second P-type transistor P2 to the gate electrode of the seventh P-type transistor P7 in the first P-type transistor unit and the gate electrode of the eighth P-type transistor P8 to the gate electrode of the thirteenth P-type transistor P13 in the second P-type transistor unit are symmetrically arranged relative to the active center line O, which can ensure the symmetry of the P-type transistor units in the level converter and improve the consistency of the output high and low levels.

[0262] In an exemplary embodiment, the length of the second P-type gate electrode 202P is equal to the length of the thirteenth P-type gate electrode 213P, and the width of the second P-type gate electrode 202P is equal to the width of the thirteenth P-type gate electrode 213P. The overlapping areas of the second P-type gate electrode 202P and the corresponding active regions are equal. A first length LP1 is defined between the edge of the second P-type gate electrode 202P on the side away from the active center line O and the active center line O, and a second length LP2 is defined between the edge of the thirteenth P-type gate electrode 213P on the side away from the active center line O and the active center line O. The ratio of the first length LP1 to the second length LP2 may be approximately 0.95 to 1.05. In an exemplary embodiment, the length refers to the dimension in the second direction Y, and the width refers to the dimension in the first direction X.

[0263] In an exemplary embodiment, the first length LP1 and the second length LP2 may be substantially equal.

[0264] In an exemplary embodiment, the length of the third P-type gate electrode 203P is equal to the length of the twelfth P-type gate electrode 212P, the width of the third P-type gate electrode 203P is equal to the width of the twelfth P-type gate electrode 212P, and the overlapping area of ​​the two with the corresponding active regions is equal; the edge of the third P-type gate electrode 203P away from the active center line O has a first sub-length LP101 with the active center line O, and the edge of the twelfth P-type gate electrode 212P away from the active center line O has a second sub-length LP102 with the active center line O, and the ratio of the first sub-length LP101 to the second sub-length LP102 can be approximately 0.95 to 1.05.

[0265] In an exemplary embodiment, the first sub-length LP101 and the second sub-length LP102 may be substantially equal.

[0266] In an exemplary embodiment, the length of the fourth P-type gate electrode 204P is equal to the length of the eleventh P-type gate electrode 211P, the width of the fourth P-type gate electrode 204P is equal to the width of the eleventh P-type gate electrode 211P, and the overlapping area of ​​the two with the corresponding active regions is equal; the edge of the fourth P-type gate electrode 204P away from the active center line O has a third sub-length LP103 from the active center line O, and the edge of the eleventh P-type gate electrode 211P away from the active center line O has a fourth sub-length LP104 from the active center line O, and the ratio of the third sub-length LP103 to the fourth sub-length LP104 can be approximately 0.95 to 1.05.

[0267] In an exemplary embodiment, the third sub-length LP103 and the fourth sub-length LP104 may be substantially equal.

[0268] In an exemplary embodiment, the length of the fifth P-type gate electrode 205P is equal to the length of the tenth P-type gate electrode 210P, the width of the fifth P-type gate electrode 205P is equal to the width of the tenth P-type gate electrode 210P, and the overlapping area of ​​the two with the corresponding active regions is equal; the edge of the fifth P-type gate electrode 205P away from the active center line O has a fifth sub-length LP105 with the active center line O, and the edge of the tenth P-type gate electrode 210P away from the active center line O has a sixth sub-length LP106 with the active center line O, and the ratio of the fifth sub-length LP105 to the sixth sub-length LP106 can be approximately 0.95 to 1.05.

[0269] In an exemplary embodiment, the fifth sub-length LP105 and the sixth sub-length LP106 may be substantially equal.

[0270] In an exemplary embodiment, the length of the sixth P-type gate electrode 206P is equal to the length of the ninth P-type gate electrode 209P, the width of the sixth P-type gate electrode 206P is equal to the width of the ninth P-type gate electrode 209P, and the overlapping area of ​​the two with the corresponding active regions is equal; the edge of the sixth P-type gate electrode 206P away from the active center line O has a seventh sub-length LP107 with the active center line O, and the edge of the ninth P-type gate electrode 209P away from the active center line O has an eighth sub-length LP108 with the active center line O, and the ratio of the seventh sub-length LP107 to the eighth sub-length LP108 can be approximately 0.95 to 1.05.

[0271] In an exemplary embodiment, the seventh sub-length LP107 and the eighth sub-length LP108 may be substantially equal.

[0272] In an exemplary embodiment, the length of the seventh P-type gate electrode 207P is equal to the length of the eighth P-type gate electrode 208P, the width of the seventh P-type gate electrode 207P is equal to the width of the eighth P-type gate electrode 208P, and the overlapping area of ​​the two with the corresponding active regions is equal; there is a ninth sub-length LP109 between the edge of the seventh P-type gate electrode 207P away from the active center line O and the active center line O, and there is a tenth sub-length LP110 between the edge of the eighth P-type gate electrode 208P away from the active center line O and the active center line O, and the ratio of the ninth sub-length LP109 to the tenth sub-length LP110 can be approximately 0.95 to 1.05.

[0273] In an exemplary embodiment, the ninth sub-length LP109 and the tenth sub-length LP110 may be substantially equal.

[0274] In an exemplary embodiment, the second N-type gate electrode 202N may be in the shape of a strip extending along the second direction Y, and the orthographic projection of the second N-type gate electrode 202N on the silicon substrate at least partially overlaps with the orthographic projection of the second N-type active region 102N on the silicon substrate. The second N-type gate electrode 202N may serve as the gate electrode of the second N-type transistor N2.

[0275] In an exemplary embodiment, the shape of the third N-type gate electrode 203N can be a strip shape extending along the second direction Y, the orthographic projection of the third N-type gate electrode 203N on the silicon substrate at least partially overlaps with the orthographic projection of the third N-type active region 103N on the silicon substrate, and the third N-type gate electrode 203N can serve as the gate electrode of the third N-type transistor N3.

[0276] In an exemplary embodiment, the second N-type gate electrode 202N and the third N-type gate electrode 203N may be sequentially disposed along the first direction X, and the two gate electrodes may be symmetrically disposed with respect to the active center line O.

[0277] In an exemplary embodiment, the gate electrode of the second N-type transistor N2 in the first N-type transistor unit and the gate electrode of the third N-type transistor N3 in the second N-type transistor unit are symmetrically arranged relative to the active center line O, which can ensure the symmetry of the N-type transistor units in the level converter and improve the consistency of the output high and low levels.

[0278] In an exemplary embodiment, the length of the second N-type gate electrode 202N is equal to the length of the third N-type gate electrode 203N, the width of the second N-type gate electrode 202N is equal to the width of the third N-type gate electrode 203N, and the overlapping area of ​​the two with the corresponding active regions is equal; there is a third length LN3 between the edge of the second N-type gate electrode 202N on the side away from the active center line O and the active center line O, and there is a fourth length LN4 between the edge of the third N-type gate electrode 203N on the side away from the active center line O and the active center line O. The ratio of the third length LN3 to the fourth length LN4 can be approximately 0.95 to 1.05.

[0279] In an exemplary embodiment, the third length LN3 and the fourth length LN4 may be substantially equal.

[0280] In an exemplary embodiment, the shape of the twenty-first P-type gate electrode 221P can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-first P-type gate electrode 221P on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-first P-type active region 121P on the silicon substrate, and the twenty-first P-type gate electrode 221P can serve as the gate electrode of the twenty-first P-type transistor P21.

[0281] In an exemplary embodiment, the shape of the twenty-first N-type gate electrode 221N can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-first N-type gate electrode 221N on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-first N-type active region 121N on the silicon substrate, and the twenty-first N-type gate electrode 221N can serve as the gate electrode of the twenty-first N-type transistor N21.

[0282] In exemplary embodiments, the twenty-first P-type gate electrode 221P and the twenty-first N-type gate electrode 221N may be an integral structure connected to each other.

[0283] In an exemplary embodiment, the shape of the twenty-second P-type gate electrode 222P can be a strip shape extending along the second direction Y, and the orthographic projection of the twenty-second P-type gate electrode 222P on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-second P-type active region 122P on the silicon substrate, and the twenty-second P-type gate electrode 222P can serve as the gate electrode of the twenty-second P-type transistor P22.

[0284] In an exemplary embodiment, the shape of the twenty-second N-type gate electrode 222N can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-second N-type gate electrode 222N on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-second N-type active region 122N on the silicon substrate, and the twenty-second N-type gate electrode 222N can serve as the gate electrode of the twenty-second N-type transistor N22.

[0285] In exemplary embodiments, the twenty-second P-type gate electrode 222P and the twenty-second N-type gate electrode 222N may be an integral structure connected to each other.

[0286] In an exemplary embodiment, the shape of the twenty-third P-type gate electrode 223P can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-third P-type gate electrode 223P on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-third P-type active area 123P on the silicon substrate, and the twenty-third P-type gate electrode 223P can serve as the gate electrode of the twenty-third P-type transistor P23.

[0287] In an exemplary embodiment, the shape of the twenty-third N-type gate electrode 223N can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-third N-type gate electrode 223N on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-third N-type active region 123N on the silicon substrate, and the twenty-third N-type gate electrode 201N can serve as the gate electrode of the twenty-third N-type transistor N23.

[0288] In an exemplary embodiment, the shape of the twenty-fourth P-type gate electrode 224P can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-fourth P-type gate electrode 224P on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-fourth P-type active area 124P on the silicon substrate, and the twenty-fourth P-type gate electrode 224P can serve as the gate electrode of the twenty-fourth P-type transistor P24.

[0289] In an exemplary embodiment, the shape of the twenty-fourth N-type gate electrode 224N can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-fourth N-type gate electrode 224N on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-fourth N-type active region 124N on the silicon substrate, and the twenty-fourth N-type gate electrode 224N can serve as the gate electrode of the twenty-fourth N-type transistor N24.

[0290] In exemplary embodiments, the twenty-fourth P-type gate electrode 224P and the twenty-fourth N-type gate electrode 224N may be an integral structure connected to each other.

[0291] In an exemplary embodiment, the shape of the twenty-fifth P-type gate electrode 225P can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-fifth P-type gate electrode 225P on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-fifth P-type active area 125P on the silicon substrate, and the twenty-fifth P-type gate electrode 225P can serve as the gate electrode of the twenty-fifth P-type transistor P22.

[0292] In an exemplary embodiment, the shape of the twenty-fifth N-type gate electrode 225N can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-fifth N-type gate electrode 225N on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-fifth N-type active region 125N on the silicon substrate, and the twenty-fifth N-type gate electrode 225N can serve as the gate electrode of the twenty-fifth N-type transistor N22.

[0293] In exemplary embodiments, the twenty-fifth P-type gate electrode 225P and the twenty-fifth N-type gate electrode 225N may be an integral structure connected to each other.

[0294] In an exemplary embodiment, the shape of the twenty-sixth P-type gate electrode 226P can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-sixth P-type gate electrode 226P on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-sixth P-type active region 126P on the silicon substrate, and the twenty-sixth P-type gate electrode 226P can serve as the gate electrode of the twenty-sixth P-type transistor P26.

[0295] In an exemplary embodiment, the shape of the twenty-sixth N-type gate electrode 226N can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-sixth N-type gate electrode 226N on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-sixth N-type active region 126N on the silicon substrate, and the twenty-sixth N-type gate electrode 226N can serve as the gate electrode of the twenty-sixth N-type transistor N26.

[0296] In exemplary embodiments, the twenty-sixth P-type gate electrode 226P and the twenty-sixth N-type gate electrode 226N may be an integral structure connected to each other.

[0297] In an exemplary embodiment, the shape of the twenty-seventh P-type gate electrode 227P can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-seventh P-type gate electrode 227P on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-seventh P-type active region 127P on the silicon substrate, and the twenty-seventh P-type gate electrode 227P can serve as the gate electrode of the twenty-seventh P-type transistor P27.

[0298] In an exemplary embodiment, the shape of the twenty-seventh N-type gate electrode 227N can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-seventh N-type gate electrode 227N on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-seventh N-type active region 127N on the silicon substrate, and the twenty-seventh N-type gate electrode 227N can serve as the gate electrode of the twenty-seventh N-type transistor N27.

[0299] In an exemplary embodiment, the shape of the twenty-eighth P-type gate electrode 228P can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-eighth P-type gate electrode 228P on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-eighth P-type active region 128P on the silicon substrate, and the twenty-eighth P-type gate electrode 228P can serve as the gate electrode of the twenty-eighth P-type transistor P28.

[0300] In an exemplary embodiment, the shape of the twenty-eighth N-type gate electrode 228N can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-eighth N-type gate electrode 228N on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-eighth N-type active region 128N on the silicon substrate, and the twenty-eighth N-type gate electrode 228N can serve as the gate electrode of the twenty-eighth N-type transistor N28.

[0301] In an exemplary embodiment, the shape of the twenty-ninth P-type gate electrode 229P can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-ninth P-type gate electrode 229P on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-ninth P-type active region 129P on the silicon substrate, and the twenty-ninth P-type gate electrode 229P can serve as the gate electrode of the twenty-ninth P-type transistor P29.

[0302] In an exemplary embodiment, the shape of the twenty-ninth N-type gate electrode 229N can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-ninth N-type gate electrode 229N on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-ninth N-type active region 129N on the silicon substrate, and the twenty-ninth N-type gate electrode 229N can serve as the gate electrode of the twenty-ninth N-type transistor N29.

[0303] In an exemplary embodiment, the shape of the thirtieth P-type gate electrode 230P can be a strip shape extending along the second direction Y, and the orthographic projection of the thirtieth P-type gate electrode 230P on the silicon substrate at least partially overlaps with the orthographic projection of the third second P-type active region 130P on the silicon substrate, and the thirtieth P-type gate electrode 230P can serve as the gate electrode of the thirtieth P-type transistor P30.

[0304] In an exemplary embodiment, the shape of the 30th N-type gate electrode 230N can be a strip shape extending along the second direction Y, the orthographic projection of the 30th N-type gate electrode 230N on the silicon substrate at least partially overlaps with the orthographic projection of the 32nd N-type active region 130N on the silicon substrate, and the 30th N-type gate electrode 230N can serve as the gate electrode of the 30th N-type transistor N30.

[0305] In example embodiments, the twenty-first to thirtieth P-type gate electrodes 221P to 230P may be sequentially disposed along the first direction X, and the twenty-first to thirtieth N-type gate electrodes 221N to 230N may be sequentially disposed along the first direction X.

[0306] In an exemplary embodiment, the widths of the twenty-first to thirtieth P-type gate electrodes 221P to 230P are substantially equal, and the widths of the twenty-first to thirtieth N-type gate electrodes 221N to 230N are substantially equal.

[0307] (4) Forming a P-type doped (SP) region pattern. In an exemplary embodiment, forming the P-type doped region pattern may include: coating a photoresist on the silicon substrate on which the aforementioned pattern is formed, forming a plurality of opening regions through exposure and development, removing the photoresist within the plurality of opening regions, and forming a plurality of P-type doped regions within the opening regions through a doping process, as shown in FIG15A and FIG15B , where FIG15B is a schematic diagram of the P-type doped region in FIG15A .

[0308] In an exemplary embodiment, the plurality of P-type doping regions may include at least a first P-type doping region 31 , a second P-type doping region 32 , a third P-type doping region 33 , and a fourth P-type doping region 34 .

[0309] In an exemplary embodiment, the first P-type doping region 31 can be arranged in the first region LS and is located outside the region where the deep N-well region 10 is located, but is located within the region where the N-well region 20 is located. The orthographic projection of the first P-type doping region 31 on the silicon substrate includes the orthographic projection of the first P-type active region 101P on the silicon substrate, so that the first P-type active regions 101P located on both sides of the first P-type gate electrode 201P in the first direction X respectively form the first P-type source region and the first P-type drain region of the first P-type transistor P1.

[0310] In an exemplary embodiment, the second P-type doping region 32 can be arranged in the first region LS and the second region LD, that is, the second P-type doping region 32 extends from the first region LS to the second region LD, and is located within the region where the deep N-well region 10 and the N-well region 20 are located. The positive projection of the second P-type doping region 32 on the silicon substrate includes the positive projections of the second P-type active region 102P to the thirteenth P-type active region 113P and the twenty-first P-type active region 121P to the thirtieth P-type active region 130P on the silicon substrate, so that the active regions located on both sides of the first direction X of the multiple P-type gate electrodes respectively form multiple P-type source regions and multiple P-type drain regions.

[0311] In an exemplary embodiment, the active region between two adjacent P-type gate electrodes in the first direction X may serve as the P-type source regions of two P-type transistors, or may serve as the P-type drain regions of two P-type transistors, or may serve as the P-type source region of one P-type transistor and the P-type drain region of another P-type transistor.

[0312] In an exemplary embodiment, the P-type source region and the P-type drain region of each P-type transistor are both P-type heavily doped regions P+.

[0313] In an exemplary embodiment, the third P-type doping region 33 can be arranged in the first region LS and the second region LD, that is, the second P-type doping region 32 extends from the first region LS to the second region LD, and is located within the region where the deep N-well region 10 is located, but outside the region where the N-well region 20 is located, and the orthographic projection of the third P-type doping region 33 on the silicon substrate includes the orthographic projection of the second power active region 100N1 on the silicon substrate.

[0314] In an exemplary embodiment, the fourth P-type doping region 34 can be set in the first region LS and is located outside the region where the deep N-well region 10 and the N-well region 20 are located. The orthographic projection of the fourth P-type doping region 34 on the silicon substrate includes the orthographic projection of the ground active region 100N2 on the silicon substrate.

[0315] (5) Forming an N-type doping (SN) region pattern. In an exemplary embodiment, forming the N-type doping region pattern may include: coating a photoresist on the silicon substrate on which the aforementioned pattern is formed, forming a plurality of opening regions by exposure and development, removing the photoresist within the plurality of opening regions, and forming a plurality of N-type doping regions within the opening regions by a doping process, as shown in FIG16A and FIG16B , where FIG16B is a schematic diagram of the N-type doping region in FIG16A .

[0316] In an exemplary embodiment, the plurality of N-type doping regions may include at least a first N-type doping region 41 , a second N-type doping region 42 , a third N-type doping region 43 , and a fourth N-type doping region 44 .

[0317] In an exemplary embodiment, the first N-type doping region 41 can be disposed in the first region LS and located outside the region where the deep N-well region 10 and the N-well region 20 are located. The orthographic projection of the first N-type doping region 41 on the silicon substrate includes the orthographic projection of the first N-type active region 101N on the silicon substrate, so that the first N-type active regions 101N located on both sides of the first N-type gate electrode 201N in the first direction X respectively form the first N-type source region and the first N-type drain region of the first N-type transistor N1.

[0318] In an exemplary embodiment, the second N-type doping region 42 can be disposed in the first region LS and is located within the region where the deep N-well region 10 is located, but outside the region where the N-well region 20 is located. The orthographic projection of the second N-type doping region 42 on the silicon substrate includes the orthographic projections of the second N-type active region 102N and the third N-type active region 103N on the silicon substrate, so that the active regions located on both sides of the second N-type gate electrode 202N and the third N-type gate electrode 203N in the first direction X form N-type source regions and N-type drain regions.

[0319] In an exemplary embodiment, the third N-type doping region 43 can be disposed in the second region LD and is located within the region where the deep N-well region 10 is located, but outside the region where the N-well region 20 is located. The orthographic projection of the third N-type doping region 43 on the silicon substrate includes the orthographic projections of the twenty-first N-type active region 121N to the thirtieth N-type active region 130N on the silicon substrate, so that the active regions located on both sides of the first direction X of the multiple N-type gate electrodes respectively form multiple N-type source regions and multiple N-type drain regions.

[0320] In an exemplary embodiment, the active region between two adjacent N-type gate electrodes in the first direction X may serve as N-type source regions of two N-type transistors, or may serve as N-type drain regions of two N-type transistors, or may serve as the N-type source region of one N-type transistor and the N-type drain region of another N-type transistor.

[0321] In an exemplary embodiment, the N-type source region and the N-type drain region of each N-type transistor are both N-type heavily doped regions N+.

[0322] In an exemplary embodiment, the fourth N-type doping region 44 can be arranged in the first region LS and the second region LD, that is, the fourth N-type doping region 44 extends from the first region LS to the second region LD, and is located outside the region where the deep N-well region 10 is located, but within the region where the N-well region 20 is located, and the orthographic projection of the fourth N-type doping region 44 on the silicon substrate includes the orthographic projection of the first power active region 100P on the silicon substrate.

[0323] (6) Forming a second insulating layer pattern. In an exemplary embodiment, forming the second insulating layer pattern may include: depositing a second insulating film on the silicon substrate having the aforementioned pattern formed thereon, patterning the second insulating film through a patterning process to form a second insulating layer covering the gate conductive layer pattern, wherein a plurality of vias are provided on the second insulating layer, as shown in FIG. 17 .

[0324] In an exemplary embodiment, the plurality of via holes may include at least first to eighty-third via holes V1 to V83 .

[0325] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the silicon substrate can be located within the range of the orthographic projection of the first P-type source region of the first P-type transistor P1 on the silicon substrate. The first insulating layer and the second insulating layer in the first via hole V1 are etched away to expose the surface of the first P-type source region. The first via hole V1 is configured to connect the subsequently formed sixteenth connecting electrode to the first P-type source region through the via hole.

[0326] In an exemplary embodiment, the orthographic projection of the second via V2 on the silicon substrate can be located within the range of the orthographic projection of the first P-type drain region of the first P-type transistor P1 on the silicon substrate, the first insulating layer and the second insulating layer in the second via V2 are etched away to expose the surface of the first P-type drain region, and the second via V2 is configured to connect the subsequently formed seventeenth connecting electrode to the first P-type drain region through the via.

[0327] In an exemplary embodiment, the orthographic projection of the third via V3 on the silicon substrate can be located within the range of the orthographic projection of the first N-type source region of the first N-type transistor N1 on the silicon substrate, the first insulating layer and the second insulating layer in the third via V3 are etched away to expose the surface of the first N-type source region, and the third via V3 is configured to connect the subsequently formed eighteenth connecting electrode to the first N-type source region through the via.

[0328] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the silicon substrate can be located within the range of the orthographic projection of the first N-type drain region of the first N-type transistor N1 on the silicon substrate, the first insulating layer and the second insulating layer within the fourth via V4 are etched away to expose the surface of the first N-type drain region, and the fourth via V4 is configured to connect the subsequently formed seventeenth connecting electrode to the first N-type drain region through the via.

[0329] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the silicon substrate can be located within the range of the orthographic projection of the second P-type source region of the second P-type transistor P2 on the silicon substrate, the second insulating layer and the second insulating layer within the fifth via V5 are etched away to expose the surface of the second P-type source region, and the fifth via V5 is configured to connect the subsequently formed nineteenth connecting electrode to the second P-type source region through the via.

[0330] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the silicon substrate can be located within the range of the orthographic projection of the second P-type drain region of the second P-type transistor P2 (also the third P-type drain region of the third P-type transistor P3) on the silicon substrate, the first insulating layer and the second insulating layer within the sixth via V6 are etched away to expose the surface of the second P-type drain region (also the third P-type drain region), and the sixth via V6 is configured to connect the subsequently formed twentieth connecting electrode to the second P-type drain region (also the third P-type drain region) through the via.

[0331] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the silicon substrate can be located within the range of the orthographic projection of the third P-type source region of the third P-type transistor P3 (also the fourth P-type source region of the fourth P-type transistor P4) on the silicon substrate, the first insulating layer and the second insulating layer in the seventh via V7 are etched away to expose the surface of the third P-type source region (also the fourth P-type source region), and the seventh via V7 is configured to connect the subsequently formed twenty-first connecting electrode to the third P-type source region (also the fourth P-type source region) through the via.

[0332] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the silicon substrate can be located within the range of the orthographic projection of the fourth P-type drain region of the fourth P-type transistor P4 (also the fifth P-type drain region of the fifth P-type transistor P5) on the silicon substrate, the first insulating layer and the second insulating layer within the eighth via V8 are etched away to expose the surface of the fourth P-type drain region (also the fifth P-type drain region), and the eighth via V8 is configured to connect the subsequently formed twenty-second connecting electrode to the fourth P-type drain region (also the fifth P-type drain region) through the via.

[0333] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the silicon substrate can be located within the range of the orthographic projection of the fifth P-type source region of the fifth P-type transistor P5 (also the sixth P-type source region of the sixth P-type transistor P6) on the silicon substrate, the first insulating layer and the second insulating layer in the ninth via V9 are etched away to expose the surface of the fifth P-type source region (also the sixth P-type source region), and the ninth via V9 is configured to connect the subsequently formed twenty-third connecting electrode to the fifth P-type source region (also the sixth P-type source region) through the via.

[0334] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the silicon substrate can be located within the range of the orthographic projection of the sixth P-type drain region of the sixth P-type transistor P6 (also the seventh P-type drain region of the seventh P-type transistor P7) on the silicon substrate, the first insulating layer and the second insulating layer within the tenth via V10 are etched away to expose the surface of the sixth P-type drain region (also the seventh P-type drain region), and the tenth via V10 is configured to connect the subsequently formed twenty-fourth connecting electrode to the sixth P-type drain region (also the seventh P-type drain region) through the via.

[0335] In an exemplary embodiment, the orthographic projection of the eleventh via V11 on the silicon substrate can be located within the range of the orthographic projection of the seventh P-type source region of the seventh P-type transistor P7 (also the eighth P-type source region of the eighth P-type transistor P8) on the silicon substrate, the first insulating layer and the second insulating layer within the eleventh via V11 are etched away to expose the surface of the seventh P-type source region (also the eighth P-type source region), and the eleventh via V11 is configured to connect the subsequently formed twenty-fifth connecting electrode to the seventh P-type source region (also the eighth P-type source region) through the via.

[0336] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the silicon substrate can be located within the range of the orthographic projection of the eighth P-type drain region of the eighth P-type transistor P8 (also the ninth P-type drain region of the ninth P-type transistor P9) on the silicon substrate, and the first insulating layer and the second insulating layer in the twelfth via V12 are etched away to expose the surface of the eighth P-type drain region (also the ninth P-type drain region), and the twelfth via V12 is configured to connect the subsequently formed twenty-sixth connecting electrode to the eighth P-type drain region (also the ninth P-type drain region) through the via.

[0337] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 on the silicon substrate can be located within the range of the orthographic projection of the ninth P-type source region of the ninth P-type transistor P9 (also the tenth P-type source region of the tenth P-type transistor P10) on the silicon substrate, the first insulating layer and the second insulating layer in the thirteenth via V13 are etched away to expose the surface of the ninth P-type source region (also the tenth P-type source region), and the thirteenth via V13 is configured to connect the subsequently formed twenty-seventh connecting electrode to the ninth P-type source region (also the tenth P-type source region) through the via.

[0338] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the silicon substrate can be located within the range of the orthographic projection of the tenth P-type drain region of the tenth P-type transistor P10 (also the eleventh P-type drain region of the eleventh P-type transistor P11) on the silicon substrate, the first insulating layer and the second insulating layer in the fourteenth via V14 are etched away to expose the surface of the tenth P-type drain region (also the eleventh P-type drain region), and the fourteenth via V14 is configured to connect the subsequently formed twenty-eighth connecting electrode to the tenth P-type drain region (also the eleventh P-type drain region) through the via.

[0339] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the silicon substrate can be located within the range of the orthographic projection of the eleventh P-type source region of the eleventh P-type transistor P11 (also the twelfth P-type source region of the twelfth P-type transistor P12) on the silicon substrate, the first insulating layer and the second insulating layer in the fifteenth via V15 are etched away to expose the surface of the eleventh P-type source region (also the twelfth P-type source region), and the fifteenth via V15 is configured to connect the subsequently formed twenty-ninth connecting electrode to the eleventh P-type source region (also the twelfth P-type source region) through the via.

[0340] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the silicon substrate can be located within the range of the orthographic projection of the twelfth P-type drain region of the twelfth P-type transistor P12 (also the thirteenth P-type drain region of the thirteenth P-type transistor P13) on the silicon substrate, the first insulating layer and the second insulating layer in the sixteenth via V16 are etched away to expose the surface of the twelfth P-type drain region (also the thirteenth P-type drain region), and the sixteenth via V16 is configured to connect the subsequently formed thirtieth connecting electrode to the twelfth P-type drain region (also the thirteenth P-type drain region) through the via.

[0341] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 on the silicon substrate can be located within the range of the orthographic projection of the thirteenth P-type source region of the thirteenth P-type transistor P13 on the silicon substrate, the first insulating layer and the second insulating layer in the seventeenth via V17 are etched away to expose the surface of the seventeenth P-type source region, and the seventeenth via V17 is configured to connect the subsequently formed thirty-first connecting electrode to the seventeenth P-type source region through the via.

[0342] In an exemplary embodiment, the position of the fifth via V5 and the position of the seventeenth via V17 can be symmetrically arranged with respect to the active center line O, the position of the sixth via V6 and the position of the sixteenth via V16 can be symmetrically arranged with respect to the active center line O, the position of the seventh via V7 and the position of the fifteenth via V15 can be symmetrically arranged with respect to the active center line O, the position of the eighth via V8 and the position of the fourteenth via V14 can be symmetrically arranged with respect to the active center line O, the position of the ninth via V9 and the position of the thirteenth via V13 can be symmetrically arranged with respect to the active center line O, the position of the tenth via V10 and the position of the twelfth via V12 can be symmetrically arranged with respect to the active center line O, and the position of the eleventh via V11 can be symmetrically arranged with respect to the active center line O, which can ensure the symmetry of the P-type transistor unit in the level converter and improve the consistency of the output high and low levels.

[0343] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 on the silicon substrate can be located within the range of the orthographic projection of the second N-type drain region of the second N-type transistor N2 on the silicon substrate, the second insulating layer and the second insulating layer in the eighteenth via V18 are etched away to expose the surface of the second N-type drain region, and the eighteenth via V18 is configured to connect the subsequently formed thirty-second connecting electrode to the second N-type drain region through the via.

[0344] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 on the silicon substrate can be located within the range of the orthographic projection of the second N-type source region of the second N-type transistor N2 (also the third N-type source region of the third N-type transistor N3) on the silicon substrate, the second insulating layer and the second insulating layer within the nineteenth via V19 are etched away to expose the surface of the second N-type source region (also the third N-type source region), and the nineteenth via V19 is configured to connect the subsequently formed thirty-third connecting electrode to the second N-type source region (also the third N-type source region) through the via.

[0345] In an exemplary embodiment, the orthographic projection of the twentieth via V20 on the silicon substrate may be located within the range of the orthographic projection of the third N-type drain region of the third N-type transistor N3 on the silicon substrate, the second insulating layer and the second insulating layer within the twentieth via V20 are etched away to expose the surface of the third N-type drain region, and the twentieth via V20 is configured to connect the subsequently formed thirty-fourth connecting electrode to the third N-type drain region through the via.

[0346] In an exemplary embodiment, the position of the eighteenth via V18 and the position of the twentieth via V20 can be symmetrically arranged relative to the active center line O, and the position of the nineteenth via V19 can be symmetrically arranged relative to the active center line O, which can ensure the symmetry of the N-type transistor unit in the level converter and improve the consistency of the output high and low levels.

[0347] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 on the silicon substrate can be located within the range of the orthographic projection of the twenty-first P-type source region of the twenty-first P-type transistor P21 on the silicon substrate, the first insulating layer and the second insulating layer within the twenty-first via V21 are etched away to expose the surface of the twenty-first P-type source region, and the twenty-first via V21 is configured to connect the subsequently formed forty-fourth connecting electrode to the twenty-first P-type source region through the via.

[0348] In an exemplary embodiment, the orthographic projection of the twenty-second via V22 on the silicon substrate can be located within the range of the orthographic projection of the twenty-first P-type drain region of the twenty-first P-type transistor P21 (also the twenty-second P-type drain region of the twenty-second P-type transistor P22) on the silicon substrate, the first insulating layer and the second insulating layer within the twenty-second via V22 are etched away to expose the surface of the twenty-first P-type drain region (also the twenty-second P-type drain region), and the twenty-second via V22 is configured to connect the subsequently formed forty-fifth connecting electrode to the twenty-first P-type drain region (also the twenty-second P-type drain region) through the via.

[0349] In an exemplary embodiment, the orthographic projection of the twenty-third via V23 on the silicon substrate can be located within the range of the orthographic projection of the twenty-second P-type source region of the twenty-second P-type transistor P22 on the silicon substrate, the first insulating layer and the second insulating layer in the twenty-third via V23 are etched away to expose the surface of the twenty-second P-type source region, and the twenty-third via V23 is configured to connect the subsequently formed forty-sixth connecting electrode to the twenty-second P-type source region through the via.

[0350] In an exemplary embodiment, the orthographic projection of the twenty-fourth via V24 on the silicon substrate can be located within the range of the orthographic projection of the twenty-third P-type source region of the twenty-third P-type transistor P23 on the silicon substrate, the first insulating layer and the second insulating layer within the twenty-fourth via V24 are etched away to expose the surface of the twenty-third P-type source region, and the twenty-fourth via V24 is configured to connect the subsequently formed forty-seventh connecting electrode to the twenty-third P-type source region through the via.

[0351] In an exemplary embodiment, the orthographic projection of the twenty-fifth via V25 on the silicon substrate can be located within the range of the orthographic projection of the twenty-third P-type drain region of the twenty-third P-type transistor P23 on the silicon substrate, the first insulating layer and the second insulating layer within the twenty-fifth via V25 are etched away to expose the surface of the twenty-third P-type drain region, and the twenty-fifth via V25 is configured to connect the subsequently formed forty-eighth connecting electrode to the twenty-third P-type drain region through the via.

[0352] In an exemplary embodiment, the orthographic projection of the twenty-sixth via V26 on the silicon substrate can be located within the range of the orthographic projection of the twenty-fourth P-type source region of the twenty-fourth P-type transistor P24 on the silicon substrate, the first insulating layer and the second insulating layer within the twenty-sixth via V26 are etched away to expose the surface of the twenty-fourth P-type source region, and the twenty-sixth via V26 is configured to connect the subsequently formed forty-ninth connecting electrode to the twenty-fourth P-type source region through the via.

[0353] In an exemplary embodiment, the orthographic projection of the twenty-seventh via V27 on the silicon substrate can be located within the range of the orthographic projection of the twenty-fourth P-type drain region of the twenty-fourth P-type transistor P24 (also the twenty-fifth P-type drain region of the twenty-fifth P-type transistor P22) on the silicon substrate, the first insulating layer and the second insulating layer within the twenty-seventh via V27 are etched away to expose the surface of the twenty-fourth P-type drain region (also the twenty-fifth P-type drain region), and the twenty-seventh via V27 is configured to connect the subsequently formed fiftieth connecting electrode to the twenty-fourth P-type drain region (also the twenty-fifth P-type drain region) through the via.

[0354] In an exemplary embodiment, the orthographic projection of the twenty-eighth via V28 on the silicon substrate can be located within the range of the orthographic projection of the twenty-fifth P-type source region of the twenty-fifth P-type transistor P25 on the silicon substrate, the first insulating layer and the second insulating layer within the twenty-eighth via V28 are etched away to expose the surface of the twenty-fifth P-type source region, and the twenty-eighth via V28 is configured to connect the subsequently formed fifty-first connecting electrode to the twenty-fifth P-type source region through the via.

[0355] In an exemplary embodiment, the orthographic projection of the twenty-ninth via V29 on the silicon substrate can be located within the range of the orthographic projection of the twenty-sixth P-type source region of the twenty-sixth P-type transistor P26 on the silicon substrate, the first insulating layer and the second insulating layer within the twenty-ninth via V29 are etched away to expose the surface of the twenty-sixth P-type source region, and the twenty-ninth via V29 is configured to connect the subsequently formed fifty-second connecting electrode to the twenty-sixth P-type source region through the via.

[0356] In an exemplary embodiment, the orthographic projection of the 30th via V30 on the silicon substrate can be located within the range of the orthographic projection of the 26th P-type drain region of the 26th P-type transistor P26 on the silicon substrate, the first insulating layer and the second insulating layer within the 30th via V30 are etched away to expose the surface of the 26th P-type drain region, and the 30th via V30 is configured to connect the subsequently formed 53rd connecting electrode to the 26th P-type drain region through the via.

[0357] In an exemplary embodiment, the orthographic projection of the thirty-first via V31 on the silicon substrate can be located within the range of the orthographic projection of the twenty-seventh P-type drain region of the twenty-seventh P-type transistor P27 on the silicon substrate, the first insulating layer and the second insulating layer within the thirty-first via V31 are etched away to expose the surface of the twenty-seventh P-type drain region, and the thirty-first via V31 is configured to connect the subsequently formed fifty-fourth connecting electrode to the twenty-seventh P-type drain region through the via.

[0358] In an exemplary embodiment, the orthographic projection of the thirty-second via V32 on the silicon substrate can be located within the range of the orthographic projection of the twenty-seventh P-type source region of the twenty-seventh P-type transistor P27 (also the twenty-eighth P-type source region of the twenty-eighth P-type transistor P8) on the silicon substrate, and the first insulating layer and the second insulating layer within the thirty-second via V32 are etched away to expose the surface of the twenty-seventh P-type source region (also the twenty-eighth P-type source region), and the thirty-second via V32 is configured to connect the subsequently formed fifty-fifth connecting electrode to the twenty-seventh P-type source region (also the twenty-eighth P-type source region) through the via.

[0359] In an exemplary embodiment, the orthographic projection of the thirty-third via V33 on the silicon substrate can be located within the range of the orthographic projection of the twenty-eighth P-type drain region of the twenty-eighth P-type transistor P28 (also the twenty-ninth P-type drain region of the twenty-ninth P-type transistor P29) on the silicon substrate, the first insulating layer and the second insulating layer within the thirty-third via V33 are etched away to expose the surface of the twenty-eighth P-type drain region (also the twenty-ninth P-type drain region), and the thirty-third via V33 is configured to connect the subsequently formed fifty-sixth connecting electrode to the twenty-eighth P-type drain region (also the twenty-ninth P-type drain region) through the via.

[0360] In an exemplary embodiment, the orthographic projection of the thirty-fourth via V34 on the silicon substrate can be located within the range of the orthographic projection of the twenty-ninth P-type source region of the twenty-ninth P-type transistor P29 (also the thirtieth P-type source region of the thirtieth P-type transistor P30) on the silicon substrate, the first insulating layer and the second insulating layer within the thirty-fourth via V34 are etched away to expose the surface of the twenty-ninth P-type source region (also the thirtieth P-type source region), and the thirty-fourth via V34 is configured to connect the subsequently formed fifty-seventh connecting electrode to the twenty-ninth P-type source region (also the thirtieth P-type source region) through the via.

[0361] In an exemplary embodiment, the orthographic projection of the thirty-fifth via V35 on the silicon substrate can be located within the range of the orthographic projection of the 30th P-type drain region of the 30th P-type transistor P30 on the silicon substrate, the first insulating layer and the second insulating layer within the thirty-fifth via V35 are etched away to expose the surface of the 30th P-type drain region, and the thirty-fifth via V35 is configured to connect the subsequently formed fifty-eighth connecting electrode to the 30th P-type drain region through the via.

[0362] In an exemplary embodiment, the orthographic projection of the thirty-sixth via V36 on the silicon substrate can be located within the range of the orthographic projection of the twenty-first N-type drain region of the twenty-first N-type transistor N21 on the silicon substrate, the first insulating layer and the second insulating layer within the thirty-sixth via V36 are etched away to expose the surface of the twenty-first N-type drain region, and the thirty-sixth via V36 is configured to connect the subsequently formed fifty-ninth connecting electrode to the twenty-first N-type drain region through the via.

[0363] In an exemplary embodiment, the orthographic projection of the thirty-seventh via V37 on the silicon substrate can be located within the range of the orthographic projection of the twenty-first N-type source region of the twenty-first N-type transistor N21 (also the twenty-second N-type drain region of the twenty-second N-type transistor N22) on the silicon substrate, and the first insulating layer and the second insulating layer within the thirty-seventh via V37 are etched away to expose the surface of the twenty-first N-type source region (also the twenty-second N-type drain region), and the thirty-seventh via V37 is configured to connect the subsequently formed sixtieth connecting electrode to the twenty-first N-type source region (also the twenty-second N-type drain region) through the via.

[0364] In an exemplary embodiment, the orthographic projection of the thirty-eighth via V38 on the silicon substrate can be located within the range of the orthographic projection of the twenty-second N-type source region of the twenty-second N-type transistor N22 on the silicon substrate, the first insulating layer and the second insulating layer within the thirty-eighth via V38 are etched away to expose the surface of the twenty-second N-type source region, and the thirty-eighth via V38 is configured to connect the subsequently formed sixty-first connecting electrode to the twenty-second N-type source region through the via.

[0365] In an exemplary embodiment, the orthographic projection of the thirty-ninth via V39 on the silicon substrate can be located within the range of the orthographic projection of the twenty-third N-type source region of the twenty-third N-type transistor N23 on the silicon substrate, the first insulating layer and the second insulating layer in the thirty-ninth via V39 are etched away to expose the surface of the twenty-third N-type source region, and the thirty-ninth via V39 is configured to connect the subsequently formed sixty-second connecting electrode to the twenty-third N-type source region through the via.

[0366] In an exemplary embodiment, the orthographic projection of the 40th via V40 on the silicon substrate can be located within the range of the orthographic projection of the 23rd N-type drain region of the 23rd N-type transistor N23 on the silicon substrate, the first insulating layer and the second insulating layer in the 40th via V40 are etched away to expose the surface of the 23rd N-type drain region, and the 40th via V40 is configured to connect the subsequently formed 63rd connecting electrode to the 23rd N-type drain region through the via.

[0367] In an exemplary embodiment, the orthographic projection of the forty-first via V41 on the silicon substrate can be located within the range of the orthographic projection of the twenty-fourth N-type drain region of the twenty-fourth N-type transistor N24 on the silicon substrate, the first insulating layer and the second insulating layer within the forty-first via V41 are etched away to expose the surface of the twenty-fourth N-type drain region, and the forty-first via V41 is configured to connect the subsequently formed sixty-fourth connecting electrode to the twenty-fourth N-type drain region through the via.

[0368] In an exemplary embodiment, the orthographic projection of the forty-second via V42 on the silicon substrate can be located within the range of the orthographic projection of the twenty-fourth N-type source region of the twenty-fourth N-type transistor N24 (also the twenty-fifth N-type drain region of the twenty-fifth N-type transistor N22) on the silicon substrate, the first insulating layer and the second insulating layer within the forty-second via V42 are etched away to expose the surface of the twenty-fourth N-type source region (also the twenty-fifth N-type drain region), and the forty-second via V42 is configured to connect the subsequently formed sixty-fifth connecting electrode to the twenty-fourth N-type source region (also the twenty-fifth N-type drain region) through the via.

[0369] In an exemplary embodiment, the orthographic projection of the forty-third via V43 on the silicon substrate can be located within the range of the orthographic projection of the twenty-fifth N-type source region of the twenty-fifth N-type transistor N25 on the silicon substrate, the first insulating layer and the second insulating layer within the forty-third via V43 are etched away to expose the surface of the twenty-fifth N-type source region, and the forty-third via V43 is configured to connect the subsequently formed sixty-sixth connecting electrode to the twenty-fifth N-type source region through the via.

[0370] In an exemplary embodiment, the orthographic projection of the forty-fourth via V44 on the silicon substrate can be located within the range of the orthographic projection of the twenty-sixth N-type source region of the twenty-sixth N-type transistor N23 on the silicon substrate, the first insulating layer and the second insulating layer within the forty-fourth via V44 are etched away to expose the surface of the twenty-sixth N-type source region, and the forty-fourth via V44 is configured to connect the subsequently formed sixty-seventh connecting electrode to the twenty-sixth N-type source region through the via.

[0371] In an exemplary embodiment, the orthographic projection of the forty-fifth via V45 on the silicon substrate can be located within the range of the orthographic projection of the twenty-sixth N-type drain region of the twenty-sixth N-type transistor N23 on the silicon substrate, the first insulating layer and the second insulating layer within the forty-fifth via V45 are etched away to expose the surface of the twenty-sixth N-type drain region, and the forty-fifth via V45 is configured to connect the subsequently formed sixty-eighth connecting electrode to the twenty-sixth N-type drain region through the via.

[0372] In an exemplary embodiment, the orthographic projection of the forty-sixth via V46 on the silicon substrate can be located within the range of the orthographic projection of the twenty-seventh N-type drain region of the twenty-seventh N-type transistor N27 on the silicon substrate, the first insulating layer and the second insulating layer within the forty-sixth via V46 are etched away to expose the surface of the twenty-seventh N-type drain region, and the forty-sixth via V46 is configured to connect the subsequently formed sixty-ninth connecting electrode to the twenty-seventh N-type drain region through the via.

[0373] In an exemplary embodiment, the orthographic projection of the forty-seventh via V47 on the silicon substrate can be located within the range of the orthographic projection of the twenty-seventh N-type source region of the twenty-seventh N-type transistor N27 (also the twenty-eighth N-type source region of the twenty-eighth N-type transistor N8) on the silicon substrate, the first insulating layer and the second insulating layer within the forty-seventh via V47 are etched away to expose the surface of the twenty-seventh N-type source region (also the twenty-eighth N-type source region), and the forty-seventh via V47 is configured to connect the subsequently formed seventieth connecting electrode to the twenty-seventh N-type source region (also the twenty-eighth N-type source region) through the via.

[0374] In an exemplary embodiment, the orthographic projection of the forty-eighth via V48 on the silicon substrate can be located within the range of the orthographic projection of the twenty-eighth N-type drain region of the twenty-eighth N-type transistor N28 (also the twenty-ninth N-type drain region of the twenty-ninth N-type transistor N29) on the silicon substrate, the first insulating layer and the second insulating layer within the forty-eighth via V48 are etched away to expose the surface of the twenty-eighth N-type drain region (also the twenty-ninth N-type drain region), and the forty-eighth via V48 is configured to connect the subsequently formed seventy-first connecting electrode to the twenty-eighth N-type drain region (also the twenty-ninth N-type drain region) through the via.

[0375] In an exemplary embodiment, the orthographic projection of the forty-ninth via V49 on the silicon substrate can be located within the range of the orthographic projection of the twenty-ninth N-type source region of the twenty-ninth N-type transistor N29 (also the thirtieth N-type source region of the thirtieth N-type transistor N30) on the silicon substrate, the first insulating layer and the second insulating layer within the forty-ninth via V49 are etched away to expose the surface of the twenty-ninth N-type source region (also the thirtieth N-type source region), and the forty-ninth via V49 is configured to connect the subsequently formed seventy-second connecting electrode to the twenty-ninth N-type source region (also the thirtieth N-type source region) through the via.

[0376] In an exemplary embodiment, the orthographic projection of the fiftieth via V50 on the silicon substrate can be located within the range of the orthographic projection of the 30th N-type drain region of the 30th N-type transistor N30 on the silicon substrate, the first insulating layer and the second insulating layer within the fiftieth via V50 are etched away to expose the surface of the 30th N-type drain region, and the fiftieth via V50 is configured to connect the subsequently formed seventy-third connecting electrode to the 30th N-type drain region through the via.

[0377] In an exemplary embodiment, the orthographic projection of the fifty-first via V51 on the silicon substrate can be located within the range of the orthographic projection of the first P-type gate electrode 201P (also the first N-type gate electrode 201N) on the silicon substrate, and the second insulating layer in the fifty-first via V51 is etched away to expose the surface of the first P-type gate electrode 201P (also the first N-type gate electrode 201N), and the fifty-first via V51 is configured to connect the subsequently formed first connecting electrode to the first P-type gate electrode 201P (also the first N-type gate electrode 201N) through the via.

[0378] In an exemplary embodiment, the orthographic projection of the fifty-second via V52 on the silicon substrate can be located within the range of the orthographic projection of the second P-type gate electrode 202P on the silicon substrate, the second insulating layer in the fifty-second via V52 is etched away to expose the surface of the second P-type gate electrode 202P, and the fifty-second via V52 is configured to connect a subsequently formed second connecting electrode to the second P-type gate electrode 202P through the via.

[0379] In an exemplary embodiment, the orthographic projection of the fifty-third via V53 on the silicon substrate can be located within the range of the orthographic projection of the third P-type gate electrode 203P on the silicon substrate, the second insulating layer in the fifty-third via V53 is etched away to expose the surface of the third P-type gate electrode 203P, and the fifty-third via V53 is configured to connect the subsequently formed third connecting electrode to the third P-type gate electrode 203P through the via.

[0380] In an exemplary embodiment, the orthographic projection of the fifty-fourth via V54 on the silicon substrate can be located within the range of the orthographic projection of the fourth P-type gate electrode 204P on the silicon substrate, the second insulating layer in the fifty-fourth via V54 is etched away to expose the surface of the fourth P-type gate electrode 204P, and the fifty-fourth via V54 is configured to connect the subsequently formed fourth connecting electrode to the fourth P-type gate electrode 204P through the via.

[0381] In an exemplary embodiment, the orthographic projection of the fifty-fifth via V55 on the silicon substrate can be located within the range of the orthographic projection of the fifth P-type gate electrode 205P on the silicon substrate, the second insulating layer in the fifty-fifth via V55 is etched away, exposing the surface of the fifth P-type gate electrode 205P, and the fifty-fifth via V55 is configured to connect the subsequently formed fifth connecting electrode to the fifth P-type gate electrode 205P through the via.

[0382] In an exemplary embodiment, the orthographic projection of the fifty-sixth via V56 on the silicon substrate can be located within the range of the orthographic projection of the sixth P-type gate electrode 206P on the silicon substrate, the second insulating layer in the fifty-sixth via V56 is etched away to expose the surface of the sixth P-type gate electrode 206P, and the fifty-sixth via V56 is configured to connect the subsequently formed sixth connecting electrode to the sixth P-type gate electrode 206P through the via.

[0383] In an exemplary embodiment, the orthographic projection of the fifty-seventh via V57 on the silicon substrate can be located within the range of the orthographic projection of the seventh P-type gate electrode 207P on the silicon substrate, the second insulating layer in the fifty-seventh via V57 is etched away to expose the surface of the seventh P-type gate electrode 207P, and the fifty-seventh via V57 is configured to connect the subsequently formed seventh connecting electrode to the seventh P-type gate electrode 207P through the via.

[0384] In an exemplary embodiment, the orthographic projection of the fifty-eighth via V58 on the silicon substrate can be located within the range of the orthographic projection of the eighth P-type gate electrode 208P on the silicon substrate, the second insulating layer in the fifty-eighth via V58 is etched away to expose the surface of the eighth P-type gate electrode 208P, and the fifty-eighth via V58 is configured to connect the subsequently formed eighth connecting electrode to the eighth P-type gate electrode 208P through the via.

[0385] In an exemplary embodiment, the orthographic projection of the fifty-ninth via V59 on the silicon substrate can be located within the range of the orthographic projection of the ninth P-type gate electrode 209P on the silicon substrate, the second insulating layer in the fifty-ninth via V59 is etched away to expose the surface of the ninth P-type gate electrode 209P, and the fifty-ninth via V59 is configured to connect the subsequently formed ninth connecting electrode to the ninth P-type gate electrode 209P through the via.

[0386] In an exemplary embodiment, the orthographic projection of the sixtieth via V60 on the silicon substrate can be located within the range of the orthographic projection of the tenth P-type gate electrode 210P on the silicon substrate, the second insulating layer in the sixtieth via V60 is etched away to expose the surface of the tenth P-type gate electrode 210P, and the sixtieth via V60 is configured to connect the subsequently formed tenth connecting electrode to the tenth P-type gate electrode 210P through the via.

[0387] In an exemplary embodiment, the orthographic projection of the sixty-first via V61 on the silicon substrate can be located within the range of the orthographic projection of the eleventh P-type gate electrode 211P on the silicon substrate, the second insulating layer in the sixty-first via V61 is etched away to expose the surface of the eleventh P-type gate electrode 211P, and the sixty-first via V61 is configured to connect the subsequently formed eleventh connecting electrode to the eleventh P-type gate electrode 211P through the via.

[0388] In an exemplary embodiment, the orthographic projection of the sixty-second via V62 on the silicon substrate can be located within the range of the orthographic projection of the twelfth P-type gate electrode 212P on the silicon substrate, the second insulating layer in the sixty-second via V62 is etched away to expose the surface of the twelfth P-type gate electrode 212P, and the sixty-second via V62 is configured to connect the subsequently formed twelfth connecting electrode to the twelfth P-type gate electrode 212P through the via.

[0389] In an exemplary embodiment, the orthographic projection of the sixty-third via V63 on the silicon substrate can be located within the range of the orthographic projection of the thirteenth P-type gate electrode 213P on the silicon substrate, the second insulating layer in the sixty-third via V63 is etched away to expose the surface of the thirteenth P-type gate electrode 213P, and the sixty-third via V63 is configured to connect the subsequently formed thirteenth connecting electrode to the thirteenth P-type gate electrode 213P through the via.

[0390] In an exemplary embodiment, the orthographic projection of the sixty-fourth via V64 on the silicon substrate can be located within the range of the orthographic projection of the second N-type gate electrode 202N on the silicon substrate, the second insulating layer in the sixty-fourth via V64 is etched away to expose the surface of the second N-type gate electrode 202N, and the sixty-fourth via V64 is configured to connect the subsequently formed fourteenth connecting electrode to the second N-type gate electrode 202N through the via.

[0391] In an exemplary embodiment, the orthographic projection of the sixty-fifth via V65 on the silicon substrate can be located within the range of the orthographic projection of the third N-type gate electrode 203N on the silicon substrate, the second insulating layer in the sixty-fifth via V65 is etched away to expose the surface of the third N-type gate electrode 203N, and the sixty-fifth via V65 is configured to connect the subsequently formed fifteenth connecting electrode to the third N-type gate electrode 203N through the via.

[0392] In an exemplary embodiment, the orthographic projection of the sixty-sixth via V66 on the silicon substrate can be located within the range of the orthographic projection of the twenty-first P-type gate electrode 221P (also the twenty-first N-type gate electrode 221N) on the silicon substrate, and the second insulating layer within the sixty-sixth via V66 is etched away to expose the surface of the twenty-first P-type gate electrode 221P (also the twenty-first N-type gate electrode 221N), and the sixty-sixth via V66 is configured to connect the subsequently formed thirty-fifth connecting electrode to the twenty-first P-type gate electrode 221P (also the twenty-first N-type gate electrode 221N) through the via.

[0393] In an exemplary embodiment, the orthographic projection of the sixty-seventh via V67 on the silicon substrate can be located within the range of the orthographic projection of the twenty-second P-type gate electrode 222P (also the twenty-second N-type gate electrode 222N) on the silicon substrate, and the second insulating layer within the sixty-seventh via V67 is etched away to expose the surface of the twenty-second P-type gate electrode 222P (also the twenty-second N-type gate electrode 222N). The sixty-seventh via V67 is configured to connect the subsequently formed thirty-sixth connecting electrode to the twenty-second P-type gate electrode 222P (also the twenty-second N-type gate electrode 222N) through the via.

[0394] In an exemplary embodiment, the orthographic projection of the sixty-eighth via V68 on the silicon substrate can be located within the range of the orthographic projection of the twenty-third P-type gate electrode 223P on the silicon substrate, the second insulating layer in the sixty-eighth via V68 is etched away to expose the surface of the twenty-third P-type gate electrode 223P, and the sixty-eighth via V68 is configured to connect the subsequently formed thirty-seventh connecting electrode to the twenty-third P-type gate electrode 223P through the via.

[0395] In an exemplary embodiment, the orthographic projection of the sixty-ninth via V69 on the silicon substrate can be located within the range of the orthographic projection of the twenty-third N-type gate electrode 223N on the silicon substrate, the second insulating layer in the sixty-ninth via V69 is etched away to expose the surface of the twenty-third N-type gate electrode 223N, and the sixty-ninth via V69 is configured to connect the subsequently formed thirty-eighth connecting electrode to the twenty-third N-type gate electrode 223N through the via.

[0396] In an exemplary embodiment, the orthographic projection of the seventieth via V70 on the silicon substrate can be located within the range of the orthographic projection of the twenty-fourth P-type gate electrode 224P (also the twenty-fourth N-type gate electrode 224N) on the silicon substrate, the second insulating layer in the seventieth via V70 is etched away to expose the surface of the twenty-fourth P-type gate electrode 224P (also the twenty-fourth N-type gate electrode 224N), and the seventieth via V70 is configured to connect the subsequently formed thirty-ninth connecting electrode to the twenty-fourth P-type gate electrode 224P (also the twenty-fourth N-type gate electrode 224N) through the via.

[0397] In an exemplary embodiment, the orthographic projection of the seventy-first via V71 on the silicon substrate can be located within the range of the orthographic projection of the twenty-fifth P-type gate electrode 225P (also the twenty-fifth N-type gate electrode 225N) on the silicon substrate, and the second insulating layer within the seventy-first via V71 is etched away to expose the surface of the twenty-fifth P-type gate electrode 225P (also the twenty-fifth N-type gate electrode 225N). The seventy-first via V71 is configured to connect the subsequently formed fortieth connecting electrode to the twenty-fifth P-type gate electrode 225P (also the twenty-fifth N-type gate electrode 225N) through the via.

[0398] In an exemplary embodiment, the orthographic projection of the seventy-second via V72 on the silicon substrate can be located within the range of the orthographic projection of the twenty-sixth P-type gate electrode 226P (also the twenty-sixth N-type gate electrode 226N) on the silicon substrate, and the second insulating layer within the seventy-second via V72 is etched away to expose the surface of the twenty-sixth P-type gate electrode 226P (also the twenty-sixth N-type gate electrode 226N), and the seventy-second via V72 is configured to connect the subsequently formed forty-first connecting electrode to the twenty-sixth P-type gate electrode 226P (also the twenty-sixth N-type gate electrode 226N) through the via.

[0399] In an exemplary embodiment, the orthographic projection of the seventy-third via V73 on the silicon substrate can be located within the range of the orthographic projection of the twenty-seventh P-type gate electrode 227P on the silicon substrate, the second insulating layer in the seventy-third via V73 is etched away to expose the surface of the twenty-seventh P-type gate electrode 227P, and the seventy-third via V73 is configured to connect the subsequently formed forty-second connecting electrode to the twenty-seventh P-type gate electrode 227P through the via.

[0400] In an exemplary embodiment, the orthographic projection of the seventy-fourth via V74 on the silicon substrate can be located within the range of the orthographic projection of the twenty-eighth P-type gate electrode 228P on the silicon substrate, the second insulating layer in the seventy-fourth via V74 is etched away to expose the surface of the twenty-eighth P-type gate electrode 228P, and the seventy-fourth via V74 is configured to connect the subsequently formed forty-second connecting electrode to the twenty-eighth P-type gate electrode 228P through the via.

[0401] In an exemplary embodiment, the orthographic projection of the seventy-fifth via V75 on the silicon substrate can be located within the range of the orthographic projection of the twenty-ninth P-type gate electrode 229P on the silicon substrate, the second insulating layer within the seventy-fifth via V75 is etched away to expose the surface of the twenty-ninth P-type gate electrode 229P, and the seventy-fifth via V75 is configured to connect the subsequently formed forty-second connecting electrode to the twenty-ninth P-type gate electrode 229P through the via.

[0402] In an exemplary embodiment, the orthographic projection of the seventy-sixth via V76 on the silicon substrate can be located within the range of the orthographic projection of the thirtieth P-type gate electrode 230P on the silicon substrate, the second insulating layer in the seventy-sixth via V76 is etched away to expose the surface of the thirtieth P-type gate electrode 230P, and the seventy-sixth via V76 is configured to connect the subsequently formed forty-second connecting electrode to the thirtieth P-type gate electrode 230P through the via.

[0403] In an exemplary embodiment, the orthographic projection of the seventy-seventh via V77 on the silicon substrate can be located within the range of the orthographic projection of the twenty-seventh N-type gate electrode 227N on the silicon substrate, the second insulating layer in the seventy-seventh via V77 is etched away to expose the surface of the twenty-seventh N-type gate electrode 227N, and the seventy-seventh via V77 is configured to connect the subsequently formed forty-third connecting electrode to the twenty-seventh N-type gate electrode 227N through the via.

[0404] In an exemplary embodiment, the orthographic projection of the seventy-eighth via V78 on the silicon substrate can be located within the range of the orthographic projection of the twenty-eighth N-type gate electrode 228N on the silicon substrate, the second insulating layer in the seventy-eighth via V78 is etched away to expose the surface of the twenty-eighth N-type gate electrode 228N, and the seventy-eighth via V78 is configured to connect the subsequently formed forty-third connecting electrode to the twenty-eighth N-type gate electrode 228N through the via.

[0405] In an exemplary embodiment, the orthographic projection of the seventy-ninth via V79 on the silicon substrate can be located within the range of the orthographic projection of the twenty-ninth N-type gate electrode 229N on the silicon substrate, the second insulating layer in the seventy-ninth via V79 is etched away to expose the surface of the twenty-ninth N-type gate electrode 229N, and the seventy-ninth via V79 is configured to connect the subsequently formed forty-third connecting electrode to the twenty-ninth N-type gate electrode 229N through the via.

[0406] In an exemplary embodiment, the orthographic projection of the 80th via V80 on the silicon substrate can be located within the range of the orthographic projection of the 30th N-type gate electrode 230N on the silicon substrate, the second insulating layer in the 80th via V80 is etched away to expose the surface of the 30th N-type gate electrode 230N, and the 80th via V80 is configured to connect the subsequently formed 43rd connecting electrode to the 30th N-type gate electrode 230N through the via.

[0407] In an exemplary embodiment, each of the first through eightieth via holes V1 through V80 may be plural in order to reduce contact resistance and increase connection reliability.

[0408] In an exemplary embodiment, the fifty-first via V51 to the eightieth via V80 can be referred to as gate vias, and one or more of the above-mentioned gate vias can be located in the gap region 50 between the P-type active region and the N-type active region, so as to facilitate the arrangement of multiple connecting electrodes formed subsequently, optimize the connection structure between the first conductive layer and the gate conductive layer, and reduce the occupied area of ​​the gate drive circuit.

[0409] In an exemplary embodiment, the gate vias in the first NAND gate and the second NAND gate may be referred to as first gate vias. The first gate vias are configured to connect a subsequently formed first gate connection electrode to the P-type gate electrode of the P-type transistor and the N-type gate electrode of the N-type transistor through the first gate vias. The first gate vias may be disposed in the gap region 50. The first gate vias may include a sixty-sixth via V66, a sixty-seventh via V67, a seventieth via V70, and a seventy-first via V71.

[0410] In an exemplary embodiment, the plurality of first gate vias in the first NAND gate and the second NAND gate may be located on the same straight line extending along the first direction X.

[0411] In an exemplary embodiment, the gate vias in the first inverter and the second inverter may be referred to as second gate vias. The second gate vias are configured to connect a subsequently formed second gate connection electrode to the P-type gate electrode of the P-type transistor and the N-type gate electrode of the N-type transistor through the second gate vias. The second gate vias may be disposed in the gap region 50. The second gate vias may include a fifty-first via V51 and a seventy-second via V72.

[0412] In an exemplary embodiment, the plurality of second gate vias in the first inverter and the second inverter may be located on the same straight line extending along the first direction X.

[0413] In an exemplary embodiment, the first gate via may be located substantially in the middle of the gap region 50 in the second direction Y, and at least one second gate via may be closer to the N-type active region of the N-type transistor than the first gate via. For example, the fifty-first via V51 (the second gate via in the first inverter) is closer to the N-type active region of the N-type transistor than the sixty-sixth via V66 (the first gate via in the first NAND gate).

[0414] In an exemplary embodiment, the gate via in the first transmission gate may be referred to as a third gate via. The third gate via may include a third P-type gate via and a third N-type gate via. The third P-type gate via is configured to connect a subsequently formed third P-type gate connection electrode to the P-type gate electrode of the P-type transistor through the third P-type gate via. The third N-type gate via is configured to connect a subsequently formed third N-type gate connection electrode to the N-type gate electrode of the N-type transistor through the third N-type gate via. The third P-type gate via and the third N-type gate via may be disposed in the gap region 50. The third P-type gate via may include a sixty-eighth via V68, and the third N-type gate via may include a sixty-ninth via V69.

[0415] In an exemplary embodiment, in the second direction Y, relative to the first gate via, the third P-type gate via is closer to the P-type active region of the P-type transistor, and the third N-type gate via is closer to the N-type active region of the N-type transistor.

[0416] In an exemplary embodiment, the gate vias in the first P-type transistor unit, the second P-type transistor unit, and the third P-type transistor unit may be referred to as fourth gate vias. The fourth gate vias are configured to connect a subsequently formed fourth gate connection electrode to the P-type gate electrode of the P-type transistor through the fourth gate vias. The fourth gate vias may be disposed in the gap region 50 , and a plurality of fourth gate vias may be located on the same straight line extending along the first direction X. The fourth gate vias may include a fifty-second via V52 to a fifty-seventh via V57 , a fifty-eighth via V58 to a sixty-third via V63 , and a seventy-third via V73 to a seventy-sixth via V76 .

[0417] In an exemplary embodiment, in the second direction Y, the fourth gate via is closer to the P-type active region of the P-type transistor than the first gate via.

[0418] In an exemplary embodiment, the gate vias in the first N-type transistor unit, the second N-type transistor unit, and the third N-type transistor unit may be referred to as fifth gate vias. The fifth gate vias are configured to connect a subsequently formed fifth gate connection electrode to the N-type gate electrode of the N-type transistor through the fifth gate vias. The fifth gate vias may be disposed in the gap region 50 , and the plurality of fifth gate vias may be located on the same straight line extending along the first direction X. The fifth gate vias may include a sixty-fourth via V64 , a sixty-fifth via V65 , and seventy-seventh vias V77 through eightieth vias V80 .

[0419] In an exemplary embodiment, in the second direction Y, the fifth gate via is closer to the N-type active region of the N-type transistor than the first gate via.

[0420] The present disclosure not only facilitates process uniformity and signal transmission uniformity by setting the position of the gate via, but also facilitates the arrangement of multiple connection electrodes formed subsequently, and optimizes the connection structure between the first conductive layer and the gate conductive layer.

[0421] In an exemplary embodiment, the orthographic projection of the eighty-first via V81 on the silicon substrate can be located within the range of the orthographic projection of the first power active area 100P on the silicon substrate, the first insulating layer and the second insulating layer in the eighty-first via V81 are etched away to expose the surface of the first power active area 100P, and the eighty-first via V81 is configured to connect a subsequently formed first power line to the first power active area 100P through the via.

[0422] In an exemplary embodiment, there are a plurality of the eighty-first via holes V81 , and the plurality of eighty-first via holes V81 are sequentially disposed along the first direction X to reduce contact resistance and increase connection reliability.

[0423] In an exemplary embodiment, the orthographic projection of the eighty-second via V82 on the silicon substrate can be located within the range of the orthographic projection of the second power active area 100N1 on the silicon substrate, the first insulating layer and the second insulating layer in the eighty-second via V82 are etched away to expose the surface of the second power active area 100N1, and the eighty-second via V82 is configured to connect a subsequently formed second power line to the second power active area 100N1 through the via.

[0424] In an exemplary embodiment, there are a plurality of the eighty-second via holes V82 , and the plurality of eighty-second via holes V82 are sequentially arranged along the first direction X to reduce contact resistance and increase connection reliability.

[0425] In an exemplary embodiment, the orthographic projection of the eighty-third via V83 on the silicon substrate may be located within the range of the orthographic projection of the ground active area 100N2 on the silicon substrate, the first insulating layer and the second insulating layer within the eighty-third via V83 are etched away to expose the surface of the ground active area 100N2, and the eighty-third via V83 is configured to connect a subsequently formed ground line to the ground active area 100N2 through the via.

[0426] In an exemplary embodiment, there are a plurality of eighty-third via holes V83 , and the plurality of eighty-third via holes V83 are sequentially arranged along the first direction X to reduce contact resistance and increase connection reliability.

[0427] In an exemplary embodiment, a plurality of eighty-first vias V81 arranged sequentially along the first direction X form a first via row, and a plurality of eighty-second vias V82 arranged sequentially along the first direction X form a second via row, and the first via row and the second via row are respectively located on both sides of the second direction of the plurality of transistors, so that the plurality of transistors are located between the first via row and the second via row, which can effectively avoid mutual interference between different gate drive circuits.

[0428] (7) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first conductive film on the silicon substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process, and forming the first conductive layer pattern on the second insulating layer, as shown in FIG. 18A and FIG. 18B , where FIG. 18B is a schematic diagram of the first conductive layer in FIG. 18A . In an exemplary embodiment, the first conductive layer may be referred to as a first metal (Metal 1) layer.

[0429] In an exemplary embodiment, the first conductive layer pattern may include at least a first power line 51 , a second power line 52 , a ground line 53 , first to seventy-fifth connection electrodes 601 to 675 , and first to fourth connection lines 701 to 704 .

[0430] In an exemplary embodiment, the shape of the first power line 51 can be a straight line or a broken line extending along the first direction X, and can be arranged on the side opposite to the second direction Y of the multiple transistors. The first power line 51 is connected to the first power active area 100P through multiple eighty-first vias V81.

[0431] In an exemplary embodiment, the first power line 51 can be disposed in the first region LS and the second region LD, that is, the first power active region 100P extends from the first region LS to the second region LD. Since the first power active region 100P is located within the region where the N-well region 20 is located, the first power line 51 can write the first power signal into the N-well region 20. This not only provides better current driving capability and response speed to meet the operating requirements of the output circuit, but also reduces voltage drop and power loss in the output circuit, thereby improving the overall efficiency of the output circuit.

[0432] In an exemplary embodiment, the second power line 52 may be in the shape of a straight line or a broken line extending along the first direction X, and may be disposed on one side of the plurality of transistors in the second direction Y. The second power line 52 is connected to the second power active area 100N1 through a plurality of eighty-second vias V82.

[0433] In an exemplary embodiment, the second power line 52 may be disposed in both the first region LS and the second region LD, i.e., the second power active region 100N1 extends from the first region LS to the second region LD. Since the second power active region 100N1 is located within the region where the deep N-well region 10 is located, the second power line 52 can write the second power signal into the deep N-well region 10, thereby ensuring a good ground connection to eliminate noise, stabilize the potential, and provide a reliable reference level. The second power line 52 also provides a low-impedance path for current to effectively return to the ground.

[0434] In an exemplary embodiment, the ground line 53 may be in the shape of a straight line or a broken line extending along the first direction X, and may be disposed on one side of the first N-type transistor N1 in the second direction Y. The ground line 53 is connected to the ground active area 100N2 through a plurality of eighty-third vias V83.

[0435] In an exemplary embodiment, the ground line 53 may be disposed in the first region LS. Since the ground active region 100N2 is located outside the deep N-well region 10 and the N-well region 20, the ground line 53 not only provides a relatively stable potential reference, ensuring consistent and reliable performance of the output circuit under different operating conditions, but also provides better signal isolation, reduces the impact of interconnect capacitance, reduces signal crosstalk and interference, and improves circuit stability and reliability.

[0436] In an exemplary embodiment, a voltage line distance LX is provided between an edge of the second power line 52 close to the ground line 53 and an edge of the ground line 53 close to the second power line 52 . The voltage line distance LX may be greater than or equal to 5 μm.

[0437] In an exemplary embodiment, the level converter is configured to perform voltage conversion, that is, converting the low potential (ground line, 0V) in the inverter circuit to the low potential (second power line, -5V) in the four-transistor unit circuit. Studies have shown that there is an interaction between the two low potentials, and the strength of the interaction is affected by the distance between the ground line and the second power line. When the distance between the ground line and the second power line is small, the insulation layer will be broken down. The present disclosure sets the minimum distance between the ground line and the second power line to 5μm, which not only avoids the insulation layer from being broken down, but also reduces the mutual influence between the ground line and the second power line, thereby improving the stability of the level converter circuit.

[0438] In an exemplary embodiment, the shape of the first connecting electrode 601 can be block-shaped (such as rectangular), and the first connecting electrode 601 is connected to the first P-type gate electrode 201P (also the first N-type gate electrode 201N) through the fifty-first via V51. The first connecting electrode 601 is configured to be connected to the first signal line formed subsequently.

[0439] In an exemplary embodiment, the second connection electrode 602 may be block-shaped (eg, rectangular), connected to the second P-type gate electrode 202P through the fifty-second via V52, and configured to be connected to a first signal line formed subsequently.

[0440] In an exemplary embodiment, the shape of the third connection electrode 603 can be block-shaped (such as rectangular), and the third connection electrode 603 is connected to the third P-type gate electrode 203P through the fifty-third via V53. The third connection electrode 603 is configured to be connected to the first signal line formed subsequently.

[0441] In an exemplary embodiment, the fourth connection electrode 604 may be block-shaped (eg, rectangular), and is connected to the fourth P-type gate electrode 204P through the fifty-fourth via V54. The fourth connection electrode 604 is configured to be connected to a first signal line formed subsequently.

[0442] In an exemplary embodiment, the shape of the fifth connection electrode 605 can be block-shaped (such as rectangular), and the fifth connection electrode 605 is connected to the fifth P-type gate electrode 205P through the fifty-fifth via V55. The fifth connection electrode 605 is configured to be connected to the first signal line formed subsequently.

[0443] In an exemplary embodiment, the shape of the sixth connection electrode 606 can be block-shaped (such as rectangular), and the sixth connection electrode 606 is connected to the sixth P-type gate electrode 206P through the fifty-sixth via V56. The sixth connection electrode 606 is configured to be connected to the first signal line formed subsequently.

[0444] In an exemplary embodiment, the shape of the seventh connection electrode 607 can be block-shaped (such as rectangular), and the seventh connection electrode 607 is connected to the seventh P-type gate electrode 207P through the fifty-seventh via V57. The seventh connection electrode 607 is configured to be connected to the first signal line formed subsequently.

[0445] In an exemplary embodiment, the shape of the eighth connecting electrode 608 can be block-shaped (such as rectangular), and the eighth connecting electrode 608 is connected to the eighth P-type gate electrode 208P through the fifty-eighth via V58. The eighth connecting electrode 608 is configured to be connected to the first signal transfer line formed subsequently.

[0446] In an exemplary embodiment, the shape of the ninth connecting electrode 609 can be block-shaped (such as rectangular), and the ninth connecting electrode 609 is connected to the ninth P-type gate electrode 209P through the fifty-ninth via V59. The ninth connecting electrode 609 is configured to be connected to the first signal transfer line formed subsequently.

[0447] In an exemplary embodiment, the shape of the tenth connecting electrode 610 can be block-shaped (such as rectangular), and the tenth connecting electrode 610 is connected to the tenth P-type gate electrode 210P through the sixtieth via V60. The tenth connecting electrode 610 is configured to be connected to the first signal transfer line formed subsequently.

[0448] In an exemplary embodiment, the shape of the eleventh connecting electrode 611 can be block-shaped (such as rectangular), and the eleventh connecting electrode 611 is connected to the eleventh P-type gate electrode 211P through the sixty-first via V61. The eleventh connecting electrode 611 is configured to be connected to the first signal transfer line formed subsequently.

[0449] In an exemplary embodiment, the shape of the twelfth connecting electrode 612 can be block-shaped (such as rectangular), and the twelfth connecting electrode 612 is connected to the twelfth P-type gate electrode 212P through the sixty-second via V62. The twelfth connecting electrode 612 is configured to be connected to the first signal transfer line formed subsequently.

[0450] In an exemplary embodiment, the shape of the thirteenth connecting electrode 613 can be block-shaped (such as rectangular), and the thirteenth connecting electrode 613 is connected to the thirteenth P-type gate electrode 213P through the sixty-third via V63. The thirteenth connecting electrode 613 is configured to be connected to the first signal transfer line formed subsequently.

[0451] In an exemplary embodiment, the fourteenth connection electrode 614 may be in a block shape (eg, a rectangular shape), and the fourteenth connection electrode 614 is connected to the second N-type gate electrode 202N through a sixty-fourth via hole V64 .

[0452] In an exemplary embodiment, the shape of the fifteenth connecting electrode 615 can be block-shaped (such as rectangular), and the fifteenth connecting electrode 615 is connected to the third N-type gate electrode 203N through the sixty-fifth via V65. The fifteenth connecting electrode 615 is configured to be connected to the second signal transfer line formed subsequently.

[0453] In exemplary embodiments, the first to fifteenth connection electrodes 601 to 615 and the thirty-fifth to forty-third connection electrodes 635 to 643 may be referred to as gate connection electrodes, which are connected to corresponding gate electrodes through corresponding gate vias.

[0454] In an exemplary embodiment, the gate connection electrode in the first NAND gate may include a thirty-fifth connection electrode 635 and a thirty-sixth connection electrode 636, and the gate connection electrode in the second NAND gate may include a thirty-ninth connection electrode 639 and a fortieth connection electrode 640, and the above-mentioned gate connection electrodes may be referred to as first gate connection electrodes.

[0455] In an exemplary embodiment, the gate connection electrode in the first inverter may include the first connection electrode 601 , and the gate connection electrode in the second inverter may include the forty-first connection electrode 641 , which may be referred to as the second gate connection electrode.

[0456] In an exemplary embodiment, the gate connection electrodes in the first transmission gate may include a thirty-seventh connection electrode 637 and a thirty-eighth connection electrode 638, the thirty-seventh connection electrode 637 may be referred to as a third P-type gate connection electrode, and the thirty-eighth connection electrode 638 may be referred to as a third N-type gate connection electrode.

[0457] In an exemplary embodiment, the gate connection electrode in the first P-type transistor unit may include the second connection electrode 602 to the seventh connection electrode 607, the gate connection electrode in the second P-type transistor unit may include the eighth connection electrode 608 to the thirteenth connection electrode 613, and the gate connection electrode in the third P-type transistor unit may include the forty-second connection electrode 642. The above gate connection electrodes may be referred to as fourth gate connection electrodes.

[0458] In an exemplary embodiment, the gate connection electrode in the first N-type transistor unit may include a fourteenth connection electrode 614, the gate connection electrode in the second N-type transistor unit may include a fifteenth connection electrode 615, and the gate connection electrode in the third N-type transistor unit may include a forty-third connection electrode 643. The above gate connection electrodes may be referred to as fifth gate connection electrodes.

[0459] In an exemplary embodiment, the shape of the sixteenth connecting electrode 616 can be a strip shape extending along the second direction Y, the first end of the sixteenth connecting electrode 616 is connected to the first power line 51, and the second end of the sixteenth connecting electrode 616 is connected to the first P-type source region through a plurality of first vias V1, thereby enabling the first power line 51 to write the first power signal into the first pole (source electrode) of the first P-type transistor P1.

[0460] In an exemplary embodiment, the shape of the seventeenth connecting electrode 617 can be a strip shape extending along the second direction Y, the first end of the seventeenth connecting electrode 617 is connected to the first P-type drain region through the second via V2, and the second end of the seventeenth connecting electrode 617 is connected to the first N-type drain region through the fourth via V4. The seventeenth connecting electrode 617 realizes the mutual connection between the second pole (drain electrode) of the first P-type transistor P1 and the second pole (drain electrode) of the first N-type transistor N1.

[0461] In an exemplary embodiment, a first bump k1 is connected to the seventeenth connection electrode 617 , and the first bump k1 is configured to be connected to a first signal transfer line formed subsequently.

[0462] In an exemplary embodiment, the shape of the eighteenth connecting electrode 618 can be a strip shape extending along the second direction Y, the first end of the eighteenth connecting electrode 618 is connected to the ground line 53, and the second end of the eighteenth connecting electrode 618 is connected to the first N-type source region through the third via V3, thereby realizing the grounding of the first pole (source electrode) of the first N-type transistor N1.

[0463] In an exemplary embodiment, the nineteenth connection electrode 619 may be in the shape of a strip extending along the second direction Y. A first end of the nineteenth connection electrode 619 is connected to the first power line 51, and a second end of the nineteenth connection electrode 619 is connected to the second P-type source region via a plurality of fifth vias V5, thereby enabling the first power line 51 to write the first power signal to the first electrode (source electrode) of the second P-type transistor P2. In an exemplary embodiment, the nineteenth connection electrode 619 may serve as the second P-type source electrode of the present disclosure.

[0464] In an exemplary embodiment, the twentieth connection electrode 620 may be in the shape of a strip extending along the second direction Y. A first end of the twentieth connection electrode 620 is connected to the first connection line 701, and a second end of the twentieth connection electrode 620 is connected to the second P-type drain region (also the third P-type drain region) through a plurality of sixth vias V6. In an exemplary embodiment, the twentieth connection electrode 620 may serve as both the second P-type drain electrode and the third P-type drain electrode of the present disclosure.

[0465] In an exemplary embodiment, the twenty-first connection electrode 621 may be in the shape of a strip extending along the second direction Y. The first end of the twenty-first connection electrode 621 is connected to the first power line 51, and the second end of the twenty-first connection electrode 621 is connected to the third P-type source region (also the fourth P-type source region) via a plurality of seventh vias V7. This enables the first power line 51 to write the first power signal to the first electrode (source electrode) of the third P-type transistor P3 and the first electrode (source electrode) of the fourth P-type transistor P4. In an exemplary embodiment, the twenty-first connection electrode 621 may serve as both the third P-type source electrode and the fourth P-type source electrode of the present disclosure.

[0466] In an exemplary embodiment, the twenty-second connection electrode 622 may be in the shape of a strip extending along the second direction Y. A first end of the twenty-second connection electrode 622 is connected to the first connection line 701, and a second end of the twenty-second connection electrode 622 is connected to the fourth P-type drain region (also the fifth P-type drain region) through a plurality of eighth vias V8. In an exemplary embodiment, the twenty-second connection electrode 622 may serve as both the fourth P-type drain electrode and the fifth P-type drain electrode of the present disclosure.

[0467] In an exemplary embodiment, the twenty-third connection electrode 623 may be in the shape of a strip extending along the second direction Y. The first end of the twenty-third connection electrode 623 is connected to the first power line 51, and the second end of the twenty-third connection electrode 623 is connected to the fifth P-type source region (also the sixth P-type source region) through a plurality of ninth vias V9. This enables the first power line 51 to write the first power signal to the first electrode (source electrode) of the fifth P-type transistor P5 and the first electrode (source electrode) of the sixth P-type transistor P6. In an exemplary embodiment, the twenty-third connection electrode 623 may serve as both the fifth P-type source electrode and the sixth P-type source electrode of the present disclosure.

[0468] In an exemplary embodiment, the twenty-fourth connection electrode 624 may be in the shape of a strip extending along the second direction Y. A first end of the twenty-fourth connection electrode 624 is connected to the first connection line 701, and a second end of the twenty-fourth connection electrode 624 is connected to the sixth P-type drain region (also the seventh P-type drain region) through a plurality of tenth vias V10. In an exemplary embodiment, the twenty-fourth connection electrode 624 may serve as both the sixth P-type drain electrode and the seventh P-type drain electrode of the present disclosure.

[0469] In an exemplary embodiment, the twenty-fifth connection electrode 625 may be in the shape of a strip extending along the second direction Y. The first end of the twenty-fifth connection electrode 625 is connected to the first power line 51, and the second end of the twenty-fifth connection electrode 625 is connected to the seventh P-type source region (also the eighth P-type source region) through a plurality of eleventh vias V11. This enables the first power line 51 to write the first power signal to the first electrode (source electrode) of the seventh P-type transistor P7 and the first electrode (source electrode) of the eighth P-type transistor P8. In an exemplary embodiment, the twenty-fifth connection electrode 625 may serve as both the seventh P-type source electrode and the eighth P-type source electrode of the present disclosure.

[0470] In an exemplary embodiment, the twenty-sixth connection electrode 626 may be in the shape of a strip extending along the second direction Y. A first end of the twenty-sixth connection electrode 626 is connected to the second connection line 702, and a second end of the twenty-sixth connection electrode 626 is connected to the eighth P-type drain region (also the ninth P-type drain region) through a plurality of twelfth vias V12. In an exemplary embodiment, the twenty-sixth connection electrode 626 may serve as both the eighth P-type drain electrode and the ninth P-type drain electrode of the present disclosure.

[0471] In an exemplary embodiment, the twenty-seventh connection electrode 627 may be in the shape of a strip extending along the second direction Y. The first end of the twenty-seventh connection electrode 627 is connected to the first power line 51, and the second end of the twenty-seventh connection electrode 627 is connected to the ninth P-type source region (also the tenth P-type source region) through a plurality of thirteenth vias V13. This enables the first power line 51 to write the first power signal to the first electrode (source electrode) of the ninth P-type transistor P9 and the first electrode (source electrode) of the tenth P-type transistor P10. In an exemplary embodiment, the twenty-seventh connection electrode 627 may serve as both the ninth P-type source electrode and the tenth P-type source electrode of the present disclosure.

[0472] In an exemplary embodiment, the twenty-eighth connection electrode 628 may be in the shape of a strip extending along the second direction Y. A first end of the twenty-eighth connection electrode 628 is connected to the second connection line 702, and a second end of the twenty-eighth connection electrode 628 is connected to the tenth P-type drain region (also the eleventh P-type drain region) through a plurality of fourteenth vias V14. In an exemplary embodiment, the twenty-eighth connection electrode 628 may serve as both the tenth P-type drain electrode and the eleventh P-type drain electrode of the present disclosure.

[0473] In an exemplary embodiment, the twenty-ninth connection electrode 629 may be in the shape of a strip extending along the second direction Y. The first end of the twenty-ninth connection electrode 629 is connected to the first power line 51, and the second end of the twenty-ninth connection electrode 629 is connected to the eleventh P-type source region (also the twelfth P-type source region) through a plurality of fifteenth vias V15. This enables the first power line 51 to write the first power signal to the first electrode (source electrode) of the eleventh P-type transistor P11 and the first electrode (source electrode) of the twelfth P-type transistor P12. In an exemplary embodiment, the twenty-ninth connection electrode 629 may serve as both the eleventh P-type source electrode and the twelfth P-type source electrode of the present disclosure.

[0474] In an exemplary embodiment, the 30th connection electrode 630 may be in the shape of a strip extending along the second direction Y. A first end of the 30th connection electrode 630 is connected to the second connection line 702, and a second end of the 30th connection electrode 630 is connected to the twelfth P-type drain region (also the thirteenth P-type drain region) through a plurality of sixteenth vias V16. In an exemplary embodiment, the 30th connection electrode 630 may serve as both the twelfth P-type drain electrode and the thirteenth P-type drain electrode of the present disclosure.

[0475] In an exemplary embodiment, the thirty-first connection electrode 631 may be in the shape of a strip extending along the second direction Y. A first end of the thirty-first connection electrode 631 is connected to the first power line 51, and a second end of the thirty-first connection electrode 631 is connected to the seventeenth P-type source region through a plurality of seventeenth vias V17, thereby enabling the first power line 51 to write the first power signal to the first electrode (source electrode) of the thirteenth P-type transistor P13. In an exemplary embodiment, the thirty-first connection electrode 631 may serve as the thirteenth P-type source electrode of the present disclosure.

[0476] In an exemplary embodiment, the nineteenth to thirty-first connection electrodes 619 to 631 may be sequentially disposed along the first direction X, and positions and shapes of the plurality of connection electrodes may be symmetrically disposed with respect to the active center line O.

[0477] In an exemplary embodiment, the first electrode (first P-type source electrode) of the second P-type transistor P2 in the first P-type transistor unit to the first electrode (seventh P-type source electrode) of the seventh P-type transistor P7 and the first electrode (eighth P-type source electrode) of the eighth P-type transistor P8 in the second P-type transistor unit to the first electrode (thirteenth P-type source electrode) of the thirteenth P-type transistor P13 are symmetrically arranged relative to the active center line O, and the first electrode (first P-type drain electrode) of the second P-type transistor P2 in the first P-type transistor unit to the second electrode (seventh P-type drain electrode) of the seventh P-type transistor P7 and the first electrode (eighth P-type drain electrode) of the eighth P-type transistor P8 in the second P-type transistor unit to the second electrode (thirteenth P-type drain electrode) of the thirteenth P-type transistor P13 are symmetrically arranged relative to the active center line O, which can ensure the symmetry of the P-type transistor units in the level converter and improve the consistency of the output high and low levels.

[0478] In an exemplary embodiment, the length of the nineteenth connecting electrode 619 is equal to the length of the thirty-first connecting electrode 631, the width of the nineteenth connecting electrode 619 is equal to the width of the thirty-first connecting electrode 631, and the contact areas of the two connected to the active area through the via are equal; the edge of the nineteenth connecting electrode 619 on the side away from the active center line O has an eleventh length LP11 and the active center line O, the edge of the thirty-first connecting electrode 631 on the side away from the active center line O has a twelfth length LP12 and the active center line O, and the ratio of the eleventh length LP11 to the twelfth length LP12 can be approximately 0.95 to 1.05.

[0479] In an exemplary embodiment, the eleventh length LP11 and the twelfth length LP12 may be substantially equal.

[0480] In an exemplary embodiment, the length of the twentieth connecting electrode 620 is equal to the length of the thirtieth connecting electrode 630, the width of the twentieth connecting electrode 620 is equal to the width of the thirtieth connecting electrode 630, and the contact area of ​​the two connected to the active area through the via is equal; there is an eleventh sub-length LP111 between the edge of the twentieth connecting electrode 620 on the side away from the active center line O and the active center line O, and there is a twelfth sub-length LP112 between the edge of the thirtieth connecting electrode 630 on the side away from the active center line O and the active center line O, and the ratio of the eleventh sub-length LP111 to the twelfth sub-length LP112 can be approximately 0.95 to 1.05.

[0481] In an exemplary embodiment, the eleventh sub-length LP111 and the twelfth sub-length LP112 may be substantially equal.

[0482] In an exemplary embodiment, the length of the twenty-first connecting electrode 621 is equal to the length of the twenty-ninth connecting electrode 629, the width of the twenty-first connecting electrode 621 is equal to the width of the twenty-ninth connecting electrode 629, and the contact areas of the two connected to the active area through the via are equal; the edge of the twenty-first connecting electrode 621 on the side away from the active center line O has a thirteenth sub-length LP113 with the active center line O, and the edge of the twenty-ninth connecting electrode 629 on the side away from the active center line O has a fourteenth sub-length LP114 with the active center line O, and the ratio of the thirteenth sub-length LP113 to the fourteenth sub-length LP114 can be approximately 0.95 to 1.05.

[0483] In an exemplary embodiment, the thirteenth sub-length LP113 and the fourteenth sub-length LP114 may be substantially equal.

[0484] In an exemplary embodiment, the length of the twenty-second connecting electrode 622 is equal to the length of the twenty-eighth connecting electrode 628, the width of the twenty-second connecting electrode 622 is equal to the width of the twenty-eighth connecting electrode 628, and the contact areas of the two connected to the active area through the via are equal; the edge of the twenty-second connecting electrode 622 on the side away from the active center line O has a fifteenth sub-length LP115 from the active center line O, and the edge of the twenty-eighth connecting electrode 628 on the side away from the active center line O has a sixteenth sub-length LP116 from the active center line O, and the ratio of the fifteenth sub-length LP115 to the sixteenth sub-length LP116 can be approximately 0.95 to 1.05.

[0485] In an exemplary embodiment, the fifteenth sub-length LP115 and the sixteenth sub-length LP116 may be substantially equal.

[0486] In an exemplary embodiment, the length of the twenty-third connecting electrode 623 is equal to the length of the twenty-seventh connecting electrode 627, the width of the twenty-third connecting electrode 623 is equal to the width of the twenty-seventh connecting electrode 627, and the contact areas of the two connected to the active area through the via are equal; the edge of the twenty-third connecting electrode 623 on the side away from the active center line O has a seventeenth sub-length LP117 and the active center line O, and the edge of the twenty-seventh connecting electrode 627 on the side away from the active center line O has an eighteenth sub-length LP118 and the active center line O, and the ratio of the seventeenth sub-length LP117 to the eighteenth sub-length LP118 can be approximately 0.95 to 1.05.

[0487] In an exemplary embodiment, the seventeenth sub-length LP117 and the eighteenth sub-length LP118 may be substantially equal.

[0488] In an exemplary embodiment, the length of the twenty-fourth connecting electrode 624 is equal to the length of the twenty-sixth connecting electrode 626, the width of the twenty-fourth connecting electrode 624 is equal to the width of the twenty-sixth connecting electrode 626, and the contact areas of the two connected to the active area through the via are equal; the edge of the twenty-fourth connecting electrode 624 on the side away from the active center line O has a nineteenth sub-length LP119 and the active center line O, and the edge of the twenty-sixth connecting electrode 626 on the side away from the active center line O has a twentieth sub-length LP120 and the active center line O, and the ratio of the nineteenth sub-length LP119 to the 20th sub-length LP120 can be approximately 0.95 to 1.05.

[0489] In an exemplary embodiment, the nineteenth sub-length LP119 and the twentieth sub-length LP120 may be substantially equal.

[0490] In an exemplary embodiment, the twenty-fifth connection electrode 625 may be symmetrically disposed with respect to the active center line O, that is, the lengths between the edges of both sides of the twenty-fifth connection electrode 625 and the active center line O may be equal.

[0491] In an exemplary embodiment, the thirty-second connection electrode 632 may be in the shape of a strip extending along the second direction Y. A first end of the thirty-second connection electrode 632 is connected to the first connection line 701, and a second end of the thirty-second connection electrode 632 is connected to the second N-type drain region through the eighteenth via hole V18. In an exemplary embodiment, the thirty-second connection electrode 632 may serve as the second N-type drain electrode of the present disclosure.

[0492] In an exemplary embodiment, the thirty-third connection electrode 633 may be in the shape of a strip extending along the second direction Y. The first end of the thirty-third connection electrode 633 is connected to the second power line 52, and the second end of the thirty-third connection electrode 633 is connected to the second N-type source region (also the third N-type source region) through the nineteenth via V19. This enables the second power line 52 to write the second power signal to the first electrode (source electrode) of the second N-type transistor N2 and the first electrode (source electrode) of the third N-type transistor N3. In an exemplary embodiment, the thirty-third connection electrode 633 may serve as both the second N-type source electrode and the third N-type source electrode of the present disclosure.

[0493] In an exemplary embodiment, the thirty-fourth connection electrode 634 may be in the shape of a strip extending along the second direction Y. A first end of the thirty-fourth connection electrode 634 is connected to the second connection line 702, and a second end of the thirty-fourth connection electrode 634 is connected to the third N-type drain region through the twentieth via hole V20. In an exemplary embodiment, the thirty-fourth connection electrode 634 may serve as the third N-type drain electrode of the present disclosure.

[0494] In an exemplary embodiment, the thirty-second connection electrode 632 and the thirty-fourth connection electrode 634 may be sequentially disposed along the first direction X, and the two connection electrodes may be symmetrically disposed with respect to the active center line O.

[0495] In an exemplary embodiment, the second electrode (second N-type drain electrode) of the second N-type transistor N2 in the first N-type transistor unit and the second electrode (third N-type drain electrode) of the third N-type transistor N3 in the second N-type transistor unit are symmetrically arranged relative to the active center line O, which can ensure the symmetry of the N-type transistor units in the level converter and improve the consistency of the output high and low levels.

[0496] In an exemplary embodiment, the length of the thirty-second connecting electrode 632 is equal to the length of the thirty-fourth connecting electrode 634, the width of the thirty-second connecting electrode 632 is equal to the width of the thirty-fourth connecting electrode 634, and the contact areas of the two connected to the active area through the via are equal; the edge of the thirty-second connecting electrode 632 on the side away from the active center line O has a thirteenth length LN13 with the active center line O, and the edge of the thirty-fourth connecting electrode 634 on the side away from the active center line O has a fourteenth length LN14 with the active center line O, and the ratio of the thirteenth length LN13 to the fourteenth length LN14 can be approximately 0.95 to 1.05.

[0497] In an exemplary embodiment, the thirteenth length LN13 and the fourteenth length LN14 may be substantially equal.

[0498] In an exemplary embodiment, the thirty-third connection electrode 633 may be symmetrically disposed with respect to the active center line O, that is, the lengths between the edges of both sides of the thirty-third connection electrode 633 and the active center line O may be equal.

[0499] In an exemplary embodiment, the shape of the first connecting line 701 can be a strip shape extending along the first direction X, and the first connecting line 701 is respectively connected to the twentieth connecting electrode 620, the twenty-second connecting electrode 622, the twenty-fourth connecting electrode 624 and the thirty-second connecting electrode 632, and the first connecting line 701 realizes the mutual connection between the second electrode of the second P-type transistor P2, the second electrode of the third P-type transistor P3, the second electrode of the fourth P-type transistor P4, the second electrode of the fifth P-type transistor P5, the second electrode of the sixth P-type transistor P6, the second electrode of the seventh P-type transistor P7 and the second electrode of the second N-type transistor N2.

[0500] In an exemplary embodiment, the first connecting line 701 can be located in the spacing region 50 and on the side of the gap region 50 close to the second N-type active area. The orthographic projection of the first connecting line 701 on the silicon substrate does not overlap with the orthographic projection of the P-type gate electrodes of the second P-type transistor P2 to the seventh P-type transistor P7 on the silicon substrate. The orthographic projection of the first connecting line 701 on the silicon substrate does not overlap with the orthographic projection of the N-type gate electrode of the second N-type transistor N2 on the silicon substrate, which can reduce the impact on the transistor channel area.

[0501] In an exemplary embodiment, the second connection line 702 can be in the shape of a strip extending along the first direction X, and is respectively connected to the fourteenth connection electrode 614, the twenty-sixth connection electrode 626, the twenty-eighth connection electrode 628, the thirtieth connection electrode 630 and the thirty-fourth connection electrode 634. The second connection line 702 realizes the mutual connection between the N-type gate electrode of the second N-type transistor N2, the second electrode of the eighth P-type transistor P8, the second electrode of the ninth P-type transistor P9, the second electrode of the tenth P-type transistor P10, the second electrode of the eleventh P-type transistor P11, the second electrode of the twelfth P-type transistor P12, the second electrode of the thirteenth P-type transistor P13 and the second electrode of the third N-type transistor N3.

[0502] In an exemplary embodiment, the second connecting line 702 can be located in the spacing region 50 and on the side of the gap region 50 close to the third N-type active area. The orthographic projection of the second connecting line 702 on the silicon substrate does not overlap with the orthographic projection of the P-type gate electrodes of the eighth P-type transistor P8 to the thirteenth P-type transistor P13 on the silicon substrate. The orthographic projection of the second connecting line 702 on the silicon substrate does not overlap with the orthographic projection of the N-type gate electrode of the third N-type transistor N3 on the silicon substrate, which can reduce the impact on the transistor channel area.

[0503] In an exemplary embodiment, a voltage domain distance LY is provided between an edge of the seventeenth connection electrode 617 on a side close to the nineteenth connection electrode 619 and an edge of the nineteenth connection electrode 619 on a side close to the seventeenth connection electrode 617 .

[0504] In exemplary embodiments, the voltage domain distance LY may be greater than or equal to 3.67 μm.

[0505] In an exemplary embodiment, the inverter in the level shifter is in a first voltage domain, and the four transistor units are in a second voltage domain, where the first and second voltage domains are distinct. Research has shown that interactions exist between transistors in the first and second voltage domains, and that the strength of these interactions is affected by the distance between the transistors. By setting a minimum distance of 3.67 μm between transistors in the two voltage domains, the present disclosure reduces the interaction between the transistors in the two voltage domains and improves the stability of the level shifter circuit.

[0506] In an exemplary embodiment, the thirty-fifth connection electrode 635 may be block-shaped (rectangular) and connected to the twenty-first P-type gate electrode 221P (also the twenty-first N-type gate electrode 221N) through the sixty-sixth via hole V66 .

[0507] In an exemplary embodiment, the shape of the thirty-sixth connecting electrode 636 can be block-shaped (rectangular), and the thirty-sixth connecting electrode 636 is connected to the twenty-second P-type gate electrode 222P (also the twenty-second N-type gate electrode 222N) through the sixty-seventh via V67, and the thirty-sixth connecting electrode 636 is configured to be connected to the second signal line formed subsequently.

[0508] In an exemplary embodiment, the shape of the thirty-seventh connecting electrode 637 can be block-shaped (rectangular), and the thirty-seventh connecting electrode 637 is connected to the twenty-third P-type gate electrode 223P through the sixty-eighth via V68. The thirty-seventh connecting electrode 637 is also connected to the seventy-fifth connecting electrode 675.

[0509] In an exemplary embodiment, the shape of the thirty-eighth connection electrode 638 can be block-shaped (rectangular), and the thirty-eighth connection electrode 638 is connected to the twenty-third N-type gate electrode 223N through the sixty-ninth via V69. The thirty-eighth connection electrode 638 is also connected to the seventy-fourth connection electrode 674.

[0510] In an exemplary embodiment, the thirty-ninth connection electrode 639 may be block-shaped (rectangular) and connected to the twenty-fourth P-type gate electrode 224P (also the twenty-fourth N-type gate electrode 224N) through the seventieth via hole V70.

[0511] In an exemplary embodiment, the shape of the fortieth connecting electrode 640 can be block-shaped (rectangular), and the fortieth connecting electrode 640 is connected to the twenty-fifth P-type gate electrode 225P (also the twenty-fifth N-type gate electrode 225N) through the seventy-first via V71, and the fortieth connecting electrode 640 is configured to be connected to the second signal line formed subsequently.

[0512] In an exemplary embodiment, the shape of the forty-first connecting electrode 641 can be block-shaped (rectangular), the forty-first connecting electrode 641 is connected to the twenty-sixth P-type gate electrode 226P (also the twenty-sixth N-type gate electrode 226N) through the seventy-second via V72, and the forty-first connecting electrode 641 is connected to the fourth connecting line 704.

[0513] In an exemplary embodiment, the shape of the forty-second connecting electrode 642 can be a strip shape extending along the first direction. The forty-second connecting electrode 642 is connected to the twenty-seventh P-type gate electrode 227P through the seventy-third via V73, connected to the twenty-eighth P-type gate electrode 228P through the seventy-fourth via V74, connected to the twenty-ninth P-type gate electrode 229P through the seventy-fifth via V75, and connected to the thirtieth P-type gate electrode 230P through the seventy-sixth via V76. The forty-second connecting electrode 642 is configured to be connected to the fourth signal transfer line formed subsequently. The forty-second connecting electrode 642 realizes the interconnection of the gate electrode of the twenty-seventh P-type transistor P27, the gate electrode of the twenty-eighth P-type transistor P28, the gate electrode of the twenty-ninth P-type transistor P29, and the gate electrode of the thirtieth P-type transistor P30.

[0514] In an exemplary embodiment, the shape of the forty-third connecting electrode 643 can be a strip shape extending along the first direction. The forty-third connecting electrode 643 is sequentially connected to the twenty-seventh N-type gate electrode 227N through the seventy-seventh via V77, to the twenty-eighth N-type gate electrode 228N through the seventy-eighth via V78, to the twenty-ninth N-type gate electrode 229N through the seventy-ninth via V79, and to the thirtieth N-type gate electrode 230N through the eightieth via V80. The forty-third connecting electrode 643 is configured to be connected to the fifth signal transfer line formed subsequently. The forty-third connecting electrode 643 realizes the interconnection of the gate electrode of the twenty-seventh N-type transistor N27, the gate electrode of the twenty-eighth N-type transistor N28, the gate electrode of the twenty-ninth N-type transistor N29, and the gate electrode of the thirtieth N-type transistor N30.

[0515] In an exemplary embodiment, the shape of the forty-fourth connecting electrode 644 can be a strip shape extending along the second direction Y, the first end of the forty-fourth connecting electrode 644 is connected to the first power line 51, and the second end of the forty-fourth connecting electrode 644 is connected to the twenty-first P-type source region through a plurality of twenty-first vias V21, thereby enabling the first power line 51 to write the first power signal into the first pole (source electrode) of the twenty-first P-type transistor P21.

[0516] In an exemplary embodiment, the shape of the forty-fifth connecting electrode 645 can be a strip shape extending along the second direction Y, the first end of the forty-fifth connecting electrode 645 is connected to the third connecting line 703, and the second end of the forty-fifth connecting electrode 645 is connected to the twenty-first P-type drain region (also the twenty-second P-type drain region) through a plurality of twenty-second vias V22.

[0517] In an exemplary embodiment, the shape of the forty-sixth connecting electrode 646 can be a strip shape extending along the second direction Y, the first end of the forty-sixth connecting electrode 646 is connected to the first power line 51, and the second end of the forty-sixth connecting electrode 646 is connected to the twenty-second P-type source region through a plurality of twenty-third vias V23, thereby enabling the first power line 51 to write the first power signal into the first pole (source electrode) of the twenty-second P-type transistor P22.

[0518] In an exemplary embodiment, the shape of the forty-seventh connecting electrode 647 can be a strip shape extending along the second direction Y, the first end of the forty-seventh connecting electrode 647 is connected to the third connecting line 703, and the second end of the forty-seventh connecting electrode 647 is connected to the twenty-third P-type source region through a plurality of twenty-fourth vias V24.

[0519] In an exemplary embodiment, the forty-eighth connection electrode 648 may have a bar shape extending along the second direction Y, and the forty-eighth connection electrode 648 is connected to the twenty-third P-type drain region through a plurality of twenty-fifth via holes V25 .

[0520] In an exemplary embodiment, a second bump k2 is connected to the forty-eighth connection electrode 648 , and the second bump k2 is configured to be connected to a third signal transfer line formed subsequently.

[0521] In an exemplary embodiment, the shape of the forty-ninth connecting electrode 649 can be a strip shape extending along the second direction Y, the first end of the forty-ninth connecting electrode 649 is connected to the first power line 51, and the second end of the forty-ninth connecting electrode 649 is connected to the twenty-fourth P-type source region through a plurality of twenty-sixth vias V26, thereby enabling the first power line 51 to write the first power signal into the first pole (source electrode) of the twenty-fourth P-type transistor P24.

[0522] In an exemplary embodiment, the shape of the fiftieth connecting electrode 650 can be a strip shape extending along the second direction Y, the first end of the fiftieth connecting electrode 650 is connected to the fourth connecting line 704, and the second end of the fiftieth connecting electrode 650 is connected to the twenty-fourth P-type drain region (also the twenty-fifth P-type drain region) through a plurality of twenty-seventh vias V27.

[0523] In an exemplary embodiment, the shape of the fifty-first connecting electrode 651 can be a strip shape extending along the second direction Y, the first end of the fifty-first connecting electrode 651 is connected to the first power line 51, and the second end of the fifty-first connecting electrode 651 is connected to the twenty-fifth P-type source region through a plurality of twenty-eighth vias V28, thereby enabling the first power line 51 to write the first power signal into the first pole (source electrode) of the twenty-fifth P-type transistor P25.

[0524] In an exemplary embodiment, the shape of the fifty-second connecting electrode 652 can be a strip shape extending along the second direction Y, the first end of the fifty-second connecting electrode 652 is connected to the first power line 51, and the second end of the fifty-second connecting electrode 652 is connected to the twenty-sixth P-type source region through a plurality of twenty-ninth vias V29, thereby enabling the first power line 51 to write the first power signal into the first pole (source electrode) of the twenty-sixth P-type transistor P26.

[0525] In an exemplary embodiment, the fifty-third connection electrode 653 may be in the shape of a strip extending along the second direction Y. A first end of the fifty-third connection electrode 653 is connected to the forty-third connection electrode 643, and a second end of the fifty-third connection electrode 653 is connected to the twenty-sixth P-type drain region through a plurality of thirtieth via holes V30. Since the forty-third connection electrode 643 is respectively connected to the gate electrode of the twenty-seventh N-type transistor N27, the gate electrode of the twenty-eighth N-type transistor N28, the gate electrode of the twenty-ninth N-type transistor N29, and the gate electrode of the thirtieth N-type transistor N30, the second electrode (drain electrode) of the twenty-sixth P-type transistor P26, the gate electrode of the twenty-seventh N-type transistor N27, the gate electrode of the twenty-eighth N-type transistor N28, the gate electrode of the twenty-ninth N-type transistor N29, and the gate electrode of the thirtieth N-type transistor N30 are interconnected.

[0526] In an exemplary embodiment, the fifty-fourth connection electrode 654 may be in a bar shape with a main portion extending along the second direction Y, and the fifty-fourth connection electrode 654 is connected to the twenty-seventh P-type drain region through a plurality of thirty-first via holes V31 .

[0527] In an exemplary embodiment, a third bump k3 is connected to the fifty-fourth connection electrode 654 , and the third bump k3 is configured to be connected to a fourth signal transfer line to be formed subsequently.

[0528] In an exemplary embodiment, the shape of the fifty-fifth connecting electrode 655 can be a strip shape extending along the second direction Y, the first end of the fifty-fifth connecting electrode 655 is connected to the first power line 51, and the second end of the fifty-fifth connecting electrode 655 is connected to the twenty-seventh P-type source region (also the twenty-eighth P-type source region) through a plurality of thirty-second vias V32, thereby enabling the first power line 51 to write the first power signal into the first pole (source electrode) of the twenty-seventh P-type transistor P27 and the first pole (source electrode) of the twenty-eighth P-type transistor P8.

[0529] In an exemplary embodiment, the shape of the fifty-sixth connecting electrode 656 can be a strip shape with the main portion extending along the second direction Y, and the fifty-sixth connecting electrode 656 is connected to the twenty-eighth P-type drain region (also the twenty-ninth P-type drain region) through multiple thirty-third vias V33.

[0530] In an exemplary embodiment, a fourth bump k4 is connected to the fifty-fourth connection electrode 654 , and the fourth bump k4 is configured to be connected to a fourth signal transfer line to be formed subsequently.

[0531] In an exemplary embodiment, the shape of the fifty-seventh connecting electrode 657 can be a strip shape extending along the second direction Y, the first end of the fifty-seventh connecting electrode 657 is connected to the first power line 51, and the second end of the fifty-seventh connecting electrode 657 is connected to the twenty-ninth P-type source region (also the thirtieth P-type source region) through a plurality of thirty-fourth vias V34, thereby enabling the first power line 51 to write the first power signal into the first pole (source electrode) of the twenty-ninth P-type transistor P29 and the first pole (source electrode) of the thirtieth P-type transistor P30.

[0532] In an exemplary embodiment, the fifty-eighth connection electrode 658 may have a bar shape extending along the second direction Y, and the fifty-eighth connection electrode 658 is connected to the thirtieth P-type drain region through a plurality of thirty-fifth via holes V35 .

[0533] In an exemplary embodiment, a fifth bump k5 is connected to the fifty-fourth connection electrode 654 , and the fifth bump k5 is configured to be connected to a fourth signal transfer line to be formed subsequently.

[0534] In an exemplary embodiment, the shape of the fifty-ninth connecting electrode 659 can be a strip shape extending along the second direction Y, the first end of the fifty-ninth connecting electrode 659 is connected to the third connecting line 703, and the second end of the fifty-ninth connecting electrode 659 is connected to the twenty-first N-type drain region through a plurality of thirty-sixth vias V36.

[0535] In an exemplary embodiment, the sixtieth connection electrode 660 may be in a strip shape extending along the second direction Y, and is connected to the twenty-first N-type source region (also the twenty-second N-type drain region) through a plurality of thirty-seventh via holes V37 .

[0536] In an exemplary embodiment, the shape of the sixty-first connecting electrode 661 can be a strip shape extending along the second direction Y, the first end of the sixty-first connecting electrode 661 is connected to the second power line 52, and the second end of the sixty-first connecting electrode 661 is connected to the twenty-second N-type source region through a plurality of thirty-eight vias V38, thereby enabling the second power line 52 to write the second power signal into the first pole (source electrode) of the twenty-second N-type transistor N22.

[0537] In an exemplary embodiment, the shape of the sixty-second connecting electrode 662 can be a strip shape extending along the second direction Y, the first end of the sixty-second connecting electrode 662 is connected to the third connecting line 703, and the second end of the sixty-second connecting electrode 662 is connected to the twenty-third N-type source region through a plurality of thirty-ninth vias V39.

[0538] In an exemplary embodiment, the shape of the sixty-third connecting electrode 663 can be a strip shape extending along the second direction Y, the first end of the sixty-third connecting electrode 663 is connected to the forty-eighth connecting electrode 648, and the second end of the sixty-third connecting electrode 663 is connected to the twenty-third N-type drain region through a plurality of fortieth vias V40, thereby realizing the mutual connection between the second electrode of the twenty-third P-type transistor P23 and the second electrode of the twenty-third N-type transistor N23.

[0539] In an exemplary embodiment, the shape of the sixty-fourth connecting electrode 664 can be a strip shape extending along the second direction Y, the first end of the sixty-fourth connecting electrode 664 is connected to the fourth connecting line 704, and the second end of the sixty-fourth connecting electrode 664 is connected to the twenty-fourth N-type drain region through multiple forty-first vias V41.

[0540] In an exemplary embodiment, the sixty-fifth connection electrode 665 may be in a strip shape extending along the second direction Y, and connected to the twenty-fourth N-type source region (also the twenty-fifth N-type drain region) through a plurality of forty-second via holes V42 .

[0541] In an exemplary embodiment, the shape of the sixty-sixth connecting electrode 666 can be a strip shape extending along the second direction Y, the first end of the sixty-sixth connecting electrode 666 is connected to the second power line 52, and the second end of the sixty-sixth connecting electrode 666 is connected to the twenty-fifth N-type source region through a plurality of forty-third vias V43, thereby enabling the second power line 52 to write the second power signal into the first pole (source electrode) of the twenty-fifth N-type transistor N25.

[0542] In an exemplary embodiment, the shape of the sixty-seventh connecting electrode 667 can be a strip shape extending along the second direction Y, the first end of the sixty-seventh connecting electrode 667 is connected to the second power line 52, and the second end of the sixty-seventh connecting electrode 667 is connected to the twenty-sixth N-type source region through the forty-fourth via V44, thereby enabling the second power line 52 to write the second power signal into the first pole (source electrode) of the twenty-sixth N-type transistor N26.

[0543] In an exemplary embodiment, the shape of the sixty-eighth connecting electrode 668 can be a strip shape extending along the second direction Y, the first end of the sixty-eighth connecting electrode 668 is connected to the forty-third connecting electrode 643, and the second end of the sixty-eighth connecting electrode 668 is connected to the twenty-sixth N-type drain region through the forty-fifth via V45.

[0544] In an exemplary embodiment, since the fifty-third connecting electrode 653 and the sixty-eighth connecting electrode 668 are both connected to the forty-third connecting electrode 643, the gate electrode of the twenty-seventh N-type transistor N27, the gate electrode of the twenty-eighth N-type transistor N28, the gate electrode of the twenty-ninth N-type transistor N29, the gate electrode of the thirtieth N-type transistor N30, the second electrode of the twenty-sixth P-type transistor P26, and the second electrode of the twenty-sixth N-type transistor N26 are interconnected.

[0545] In exemplary embodiments, the forty-third connection electrode 643 , the fifty-third connection electrode 653 , and the sixty-eighth connection electrode 668 may be an integral structure connected to each other.

[0546] In an exemplary embodiment, the sixty-ninth connection electrode 669 may be in a bar shape with a main portion extending along the second direction Y, and the sixty-ninth connection electrode 669 is connected to the twenty-seventh N-type drain region through a plurality of forty-sixth via holes V46 .

[0547] In an exemplary embodiment, a sixth bump k6 is connected to the sixty-ninth connection electrode 669 , and the sixth bump k6 is configured to be connected to a fifth signal transfer line to be formed subsequently.

[0548] In an exemplary embodiment, the shape of the seventieth connecting electrode 670 can be a strip shape extending along the second direction Y, the first end of the seventieth connecting electrode 670 is connected to the second power line 52, and the second end of the seventieth connecting electrode 670 is connected to the twenty-seventh N-type source region (also the twenty-eighth N-type source region) through a plurality of forty-seventh vias V47, thereby enabling the second power line 52 to write the second power signal into the first pole (source electrode) of the twenty-seventh N-type transistor N27 and the first pole (source electrode) of the twenty-eighth N-type transistor N28.

[0549] In an exemplary embodiment, the shape of the seventy-first connection electrode 671 can be a strip shape with the main portion extending along the second direction Y, and the seventy-first connection electrode 671 is connected to the twenty-eighth N-type drain region (also the twenty-ninth N-type drain region) through multiple forty-eighth vias V48.

[0550] In an exemplary embodiment, a seventh bump k7 is connected to the seventy-first connection electrode 671 , and the seventh bump k7 is configured to be connected to a fifth signal transfer line formed subsequently.

[0551] In an exemplary embodiment, the shape of the seventy-second connecting electrode 672 can be a strip shape extending along the second direction Y, the first end of the seventy-second connecting electrode 672 is connected to the second power line 52, and the second end of the seventy-second connecting electrode 672 is connected to the twenty-ninth N-type source region (also the thirtieth N-type source region) through a plurality of forty-ninth vias V49, thereby enabling the second power line 52 to write the second power signal into the first pole (source electrode) of the twenty-ninth N-type transistor N29 and the first pole (source electrode) of the thirtieth N-type transistor N30.

[0552] In an exemplary embodiment, the shape of the seventy-third connecting electrode 673 can be a strip shape extending along the second direction Y, the first end of the seventy-third connecting electrode 673 is connected to the fifty-eighth connecting electrode 658, and the second end of the seventy-third connecting electrode 673 is connected to the thirtieth N-type drain region through a plurality of fiftieth vias V50, thereby realizing the mutual connection between the second pole (drain electrode) of the thirtieth P-type transistor P30 and the second pole (drain electrode) of the thirtieth N-type transistor N30.

[0553] In an exemplary embodiment, an eighth bump k8 is connected to the seventy-third connection electrode 673 , and the eighth bump k8 is configured to be connected to a fifth signal transfer line to be formed subsequently.

[0554] In an exemplary embodiment, the shape of the seventy-fourth connecting electrode 674 can be a strip shape extending along the second direction Y, the first end of the seventy-fourth connecting electrode 674 is connected to the first power line 51, and the second end of the seventy-fourth connecting electrode 674 is connected to the thirty-eighth connecting electrode 638, realizing the connection between the first power line 51 and the gate electrode of the twenty-third N-type transistor N23.

[0555] In an exempla...

Claims

A gate drive circuit includes an output circuit disposed on a silicon substrate, the output circuit comprising at least one level converter and at least one row drive enhancer. The level converter is configured to perform voltage domain conversion on a target timing sequence, and the row drive enhancer is configured to enhance the converted signal and output it to a scan signal line in a display area. At least one input signal of the row drive enhancer is provided by the level converter, and the row drive enhancer is disposed on a side of the level converter close to the display area. The gate drive circuit according to claim 1, wherein The level converter comprises at least a first inverter, a first level conversion unit and a second level conversion unit; The input end of the first level conversion unit is connected to the input end of the first inverter, and the output end of the first level conversion unit is connected to the row driver enhancer; The input end of the second level conversion unit is connected to the output end of the first inverter, and the output end of the second level conversion unit is connected to the row driver enhancer; The first level conversion unit is disposed on a side of the first inverter close to the display area, and the second level conversion unit is disposed on a side of the first level conversion unit close to the display area. The gate drive circuit according to claim 2, wherein: The level converter further includes a selection output unit, which is connected to the output end of the first level conversion unit and the output end of the second level conversion unit respectively. The selection output unit is configured to select and output the output signal of the first level conversion unit or the output signal of the second level conversion unit under the control of a selection input signal. The gate drive circuit according to claim 2, wherein: The first inverter includes a first P-type transistor and a first N-type transistor arranged on one side of the first P-type transistor in the second direction; The first level conversion unit includes a first P-type transistor unit arranged on a first direction side of the first P-type transistor and a first N-type transistor unit arranged on a second direction side of the first P-type transistor unit; the second level conversion unit includes a second P-type transistor unit arranged on a first direction side of the first P-type transistor and a second N-type transistor unit arranged on a second direction side of the second P-type transistor unit, and the first direction and the second direction intersect; the first P-type transistor unit includes a second P-type transistor to a seventh P-type transistor arranged on the first direction side of the first P-type transistor and arranged in sequence along the first direction; the second P-type transistor unit includes an eighth P-type transistor to a thirteenth P-type transistor arranged on the first direction side of the seventh P-type transistor and arranged in sequence along the first direction; the first N-type transistor unit includes a second N-type transistor arranged on the second direction side of the seventh P-type transistor, and the second N-type transistor unit includes a third N-type transistor arranged on the second direction side of the eighth P-type transistor; At least one P-type transistor includes at least a P-type active layer, at least one N-type transistor includes at least an N-type active layer, and the P-type active layers of the second P-type transistor to the thirteenth P-type transistor are an integrated structure connected to each other; the second P-type transistor to the seventh P-type transistor and the eighth P-type transistor to the thirteenth P-type transistor are symmetrical with respect to an active center line, and the second N-type transistor and the third N-type transistor are symmetrical with respect to an active center line, and the active center line is a straight line that bisects the P-type active layers of the second P-type transistor to the thirteenth P-type transistor in the first direction and extends along the second direction. The gate drive circuit according to claim 4, wherein: At least one P-type transistor also includes a P-type gate electrode, and at least one N-type transistor also includes an N-type gate electrode; the P-type gate electrodes of the second P-type transistor to the seventh P-type transistor and the P-type gate electrodes of the eighth P-type transistor to the thirteenth P-type transistor are symmetrical with respect to the active center line, and the N-type gate electrode of the second N-type transistor and the N-type gate electrode of the third N-type transistor are symmetrical with respect to the active center line. The gate drive circuit according to claim 5, wherein: The edge of the P-type gate electrode of the second P-type transistor away from the active center line has a first length with the active center line, the edge of the P-type gate electrode of the thirteenth P-type transistor away from the active center line has a second length with the active center line, and the ratio of the first length to the second length is 0.95 to 1.05; the edge of the N-type gate electrode of the second N-type transistor away from the active center line has a third length with the active center line, the edge of the N-type gate electrode of the third N-type transistor away from the active center line has a fourth length with the active center line, and the ratio of the third length to the fourth length is 0.95 to 1.

05. The gate drive circuit according to claim 4, wherein: At least one P-type transistor further includes a P-type source electrode and a P-type drain electrode, and at least one N-type transistor further includes an N-type source electrode and an N-type drain electrode; the P-type source electrodes of the second P-type transistor to the seventh P-type transistor and the P-type source electrodes of the eighth P-type transistor to the thirteenth P-type transistor are symmetrical with respect to the active center line, and the P-type drain electrodes of the second P-type transistor to the seventh P-type transistor and the P-type drain electrodes of the eighth P-type transistor to the thirteenth P-type transistor are symmetrical with respect to the active center line; the N-type source electrode of the second N-type transistor and the N-type source electrode of the third N-type transistor are symmetrical with respect to the active center line, and the N-type drain electrode of the second N-type transistor and the N-type drain electrode of the third N-type transistor are symmetrical with respect to the active center line. The gate drive circuit according to claim 7, wherein: The edge of the P-type source electrode of the second P-type transistor away from the active center line has an eleventh length from the active center line, the edge of the P-type source electrode of the thirteenth P-type transistor away from the active center line has a twelfth length from the active center line, and the ratio of the eleventh length to the twelfth length is 0.95 to 1.05; the edge of the N-type drain electrode of the second N-type transistor away from the active center line has a thirteenth length from the active center line, the edge of the N-type drain electrode of the third N-type transistor away from the active center line has a fourteenth length from the active center line, and the ratio of the thirteenth length to the fourteenth length is 0.95 to 1.

05. The gate drive circuit according to claim 4, wherein: In the first direction, there is a voltage domain distance between the edge of the P-type drain electrode of the first P-type transistor close to the side of the second P-type transistor and the edge of the P-type source electrode of the second P-type transistor close to the side of the first P-type transistor, and the voltage domain distance is greater than or equal to 3.67μm. The gate drive circuit according to claim 4, wherein: The level converter also includes a first power line, a second power line and a ground line, and the shapes of the first power line, the second power line and the ground line are linear or zigzag lines extending along the first direction; the first power line is arranged on the side of the first P-type transistor to the thirteenth P-type transistor away from the first N-type transistor to the third N-type transistor, the second power line is arranged on the side of the second N-type transistor to the third N-type transistor away from the second P-type transistor to the thirteenth P-type transistor, and the ground line is arranged on the side of the first N-type transistor away from the first P-type transistor; there is a voltage line distance between the edge of the second power line close to the ground line and the edge of the ground line close to the second power line, and the voltage line distance is greater than or equal to 5μm. The gate drive circuit according to claim 4, wherein: In the second direction, the size of the P-type transistor in the first P-type transistor unit is larger than that of the P-type transistor in the first inverter, and the size of the P-type transistor in the second P-type transistor unit is larger than that of the P-type transistor in the first inverter. The gate drive circuit according to claim 4, wherein: At least one P-type transistor also includes a P-type gate electrode, and at least one N-type transistor also includes an N-type gate electrode; the level converter also includes a first signal line, one end of the first signal line is connected to the P-type gate electrode of the first P-type transistor and the N-type gate electrode of the first N-type transistor, and the other end of the first signal line is respectively connected to the P-type gate electrodes of the second P-type transistor to the seventh P-type transistor; the first signal line is arranged in a gap area between the P-type active area and the N-type active area, and is located on a side of the gap area close to the P-type active area. The gate drive circuit according to claim 12, wherein: At least one P-type transistor further includes a P-type drain electrode, and at least one N-type transistor further includes an N-type drain electrode; the level converter further includes a first signal transfer line, one end of the first signal transfer line is connected to the P-type drain electrode of the first P-type transistor and the N-type drain electrode of the first N-type transistor, and the other end of the first signal transfer line is respectively connected to the P-type gate electrodes of the eighth P-type transistor to the thirteenth P-type transistor; at least part of the first signal transfer line is arranged on a side of the first signal line away from the second N-type transistor, and the orthographic projection of the first signal line on the silicon substrate at least partially overlaps with the orthographic projection of the channel region of the second P-type transistor to the seventh P-type transistor on the silicon substrate; at least part of the first signal transfer line is arranged in a gap area between the P-type active area and the N-type active area, and is located on a side of the gap area close to the P-type active area. The gate drive circuit according to claim 12, wherein: At least one P-type transistor also includes a P-type drain electrode, and at least one N-type transistor also includes an N-type drain electrode; the level converter also includes a first connecting line and a second connecting line, the P-type drain electrodes of the second P-type transistor to the seventh P-type transistor are connected to the N-type drain electrode of the second N-type transistor through the first connecting line, and the P-type drain electrodes of the eighth P-type transistor to the thirteenth P-type transistor are connected to the N-type drain electrode of the third N-type transistor through the second connecting line; the first connecting line and the second connecting line are arranged in a gap area between the P-type active area and the N-type active area, and are located on the side of the gap area close to the N-type active area. The gate drive circuit according to claim 14, wherein: The level converter also includes a second signal transfer line, the first connection line is connected to the N-type gate electrode of the third N-type transistor through the second signal transfer line, and the second connection line is directly connected to the N-type gate electrode of the second N-type transistor; the second signal transfer line is arranged in the gap area between the P-type active area and the N-type active area, and is located on the side of the gap area close to the N-type active area. The gate drive circuit according to claim 15, wherein: In a direction perpendicular to the silicon substrate, the output circuit includes at least a first conductive layer and a second conductive layer arranged on a side of the first conductive layer away from the silicon substrate, the first connecting line and the second connecting line are arranged in the first conductive layer, and the second signal transfer line is arranged in the second conductive layer. The gate drive circuit according to claim 1, wherein The row drive enhancer includes a plurality of transistor groups arranged in sequence along a first direction, at least one transistor group includes a P-type transistor and an N-type transistor arranged on one side of the P-type transistor in a second direction, and the first direction and the second direction intersect; the plurality of transistor groups form a first NAND gate, a first transmission gate, a second NAND gate, a second inverter, and an output unit arranged in sequence along a direction close to the display area, a first distance is provided between the transistor group in the second inverter and the transistor group in the output unit, a second distance is provided between two adjacent transistor groups in the first NAND gate, the first transmission gate, the second NAND gate, and the second inverter, the first distance is greater than the second distance, and the first distance and the second distance are both dimensions in the first direction. The gate drive circuit according to claim 17, wherein: A ratio of the first distance to the second distance is 0.7 to 0.

8. The gate drive circuit according to claim 17, wherein: The first distance is greater than or equal to 0.5 μm, and the second distance is greater than or equal to 0.36 μm. The gate drive circuit according to claim 17, wherein: There is a first distance between the P-type transistor in the second inverter and the P-type transistor in the output unit, and a second distance between the first NAND gate, the first transmission gate, the second NAND gate and two adjacent P-type transistors in the second inverter; and / or, there is a first distance between the N-type transistor in the second inverter and the N-type transistor in the output unit, and a second distance between the first NAND gate, the first transmission gate, the second NAND gate and two adjacent N-type transistors in the second inverter. The gate drive circuit according to claim 20, wherein: At least one P-type transistor includes a P-type active area, and at least one N-type transistor includes an N-type active area; there is a first distance between the P-type active area in the second inverter and the P-type active area in the output unit, and there is a second distance between two adjacent P-type active areas in the first NAND gate, the first transmission gate, the second NAND gate, and the second inverter; and / or, there is a first distance between the N-type active area in the second inverter and the N-type active area in the output unit, and there is a second distance between two adjacent N-type active areas in the first NAND gate, the first transmission gate, the second NAND gate, and the second inverter. The gate drive circuit according to claim 17, wherein: At least one P-type transistor includes a P-type active region, and at least one N-type transistor includes an N-type active region; in the second direction, a gap region is provided between the P-type active layer of the at least one P-type transistor and the N-type active layer of the at least one N-type transistor, edges of the P-type active regions of the plurality of P-type transistors close to the gap region are located on a same straight line extending along the first direction, and edges of the N-type active regions of the plurality of N-type transistors close to the gap region are located on a same straight line extending along the first direction. The gate drive circuit according to claim 22, wherein At least one P-type transistor also includes a P-type gate electrode, and at least one N-type transistor also includes an N-type gate electrode; at least one transistor group in the first NAND gate and the second NAND gate includes a first gate connection electrode, and the first gate connection electrode is connected to the P-type gate electrode of the P-type transistor and the N-type gate electrode of the N-type transistor through a first gate via, and the first gate via is arranged in the gap area. The gate drive circuit according to claim 23, wherein At least one transistor group in the second inverter includes a second gate connection electrode, which is connected to the P-type gate electrode of the P-type transistor and the N-type gate electrode of the N-type transistor through a second gate via, and the second gate via is arranged in the gap area; in the second direction, the second gate via is closer to the N-type active area of ​​the N-type transistor than the first gate via. The gate drive circuit according to claim 23, wherein The transistor group in the first transmission gate includes a third P-type gate connection electrode and a third N-type gate connection electrode, the third P-type gate connection electrode is connected to the P-type gate electrode of the P-type transistor through a third P-type gate via, and the third N-type gate connection electrode is connected to the N-type gate electrode of the N-type transistor through a third N-type gate via, and the third P-type gate via and the third N-type gate via are arranged in the gap area; in the second direction, relative to the first gate via, the third P-type gate via is closer to the P-type active area of ​​the P-type transistor, and the third N-type gate via is closer to the N-type active area of ​​the N-type transistor. The gate drive circuit according to claim 23, wherein The output unit includes a third P-type transistor unit and a third N-type transistor unit; the third P-type transistor unit includes a fourth gate connection electrode, and the fourth gate connection electrode is connected to the P-type gate electrode of the P-type transistor through a fourth gate via; the third N-type transistor unit includes a fifth gate connection electrode, and the fifth gate connection electrode is connected to the N-type gate electrode of the N-type transistor through a fifth gate via; the fourth gate via and the fifth gate via are arranged in the gap area; relative to the first gate via, the fourth gate via is closer to the P-type active area of ​​the P-type transistor, and the fifth gate via is closer to the N-type active area of ​​the N-type transistor. The gate drive circuit according to claim 17, wherein: At least one P-type transistor further includes a P-type gate electrode and a P-type active layer, and at least one N-type transistor further includes an N-type gate electrode and an N-type active layer; the first NAND gate includes at least a twenty-second P-type transistor P22 and a twenty-second N-type transistor N22, and the second NAND gate includes at least a twenty-fifth P-type transistor P25 and a twenty-fifth N-type transistor N25; the row drive enhancer further includes a second signal line, one end of the second signal line is connected to the P-type gate electrode of the twenty-second P-type transistor P22 and the N-type gate electrode of the twenty-second N-type transistor N22, and the other end of the second signal line is connected to the P-type gate electrode of the twenty-fifth P-type transistor P25 and the N-type gate electrode of the twenty-fifth N-type transistor N25; The second signal line is disposed in a gap region between the P-type active layer and the N-type active layer, and is located on a side of the gap region close to the P-type active region. The gate drive circuit according to claim 27, wherein: At least one P-type transistor also includes a P-type drain electrode, and at least one N-type transistor also includes an N-type drain electrode; the first transmission gate includes a twenty-third P-type transistor P23 and a twenty-third N-type transistor N23, and the output unit includes at least a twenty-seventh P-type transistor P27 and a twenty-seventh N-type transistor N27; the row drive enhancer also includes a third signal transfer line, one end of the third signal transfer line is connected to the P-type drain electrode of the twenty-third P-type transistor P23 and the P-type drain electrode of the twenty-third N-type transistor N23, and the other end of the third signal transfer line is connected to the P-type gate electrode of the twenty-seventh P-type transistor P27; the third signal transfer line is arranged on the side of the second signal line away from the N-type active layer. The gate drive circuit according to claim 28, wherein Along the first direction, an extension length of the third signal transfer line is greater than an extension length of the second signal line. The gate drive circuit according to claim 28, wherein The first NAND gate also includes a twenty-first P-type transistor and a twenty-first N-type transistor, and the second NAND gate also includes a twenty-fourth P-type transistor and a twenty-fourth N-type transistor; the row driver enhancer also includes a third connecting line, a first end of the third connecting line is connected to the N-type drain electrode of the twenty-first N-type transistor, a second end of the third connecting line is connected to the P-type source electrode of the twenty-third P-type transistor and the N-type source electrode of the twenty-third N-type transistor, an area between the first end and the second end of the third connecting line is connected to the P-type drain electrode of the twenty-first P-type transistor and the P-type drain electrode of the twenty-second P-type transistor, and the third connecting line is arranged in a gap area between the P-type active layer and the N-type active layer; in the second direction, the spacing between the second signal line and the third connecting line is greater than the spacing between the second signal line and the third signal switching line. The gate drive circuit according to claim 28, wherein The second NAND gate also includes a twenty-fourth P-type transistor and a twenty-fourth N-type transistor, and the second inverter includes a twenty-sixth P-type transistor and a twenty-sixth N-type transistor; the row drive enhancer also includes a fourth connecting line, a first end of the fourth connecting line is connected to the N-type drain electrode of the twenty-fourth N-type transistor, a second end of the fourth connecting line is connected to the P-type gate electrode of the twenty-sixth P-type transistor and the N-type gate electrode of the twenty-sixth N-type transistor, and an area between the first end and the second end of the fourth connecting line is connected to the P-type drain electrode of the twenty-fourth P-type transistor and the P-type drain electrode of the twenty-fifth P-type transistor; the fourth connecting line is arranged in a gap area between the P-type active layer and the N-type active layer; in the second direction, the spacing between the second signal line and the fourth connecting line is greater than the spacing between the second signal line and the third signal switching line. The gate drive circuit according to claim 17, wherein: The output unit includes at least a third P-type transistor unit, and the third P-type transistor unit includes at least a twenty-seventh P-type transistor and a twenty-eighth P-type transistor arranged in sequence along the first direction. At least one P-type transistor includes at least a P-type drain electrode, and the P-type drain electrode of the twenty-seventh P-type transistor is arranged on a side opposite to the first direction of the twenty-seventh P-type transistor, and the P-type drain electrode of the twenty-eighth P-type transistor is arranged on a side of the first direction of the twenty-eighth P-type transistor; the row drive enhancer also includes a fourth signal switching line, and the fourth signal switching line is respectively connected to the P-type drain electrode of the twenty-seventh P-type transistor and the P-type drain electrode of the twenty-eighth P-type transistor. The gate drive circuit according to claim 32, wherein: The third P-type transistor unit also includes a twenty-ninth P-type transistor and a thirtieth P-type transistor arranged in sequence along the first direction, at least one P-type transistor also includes a P-type drain electrode, the P-type drain electrode of the twenty-ninth P-type transistor is arranged on the side opposite to the first direction of the twenty-ninth P-type transistor, the P-type drain electrode of the thirtieth P-type transistor is arranged on the side of the first direction of the thirtieth P-type transistor, and the fourth signal transfer line is respectively connected to the P-type drain electrode of the twenty-ninth P-type transistor and the P-type drain electrode of the thirtieth P-type transistor. The gate drive circuit according to claim 33, wherein In the second direction, the fourth signal transfer line is arranged on the side of the P-type channel center line close to the first power line, and the P-type channel center line is a straight line that bisects the channel area from the twenty-seventh P-type transistor to the thirtieth P-type transistor in the second direction and extends along the first direction. The gate drive circuit according to claim 17, wherein: The output unit includes at least a third N-type transistor unit, the third N-type transistor unit includes at least a twenty-seventh N-type transistor and a twenty-eighth N-type transistor arranged in sequence along the first direction, at least one N-type transistor includes at least an N-type drain electrode, the N-type drain electrode of the twenty-seventh N-type transistor is arranged on a side opposite to the first direction of the twenty-seventh N-type transistor, and the N-type drain electrode of the twenty-eighth N-type transistor is arranged on a side of the twenty-eighth N-type transistor in the first direction; the row drive enhancer also includes a fifth signal switching line, and the fifth signal switching line is respectively connected to the N-type drain electrode of the twenty-seventh N-type transistor and the N-type drain electrode of the twenty-eighth N-type transistor. The gate drive circuit according to claim 35, wherein The third N-type transistor unit also includes a twenty-ninth N-type transistor and a thirtieth N-type transistor arranged in sequence along the first direction, at least one N-type transistor also includes an N-type drain electrode, the N-type drain electrode of the twenty-ninth N-type transistor is arranged on the side opposite to the first direction of the twenty-ninth N-type transistor, the N-type drain electrode of the thirtieth N-type transistor is arranged on the side of the first direction of the thirtieth N-type transistor, and the fifth signal transfer line is respectively connected to the N-type drain electrode of the twenty-ninth N-type transistor and the N-type drain electrode of the thirtieth N-type transistor. The gate drive circuit according to claim 36, wherein In the second direction, the fourth signal transfer line is arranged on the side of the N-type channel center line close to the first power line, and the N-type channel center line is a straight line that bisects the channel area from the twenty-seventh N-type transistor to the thirtieth N-type transistor in the second direction and extends along the first direction. The gate drive circuit according to claims 1 to 37, wherein: The gate driving circuit further includes a shift register circuit and a logic operation circuit provided on a silicon substrate. The shift register circuit is configured to generate a row-by-row shift timing according to a timing signal, and the logic operation circuit is configured to generate a target timing through a logic operation. A display substrate comprises a display area and a non-display area; the display area comprises a plurality of sub-pixels, at least one sub-pixel comprises a pixel driving circuit and at least one scanning signal line, the scanning signal line being configured to provide a scanning signal to the connected pixel driving circuit; the non-display area comprises a plurality of cascaded gate driving circuits, at least one gate driving circuit is connected to the scanning signal line in the display area, and at least one gate driving circuit comprises the gate driving circuit as described in any one of claims 1 to 38. A display device comprising the display substrate as claimed in claim 39.

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