A can overcurrent detection circuit

Abstract

The application relates to the technical field of communication circuits, and discloses a CAN overcurrent detection circuit which comprises a driving module, a MOS tube M1 and a MOS tube M2, the gate of the MOS tube M1 is connected with a DRVH level, the MOS tube M1 is controlled to be turned on or turned off, the drain of the MOS tube M1 is connected with one end of a diode D1, the other end of the diode D1 outputs a CANH transmission signal, the source of the MOS tube M2 is grounded, the gate of the MOS tube M2 is connected with a DRVL level, the drain of the MOS tube M2 is connected with one end of a diode D2, the other end of the diode D2 outputs a CANL transmission signal, the substrate of the MOS tube M2 is connected with the input end of a substrate leakage current detection module, the output end of the substrate leakage current detection module is fed back to the driving module, through the substrate leakage current detection module, the parasitic correlation between the MOS tube substrate leakage current and the main current is utilized to indirectly monitor the driving current of the MOS tube M1 and the MOS tube M2 in the CAN circuit, and through voltage conversion by a sampling resistor, operational amplifier amplification, ADC conversion and threshold value judgment, the overcurrent state can be accurately identified.

Description

Technical Field

[0001] The present invention relates to the technical field of communication circuits, and in particular to a CAN overcurrent detection circuit. Background Art

[0002] CAN bus is a serial communication protocol and a multi-master bus. Each node in the network can act as a master node to actively communicate with other nodes. Unlike the traditional master-slave bus, only the master node can initiate communication. Differential signal transmission is often used. The signals transmitted by the CANH and CANL lines are differential with each other, which can effectively suppress common-mode interference. For example, in various electromagnetic interference environments faced by cars during driving, data can still be accurately transmitted.

[0003] like Figure 1 As shown in the figure, the traditional CAN receiving circuit usually includes a reference module, a transceiver control module, an output shaping module, a receiving module and a protection module. The reference module provides a stable reference voltage or current for the internal circuit of the chip to ensure the accurate operation of the threshold judgment, signal amplification and other functions of each module (such as driving and receiving). The transceiver control module controls the working status of the chip through RS, coordinates the flow of data in the sending path and the receiving path, and decides when to allow data to be sent and when to start receiving monitoring. The output shaping module receives the TXD signal from the MCU, regularizes the waveform of the digital signal, makes the signal conform to the electrical specifications of the CAN bus, and provides clean data to be sent to the driving module. The driver module receives the shaped signal, outputs a level with strong driving capability through DRVH and DRVL, controls the on and off of the external MOS tubes M1 and M2, and finally generates a differential voltage that complies with the CAN protocol on the CANH and CANL buses to push data to the bus. The receiving module monitors the differential voltage on the CANH and CANL buses in real time, converts it into the RXD digital level that the MCU can recognize, completes the reverse conversion of the bus signal to the chip signal, and allows the MCU to read the data on the bus. The protection module is usually responsible for overvoltage or overcurrent protection. For example, when the bus is subjected to surge impact or short circuit, it limits the voltage or current to avoid chip damage and improve system reliability.

[0004] MOS transistors M1 and M2 are often connected to diodes D1 and D2 to prevent backflow. When a reverse voltage (such as a surge or incorrect wiring) appears on the bus, the diodes are reversely cut off, preventing abnormal current from flowing back into MOS transistors M1 and M2, thereby protecting MOS transistors M1 and M2.

[0005] However, due to the lack of overcurrent detection, when the CAN bus appears abnormal conditions such as short circuit or external strong interference leading to excessive current, there is no special detection mechanism, which may cause the CAN transceiver chip to bear excessive current for a long time, and then cause the chip to overheat, performance degradation, and even permanent damage. For example, in the complex electrical environment of a car, the cables between electrical equipment may be short-circuited due to wear, extrusion, etc. At this time, if the excessive current is not effectively detected and processed, it will cause damage to the CAN transceiver chip and affect the communication of the entire car CAN bus network.

[0006] In addition, in the CAN receiving circuit without overcurrent detection function, when the chip fails, it is difficult to quickly determine whether the failure is caused by overcurrent. Maintenance personnel need to spend a lot of time and effort to troubleshoot various possible failure causes, increasing the difficulty of fault diagnosis and maintenance cost.

[0007] Therefore, it is necessary to provide a CAN overcurrent detection circuit to solve the above problems. SUMMARY

[0008] The purpose of the present application is to provide technical solutions to solve the problems in the prior art mentioned in the background.

[0009] To achieve the above purpose, the present application adopts the following technical solutions:

[0010] A CAN overcurrent detection circuit, comprising a driving module, a MOS tube M1 and a MOS tube M2, the driving module receives a shaped signal and supplies the MOS tube M1 and the MOS tube M2 with a DRVH level and a DRVL level;

[0011] The source electrode of the MOS tube M1 is connected to a chip working power supply VCC to provide a driving voltage for the MOS tube M1, the gate electrode of the MOS tube M1 is connected to the DRVH level to control the conduction or cutoff of the MOS tube M1, and the drain electrode of the MOS tube M1 is connected to one end of a diode D1, and the other end of the diode D1 outputs a CANH transmission signal;

[0012] The source electrode of the MOS tube M2 is connected to ground, the gate electrode of the MOS tube M2 is connected to the DRVL level, the drain electrode of the MOS tube M2 is connected to one end of a diode D2, the other end of the diode D2 outputs a CANL transmission signal, a resistor R1 is connected in series between the substrate of the MOS tube M2 and the source electrode, and the substrate of the MOS tube M2 is connected to the input end of a substrate leakage current detection module, and the output end of the substrate leakage current detection module is fed back to the driving module.

[0013] Preferably, the substrate leakage current detection module comprises an amplifier OPA0, an ADC module and a judging module, the non-inverting input terminal of the amplifier OPA0 is connected with the substrate of the MOS transistor M1, the output terminal of the amplifier OPA0 is connected with the input terminal of the ADC module, and the output terminal of the ADC module is connected with the input terminal of the judging module.

[0014] Preferably, the output terminal of the amplifier OPA0 is connected with one end of a resistor R2, the resistor R2 is connected with a resistor R3 in series, and the inverting input terminal of the amplifier OPA0 is connected with the other end of the resistor R2.

[0015] Preferably, the substrate of the MOS transistor M2 is grounded through a resistor R1, when the substrate of the MOS transistor M2 has a leakage current I_sub, a voltage drop Vsub signal is generated on the resistor R1, the voltage drop Vsub signal is amplified by the amplifier OPAO and output as an analog voltage V1, the analog voltage V1 is converted into a code value of a digital signal by the ADC module, the code value of the digital signal is input into the judging module, the code value converted by the ADC module is compared with a preset code value by the judging module, and a determination result S0 is output to the driving module;

[0016] If there is no overcurrent, S0=0;

[0017] If there is an overcurrent, S0=1;

[0018] The driving module adjusts the on-off of the MOS transistor M2 according to the detection result of S0.

[0019] Preferably, the source of the MOS transistor M1 is connected with the source of a MOS transistor M3, the gate of the MOS transistor M1 and the gate of the MOS transistor M3 are connected with a DRVH level, the drain of the MOS transistor M3 is connected with the drain of the MOS transistor M2, the gate of the MOS transistor M2 is connected with one end of a resistor R2, and the other end of the resistor R2 is connected with a power supply VDD.

[0020] Preferably, when the MOS transistor M1 is turned on to output a current Ip1, the gate of the MOS transistor M1 and the gate of the MOS transistor M3 are connected with the DRVH level, the MOS transistor M3 mirrors the current of the MOS transistor M1, the drain of the MOS transistor M3 outputs a current Ip2 to the MOS transistor M2, and the current of the MOS transistor M1 is indirectly detected by the substrate leakage current detection module.

[0021] Preferably, the first current mirror module is used for mirroring the current of the MOS transistor M1, the second current mirror module is used for mirroring the current of the MOS transistor M2, and the current superposition module is used for superimposing the current of the MOS transistor M1 and the MOS transistor M2, and the current superposition module indirectly detects the current of the MOS transistor M1 and the MOS transistor M2 through the substrate leakage current detection module.

[0022] Preferably, the first current mirror module comprises a MOS transistor M3, the source of the MOS transistor M1 is connected with the source of the MOS transistor M3, and the gate of the MOS transistor M1 and the MOS transistor M3 is connected with the DRVH level.

[0023] Preferably, the second current mirror module comprises a MOS transistor M4, a MOS transistor M5 and a MOS transistor M6, the gate of the MOS transistor M4 is connected with the gate of the MOS transistor M2, the source of the MOS transistor M4 is grounded, the drain of the MOS transistor M4 is connected with the drain of the MOS transistor M5, the source of the MOS transistor M5 is connected with the source of the MOS transistor M6, the gate of the MOS transistor M5 is connected with the gate of the MOS transistor M6, and the gate of the MOS transistor M5 is short-circuited with the drain of the MOS transistor M5.

[0024] Preferably, the current superposition module comprises a MOS transistor M7, a MOS transistor M8 and a MOS transistor M9, the drain of the MOS transistor M7 is connected with the drain of the MOS transistor M3, the drain of the MOS transistor M8 is connected with the drain of the MOS transistor M6, the source of the MOS transistor M7 and the source of the MOS transistor M8 are both connected with the drain of the MOS transistor M9, the resistance R1 is connected between the substrate and the source of the MOS transistor M9, and the input end of the substrate leakage current detection module is connected with the substrate of the MOS transistor M9.

[0025] The gate of the MOS transistor M7 is connected with one end of the resistance R3, the gate of the MOS transistor M8 is connected with one end of the resistance R4, the gate of the MOS transistor M9 is connected with one end of the resistance R2, and the other ends of the resistance R2, the resistance R3 and the resistance R4 are all connected with the power supply VDD.

[0026] The CAN overcurrent detection circuit provided by the application has the following advantages compared with the prior art.

[0027] 1. The application indirectly monitors the driving current of MOS tube M1 and MOS tube M2 in the CAN circuit by the parasitic correlation between the substrate leakage current of the MOS tube and the main current, through the sampling resistance voltage conversion, operational amplifier amplification, ADC conversion and threshold judgment, the overcurrent state is accurately identified, the driving module dynamically adjusts the on-off of MOS tube M1 and MOS tube M2 according to S0, the overcurrent loop is quickly cut off, the chip is effectively prevented from overheating and damage due to continuous overcurrent, the reliability of the CAN transceiver system in complex scenes such as automobiles is significantly improved, even if the bus is short-circuited, it can also be protected in time to prevent fault diffusion to the vehicle CAN network.

[0028] 2. The application associates the fault state by the overcurrent flag S0, that is, S0=1 represents overcurrent, S0=0 represents normal, through current mirroring and substrate detection, the main current anomaly is converted into easy-to-monitor voltage and digital signal, when repairing, engineers only need to monitor S0, V1 and other signals, whether overcurrent occurs and the overcurrent source is M1 or M2 can be quickly determined, the fault diagnosis time is greatly shortened, and the manual troubleshooting cost is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 It is a structural schematic diagram of the traditional CAN receiving circuit;

[0030] Figure 2 It is a system block diagram of the CAN overcurrent detection circuit of the application;

[0031] Figure 3 It is a circuit diagram of embodiment 1 of the application;

[0032] Figure 4 It is a circuit diagram of embodiment 2 of the application;

[0033] Figure 5 It is a circuit diagram of embodiment 3 of the application;

[0034] Figure 6 It is a signal waveform timing diagram of embodiment 1 of the application;

[0035] Figure 7 It is a signal waveform timing diagram of embodiment 2 of the application;

[0036] Figure 8 It is a signal waveform timing diagram of embodiment 3 of the application. DETAILED DESCRIPTION

[0037] The subject matter described herein will now be discussed with reference to example implementations. It should be understood that the discussion of these implementations is merely meant to provide a better understanding of the subject matter described herein, and that changes to the functions and arrangements of elements discussed can be made without departing from the scope of the content of this specification. Various examples can omit, substitute, or add various procedures or components as desired. Additionally, features described with respect to some examples can be combined in other examples.

[0038] Referring now to the drawings Figures 2 to 8 , the present application provides the following examples:

[0039] Example 1

[0040] As shown in Figure 2 and Figure 3 , a CAN overcurrent detection circuit includes a driving module, a MOS tube M1, and a MOS tube M2. The driving module receives a shaped signal and delivers a DRVH level and a DRVL level to the MOS tube M1 and the MOS tube M2.

[0041] The source of the MOS tube M1 is connected to a chip operating power supply VCC to provide a driving voltage for the MOS tube M1. The gate of the MOS tube M1 is connected to the DRVH level to control the conduction or cutoff of the MOS tube M1. The drain of the MOS tube M1 is connected to one end of a diode D1, and the other end of the diode D1 outputs a CANH transmission signal.

[0042] The source of the MOS tube M2 is connected to ground. The gate of the MOS tube M2 is connected to the DRVL level. The drain of the MOS tube M2 is connected to one end of a diode D2, and the other end of the diode D2 outputs a CANL transmission signal. A resistor R1 is connected in series between the substrate of the MOS tube M2 and the source of the MOS tube M2, and the substrate of the MOS tube M2 is connected to an input end of a substrate leakage current detection module. An output end of the substrate leakage current detection module is fed back to the driving module.

[0043] The substrate leakage current detection module includes an amplifier OPA0, an ADC module, and a judgment module. The non-inverting input end of the amplifier OPA0 is connected to the substrate of the MOS tube M1. The output end of the amplifier OPA0 is connected to the input end of the ADC module. The output end of the ADC module is connected to the input end of the judgment module. One end of a resistor R2 is connected to the output end of the amplifier OPA0. The resistor R2 is connected in series with a resistor R3. The inverting input end of the amplifier OPA0 is connected to the other end of the resistor R2.

[0044] The substrate of the MOS tube M2 is connected to ground through the resistor R1. When there is a leakage current I_sub of the substrate of the MOS tube M2, a voltage drop Vsub signal is generated on the resistor R1. The current flowing through the resistor R1 generates a voltage Vsub=I_sub*r1.

[0045] For MOS transistors, the ionization effect also occurs, but the effect on the device characteristics is significantly different from that of bipolar transistors. The difference is that the electrons in the channel (for NMOS) generate electron-hole pairs in the drain depletion region through lattice collision, and part of the holes flow to the substrate to form a substrate current. The electrons generated in the process flow to the drain end, so the carriers generated in the ionization effect are not confined within the device as in bipolar transistors. For NMOS devices, the result can be equivalent to connecting a controlled current source in series from the drain to the substrate layer;

[0046] The order of magnitude of the substrate layer current depends on the voltage drop on the drain depletion region, which can be obtained according to the substrate drain current formula of the NMOS tube as follows:

[0047]

[0048] In the formula:

[0049] I DB： The substrate drain current of the MOS tube;

[0050] K1, K2: process parameters;

[0051] V DS : The voltage from the drain to the source of the MOS tube;

[0052] V DS（act） : The minimum Vds voltage value of the operating amplification region of the MOS tube;

[0053] I D : The drain current of the MOS tube;

[0054] Therefore, the drain current I DB is proportional to the drain current I D , so Vsub can indirectly reflect the size of the current Id of the power tube M2. The voltage drop Vsub signal is amplified by the amplifier OPAO to output an analog voltage V1, V1 = Vsub * (R2 + R3) / R3. The analog voltage V1 is converted into a digital signal code value by the ADC module. The digital signal code value is input to the judgment module, and the code value converted by the ADC module is compared with the preset code value by the judgment module. The determination result S0 is output to the driving module;

[0055] If there is no overcurrent, S0 = 0;

[0056] If the output is overcurrent, S0 = 1;

[0057] The driving module adjusts the on-off of the MOS tube M2 according to the detection result of S0.

[0058] The potential is detected, such as Figure 6As shown, in normal operation, IDS slowly rises with the input signal, and when overcurrent occurs, IDS exceeds IDS_max, exceeding the safe threshold of the device. During this process, the substrate leakage current Isub is associated with IDS, and the waveform of Isub is consistent with Isub. In normal operation, it is flat, and when overcurrent occurs, it rises with the increase of Isub. After being amplified by the amplifier OP AO, the waveform of the output analog voltage V1 is consistent with Vsub, but the amplitude is amplified, which is convenient for ADC collection. When the SO output by the judgment module is in normal operation, the judgment module detects that V1 is lower than the threshold, and outputs S0=0, indicating no overcurrent. When overcurrent occurs, V1 exceeds the threshold, and the judgment module outputs S0=1, indicating overcurrent alarm.

[0059] Embodiment 2

[0060] As shown in Figure 4 Based on embodiment 1, in order to detect the current of MOS tube M1 and further control the on-off of MOS tube M1 by the driving module, the following technical scheme is provided:

[0061] The source of MOS tube M1 is connected with the source of MOS tube M3, the gate of MOS tube M1 and MOS tube M3 is connected to DRVH level, the drain of MOS tube M3 is connected with the drain of MOS tube M2, the gate of MOS tube M2 is connected with one end of resistor R2, and the other end of resistor R2 is connected with power supply VDD.

[0062] When MOS tube M1 is turned on to output current Ip1, the gate of MOS tube M1 and MOS tube M3 is connected to DRVH level, MOS tube M3 mirrors the current of MOS tube M1, so that Ip1=Ip2, the drain of MOS tube M3 outputs current Ip2 to MOS tube M2, so that MOS tube M2 is in the on state, and the on current of MOS tube M2 is determined by the mirrored Ip2 of MOS tube M3, which is indirectly associated with the output current Ip1 of MOS tube M1. Then the current of MOS tube M1 is indirectly detected by the substrate leakage current detection module in embodiment 1. The specific substrate leakage current detection module is described in detail in embodiment 1, which will not be described here.

[0063] When MOS tube M1 is turned on, current detection is performed, as shown in Figure 7 When DRVH signal is high, DRVH=1, MOS tube M1 and MOS tube M3 are cut off, which means that Ip1, Ip2, Vsub, V1 and S0 are 0.

[0064] When the DRVH signal is low, DRVH=0, MOS tubes M1 and M3 are turned on, Ip1 and Ip2 jump from 0 to a stable value. If there is overcurrent, Ip1 exceeds Ids_max, Vsub and V1 rise synchronously. If Ip1 exceeds Ids_max, V1 will also exceed V1_max, S0 jumps, and when V1 exceeds the judgment module threshold, SO=1 and an overcurrent alarm can be issued.

[0065] Example 3

[0066] like Figure 5 As shown, based on Example 2, in order to be able to indirectly detect the current of the MOS transistor M1 and the MOS transistor M2 at the same time, the following technical solution is also provided:

[0067] The CAN overcurrent detection circuit also includes a first current mirror module, a second current mirror module and a current superposition module. The first current mirror module is used to mirror the current of the MOS tube M1, the second current mirror module is used to mirror the current of the MOS tube M2, and the current superposition module is used to superimpose the mirrored currents of the MOS tubes M1 and M2. The current superposition module indirectly detects the currents of the MOS tubes M1 and M2 through the substrate leakage current detection module.

[0068] Specifically, the first current mirror module includes a MOS transistor M3, the source of the MOS transistor M1 and the source of the MOS transistor M3 are connected in common, and the gates of the MOS transistor M1 and the MOS transistor M3 are connected in common to the DRVH level;

[0069] The second current mirror module includes a MOS transistor M4, a MOS transistor M5, and a MOS transistor M6. The gate of the MOS transistor M4 is connected to the gate of the MOS transistor M2, the source of the MOS transistor M4 is grounded, the drain of the MOS transistor M4 is connected to the drain of the MOS transistor M5, the source of the MOS transistor M5 is connected to the source of the MOS transistor M6, the gate of the MOS transistor M5 is connected to the gate of the MOS transistor M6, and the gate and drain of the MOS transistor M5 are short-circuited.

[0070] The current superposition module includes MOS transistors M7, M8, and M9. The drain of MOS transistor M7 is connected to the drain of MOS transistor M3, the drain of MOS transistor M8 is connected to the drain of MOS transistor M6, the source of MOS transistor M7 and the source of MOS transistor M8 are both connected to the drain of MOS transistor M9, a resistor R1 is connected in series between the substrate and the source of MOS transistor M9, and the input end of the substrate leakage current detection module is connected to the substrate of MOS transistor M9.

[0071] The gate of MOS transistor M7 is connected to one end of resistor R3, the gate of MOS transistor M8 is connected to one end of resistor R4, the gate of MOS transistor M9 is connected to one end of resistor R2, and the other ends of resistors R2, R3 and R4 are all connected to power supply VDD.

[0072] The MOS transistor M3 of the first current mirror module has the same function as the MOS transistor M3 in Embodiment 2, and mirrors the current of the MOS transistor M1, Ip1=Ip2, so as to indirectly obtain the current on the MOS transistor M1;

[0073] The MOS transistor M4, the MOS transistor M5 and the MOS transistor M6 of the second current mirror module mirror the current In1 of the MOS transistor M2, the MOS transistor M4 has the current In2=In1 on it due to the common connection of the gate of the MOS transistor M4 and the gate of the MOS transistor M2, then the MOS transistor M5 and the MOS transistor M6 mirror the current In2 of the MOS transistor M4, In3=In2, so as to indirectly obtain the mirrored current on the MOS transistor M2;

[0074] The MOS transistor M7 and the MOS transistor M8 of the current superposition module superimpose the current Ip2 from the MOS transistor M3 and the current In3 from the MOS transistor M6, and the total output current is In4=Ip2+In3, the current In4 flows through the MOS transistor M9, so that the MOS transistor M9 is turned on, thereby generating the current I_sub on the substrate of the MOS transistor M9, which has the same principle as the substrate current on M2 in Embodiment 1, the difference is that the substrate current in this embodiment is affected by the current size of Ip2 and In3, and finally the substrate leakage current detection module indirectly detects the currents on the MOS transistor M1 and the MOS transistor M2, and feeds back to the driving module, so as to control the on-off of the MOS transistor M1 and the MOS transistor M2 through the driving module.

[0075] As shown in FIG. 4, when the MOS transistor M1 and the MOS transistor M2 are turned on at the same time, the current detection is performed: Figure 8

[0076] Phase one: DRVH=1, DRVL=1, the MOS transistor M1 and the MOS transistor M2 are turned off, DRVH and DRVL are high level, the MOS transistor M3 and the MOS transistor M4 are cut off, Ip1, In1, Vsub, V1 and S0 are 0, at this time, there is no overcurrent, and the judgment module outputs 0;

[0077] Phase two: DRVH=0, DRVL=0, the MOS transistor M1 and the MOS transistor M2 are turned on, DRVH and DRVL are low level, the MOS transistor M3 and the MOS transistor M4 are turned on, Ip1 and In1 increase, respectively driving the CANH bus and the CANL bus, if overcurrent, Ids_max is reached, the MOS transistor M9 is turned on due to the mirrored current In4, the substrate leakage current I_sub increases, and Vsub also rises, the amplifier OPAO amplifies Vsub, so that V1 rises with Vsub, if overcurrent, V1 reaches V1_max, the judgment module detects that V1>threshold, S0 is equal to 1, and it is judged that overcurrent occurs; ​

[0078] Phase three: DRVH=1, DRVL=1, the driving module controls MOS M1 and MOS M2 to be closed, so that Ip1 and In1 are zero, so that the substrate leakage current Isub of MOS M9 is zero, Vsub and V1 return to 0, the judging module detects that V1< threshold, S0 is equal to 0, and the overcurrent is removed.

[0079] Therefore, through multi-stage current mirror, superposition circuit and substrate leakage current detection, the driving current of MOS M1 and MOS M2 can be indirectly monitored, without directly connecting a sampling resistor to affect the driving ability of the main circuit, which not only protects the driving efficiency of the CAN bus, but also accurately detects the overcurrent risk.

[0080] The above describes the embodiments of the present application, but the present application is not limited to the above specific embodiments, and the above specific embodiments are only illustrative but not restrictive, and those skilled in the art can make many forms under the inspiration of the present application, which all belong to the protection of the present application.

Claims

1. A CAN overcurrent detection circuit, characterized by, The drive module receives the shaped signal and then supplies the MOS transistor M1 and the MOS transistor M2 with a DRVH level and a DRVL level; The source of the MOS transistor M1 is connected to a chip working power supply VCC to provide a driving voltage for the MOS transistor M1, the gate of the MOS transistor M1 is connected to the DRVH level to control the conduction or cutoff of the MOS transistor M1, the drain of the MOS transistor M1 is connected to one end of a diode D1, and the other end of the diode D1 outputs a CANH transmission signal. The source of the MOS transistor M2 is connected to the ground, the gate of the MOS transistor M2 is connected to the DRVL level, the drain of the MOS transistor M2 is connected to one end of a diode D2, the other end of the diode D2 outputs a CANL transmission signal, a resistor R1 is connected in series between the substrate of the MOS transistor M2 and the source, and the substrate of the MOS transistor M2 is connected to the input end of a substrate leakage current detection module, and the output end of the substrate leakage current detection module is fed back to the drive module. The substrate leakage current detection module comprises an amplifier OPA0, an ADC module and a judgment module, the non-inverting input end of the amplifier OPA0 is connected to the substrate of the MOS transistor M1, the output end of the amplifier OPA0 is connected to the input end of the ADC module, and the output end of the ADC module is connected to the input end of the judgment module. The output end of the amplifier OPA0 is connected to one end of a resistor R2, the resistor R2 is connected in series with a resistor R3, and the inverting input end of the amplifier OPA0 is connected to the other end of the resistor R2. The substrate of the MOS transistor M2 is connected to the ground through the resistor R1, when there is a leakage current I_sub in the substrate of the MOS transistor M2, a voltage drop Vsub signal is generated on the resistor R1, the voltage drop Vsub signal is amplified by the amplifier OPAO and then an analog voltage V1 is output, the analog voltage V1 is converted into a code value of a digital signal by the ADC module, the code value of the digital signal is input to the judgment module, the code value converted by the ADC module is compared with a preset code value by the judgment module, and a determination result S0 is output to the drive module. If there is no overcurrent, S0=0. If there is an overcurrent, S0=1. The drive module adjusts the on-off of the MOS transistor M2 according to the detection result of S0.

2. The CAN overcurrent detection circuit according to claim 1, characterized in that, The source of the MOS transistor M1 is connected to the source of a MOS transistor M3, the gates of the MOS transistor M1 and the MOS transistor M3 are connected to the DRVH level, the drain of the MOS transistor M3 is connected to the drain of the MOS transistor M2, the gate of the MOS transistor M2 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the power supply VDD.

3. The CAN overcurrent detection circuit of claim 2, wherein, When the MOS transistor M1 is turned on to output a current Ip1, the gates of the MOS transistor M1 and the MOS transistor M3 are connected to the DRVH level, the MOS transistor M3 mirrors the current of the MOS transistor M1, the drain of the MOS transistor M3 outputs a current Ip2 to the MOS transistor M2, and the current of the MOS transistor M1 is indirectly detected by the substrate leakage current detection module.

4. The CAN overcurrent detection circuit of claim 1, wherein, The current mirror module comprises a first current mirror module, a second current mirror module and a current superposition module, the first current mirror module is used for mirroring the current of MOS transistor M1, the second current mirror module is used for mirroring the current of MOS transistor M2, the current superposition module is used for superimposing the current of MOS transistor M1 and MOS transistor M2, and the current superposition module indirectly detects the current of MOS transistor M1 and MOS transistor M2 through a substrate leakage current detection module.

5. The CAN overcurrent detection circuit of claim 4, wherein, The first current mirror module comprises MOS transistor M3, the source of MOS transistor M1 is connected with the source of MOS transistor M3, and the gate of MOS transistor M1 and MOS transistor M3 is connected with DRVH level.

6. The CAN overcurrent detection circuit of claim 5, wherein, The second current mirror module comprises MOS transistor M4, MOS transistor M5 and MOS transistor M6, the gate of MOS transistor M4 is connected with the gate of MOS transistor M2, the source of MOS transistor M4 is grounded, the drain of MOS transistor M4 is connected with the drain of MOS transistor M5, the source of MOS transistor M5 is connected with the source of MOS transistor M6, the gate of MOS transistor M5 is connected with the gate of MOS transistor M6, and the gate of MOS transistor M5 is short-circuited with the drain of MOS transistor M5.

7. The CAN overcurrent detection circuit of claim 6, wherein, The current superposition module comprises MOS transistor M7, MOS transistor M8 and MOS transistor M9, the drain of MOS transistor M7 is connected with the drain of MOS transistor M3, the drain of MOS transistor M8 is connected with the drain of MOS transistor M6, the source of MOS transistor M7 and the source of MOS transistor M8 are connected with the drain of MOS transistor M9, the resistance R1 is connected between the substrate and the source of MOS transistor M9, and the input end of the substrate leakage current detection module is connected with the substrate of MOS transistor M9. The gate of MOS transistor M7 is connected with one end of resistance R3, the gate of MOS transistor M8 is connected with one end of resistance R4, the gate of MOS transistor M9 is connected with one end of resistance R2, and the other ends of resistance R2, resistance R3 and resistance R4 are connected with power supply VDD.

Images