Probe card emulation method, apparatus, medium, and program product

Abstract

The application discloses a probe card simulation method, device, medium and program product, relates to the technical field of semiconductor testing, and discloses a probe card simulation method, which comprises the following steps: constructing a simulation model of each substructure in a plurality of substructures included in a probe card, performing parameterization setting on each substructure simulation model, setting link configuration information between each parameterized substructure simulation model, obtaining a simulation template file, and performing simulation testing based on input actual parameter values of the probe card and the simulation template file. According to the simulation test result, potential risks existing in the design can be found in time, the number of repeated design modifications is reduced, the product design quality is improved, and the product development progress is accelerated. In addition, by constructing the parameterized simulation model, the constructed simulation model can be reused on the same type of product, so that the model and the link need not be repeatedly created and built, time and labor cost are saved, and efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor testing, and in particular to a simulation method, device, medium and program product of a probe card. BACKGROUND

[0002] In the field of probe card products, as a key component for connecting a tester and a chip under test, a probe card has a very high complexity in design. Specifically, a large number of networks need to be connected in the circuit design of the probe card, which is difficult to plan. Meanwhile, the probe card has a large number of printed circuit board layers, each layer has a specific functional layout, and some complex designs need to be matched with a multi-layer ceramic substrate (MLC), and the function and role of the semiconductor probe card are realized by connecting the printed circuit board and the multi-layer ceramic substrate through a probe, which increases the design difficulty and complexity. Due to the existence of complex design factors, the designer needs to invest a lot of effort in key links such as circuit planning, layout and wiring, and needs to consider many complex factors, and any slight oversight may have a global impact on the overall design effect.

[0003] In the traditional scheme, a probe card is designed according to specific requirements, and after the design is completed, it is evaluated. If the evaluation is abnormal, it needs to be reworked and adjusted, which will cause the product development progress to lag seriously, and the product delivery period cannot be guaranteed. SUMMARY

[0004] The present application provides a simulation method, device, medium and program product of a probe card, which simulates the probe card to discover potential risks in the design in a timely manner according to the simulation test results, reduce the number of repeated design modifications, improve the product design quality, and speed up the product development progress.

[0005] To achieve the above-mentioned purpose, the present application provides a simulation method of a probe card, which comprises:

[0006] Constructing a simulation model of each substructure in a plurality of substructures included in the probe card;

[0007] Parameterizing each substructure simulation model;

[0008] Setting link configuration information between each parameterized substructure simulation model to obtain a simulation template file;

[0009] Based on the input actual parameter value of the probe card and the simulation template file, performing simulation testing.

[0010] In an embodiment, the setting of the link configuration information between each parameterized substructure simulation model to obtain the simulation template file comprises:

[0011] configuring link connection information between each of the parameterized substructure simulation models;

[0012] adding a link sending port and a link receiving port for each link;

[0013] adding an excitation source and a detection point on the link;

[0014] configuring link connection relationships between the excitation source, the detection point, the link sending port and the link receiving port, to obtain the simulation template file.

[0015] In an embodiment, after the parameterization of each substructure simulation model, the method further comprises:

[0016] saving model creation information of each parameterized substructure simulation model, to obtain a substructure simulation model file;

[0017] The configuring link connection information between each of the parameterized substructure simulation models comprises:

[0018] obtaining each of the substructure simulation model files;

[0019] associating each of the substructure simulation model files to the same engineering file;

[0020] performing a link connection operation on each of the parameterized substructure simulation models, to obtain link connection information between each of the parameterized substructure simulation models.

[0021] In an embodiment, the simulation test based on the input probe card actual parameter value and the simulation template file comprises:

[0022] parsing the simulation template file to obtain a full-link parameterized simulation model comprising each of the parameterized substructure simulation models and link relationships thereof;

[0023] inputting the probe card actual parameter value into the full-link parameterized simulation model, to update the full-link parameterized simulation model, to obtain a target full-link simulation model;

[0024] performing a simulation test in the target full-link simulation model.

[0025] In an embodiment, the simulation test in the target full-link simulation model comprises:

[0026] obtaining simulation setting information, the simulation setting information comprising a setting of a parameter value of the excitation source and / or a setting of a rise time and a fall time of the excitation source;

[0027] perform simulation test in the target full-link simulation model based on the simulation setting information.

[0028] In an embodiment, the parameterized setting of each substructure simulation model comprises:

[0029] determining variable parameters of each substructure simulation model;

[0030] configuring independent variables for each variable parameter;

[0031] associating each variable with the corresponding substructure simulation model.

[0032] In an embodiment, the substructure simulation model comprises a printed circuit board simulation model, a multilayer ceramic substrate simulation model and a probe simulation model.

[0033] In addition, to achieve the above object, the present application further provides an electronic device, which comprises a memory, a processor and a computer program stored in the memory and executable on the processor, and the computer program is configured to implement the steps of the simulation method of the probe card as described above.

[0034] In addition, to achieve the above object, the present application further provides a storage medium, which is a computer readable storage medium, and the storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of the simulation method of the probe card as described above.

[0035] In addition, to achieve the above object, the present application further provides a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement the steps of the simulation method of the probe card as described above.

[0036] The one or more technical solutions provided by the present application have at least the following technical effects:

[0037] By constructing the simulation model of each substructure in the probe card, parameterizing each substructure simulation model, setting the link configuration information between each parameterized substructure simulation model, obtaining the simulation template file, and performing simulation test based on the input actual parameter value of the probe card and the simulation template file, potential risks existing in the design can be found in time according to the simulation test result, the number of repeated design modifications is reduced, the product design quality is improved, and the product development progress is accelerated. In addition, by constructing the parameterized simulation model, the constructed simulation model can be reused on the same type of product, without the need to repeatedly create models and build links, saving time and labor cost, and improving efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0038] The accompanying drawings, which are incorporated into and form a part of the specification, illustrate preferred embodiments of the present application and, together with the description, serve to explain the principles of the application.

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings required to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, those skilled in the art can obtain other drawings from these drawings without any creative effort.

[0040] Figure 1 A flowchart of an embodiment of the probe card simulation method of the present application is provided.

[0041] Figure 2 A schematic diagram of a PCB simulation model involved in the probe card simulation method of the present application is provided.

[0042] Figure 3 A schematic diagram of an MLC simulation model involved in the probe card simulation method of the present application is provided.

[0043] Figure 4 A schematic diagram of a probe simulation model involved in the probe card simulation method of the present application is provided.

[0044] Figure 5 A device structure schematic diagram of a hardware running environment involved in the probe card simulation method of the embodiment of the present application is provided. DETAILED DESCRIPTION

[0045] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application, and are not used to limit the present application.

[0046] In order to better understand the technical solutions of the present application, the following will be described in detail in combination with the drawings of the specification and specific embodiments.

[0047] In the conventional scheme, when designing a probe card, a probe card is designed according to specific requirements. After the design is completed, evaluation is performed. If the evaluation is abnormal, rework is required for adjustment, which will cause the product development schedule to lag seriously and the product delivery period to be unable to be guaranteed.

[0048] To solve the above problems, the present application provides a probe card simulation method. The following will describe the probe card simulation method of the present embodiment in detail in combination with the drawings.

[0049] Please refer to Figure 1 , Figure 1 A flowchart of an embodiment of the probe card simulation method of the present application is provided. In the present embodiment, the probe card simulation method comprises steps S10-S40.

[0050] Step S10, constructing a simulation model of each of the plurality of substructures included in the probe card.

[0051] Specifically, the probe card includes a printed circuit board (PCB), a multi-layer ceramic substrate (MLC), and a plurality of substructures such as probes for connecting the PCB and the MLC. Thus, the constructed simulation model of the plurality of substructures includes a printed circuit board simulation model (hereinafter referred to as a PCB simulation model), a multi-layer ceramic substrate simulation model (hereinafter referred to as an MLC simulation model), and a probe simulation model.

[0052] In some embodiments, when modeling the plurality of substructures such as the PCB, the MLC, and the probes, the parameter values of the material parameters, the electrical parameters, and the geometric parameters in each substructure are set to default initial values.

[0053] In some embodiments, constructing the PCB simulation model includes modeling the PCB layer structure, the Pogo resource interface module, and the PCB-DUT interface module. As an example, the constructed PCB simulation model is as shown in Figure 2 .

[0054] The Pogo resource interface module refers to the connection structure (i.e., the Pogo Pin and its surrounding structure) on the probe card connected to the tester, and its electrical characteristics, mechanical behavior, and signal transmission performance are accurately simulated by simulation.

[0055] The PCB-DUT interface module refers to the connection structure on the probe card connected to the wafer chip under test, and the performance of the signal transmission from the PCB to the wafer chip is accurately simulated by simulation.

[0056] For example, when modeling the PCB layer structure, key parameters such as the PCB board thickness, the number of PCB layer stacks, the thickness of each layer, the PCB board material, the dielectric constant of the board material, the dielectric loss factor of the board material, the copper foil etching factor, and the copper foil roughness are modeled to accurately simulate the physical and electrical characteristics of the PCB layer structure.

[0057] For example, modeling the Pogo resource interface module includes modeling the pads, vias, wires, and separate components of the Pogo resource interface module.

[0058] For example, modeling the PCB-DUT interface module includes modeling the pads, vias, wires, and separate components of the PCB-DUT interface module.

[0059] In some embodiments, constructing the MLC simulation model comprises modeling the MLC layer structure, the MLC-DUT interface module, and the Wafer-DUT interface module. As an example, the constructed MLC simulation model is shown in FIG. 1. Figure 3

[0060] The MLC-DUT interface module is a connection structure for interconnecting the PCB-DUT interface module through probes. The Wafer-DUT interface module is a connection structure for interconnecting the DUTs on the wafer in the MLC. The electrical, thermal, and mechanical properties of the signal transmission from the MLC to the wafer DUTs are simulated by simulating the MLC simulation model.

[0061] As an example, the MLC layer structure is modeled by modeling the MLC board thickness, the number of MLC layers, the thickness of each layer, the MLC board material, the dielectric constant of the board material, the dielectric loss factor of the board material, the copper foil etching factor, and the copper foil roughness. By modeling the MLC layer structure, the physical and electrical properties of the MLC can be simulated, providing a solid foundation for subsequent simulation analysis.

[0062] As an example, the MLC-DUT interface module is modeled by modeling the pads, vias, wires, and separate components of the MLC-DUT interface module.

[0063] As an example, the Wafer-DUT interface module is modeled by modeling the pads, vias, wires, and separate components of the Wafer-DUT interface module.

[0064] In some embodiments, the probe simulation model is constructed by converting the 3D structure model of the probe into a model suitable for simulation analysis, and modeling the probe material and the contact port of the probe. As an example, the constructed probe simulation model is shown in FIG. 2. Figure 4

[0065] Step S20, parameterizing the sub-structure simulation models.

[0066] In some embodiments, parameterizing the sub-structure simulation models can include:

[0067] determining the variable parameters of each sub-structure simulation model;

[0068] configuring an independent variable for each variable parameter;

[0069] associating each variable with the corresponding sub-structure simulation model.

[0070] ​​Specifically, when modeling each sub-structure in the step S10, the parameter values of the material parameters, the electrical parameters and the geometric parameters in each sub-structure are set as default initial values.

[0071] To enable each sub-structure simulation model to be applied to other probe card products of the same type, the embodiment parameterizes each sub-structure simulation model. Specifically, first, parameters in each sub-structure simulation model that affect the performance or the result of the model are determined, and these parameters are variable parameters. For example, the geometric parameters, the physical parameters and the electrical parameters of the PCB simulation model, the MLC simulation model and the probe simulation model can be set as the variable parameters. The variable parameters include, but are not limited to, the pad diameter, the pad pitch, the via diameter, the wire width, the size and the number of separated components, and the number of probes.

[0072] Then, for each variable parameter, an independent variable is configured, and the variable is associated with the corresponding sub-structure simulation model. Taking the pad diameter as an example, the variable can be set as D. Subsequently, in the PCB simulation model, the pad at a specific position is found, and the variable D is associated with the diameter parameter of the pad. In this way, when the diameter of the pad needs to be adjusted, the value of the variable D is only needed to be modified, and the diameter of the corresponding pad in the PCB simulation model is automatically updated.

[0073] In some embodiments, after the parameterization of each sub-structure simulation model is completed, the model creation information of each parameterized sub-structure simulation model is saved to obtain a sub-structure simulation model file. By recording the model creation information of each parameterized sub-structure simulation model in a file, subsequent simulation operations, model management and reuse are facilitated.

[0074] In the step S30, link configuration information between each parameterized sub-structure simulation model is set to obtain a simulation template file.

[0075] In some embodiments, the simulation template file is obtained by performing the following steps:

[0076] The link connection information between each parameterized sub-structure simulation model is configured.

[0077] A link sending port and a link receiving port are added for each link.

[0078] A stimulus source and a detection point are added on the link.

[0079] The link connection relationship between the stimulus source, the detection point, the link sending port and the link receiving port is configured to obtain the simulation template file.

[0080] In practical implementation, the first step is to interconnect the simulation links between the parameterized PCB simulation model, MLC simulation model, and probe simulation model. After completing the link interconnection, a transmit port and a receive port are added to each link. The transmit port is responsible for sending signals out, while the receive port is used to receive incoming signals. Then, according to the actual simulation requirements, corresponding excitation sources and probe points are added to the links. Excitation sources provide input signals to the simulation system; common excitation sources include voltage excitation sources, eye diagram excitation sources, and current excitation sources. Different excitation sources are suitable for different simulation scenarios; for example, voltage excitation sources can be used to simulate DC or AC voltage signals, while eye diagram excitation sources are often used for simulation analysis of high-speed signal transmission. Probe points are used to collect signal information in the links to analyze and evaluate parameters such as waveform, amplitude, and frequency. Common probe points include voltage probe points, eye diagram probe points, and current probe points. In addition, a reference ground needs to be added to provide a stable potential reference for the entire simulation link. Finally, using tools such as Circuit Wire provided by simulation software, the excitation source, port, probe point and reference ground in the link are connected to form a complete closed-loop link.

[0081] In some embodiments, the link connectivity information between the various parameterized substructure simulation models is configured through the following steps:

[0082] Obtain the simulation model files for each substructure;

[0083] Associate the simulation model files of each substructure with the same project file;

[0084] Link connectivity operations are performed on each parameterized substructure simulation model to obtain link connectivity information between the various parameterized substructure simulation models.

[0085] Specifically, the system first retrieves the respective substructure simulation model files from their storage locations. Then, these files are associated with the same project file for unified management. Next, using tools and interfaces provided by the simulation software, connections are established between substructures via drag-and-drop and connecting lines. For example, the network structures of the PCB simulation model, MLC simulation model, and probe simulation model are connected to achieve interconnection of multiple substructure simulation models. After link connectivity is established, the system automatically records the link connectivity information between each parameterized substructure simulation model. Since all substructure simulation model files are associated with the same project file, modifications to one substructure simulation model file are automatically synchronized to all interconnected substructure simulation models.

[0086] Through the above steps, a simulation template file containing each parameterized substructure simulation model and link configuration information thereof is obtained. The file provides a complete model framework and data support for subsequent simulation analysis, and users only need to adjust model parameters and simulation conditions according to actual requirements, so that simulation tests in different scenarios can be quickly performed, and the efficiency of simulation work is greatly improved.

[0087] Step S40, simulation test is performed based on the input probe card actual parameter value and the simulation template file.

[0088] In some embodiments, the above S40 can include:

[0089] The simulation template file is parsed to obtain a full-link parameterized simulation model containing each parameterized substructure simulation model and a link relationship thereof;

[0090] The input probe card actual parameter value is input to update the full-link parameterized simulation model to obtain a target full-link simulation model;

[0091] Simulation test is performed in the target full-link simulation model.

[0092] Specifically, the input probe card actual parameter value is input to the parsed full-link parameterized simulation model to set the parameter value of the related parameter in the link parameterized simulation model to obtain the target full-link simulation model.

[0093] In some embodiments, the simulation test in the target full-link simulation model can include:

[0094] Simulation setting information is obtained, and the simulation setting information includes setting of a parameter value of an excitation source and / or setting of a rise time and a fall time of the excitation source;

[0095] The simulation test is performed in the target full-link simulation model based on the simulation setting information.

[0096] In specific implementation, the simulation setting information input by the user is obtained, and the simulation setting information includes but is not limited to voltage setting of a voltage excitation source, rise time and fall time setting of an eye diagram excitation source, symbol rate and symbol type setting of a link channel transmission, rise time and fall time setting of a current excitation source, and signal frequency and pulse width setting of a link channel.

[0097] After the simulation setup is completed, various types of simulation analysis can be carried out to comprehensively evaluate the performance of the target full-link simulation model. The simulation analysis can include transient analysis, fast eye diagram analysis, and linear network analysis. Transient analysis aims to analyze the signal response of the target full-link simulation model during the transient process, such as the rising edge, falling edge, overshoot, undershoot, and other characteristics of the signal, to evaluate the performance of the probe card when the signal changes rapidly. Through eye diagram analysis, the eye diagram quality of the signal can be directly observed, including parameters such as eye height and eye width. Among them, the eye height of the eye diagram represents noise; the eye width represents jitter. Linear network analysis is a linear network analysis of the target full-link simulation model, which calculates the insertion loss, return loss, and impedance of the power distribution network (PDN) at the test points on the link, to evaluate the electrical characteristics of the probe card at different frequencies, providing a reference for optimizing the design of the probe card.

[0098] After the simulation analysis is completed, the simulation analysis results of the target full-link simulation model are output, including but not limited to voltage result output, fast eye diagram result output, current result output, insertion loss and return loss output, and power distribution network impedance result output, etc. The output form can be a data table, a curve graph, etc., so that users can intuitively view and analyze the simulation analysis results, providing strong support for the design and optimization of the probe card.

[0099] In some embodiments, the simulation method of the probe card further comprises:

[0100] Obtaining the simulation test result corresponding to the actual parameter value of the probe card input this time, and recording it as the simulation test result this time;

[0101] If the simulation test result this time does not meet the preset condition, updating the parameter value of the full-link parameterized simulation model, and performing simulation test on the full-link parameterized simulation model based on the updated parameter value until the simulation test result meets the preset condition.

[0102] Specifically, after each simulation test is completed, the system automatically obtains the simulation test result corresponding to the actual parameter value of the probe card input this time from the simulation software or the storage module. The simulation test result includes multiple dimensions of data, such as voltage waveform, current waveform, insertion loss, return loss, and other key indicator data.

[0103] Then, it is determined whether the current simulation test result meets a preset condition. The preset condition can be determined according to the actual application scenario of the probe card, performance requirements, and relevant industry standards. In some embodiments, the simulation result of each specific performance indicator in the current simulation test result can be extracted, and it is determined whether the simulation result of each specific performance indicator meets the corresponding specific performance indicator target setting condition. If the simulation result of all specific performance indicators meets the corresponding specific performance indicator target setting condition, it is determined that the current simulation test result meets the preset condition. If the simulation result of any specific performance indicator does not meet the corresponding specific performance indicator target setting condition, it is determined that the current simulation test result does not meet the preset condition.

[0104] As an example, the peak value of the voltage waveform (hereinafter referred to as "voltage peak value"), the peak value of the current waveform (hereinafter referred to as "current peak value"), eye height, eye width, insertion loss, and return loss can be taken as specific performance indicators. Then, the simulation result of the voltage peak value (hereinafter referred to as "simulation voltage peak value"), the simulation result of the current peak value (hereinafter referred to as "simulation current peak value"), the simulation result of the eye height (hereinafter referred to as "eye height simulation value"), the simulation result of the eye width (hereinafter referred to as "eye width simulation value"), the simulation result of the insertion loss (hereinafter referred to as "insertion loss simulation value"), and the simulation result of the return loss (hereinafter referred to as "return loss simulation value") of the current simulation test output are obtained, and it is determined whether the simulation voltage peak value, the simulation current peak value, the eye height simulation value, the eye width simulation value, the insertion loss simulation value, and the return loss simulation value all meet the corresponding specific performance indicator target setting condition. Specifically, if the difference between the simulation voltage peak value and the voltage peak value threshold is within a preset first range, the difference between the simulation current peak value and the current peak value threshold is within a preset second range, the difference between the eye height simulation value and the eye height threshold is within a preset third range, the difference between the eye width simulation value and the eye width threshold is within a preset fourth range, the difference between the insertion loss simulation value and the insertion loss threshold is within a preset fifth range, and the difference between the return loss simulation value and the return loss threshold is within a preset sixth range, it is determined that the current simulation test result meets the preset condition. The preset first range, the preset second range, the preset third range, the preset fourth range, the preset fifth range, and the preset sixth range can be set according to actual requirements or experience, and the present application does not limit this.

[0105] In some embodiments, if the current simulation test result does not meet the preset condition, the parameter values of the full-link parameterized simulation model can be updated, which can include:

[0106] A specific performance indicator in the current simulation test result that does not meet the corresponding specific performance indicator target setting condition is determined, and is recorded as a specific performance indicator to be optimized.

[0107] determine parameters associated with each specific performance indicator to be optimized, and record them as parameters to be optimized;

[0108] For each parameter to be optimized, calculate the difference between the simulation result of the corresponding specific performance indicator to be optimized and the corresponding specific performance indicator threshold value, and determine the difference value range according to the pre-set rules;

[0109] Adjust the parameter value of the corresponding parameter to be optimized according to the adjustment range and adjustment direction matched with the corresponding difference value range.

[0110] Specifically, first analyze the current simulation test result, filter out the specific performance indicators that do not meet the corresponding specific performance indicator target setting condition, and record them as specific performance indicators to be optimized. Then, determine the corresponding associated parameters of each specific performance indicator to be optimized through the pre-established performance indicator association reference table. And, the difference between the simulation result of each specific performance indicator to be optimized and the corresponding specific performance indicator threshold value is calculated to obtain the difference value. Taking the voltage peak value as an example, the difference between the simulation voltage peak value and the voltage peak value threshold value is obtained by subtracting the voltage peak value threshold value from the simulation voltage peak value.

[0111] Then, based on the corresponding relationship between the parameters, the difference value range, the adjustment direction and the adjustment range, for each parameter to be optimized, the parameter value of the parameter to be optimized is adjusted according to the adjustment range and adjustment direction matched with the corresponding difference value range. Among them, the adjustment direction includes positive direction and negative direction, the positive direction means increasing the parameter value of the parameter on the basis of the original parameter value, and the negative direction means decreasing the parameter value of the parameter on the basis of the original parameter value. For example, assuming that the pad diameter is A, the adjustment direction is positive, and the adjustment range is F%, then the adjusted pad diameter A' = A + A*F%; and assuming that the pad diameter is A, the adjustment direction is negative, and the adjustment range is F%, then the adjusted pad diameter A' = A - A*F%.

[0112] It should be noted that the difference value range divided by different parameters can be different. For example, for the pad diameter parameter, the difference value range can be divided into [D1, D3], [D3, D4], and for the PCB board thickness parameter, the difference value range can be divided into [D1, D2], [D2, D3], [D3, D5]. Wherein, D1, D2, D3, D4 and D5 are pre-set threshold values, and D1 < D2 < D3 < D4 < D5.

[0113] Through the above difference differentiation adjustment strategy, the influence degree of different parameters on system performance and the severity of deviation are fully considered, and the parameters can be reasonably adjusted, so as to more effectively improve the system performance.

[0114] It should be noted that the above examples are only used for understanding the present application and do not constitute a limitation on the simulation method of the probe card of the present application, and more forms of simple transformation based on this technical concept are within the protection scope of the present application.

[0115] The present application provides an electronic device, comprising: at least one processor; and a memory connected in communication with the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the simulation method of the probe card in the above-mentioned embodiment one.

[0116] Reference will be made to the following description of the embodiments of the present application, taken in conjunction with the accompanying drawings, in which Figure 5 which shows a structural schematic diagram of an electronic device suitable for implementing the embodiments of the present application. The electronic device in the embodiments of the present application can include, but is not limited to, mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (Personal Digital Assistant: Personal Digital Assistant), PADs (Portable Application Description: Tablet PC), PMPs (Portable Media Player: Portable Multimedia Player), vehicle terminals (such as vehicle navigation terminals), and the like, and fixed terminals such as digital TVs, desktop computers, and the like. Figure 5 The electronic device shown is only an example and should not bring any limitation on the function and use range of the embodiments of the present application.

[0117] As Figure 5As shown, the electronic device can include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.) that can perform various appropriate actions and processes according to a program stored in a read only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. Various programs and data required for operation of the electronic device are also stored in the RAM 1004. The processing device 1001, the ROM 1002, and the RAM 1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems can be connected to the I / O interface 1006: input devices 1007 including, for example, a touch screen, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; the storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the electronic device to communicate wirelessly or wired with other devices to exchange data. Although the electronic device having various systems is shown in the figure, it should be understood that all of the shown systems are not required to be implemented or possessed. More or less systems can be alternatively implemented or possessed.

[0118] In particular, according to embodiments of the present disclosure, the processes described above with reference to the flowcharts can be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a computer readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network by a communication device, or installed from the storage device 1003, or installed from the ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the methods of the embodiments of the present disclosure are performed.

[0119] The electronic device provided by the present application adopts the probe card simulation method in the above-mentioned embodiments. Compared with the prior art, the electronic device provided by the present application has the same beneficial effects as the probe card simulation method provided by the above-mentioned embodiments, and other technical features in the electronic device are the same as the features disclosed in the previous embodiment method, which will not be repeated here.

[0120] It should be understood that parts of the present disclosure can be realized by hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any appropriate manner in one or more embodiments or examples.

[0121] The present application provides a computer readable storage medium having stored thereon computer readable program instructions (i.e., a computer program) for performing the simulation method of the probe card in the above embodiment.

[0122] The computer readable storage medium provided by the present application may, for example, be a U disk, but is not limited to an electric, magnetic, optical, electromagnetic, infrared, or semiconductor system, system, or device, or any combination thereof. More specific examples of the computer readable storage medium can include, but are not limited to, an electric connection with one or more conductive wires, a portable computer disk, a hard disk, a random access memory (RAM), a read only memory (ROM), an erasable programmable read only memory (EPROM or flash memory), an optical fiber, a portable compact disk read only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present embodiment, the computer readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer readable storage medium can be transmitted by any suitable medium, including but not limited to an electric wire, an optical cable, an RF (Radio Frequency), etc., or any suitable combination thereof.

[0123] The above computer readable storage medium can be contained in an electronic device; or can exist separately without being assembled into an electronic device.

[0124] Computer program code for carrying out operations of the present application can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0125] The flow diagrams and the block diagrams in the drawings are illustrations of architectures, functionalities, and operations of possible implementations of systems, methods, and computer program products according to various embodiments of the present application. In this regard, each block in the flow diagrams or block diagrams can represent a module, a segment, or a portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or the blocks may

[0126] The modules involved in the embodiments of the present application can be implemented in the form of software or in the form of hardware. In some cases, the name of the module does not constitute a limitation on the module itself.

[0127] The readable storage medium provided by the present application is a computer readable storage medium, which stores computer readable program instructions (i.e., computer programs) for executing the simulation method of the probe card. Compared with the prior art, the computer readable storage medium provided by the present application has the same beneficial effects as the simulation method of the probe card provided by the above-mentioned embodiments, which will not be repeated here.

[0128] The application further provides a computer program product comprising a computer program which, when executed by a processor, implements the steps of the simulation method of the probe card as described above.

[0129] Compared with the prior art, the computer program product provided by the application has the same beneficial effects as the simulation method of the probe card provided by the above-mentioned embodiments, and will not be described here.

[0130] The above are only some embodiments of the application, and do not limit the patent scope of the application. Any equivalent structural transformation made by using the content of the application specification and drawings, or direct / indirect application in other related technical fields is included in the patent protection scope of the application.

Claims

1. A method of emulating a probe card, characterized by, The method comprises the following steps: constructing a substructure simulation model of each of a plurality of substructures included in the probe card, wherein the substructure simulation model comprises a printed circuit board simulation model, a multilayer ceramic substrate simulation model, and a probe simulation model; performing parameterization setting on the printed circuit board simulation model, the multilayer ceramic substrate simulation model, and the probe simulation model respectively, and saving model creation information of the parameterized printed circuit board simulation model, the parameterized multilayer ceramic substrate simulation model, and the parameterized probe simulation model respectively to obtain a printed circuit board simulation model file, a multilayer ceramic substrate simulation model file, and a probe simulation model file; associating the printed circuit board simulation model file, the multilayer ceramic substrate simulation model file, and the probe simulation model file to the same engineering file; performing link connection operation on the parameterized printed circuit board simulation model, the parameterized multilayer ceramic substrate simulation model, and the parameterized probe simulation model to obtain link connection information between the printed circuit board simulation model, the multilayer ceramic substrate simulation model, and the probe simulation model; adding a link sending port and a link receiving port to each link; adding an excitation source and a detection point on the link; configuring a link connection relationship between the excitation source, the detection point, the link sending port, and the link receiving port to obtain a simulation template file; performing simulation test based on the simulation template file and actual parameter values of the probe card input at this time to obtain a simulation test result at this time; if the simulation test result at this time does not satisfy a preset condition, determining a specific performance index that does not satisfy a corresponding specific performance setting condition in the simulation test result at this time, and marking it as a specific performance index to be optimized; determining a parameter that has an association relationship with each specific performance index to be optimized through a pre-established performance index association reference table, and marking it as a parameter to be optimized; obtaining a specific performance index simulation result associated with the parameter to be optimized in the simulation test result at this time; for each parameter to be optimized, calculating a difference value between the corresponding specific performance index simulation result and a corresponding specific performance index setting threshold value, and determining a difference value range in which the difference value is located according to a pre-set rule; adjusting the parameter value of the corresponding parameter to be optimized according to an adjustment amplitude and an adjustment direction matched with the corresponding difference value range until the simulation test result at this time satisfies the preset condition.

2. The probe card emulation method of claim 1, wherein, The simulation test based on the simulation template file and the actual parameter values of the probe card input at this time comprises the following steps: parsing the simulation template file to obtain a full-link parameterized simulation model comprising each parameterized substructure simulation model and a link relationship thereof; inputting the actual parameter values of the probe card into the full-link parameterized simulation model to update the full-link parameterized simulation model to obtain a target full-link simulation model; performing simulation test in the target full-link simulation model.

3. The probe card emulation method of claim 2, wherein, The simulation test in the target full-link simulation model comprises the following steps: obtaining simulation setting information, the simulation setting information including setting of parameter values of the stimulus source and / or setting of rise time and fall time of the stimulus source; performing simulation test in the target full-link simulation model based on the simulation setting information.

4. The probe card emulation method of claim 1, wherein, The parameterized setting of the printed circuit board simulation model, the multi-layer ceramic substrate simulation model and the probe simulation model respectively includes: determining variable parameters of the printed circuit board simulation model, the multi-layer ceramic substrate simulation model and the probe simulation model; configuring independent variables for each variable parameter; associating each variable with the corresponding sub-structure simulation model.

5. An electronic device, comprising: The electronic device includes a memory, a processor and a computer program stored on the memory and executable on the processor, and the computer program is configured to implement the steps of the probe card simulation method according to any one of claims 1 to 4.

6. A storage medium, characterized by The storage medium is a computer readable storage medium, and the storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of the probe card simulation method according to any one of claims 1 to 4.

7. A computer program product, characterised in that, The computer program product includes a computer program, and the computer program is executed by a processor to implement the steps of the probe card simulation method according to any one of claims 1 to 4.

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