Thermistor packaging structure and packaging process thereof

Abstract

The thermistor packaging structure comprises a base body with electrode layers covering two surfaces in the length direction, a conductive layer arranged on the outer side of the base body in the height direction, a top surface buffer layer filled in a groove formed by etching the electrode layers, and a side surface buffer layer filled between the side surface of the conductive layer and the side surface of the base body, the conductive layer is electrically connected with the electrode layer, the packaging layer and the conductive layer jointly form a peripheral package of the packaging structure, the grooves etched in the electrode layer on the two surfaces of the length direction of the base body are vertically symmetrical about the base body, the grooves are uniformly distributed in the surfaces of the electrode layer, and the bottoms of the grooves are in contact or not in contact with the base body; according to the invention, each buffer layer and the base body are synchronously expanded and deformed, the deformation of the base body is not suppressed, the sensitive performance of the thermistor is maintained, and the level of a jump point and the stability of the resistance recovery characteristic are ensured.

Description

Technical Field

[0001] The present invention belongs to the technical field of thermistors, and in particular relates to a thermistor packaging structure and a packaging process thereof. Background Art

[0002] Thermistors are classified according to how their resistance changes with temperature. They can be divided into negative temperature coefficient thermistors (NTC), positive temperature coefficient thermistors (PTC), and critical temperature thermistors (CTR). PTC thermistors have a small resistance value and a gradual change below a specific temperature range (called the Curie point or switching temperature). When the temperature exceeds this point, the resistance value increases sharply by several orders of magnitude, indicating a strong positive temperature coefficient. This specific temperature point can be designed through material formulation. Such thermistors are commonly used in temperature sensing, current limiting, and overheating protection.

[0003] PPTC thermistors are a type of PTC thermistor. Their core is a composite material composed of a conductive filler (such as carbon black particles) dispersed in a high molecular weight polymer matrix (usually a crystalline polymer such as polyethylene). Their "trip" protection function relies on the significant crystalline-to-amorphous phase transition and thermal expansion of the polymer matrix when the temperature rises. This phase transition and expansion disrupt the conductive path, causing a sharp increase in resistance. The initial compressive stress exerted on the matrix by the curing of the encapsulant after encapsulation of the PPTC device, combined with the thermal stress generated by the different thermal expansion coefficients during temperature changes, restricts the expansion of the polymer matrix, leading to a shift in the trip point and a deterioration in resistance recovery characteristics, affecting product performance and even causing failure.

[0004] Therefore, it is urgent to design a thermistor packaging structure and packaging process that can buffer stress to solve the above problems. Summary of the Invention

[0005] In order to solve the above problems in the prior art, the present invention provides a thermistor packaging structure and a packaging process thereof.

[0006] To achieve the above-mentioned object, the present invention proposes a thermistor packaging structure, comprising a substrate covered with electrode layers on both surfaces along the length direction, a conductive layer disposed on the outer side of the substrate in the height direction, and further comprising: a top surface buffer layer, filling the groove formed by etching the electrode layer; A side buffer layer is filled between the side of the conductive layer and the side of the substrate, and the conductive layer is electrically connected to the electrode layer; The packaging layer and the conductive layer together form the outer envelope of the packaging structure.

[0007] The grooves etched on the electrode layers on both surfaces in the length direction of the substrate are symmetrical about the substrate.

[0008] The grooves are evenly distributed on the surface of the electrode layer, and the bottoms of the grooves are in contact with or not in contact with the substrate.

[0009] The side buffer layer covers the side surface of the substrate, and the side surface of the conductive layer is connected to the side surface of the side buffer layer.

[0010] The side buffer layer covers the middle section of the substrate side, the upper and lower ends of the side buffer layer are electroplated with metal layers connected to the electrode layer, the metal layer and the side buffer layer jointly cover the substrate side, and the side of the conductive layer is connected to the metal layer and the side buffer layer.

[0011] The top buffer layer and the side buffer layer have a thermal expansion coefficient that is no more than (1-3)×10 -6 / ℃ insulating rubber layer.

[0012] A thermistor packaging process includes the following steps: Electroplating electrode layer: covering the two surfaces of the substrate in the length direction with electrode layers, encapsulating the substrate and the electrode layer, with the surface of the electrode layer exposed; Processing of both sides of the encapsulation material: vertically etching the electrode layer to form a groove, and filling the groove with the top surface buffer layer; vertically etching the encapsulation material to expose the side surface of the substrate and filling the side buffer layer; The encapsulation material is vertically etched to expose the side of the side buffer layer, and a conductive layer connected to the electrode layer is electroplated. The encapsulation material is continued to be covered and the top surface of the conductive layer is exposed to form a packaging layer. The packaging layer and the conductive layer together constitute the peripheral encapsulation.

[0013] Wherein, in the step of electroplating the electrode layer, the grooves etched on the electrode layers on both surfaces in the length direction of the substrate are symmetrical about the upper and lower sides of the substrate.

[0014] Wherein, in the step of electroplating the electrode layer, the grooves are evenly distributed on the surface of the electrode layer, and the bottoms of the grooves are in contact with or not in contact with the substrate.

[0015] Wherein, in the step of processing both sides of the encapsulating material, the side buffer layer covers the side surface of the substrate, and the side surface of the conductive layer is connected to the side surface of the side buffer layer.

[0016] Among them, in the step of processing both sides of the encapsulating material, the side buffer layer covers the middle section of the side of the substrate, the upper and lower ends of the side buffer layer are electroplated with a metal layer connected to the electrode layer, the metal layer and the side buffer layer jointly cover the side of the substrate, and the side of the conductive layer is connected to the metal layer and the side buffer layer.

[0017] In the step of processing both sides of the encapsulation material, the top buffer layer and the side buffer layer have a thermal expansion coefficient that differs from that of the substrate by no more than (1-3)×10 -6 / ℃ insulating rubber layer.

[0018] The present invention has the following advantages: 1. Each buffer layer expands and deforms synchronously with the substrate, which will not suppress the deformation of the substrate, maintain the sensitive performance of the thermistor, and ensure the stability of the trip point and resistance recovery characteristics; 2. The entire structure is symmetrical, balancing the thermal stress distribution on the substrate 7, preventing stress concentration from causing cracking in each layer, and improving the long-term reliability of the structure; 3. The initial compressive stress exerted on the substrate by the encapsulation material during plastic sealing and curing is greatly reduced, thereby reducing the initial compressive stress on the substrate and ensuring product performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a three-dimensional diagram of the existing thermistor structure; Figure 2 is a cross-sectional view of an existing thermistor structure; Figure 3 A three-dimensional diagram of a thermistor packaging structure of the present invention; Figure 4 A cross-sectional view of a first embodiment of a thermistor packaging structure of the present invention; Figure 5 A cross-sectional view of a second embodiment of a thermistor packaging structure of the present invention; Figure 6-Figure 8 A cross-sectional view of the step of electroplating the electrode layer in Example 1 of a thermistor packaging process of the present invention; Figure 9-Figure 23 This is a cross-sectional view of the steps of processing both sides of the encapsulation material in Example 1 of a thermistor packaging process of the present invention.

[0020] In the figure: 1. Electrode layer; 2. Conductive layer; 3. Top buffer layer; 4. Side buffer layer; 5. Encapsulation layer; 6. Groove; 7. Substrate; 8. Metal layer. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the drawings in the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. The content of the present invention will be explained below in conjunction with specific implementation methods. Examples of the implementation methods are shown in the drawings, where the same or similar numbers throughout represent the same or similar components or components with the same or similar functions.

[0022] The terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein; the directional terms mentioned in the present invention, such as: up, down, left, right, front, back, inside, outside, front, back, side, etc., are only reference to the directions of the drawings. The implementation methods and directional terms used in the following description with reference to the drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention. In addition, the examples of various specific processes and materials provided by the present invention are all examples of other processes and / or the use of other materials that a person of ordinary skill in the art can recognize.

[0023] The polymer thermistor (PPTC) in the positive temperature coefficient thermistor includes a central core polymer matrix 7, which is the physical support structure of the entire device; the conductive filler is evenly dispersed in the polymer matrix 7 to form a continuous conductive path network; the electrode is attached to the surface of the polymer matrix 7 by electroplating or other means, electrically connected to its internal conductive network and conducts current, which is the interface between the PPTC and the circuit. The electrode can be set on the same surface or different surfaces of the matrix 7; the electrode and the encapsulation layer 5 are wrapped together on the outside of the component to form physical protection and the electrical external interface of the device (the structure of the existing PPTC thermistor is shown in Figure 2). Figure 1 and Figure 2 As shown), the exposed electrodes can be treated to prevent oxidation.

[0024] Under normal operating conditions, the polymer matrix 7 of the PPTC is in a crystalline or tightly arranged state, and the conductive filler particles are in contact with each other to form a dense conductive network. The device resistance is extremely low (usually in the milliohm to ohm range). When the circuit is overloaded (such as a short circuit or overcurrent), the current passes through the PPTC to generate heat, or the ambient temperature rises, causing the temperature of the polymer matrix 7 to exceed its critical temperature. The polymer matrix 7 changes from a crystalline state to an amorphous state due to expansion, and the volume expands significantly. The expansion causes the conductive filler particles to separate from each other, the conductive network to break, the current conduction path to decrease sharply, and the resistance increases to a high-resistance state. When the circuit fault is eliminated or the temperature drops, the polymer matrix 7 contracts and returns to the crystalline state. The conductive filler particles approach and contact again, the conductive network is restored, and the PPTC resistance drops to the initial low-resistance state, realizing the self-recovery function.

[0025] After the PPTC thermistor is packaged, the polymer matrix 7, which serves as the core component, is encapsulated in a plastic encapsulation compound. The plastic encapsulation compound will shrink in volume during the high-temperature curing process, and this shrinkage will produce compressive stress on the component. The polymer matrix 7 itself has a very high thermal expansion coefficient. When temperature changes occur, different materials will produce cyclic thermal stress at the interface and inside the material due to different thermal expansion coefficients.

[0026] The initial compressive stress imposed by the shrinkage of the plastic compound during curing, combined with the thermal stress generated by the temperature cycle, will significantly enhance the restraint on the PPTC core and limit the expansion of the polymer matrix 7, thereby causing the trip point to shift (the trip temperature to increase or be inaccurate), deterioration of the resistance recovery characteristics (after the fault is cleared, excessive residual stress may prevent the polymer matrix 7 from fully shrinking and recovering, resulting in the resistance being unable to return to the low-resistance state normally), damage to the internal structure (repeated stress may cause interface separation of the conductive filler in the polymer matrix, uneven distribution of the filler, and even internal microcracks, affecting long-term reliability and electrical performance), and overall warping or cracking of the device (in extreme cases, excessive internal stress may cause the entire plastic package to warp or crack at weak interfaces).

[0027] Polymer material (ingredients, components, thermal expansion coefficient) filling the matrix 7: Polymers typically include polyolefins such as polyethylene, polypropylene, and ethylene / propylene copolymers. The polymer of the PTC material can be a crystalline polymer selected from the group consisting of polyethylene, polypropylene, polyoctene, polyvinylidene chloride, and mixtures thereof. Conductive fillers can be dispersed in the polymer and selected from the group consisting of carbon black, metal powder, conductive ceramic powder, and mixtures thereof. Furthermore, to improve the sensitivity and physical properties of the PTC material, the PTC conductive composition may also include additives such as photoinitiators, crosslinkers, coupling agents, dispersants, stabilizers, antioxidants, and / or non-conductive arc-blocking fillers.

[0028] In order to better understand the purpose, structure and function of the present invention, the following is a detailed description of a thermistor packaging structure and its packaging process proposed by the present invention in conjunction with the accompanying drawings. The packaging process can be summarized as follows: Electroplating the electrode layer 1: covering the two surfaces of the substrate 7 in the length direction with the electrode layer 1, encapsulating the substrate 7 and the electrode layer 1, with the surface of the electrode layer 1 exposed; Processing of both sides of the encapsulation material: vertically etching the electrode layer 1 to form a groove 6, and filling the groove 6 with the top surface buffer layer 3; Vertically etching the encapsulation material to expose the side surface of the substrate 7 and fill the side buffer layer 4; The encapsulation material is vertically etched to expose the side of the side buffer layer 4, and the conductive layer 2 connected to the electrode layer 1 is electroplated. The encapsulation material is continued to be covered and the top surface of the conductive layer 2 is exposed to form the packaging layer 5. The packaging layer 5 and the conductive layer 2 together constitute the peripheral package. Example 1

[0029] Specifically, the process steps can be broken down into the following parts: S1: Provide a carrier board, and mount multiple substrates 7 (such as Figure 6 shown); Among them, the carrier is a substrate commonly used in this field, such as an FR-4 resin substrate, etc. According to the surface size of the carrier and the product design, a reasonable layout is performed, and multiple substrates 7 are evenly spaced on the carrier (the present invention takes two substrates as an example). The surfaces to be electroplated of the substrate 7 are the two surfaces in the length direction of the substrate 7. First, one of the two surfaces of the substrate 7 is firmly mounted on the carrier with adhesive (such as epoxy resin adhesive), and each substrate 7 is firmly bonded at the set position.

[0030] Among them, the matrix 7 is a core component commonly used in polymer thermistors. The matrix 7 is a polymer material filled inside, usually including a polyolefin copolymer, which can be a crystalline polymer composed of polyethylene, polypropylene, polyoctene, polyvinylidene chloride and a mixture thereof. The conductive filler is dispersed in the polymer of the matrix 7. The conductive filler can be composed of carbon black, metal powder, conductive ceramic powder and a mixture thereof. In addition, the matrix 7 also includes some additives that can improve the sensitivity and physical properties of the thermistor, such as photoinitiators, cross-linking agents, coupling agents, dispersants, stabilizers, etc.

[0031] Among them, the thermodynamic properties of the polymer matrix 7 high molecular material determine its expansibility, which is essentially the thermal motion of the molecular chain, the change of the crystalline and amorphous structures and the adjustment of the free volume driven by temperature. The macroscopic manifestation is volume expansion and contraction. When the thermistor is in normal working condition, the matrix 7 is in a crystalline or tightly arranged state and the resistance is low; when the circuit is overloaded, the volume of the matrix 7 expands significantly and the resistance increases; when the circuit fault is eliminated, the matrix 7 contracts and returns to normal working condition.

[0032] For example, matrix 7 can be composed, by weight, of 10-30 parts high-density polyethylene, 40-60 parts linear low-density polyethylene, 5-15 parts maleic anhydride-grafted polyethylene, 15-35 parts acetylene black, and 0.1-0.5 parts antioxidant. The carbon black particle size should be 40-100 nm, and antioxidant 1010 (2,6-di-tert-butyl-p-cresol) can be used as the antioxidant. The coefficient of thermal expansion is typically calculated using the linear expansion coefficient, using the formula α = (ΔL / L0) / ΔT (where α is the linear expansion coefficient, ΔL is the length change, L0 is the original length, and ΔT is the temperature change). Experimental methods such as thermomechanical analysis can be used to measure the length change of the material at different temperatures, and the coefficient of thermal expansion at the corresponding temperature can then be calculated using this formula. In addition, it can also be calculated using the volume expansion coefficient, using the formula γ=(ΔV / V0) / ΔT, where γ is the volume expansion coefficient, ΔV is the volume change, V0 is the original volume, and ΔT is the temperature change.

[0033] The content of maleic anhydride grafted polyethylene is relatively low, which has little effect on the overall thermal expansion coefficient. The carbon black particle size is small and the content is moderate, which will reduce the thermal expansion coefficient of the system to a certain extent, but the specific degree of reduction is related to factors such as the dispersion of carbon black. The antioxidant content is very low and has basically no effect on the thermal expansion coefficient. Generally speaking, the thermal expansion coefficient of high-density polyethylene is about (100-130)×10 -6 / ℃, the thermal expansion coefficient of linear low-density polyethylene is similar to that of linear low-density polyethylene. The thermal expansion coefficient of the PPTC thermistor of the above composition will be between that of pure polyethylene and polyethylene composite materials containing carbon black. The specific value needs to be accurately determined through experiments and will vary depending on the actual formulation ratio and preparation process. It is expected that the thermal expansion coefficient of the PPTC thermistor of the polyethylene-carbon black system is usually (50~100)×10 -6 / ℃about.

[0034] S2: Electrode layers 1 are formed on the two surfaces of the substrate 7 in the length direction (such as Figure 7 shown); Among them, the electrode layer 1 is formed into the thickness range required for actual product application through electroplating, sputtering and other processes commonly used in this field. The electrode layer 1 can be silver, copper, nickel and their alloys. The electrode layers 1 on the two relative surfaces of the substrate 7 are symmetrical about the center of the substrate 7. The electrode layer 1 can partially cover or completely cover the surface of the substrate 7, which is set according to actual product requirements.

[0035] Among them, after the substrate 7 is mounted, an electrode layer 1 is formed on its surface, and the substrate 7 is peeled off to remove the adhesive. The adhesive is pasted on the electrode layer 1 and then re-mounted on the carrier. The electrode layer 1 continues to be formed on the other surface of the substrate 7, and finally the surface electrode layer 1 of the substrate 7 along the length direction is formed. In other embodiments, the electrode layer 1 can also be formed on other surfaces of the substrate 7.

[0036] S3: Use the encapsulation material to encapsulate the substrate 7 and the electrode layer 1 on the upper surface of the substrate 7, and mechanically grind the encapsulation material horizontally on the top surface of the encapsulation until the top surface of the electrode layer 1 is exposed (such as Figure 8 As shown), at this time, another electrode layer 1 is attached to the carrier by adhesive and encapsulated in the encapsulation material.

[0037] S4: forming a plurality of grooves 6 (such as Figure 9 shown); Among them, a suitable etching solution is selected according to the material of the electrode layer 1, and parameters such as etching time, etching solution concentration, and etching rate are controlled to etch multiple grooves 6 on the electrode layer 1 through a wet etching process. For example, when the electrode layer 1 is a copper layer, organic acids, phosphates, and hydrogen peroxide can be selected as etching solutions. Other etching methods are also acceptable. This etching process is a commonly used process in this field. The shape of the groove 6 is not limited. The present invention takes a rectangular parallelepiped as an example.

[0038] The etched grooves 6 are evenly spaced and arranged uniformly on the electrode layer 1. The electrode layer 1 can be completely or partially etched, i.e., the bottom of the etched grooves 6 may or may not contact the substrate 7. When the bottom of the grooves 6 directly contacts the substrate 7, the electrode layer 1 is completely and vertically etched away. The etching solution does not affect the material of the substrate 7. For example, an etching solution composed of organic acids, phosphates, and hydrogen peroxide has little reaction with the core components of PPTC at room temperature, acting only physically. The concentration of hydrogen peroxide in the etching solution is relatively low, and the chemical reaction with the polymer material of the substrate 7 during low concentration and short contact time is weak and negligible. Reducing the etching time or rate can eliminate contact between the bottom of the grooves 6 and the substrate 7.

[0039] S5: Fill the top surface buffer layer 3 (such as Figure 10 shown); The top buffer layer 3 can be of various thermal expansion coefficients, and the difference between the thermal expansion coefficient of the substrate 7 and the thermal expansion coefficient is not more than (1 to 3) × 10 -6 / ℃ insulating rubber layer, the top surface buffer layer 3 in the present invention can be silicone rubber, and its thermal expansion coefficient is about (50-100)×10 -6 / ℃, it can be further optimized by filling fillers such as silica. Silicone rubber has excellent insulation properties and forms an elastomer after curing. It can fit tightly to the surface of the substrate 7, buffer thermal stress and mechanical stress, and is corrosion-free. It is suitable for long-term use of electronic components. The top surface buffer layer 3 fills the groove 6, and the top surface is flush with the top surface of the groove 6. The top surface buffer layer 3 is filled according to the etching depth of the groove 6; when the bottom of the groove 6 exposes the surface of the substrate 7, the bottom of the top surface buffer layer 3 is in direct contact with the surface of the substrate 7, and the thermal expansion deformation of the substrate 7 is directly deformed synchronously with the top surface buffer layer 3, and there is no electrode layer 1 pressing; the bottom of the groove 6 is close to the surface of the substrate 7 and the surface of the substrate 7 is not exposed. The bottom of the filled top surface buffer layer 3 is not in contact with the surface of the substrate 7. Although there is a thin layer of pressing of the electrode layer 1, it effectively prevents damage to the substrate 7 body when the groove 6 is etched to the surface of the substrate 7, thereby ensuring the integrity of the structure.

[0040] Silicone rubber is an elastomer with polysiloxane as the basic structural unit, and specifically may include base polymer: polydimethylsiloxane (PDMS); crosslinking agent: room temperature vulcanizing (RTV) silicone rubber; reinforcing filler: fumed silica (white carbon black) to improve mechanical strength and tear resistance; functional fillers: calcium carbonate, aluminum hydroxide (to reduce cost and adjust hardness), iron oxide (to impart color), platinum catalyst (crosslinking catalyst for addition-type silicone rubber); plasticizer (such as methyl silicone oil), coupling agent (to improve filler dispersion), inhibitor (to adjust curing speed), antioxidant (to extend aging resistance). By adjusting the components of the silicone rubber and the substrate 7, the thermal expansion coefficient of the top surface buffer layer 3 and the substrate 7 is kept within (1 to 3) × 10 -6 / ℃.

[0041] Parameters such as the thickness of the electrode layer 1, the depth of the groove 6, and the filling height of the top surface buffer layer 3 are all calculated through actual product design to avoid stress concentration caused by overfilling.

[0042] When the top buffer layer 3 is in direct contact with the substrate 7, the cured silicone rubber is chemically stable, contains no free acids, bases, or strongly polar groups, and exhibits no chemical reaction with the polyethylene-carbon black PPTC substrate 7. Long-term contact will not cause swelling or degradation of the PPTC substrate 7. The top buffer layer 3 and substrate 7 have similar coefficients of thermal expansion, minimizing interfacial thermal stress during temperature cycling, reducing cracking or debonding caused by differential expansion. The rubber maintains stable performance within a temperature range of -60°C to 200°C, and will not soften at high temperatures or harden at low temperatures during long-term use, thus ensuring structural stability.

[0043] S6: vertically etch the encapsulation material to expose the side of the substrate 7 (eg Figure 11 shown); Part of the encapsulating material is removed by dry or wet etching, and the encapsulating material is vertically etched to expose the side of the substrate 7. The present invention takes dry etching as an example, and the encapsulating material is vertically etched on the encapsulating top surface formed in the S3 step. The etching depth is not limited. The present invention takes etching to the middle of the substrate 7 as an example, and the etching width is not limited. The etching width here in the present invention maintains an error of no more than 0.01 times the height of the top surface buffer layer 3 filled in the groove 6.

[0044] S7: Fill the bottom of the recessed area etched in step S6 with a side buffer layer 4 (such as Figure 12 shown); Among them, the side buffer layer 4 can be made of the same material and components as the top buffer layer 3, such as silicone rubber, and has the same function as the top buffer layer 3; the width of the side buffer layer 4 and the height of the top buffer layer 3 are kept within an error of no more than 0.01 times, so that the buffer layer thickness on the top and side surfaces of the substrate 7 remains similar, the stress is relatively symmetrical, and the structure is symmetrical.

[0045] The side buffer layer 4 does not completely fill the recessed area etched in step S6, and a portion of the top of the recessed area is reserved and not filled. In the present invention, the reserved height does not exceed one third of the height of the etched recessed area.

[0046] S8: The recessed area reserved in step S7 is completely filled with a metal layer 8 by electroplating (e.g. Figure 13 shown); Among them, the electroplating process is a commonly used process in this field. The metal layer 8 completely fills the reserved recessed area, and the top is flush with the top surface of the package. The side of the metal layer 8 and the electrode layer 1 are electroplated as a whole, forming a right-angle edge package of the substrate 7, and the two can be made of the same material. The electroplated metal layer 8 can be selected to be filled at the end position of the reserved recessed area by electroplating the metal layer 8, or it can be completely electroplated to fill the reserved recessed area. The present invention takes the latter as an example.

[0047] S9: vertically etch the encapsulation material to expose the side of the side buffer layer 4 (such as Figure 14 shown); Part of the encapsulation material is removed by dry or wet etching, and the encapsulation material is vertically etched to expose the side of the side buffer layer 4. The present invention takes dry etching as an example, and the encapsulation material is vertically etched on the top surface of the encapsulation formed in step S3. The etching depth is not limited. The present invention uses the encapsulation material vertically etched here as the same depth as the encapsulation material etched in S6. At this time, the side buffer layer 4 and the side of the metal layer 8 are exposed in the etching area.

[0048] S10: Electroplating the conductive layer 2 fills the area etched in S9, and the conductive layer 2 is electroplated to extend above the electrode layer 1 and is connected to the electrode layer 1 as a whole (such as Figure 15 shown); Among them, the electroplated conductive layer 2 can be made of the same material as the electrode layer 1, and the side of the conductive layer 2 is also electroplated and connected to the metal layer 8 as a whole, that is, the conductive layer 2 wraps the right-angle edge of the substrate 7 formed by the metal layer 8 and the electrode layer 1. The electrode layer 1 increases the contact surface through the metal layer 8, thereby increasing the stability of the electrical connection with the conductive layer 2, avoiding the delamination of the right-angle edge line of the substrate 7 due to the thermal expansion of the polymer of the substrate 7 and disconnection from the electrical connection relationship, and the line transmission stability is better.

[0049] S11: Continue to use the encapsulation material to encapsulate the conductive layer 2 on the top surface of the encapsulation (such as Figure 16 As shown, the top surface of the encapsulation is horizontally polished by mechanical grinding until the top surface of the conductive layer 2 is exposed. This completes the surface of the substrate 7. The entire substrate 7 is then peeled from the carrier, flipped upside down, and reattached to the carrier. The opposite surface of the substrate 7 is then processed in the same manner, with the electrode layer 1 on this surface flush with the encapsulation material and exposed.

[0050] S12: forming a plurality of grooves 6 (such as Figure 17 shown); The etching method and the formed grooves 6 and S4 are the same. The grooves 6 on the two electrode layers 1 are symmetrical about the substrate 7 and are evenly distributed on the electrode layers 1.

[0051] S13: Fill the top surface buffer layer 3 (such as Figure 18 shown); The top surface buffer layer 3 is filled inside the groove 6, and the thermal expansion coefficient of the substrate 7 is similar to that of the top surface buffer layer 3. When the substrate 7 thermally expands, the top surface buffer layer 3 and the substrate 7 expand and deform synchronously, instead of expanding and deforming like the electrode layer 1 with a smaller thermal expansion coefficient. The thermal expansion deformation of the substrate 7 is suppressed, thereby maintaining the sensitive performance of the thermistor and ensuring the stability of the trip point position and the resistance recovery characteristics.

[0052] Symmetrical top surface buffer layers 3 are provided on the upper and lower surfaces of the substrate 7, and the top surface buffer layers 3 are evenly dispersed on the surface of the electrode layer 1, so that the thermal expansion changes on the surfaces of the two electrode layers 1 of the substrate 7 are uniform, the structure is symmetrical, the deformation is symmetrical, the thermal stress is symmetrical, the structural stability is better, and the service life is long.

[0053] The encapsulation material is filled in the top surface buffer layer 3 and then encapsulated to form the packaging layer 5. The initial compressive stress applied to the substrate 7 by the encapsulation material after plastic sealing and curing is greatly reduced, thereby reducing the initial compressive stress on the substrate 7 and ensuring product performance.

[0054] The symmetrical groove 6 structure balances the thermal stress distribution on the substrate 7, preventing stress concentration from causing cracking of the layers, and improving the long-term reliability of the structure.

[0055] S14: vertically etch the encapsulation material to expose the side of the substrate 7 (eg Figure 19 shown); The bottom of the etched recessed area exposes the end of the side buffer layer 4 filled in step S7.

[0056] S15: The side buffer layer 4 is filled at the bottom of the recessed area etched in step S14. The side buffer layers 4 filled twice are connected as a whole and are symmetrical about the substrate 7. After the same recessed area is filled with the side buffer layer 4, a part of the area is reserved (such as Figure 20 shown); The side stress buffer of the substrate 7 is increased, the side buffer layer 4 is in contact with the side of the substrate 7, and the side buffer layer 4 is spaced between the side of the substrate 7 and the side of the conductive layer 2. The thermal expansion coefficient of the substrate 7 is similar to the thermal expansion coefficient of the side buffer layer 4. When the substrate 7 expands thermally, the side buffer layer 4 expands and deforms synchronously with the substrate 7, and will not expand and deform like the conductive layer 2 with a smaller thermal expansion coefficient. The thermal expansion deformation of the substrate 7 is suppressed, the sensitive performance of the thermistor is maintained, and the trip point position and resistance recovery characteristics are guaranteed to be stable.

[0057] S16: The recessed area reserved in step S15 is completely filled with a metal layer 8 by electroplating (e.g. Figure 21 As shown), the metal layer 8 formed in step S8 and step S16 is symmetrical about the substrate 7 in the upper and lower parts, and the structure is symmetrical; S17: vertically etch the encapsulation material to expose the side of the side buffer layer 4 (such as Figure 22 As shown), at this time, the end of the conductive layer 2 formed in step S10 is exposed in the etching area; S18: Electroplating the conductive layer 2 in the etching area of ​​S17, the conductive layer 2 is electroplated and extended to the top of the electrode layer 1 and connected to the electrode layer 1 as a whole. The electroplated conductive layer 2 is electroplated and connected to the conductive layer 2 electroplated in S10 as a whole, and is symmetrical about the substrate 7. The top surface of the package is further covered with the encapsulating material to cover the conductive layer 2. The top surface of the package is horizontally ground until the top surface of the conductive layer 2 is exposed. The encapsulating material is encapsulated multiple times to form an encapsulated whole, that is, the encapsulation layer 5 (such as Figure 23 shown).

[0058] Steps S12 to S18 are respectively the same as steps S4 to S11, except that two opposite surfaces in the length direction of the substrate 7 are processed separately, and finally the conductive layer 2, the side buffer layer 4, the metal layer 8, etc. are obtained.

[0059] For the packaging case where multiple substrates 7 are mounted on a carrier, a cutting step is finally included, in which vertical cutting is performed from the top surface of the package along the side of the conductive layer 2 until it is completely cut and separated into product units. Finally, multiple product units are obtained by peeling off from the carrier. The surface of the conductive layer 2 of each product unit is exposed, and the packaging layer 5 and the conductive layer 2 together constitute the outer envelope of the thermistor structure.

[0060] The exposed conductive layer 2 serves as an electrical connection medium for the internal and external circuits of the thermistor package structure. The exposed conductive layer 2 is surface-mounted on a PCB or other work area. The electrical orientation of the thermistor package structure is designed based on the actual product conditions and is a common electrical orientation and circuit connection in the field. Other different circuit connections and electrical orientations are also within the scope of protection of the present invention. A thin protective layer can be coated on the surface of the exposed conductive layer 2 by electroplating, chemical oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), etc. The protective layer can prevent oxidation, corrosion, and wear of the conductive layer 2. Common protective layers can be stable metal coatings, etc. The protective layer does not affect the structure and function of the conductive layer 2.

[0061] The conductive layer 2 can be a continuous structure that completely covers the side of the thermistor structure, or it can be a connected structure that does not completely cover the side of the thermistor (to reduce parasitic capacitance). Regardless of whether it is complete coverage or incomplete coverage, the conductive layer 2 is symmetrically arranged about the substrate 7 from top to bottom, and the entire structure is symmetrical, balancing stress and preventing stress concentration.

[0062] According to the present invention, after uniformly etching grooves 6 on the electrode, a top surface buffer layer 3 is filled, and side buffer layers 4 are filled on the sides of the conductive layer 2 and the substrate 7. The thermal expansion coefficient of the substrate 7 is similar to that of each buffer layer. When the substrate 7 thermally expands, each buffer layer expands and deforms synchronously with the substrate 7, and does not suppress the thermal expansion and deformation of the substrate 7 like the conductive layer 2 with a smaller thermal expansion coefficient, thereby maintaining the sensitive performance of the thermistor and ensuring the stability of the trip point position and resistance recovery characteristics; the entire structure is symmetrical, balancing the thermal stress distribution on the substrate 7, preventing stress concentration from causing cracking of each layer, and improving the long-term reliability of the structure; the encapsulation material is encapsulated to form the packaging layer 5 after filling the top surface buffer layer 3, and the initial compressive stress applied to the substrate 7 by the plastic sealing and curing of the encapsulation material is greatly reduced, thereby reducing the initial compressive stress on the substrate 7 and ensuring product performance. Example 2

[0063] Compared with Example 1, Example 2 differs in that the metal layer 8 is not electroplated in Example 2, but the side buffer layer 4 is filled entirely, that is, the side buffer layer 4 is set on the side of the substrate 7, and the side of the conductive layer 2 is separated from the side of the substrate 7 by only the side buffer layer 4. The other steps are the same.

[0064] The thermal expansion coefficient of the substrate 7 is similar to that of the side buffer layer 4. When the substrate 7 thermally expands, the side buffer layer 4 and the substrate 7 expand and deform synchronously, without the local expansion suppression of the metal layer 8. The sensitivity of the thermistor is more stable, ensuring that the trip point position and resistance recovery characteristics are more stable.

[0065] The buffer layers of the present invention expand and deform synchronously with the substrate 7, without suppressing the deformation of the substrate 7, maintaining the sensitive performance of the thermistor, ensuring the accuracy of the trip point and the stability of the resistance recovery characteristics; the entire structure is symmetrical, balancing the thermal stress distribution on the substrate 7, preventing stress concentration from causing cracking of the layers, and improving the long-term reliability of the structure; the initial compressive stress applied to the substrate 7 by the encapsulation material during plastic sealing and curing is greatly reduced, reducing the initial compressive stress on the substrate 7 and ensuring product performance.

[0066] The above-mentioned thermistor packaging process can obtain a thermistor packaging structure, which includes a substrate 7 with electrode layers 1 covering both surfaces along the length direction, a conductive layer 2 disposed outside the substrate 7 in the height direction, and further includes: The top buffer layer 3 is filled in the grooves 6 formed by etching the electrode layer 1. The grooves 6 etched on the electrode layers 1 on both surfaces of the substrate 7 in the length direction are symmetrical about the substrate 7. The grooves 6 are evenly distributed on the surface of the electrode layer 1. The bottom of the grooves 6 is in contact with or not in contact with the substrate 7. The side buffer layer 4 is filled between the side of the conductive layer 2 and the side of the substrate 7. The conductive layer 2 is electrically connected to the electrode layer 1. The side buffer layer 4 covers the side of the substrate 7, or the side buffer layer 4 covers the middle section of the side of the substrate 7. The upper and lower ends of the side buffer layer 4 are electroplated with a metal layer 8 connected to the electrode layer 1. The metal layer 8 and the side buffer layer 4 jointly cover the side of the substrate 7. The side of the conductive layer 2 is connected to the metal layer 8 and the side buffer layer 4, and the side of the conductive layer 2 is connected to the side of the side buffer layer 4. The top buffer layer 3 and the side buffer layer 4 have a thermal expansion coefficient that differs from that of the substrate 7 by no more than (1 to 3) × 10 -6 / ℃ insulation layer; The packaging layer 5 and the conductive layer 2 together form the outer envelope of the packaging structure.

[0067] In the thermistor packaging structure of the present invention, the buffer layers expand and deform synchronously with the substrate 7, without suppressing the deformation of the substrate 7, maintaining the sensitive performance of the thermistor, and ensuring the accuracy of the trip point and the stability of the resistance recovery characteristics; the entire structure is symmetrical, balancing the thermal stress distribution on the substrate 7, preventing stress concentration from causing cracking in the layers, and improving the long-term reliability of the structure; the initial compressive stress applied to the substrate 7 by the encapsulation material during plastic sealing and curing is greatly reduced, reducing the initial compressive stress on the substrate 7 and ensuring product performance.

[0068] It will be understood that the present invention is described by way of some embodiments, and it will be appreciated by those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of the present invention are intended to be protected by the present invention.

Claims

1. A thermistor packaging structure, comprising a substrate covered with electrode layers on both surfaces along the length direction, and a conductive layer disposed on the outer side of the substrate in the height direction, characterized in that: Also includes: a top surface buffer layer, filling the groove formed by etching the electrode layer; A side buffer layer is filled between the side of the conductive layer and the side of the substrate, and the conductive layer is electrically connected to the electrode layer; The packaging layer and the conductive layer together form the outer envelope of the packaging structure.

2. The thermistor packaging structure according to claim 1, wherein: The grooves etched on the electrode layers on both surfaces in the length direction of the substrate are symmetrical about the substrate.

3. The thermistor packaging structure according to claim 2, wherein: The grooves are evenly distributed on the surface of the electrode layer, and the bottoms of the grooves are in contact with or not in contact with the substrate.

4. The thermistor packaging structure according to claim 1, wherein: The side buffer layer covers the side surface of the substrate, and the side surface of the conductive layer is connected to the side surface of the side buffer layer.

5. The thermistor packaging structure according to claim 1, wherein: The side buffer layer covers the middle section of the side of the substrate. The upper and lower ends of the side buffer layer are electroplated with metal layers connected to the electrode layer. The metal layer and the side buffer layer jointly cover the side of the substrate. The side of the conductive layer is connected to the metal layer and the side buffer layer.

6. The thermistor packaging structure according to claim 1, wherein: The top buffer layer and the side buffer layer have a thermal expansion coefficient that is no more than (1 to 3) × 10 -6 / ℃ insulating rubber layer.

7. A thermistor packaging process, characterized in that: The following steps are involved: Electroplating electrode layer: covering the two surfaces of the substrate in the length direction with electrode layers, encapsulating the substrate and the electrode layer, with the surface of the electrode layer exposed; Processing of both sides of the encapsulation material: vertically etching the electrode layer to form a groove, and filling the groove with the top surface buffer layer; vertically etching the encapsulation material to expose the side surface of the substrate and filling the side buffer layer; The encapsulation material is vertically etched to expose the side of the side buffer layer, and a conductive layer connected to the electrode layer is electroplated. The encapsulation material is continued to be covered and the top surface of the conductive layer is exposed to form a packaging layer. The packaging layer and the conductive layer together constitute the peripheral encapsulation.

8. The thermistor packaging process according to claim 7, characterized in that: In the step of electroplating the electrode layer, the grooves etched on the electrode layers on both surfaces in the length direction of the substrate are symmetrical about the upper and lower sides of the substrate.

9. The thermistor packaging process according to claim 8, characterized in that: In the step of electroplating the electrode layer, the grooves are evenly distributed on the surface of the electrode layer, and the bottoms of the grooves are in contact with or not in contact with the substrate.

10. The thermistor packaging process according to claim 7, characterized in that: In the step of processing both sides of the encapsulating material, the side buffer layer covers the side surface of the substrate, and the side surface of the conductive layer is connected to the side surface of the side buffer layer.

11. The thermistor packaging process according to claim 7, characterized in that: In the step of processing both sides of the encapsulating material, the side buffer layer covers the middle section of the side surface of the substrate, the upper and lower ends of the side buffer layer are electroplated with a metal layer connected to the electrode layer, the metal layer and the side buffer layer jointly cover the side surface of the substrate, and the side surface of the conductive layer is connected to the metal layer and the side buffer layer.

12. The thermistor packaging process according to claim 10, characterized in that: In the step of processing both sides of the encapsulation material, the top buffer layer and the side buffer layer have a thermal expansion coefficient that differs from that of the substrate by no more than (1-3)×10 -6 / ℃ insulating rubber layer.

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