Package structure and forming method thereof

Abstract

A package structure and a method of forming the same are provided. The method includes placing a wafer-containing structure on a substrate and forming a thermally conductive layer on the wafer-containing structure. The method also includes placing a heat sink over the wafer-containing structure and the thermally conductive layer. The metallization structure is embedded in the heat dissipation cover, and the metallization structure faces the heat conduction layer. The method further includes warming and pressing the thermally conductive cap toward the wafer-containing structure to convert a portion or all of the metallization structure and a portion or all of the thermally conductive layer into an intermetallic compound material.

Description

Technical Field

[0001] The embodiments of the present invention relate to a packaging structure, and in particular to a heat dissipation structure thereof. Background Art

[0002] The semiconductor integrated circuit industry has experienced rapid growth. Continuous advancements in semiconductor manufacturing processes have resulted in semiconductor devices with finer structures and / or higher levels of integration. Functional density (i.e., the number of interconnect devices per unit chip area) generally increases as feature size (i.e., the smallest component that can be produced by the fabrication process) decreases. This process size reduction generally increases production capacity and reduces associated costs.

[0003] The packaging structure not only protects the semiconductor device from environmental contamination, but also provides a connection interface for the semiconductor device packaged therein. Smaller packaging structures that occupy less space and have a smaller height have been developed to package semiconductor devices.

[0004] New packaging technologies have been developed to further improve the density and functionality of semiconductor dies. Newer packaging technologies for semiconductor dies present manufacturing challenges. For example, heat dissipation from the package structure becomes more important. Summary of the Invention

[0005] In some embodiments, a method for forming a package structure is provided. The method includes placing a chip-containing structure on a substrate and forming a thermally conductive layer on the chip-containing structure. The method also includes placing a heat dissipation cover over the chip-containing structure and the thermally conductive layer. A metallized structure is embedded in the heat dissipation cover, with the metallized structure facing the thermally conductive layer. The method also includes heating and pressing the thermally conductive cover against the chip-containing structure to convert at least a portion of the metallized structure and at least a portion of the thermally conductive layer into an intermetallic compound material.

[0006] In some embodiments, a method for forming a package structure is provided. The method includes placing a logic chip structure and a memory chip structure on a substrate, and forming a metal adhesive layer on the logic chip structure and the memory chip structure. The method also includes forming an indium layer on the metal adhesive layer and placing a heat sink cover on the indium layer. A patterned metallization structure is embedded in the heat sink cover and directly contacts the indium layer. The method also includes heating and pressing the heat sink cover and the substrate together, so that at least a portion of the patterned metallization structure and at least a portion of the indium layer together form an indium-containing alloy.

[0007] In some embodiments, a packaging structure is provided. The packaging structure includes a substrate and a heat dissipation cover positioned on the substrate. The packaging structure also includes a chip-containing structure positioned between the substrate and the heat dissipation cover. The packaging structure also includes a thermally conductive structure positioned between the chip-containing structure and the heat dissipation cover. The thermally conductive structure includes an intermetallic compound material comprising a plurality of first metallization elements and a plurality of second metallization elements. The intermetallic compound material extends into the heat dissipation cover. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1A to 1G 1 is a cross-sectional view of various stages of a process for forming a portion of a package structure in some embodiments.

[0009] Figure 2 is a plan view of an intermediate stage in a process for forming a portion of a package structure in some embodiments.

[0010] Figure 3 is a plan view of an intermediate stage in a process for forming a portion of a package structure in some embodiments.

[0011] Figures 4A to 4C 1 is a cross-sectional view of various stages of a process for forming a portion of a package structure in some embodiments.

[0012] Figure 5A and Figure 5B 1 is a cross-sectional view of various stages of a process for forming a portion of a package structure in some embodiments.

[0013] Figure 6A and Figure 6B 1 is a cross-sectional view of various stages of a process for forming a portion of a package structure in some embodiments.

[0014] Figure 7A and Figure 7B 1 is a cross-sectional view of various stages of a process for forming a portion of a package structure in some embodiments.

[0015] Figure 8 is a plan view of an intermediate stage in a process for forming a portion of a package structure in some embodiments.

[0016] Figure 9A is a cross-sectional view of a portion of a package structure in some embodiments.

[0017] Figure 9B is a cross-sectional view of a portion of a package structure in some embodiments.

[0018] Figure 10A and Figure 10B is a plan view of various stages of a process for forming a portion of a package structure in some embodiments.

[0019] Figures 11A to 11C 1 is a cross-sectional view of various stages of a process for forming a portion of a package structure in some embodiments.

[0020] Figure 12A and Figure 12B is a plan view of various stages of a process for forming a portion of a package structure in some embodiments.

[0021] 13A to 13C1 is a cross-sectional view of various stages of a process for forming a portion of a package structure in some embodiments.

[0022] Figure 14A and Figure 14B is a plan view of various stages of a process for forming a portion of a package structure in some embodiments.

[0023] Figures 15A to 15C 1 is a cross-sectional view of various stages of a process for forming a portion of a package structure in some embodiments.

[0024] Figure 16A is a plan view of an intermediate stage in a process for forming a portion of a package structure in some embodiments.

[0025] Figure 16B is a plan view of an intermediate stage in a process for forming a portion of a package structure in some embodiments.

[0026] The description of the accompanying drawings is as follows:

[0027] 10: Chip packaging

[0028] 20: Substrate

[0029] 100A, 100B: Chip structure

[0030] 102: Intermediate substrate

[0031] 104: Joint structure

[0032] 106: Through-substrate via

[0033] 110: Protective layer

[0034] 112,120,210: Joint structure

[0035] 114: Bottom fill structure

[0036] 116: Backside metallization layer

[0037] 118: Surface embedded device

[0038] 126: Thermal conductive layer

[0039] 132: Adhesion structure

[0040] 134: Medial adhesive structure

[0041] 136: Heat dissipation cover

[0042] 150, 150A, 150B, 550, 650, 750: Metallized structure

[0043] 160,160A,160B,560,660,760,960: alloy structure

[0044] 202: Insulation layer

[0045] 204: Conductive structure

[0046] 402: Groove

[0047] 702,1302: Depression DETAILED DESCRIPTION

[0048] The following detailed description is accompanied by accompanying drawings to facilitate an understanding of various aspects of the present invention. It should be noted that the various structures are for illustrative purposes only and are not drawn to scale, as is common practice in the industry. In practice, the dimensions of the various structures may be arbitrarily increased or decreased for clarity.

[0049] The following provides different embodiments or examples for implementing different structures of the embodiments of the present invention. The specific components and arrangements are provided to simplify the present disclosure and are not intended to limit the present invention. For example, the description of forming a first component on a second component includes the two being in direct contact, or the two being separated by additional components rather than in direct contact. The same reference numerals may be repeatedly used in various embodiments of the present invention for simplicity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same corresponding relationship.

[0050] Additionally, spatially relative terms such as "below," "beneath," "lower," "above," "upper," or similar terms are used to describe the relationship of one element or structure to another element or structure in the drawings. These spatially relative terms encompass various orientations of the device in use or operation, as well as the orientation depicted in the drawings. When the device is rotated 90 degrees or otherwise, the spatially relative adjectives used will be interpreted based on that orientation.

[0051] Some embodiments of the present invention are described herein. Additional steps may be provided before, during, and / or after the stages described in these embodiments. Different embodiments may replace or omit some of the stages described. Additional structures may be added to the semiconductor device structure and / or the packaging structure. Different embodiments may replace or omit some of the structures described below. Although some embodiments describe steps performed in a specific order, these steps may be performed in another logical order.

[0052] Embodiments of the present invention may be related to packaging structures such as three-dimensional packages, three-dimensional integrated circuit devices, and 2.5-dimensional packages. The package structures formed by the embodiments of the present invention include a substrate supporting one or more dies or packages and a protective element (e.g., a protective cover) adjacent to the die or package. The protective element may also serve as a warpage control element and / or a heat sink.

[0053] Other structures and processes may also be included. For example, test structures may be included to facilitate verification testing of 3D packages, 3D integrated circuit devices, and / or 2.5D packages. For example, the test structures may include test pads formed in a redistribution layer or on a substrate to facilitate testing of 3D packages or 3D integrated circuits using carbon pins, carbon pin cards, and / or the like. Verification testing may be performed on intermediate structures as well as final structures. Furthermore, the structures and methods described herein may be combined with testing methods for intermediate verification of known good die to increase yield and reduce costs.

[0054] Figures 1A to 1G 1 is a cross-sectional view of various stages of a process for forming a portion of a package structure in some embodiments. Figure 1A In some embodiments shown, chip package 10 is positioned on substrate 20. In some embodiments, chip package 10 is bonded to substrate 20 via a plurality of bonding structures 112. Bonding structures 112 may be composed of or include a solder material. The solder material may be a tin-containing material. The tin-containing material may further include copper, silver, gold, aluminum, lead, one or more other suitable materials, or combinations thereof. In some other embodiments, the solder material is lead-free.

[0055] like Figure 1A In some embodiments shown, an underfill structure 114 is formed to laterally surround and protect the bonding structure 112. A portion of the underfill structure 114 is located between the substrate 20 and the bottom of the chip package 10. A second portion of the underfill structure 114 may extend upward along the sidewalls of the chip package 10. The underfill structure 114 may be composed of or include an epoxy-based resin with a filler dispersed therein. The filler may include fibers (e.g., silica fibers and / or carbon fibers), particles (e.g., silica particles and / or carbon particles), or a combination thereof.

[0056] In some embodiments, an underfill liquid is dispensed onto the substrate 20 along one side of the chip package 10. The underfill liquid may be composed of or include a polymer material, such as an epoxy-based resin, and a filler dispersed therein. The filler may include fibers (such as silica fibers and / or carbon fibers), particles (such as silica particles and / or carbon particles), or a combination thereof. The underfill liquid may be drawn into the space between the substrate 20 and the chip package 10 by capillary forces to surround the bonding structure 112. A thermal step may then be employed to cure the underfill liquid. In this manner, an underfill structure 114 may be formed.

[0057] In some embodiments, the chip package 10 includes multiple chip structures (or chip-containing structures). Figure 1AAs shown, the chip package 10 includes chip structures 100A and 100B. The chip structures 100A and 100B can each be a single semiconductor die and / or an integrated chip system. For an integrated chip system, multiple semiconductor dies (or small chips) are stacked and bonded together to form an electrical connection between these semiconductor dies (or small chips). In some embodiments, the semiconductor die is a chip system chip containing multiple functions. In some embodiments, one or more chip structures 100A and 100B include high-frequency devices, optoelectronic devices, photonic devices, logic devices, memory devices, one or more other suitable devices, or a combination of the above. In some embodiments, the chip structure 100B includes multiple memory devices and serves as a memory chip structure. In some embodiments, the chip structure 100B serves as a high-bandwidth memory. In some embodiments, the chip structure 100A includes multiple logic devices and serves as a logic chip structure.

[0058] like Figure 1A In some embodiments shown, chip package 10 includes an interposer substrate 102. In some embodiments, chip structures 100A and 100B are bonded to interposer substrate 102 via a plurality of bonding structures 104. Bonding structures 104 may each include a conductive pillar (e.g., a copper pillar) and a tin-containing solder bump. An underfill structure may be formed on interposer substrate 102 to laterally surround and protect bonding structures 104. The materials and formation methods of the underfill structure may be similar to those of underfill structure 114. In some other embodiments, no underfill structure is formed.

[0059] In some embodiments, a protective layer 110 is formed on the interposer substrate 102 to seal and protect the wafer structures 100A and 100B. The protective layer 110 may be composed of or include a molding material. The protective layer 110 may be composed of or include an epoxy-based resin with a filler dispersed therein. The filler may include insulating fibers, insulating particles, one or more other suitable elements, or a combination thereof. In some embodiments, the average size of the filler in the protective layer 110 is larger than the average size of the filler in the underfill structure 114. In some embodiments, the weight percent of the filler in the protective layer 110 is greater than the weight percent of the filler in the underfill structure 114.

[0060] In some embodiments, interposer substrate 102 is a semiconductor substrate (e.g., a silicon substrate) having a plurality of through-substrate vias (TSVs) 106 formed therein. TSVs 106 can provide electrical connections between elements on interposer substrate 102 (e.g., wafer structures 100A and 100B) and elements below interposer substrate 102 (e.g., bonding structure 112).

[0061] However, the embodiments of the present invention are not limited thereto. Numerous variations and / or modifications are possible. In some other embodiments, the interposer substrate 102 is a redistribution structure comprising a polymer-based substrate. The polymer-based substrate includes a plurality of conductive structures formed therein. In some other embodiments, the interposer substrate 102 includes a polymer-based substrate and an interconnect die embedded in the polymer-based substrate (or the polymer-based substrate surrounds the interconnect die).

[0062] like Figure 1A In some embodiments shown, a backside metallization layer 116 is formed on the surfaces of the protective layer 110 and the wafer structures 100A and 100B. The backside metallization layer 116 may serve as an adhesive layer, which helps improve the adhesion between a subsequently placed thermally conductive layer and the wafer package 10. The backside metallization layer 116 may be composed of or include aluminum, titanium, gold, nickel, copper, palladium, vanadium, a nickel-vanadium alloy, another suitable material, or a combination thereof.

[0063] like Figure 1A In some embodiments shown, one or more surface embedded devices 118 are located on the substrate 20. In some embodiments, the surface embedded device 118 is bonded to the substrate 20 via a bonding structure 120. Figure 1A As shown, the surface-embedded device 118 is laterally separated from the chip package 10 .

[0064] Each of the surface-embedded devices 118 may include one or more passive devices such as resistors, capacitors, inductors, other suitable devices, or combinations thereof. In some other embodiments, the surface-embedded devices 118 include one or more active devices such as transistors, diodes, other suitable devices, or combinations thereof. In some other embodiments, one or more surface-embedded devices 118 include a combination of passive and active devices.

[0065] In some embodiments, the substrate 20 is a circuit board, which includes a plurality of insulating layers 202 and a plurality of conductive structures 204 surrounded by the insulating layers 202. The conductive structures 204 may include conductive lines and conductive vias.

[0066] In some embodiments, a flux is provided on the backside metallization layer 116. The flux material facilitates the subsequent placement of the thermally conductive layer. In some embodiments, a flux spraying step is performed using a flux dispenser to provide the flux material on the backside metallization layer 116. The flux material can include one or more rosins, one or more acids, one or more bases, one or more fluxes, another suitable material, or a combination thereof.

[0067] like Figure 1BIn some embodiments shown, a thermally conductive layer 126 is disposed on the chip package 10. In some embodiments, the thermally conductive layer 126 may be composed of or include a metal material. In some embodiments, the thermally conductive layer 126 may be composed of or include a metal material with a low melting point and low stress. The thermally conductive layer 126 may have suitable fluidity when heated to near its low melting point.

[0068] In some embodiments, the melting point of the thermally conductive layer 126 is less than about 160° C. In some embodiments, the melting point of the thermally conductive layer 126 may be between about 50° C. and about 160° C. The thermally conductive layer 126 may be an indium-based material, a gallium-based material, another suitable material, or a combination thereof. In some embodiments, the thermally conductive layer 126 is an indium layer.

[0069] like Figure 1C In some embodiments shown, one or more adhesive structures 132 are formed on substrate 20. In some embodiments, an adhesive layer dispenser is used to dispense adhesive material onto predetermined areas on substrate 20. The adhesive material dispensed onto the predetermined areas forms adhesive structures 132. Adhesive structures 132 can be composed of an epoxy-based adhesive, a silicone-based adhesive, another suitable adhesive, or a combination thereof. In some embodiments, adhesive structures 132 laterally surround surface-embedded device 118 and chip package 10.

[0070] like Figure 1C In some embodiments shown, an inner adhesive structure 134 is formed on substrate 20. Similar to the method for forming adhesive structure 132, an adhesive layer provider can be used to assist in forming inner adhesive structure 134. In some embodiments, inner adhesive structure 134 laterally surrounds chip package 10. In some embodiments, inner adhesive structure 134 is located between chip package 10 and surface-embedded device 118.

[0071] In some embodiments, the inner adhesive structure 134 has a lower portion and an upper portion. In some embodiments, an adhesive layer provider can be used to separately form the upper and lower portions of the inner adhesive structure 134. The lower portion and the upper portion formed after the lower portion is formed can together form the inner adhesive structure 134. In some embodiments, the inner adhesive structure 134 laterally surrounds the chip package 10. In some embodiments, the inner adhesive structure 134 laterally surrounds the thermally conductive layer 126 disposed on the chip package 10.

[0072] like Figure 1D In some embodiments shown, the heat dissipation cover 136 is located on the chip package 10 and the substrate 20. In some embodiments, the metallization structure 150 is formed on the heat dissipation cover 136. In some embodiments, the metallization structure 150 is a patterned metallization structure embedded in the body of the heat dissipation cover 136. Figure 1DIn some embodiments shown, the metallization structure 150 faces the thermally conductive layer 126 .

[0073] The main body of the heat sink cover 136 may be composed of or include copper, steel, nickel, aluminum, another suitable material, or a combination thereof. The metallization structure 150 may be composed of or include gold, silver, tin, zinc, another suitable material, or a combination thereof. In some embodiments, one or more recesses having a desired profile and distribution are formed in the main body of the heat sink cover 136. A metal layer is then deposited to fill the recesses. The portion of the metal layer outside the recesses may then be removed. The remaining portion of the metal layer thus forms the metallization structure 150.

[0074] like Figure 1D In some embodiments shown, the heat dissipation cover 136 includes one or more grooves 402. In some embodiments, after the heat dissipation cover 136 is bonded to the substrate 20, a portion of the thermally conductive layer 126 may extend into the grooves 402. The grooves 402 may contain a portion of the thermally conductive layer 126 and help maintain the thermally conductive layer 126 in a predetermined area. This prevents the thermally conductive layer 126 from contacting and negatively impacting other nearby units (such as the surface-mounted device 118).

[0075] However, the present invention is not limited thereto. The present invention may have many variations and / or adjustments. In some other embodiments, the groove 402 is not formed.

[0076] Figure 2 is a plan view of an intermediate stage of a process for forming a portion of a package structure in some embodiments. Figure 2 A plan view of a portion of the heat spreader cover 136 proximate the metallization structure 150 is shown. Figure 2 The grooves 402 are not shown for simplicity and clarity of the drawing. In some embodiments, the metallization structure 150 has a rectangular or square profile. In some embodiments, the metallization structure 150 extends over both side edges of the wafer structure 100A and both side edges of the wafer structure 100B.

[0077] like Figure 1E In some embodiments shown, the heat dissipation cover 136 is lowered. In this way, the metallization structure 150 directly contacts the thermal conductive layer 126. Figure 1E As shown, an interface can be formed between the metallization structure and the thermal conductive layer 126. Figure 1E In some embodiments shown, the heat dissipation cover 136 directly contacts the inner adhesive structure 134 .

[0078] Then, the heat is raised and the heat dissipation cover 136 is pressed against the heat conducting layer 126 and the inner adhesive structure 134. In this way, some embodiments form Figure 1FIn some embodiments, a thermal clamping process may be used to bond the heat dissipation cover 136 to the substrate 20 supporting the chip package 10. The elevated temperature may be from about 130°C to about 200°C. Figure 1F As shown, the adhesive structure 132 and the inner adhesive structure 134 help adhere the heat dissipation cover 136 to the substrate 20 .

[0079] like Figure 1F In some embodiments shown, the metallization structure 150 and the thermally conductive layer 126 are converted into an alloy structure 160 under hot pressing. The alloy structure 160 can serve as a thermally conductive structure and a bonding structure, which can provide strong adhesion between the chip package 10 and the heat dissipation cover 136. The alloy structure 160 can include an intermetallic compound material, a substitution alloy material, an interstitial alloy material, a two-phase alloy material, another suitable alloy material, or a combination thereof. Figure 1F In some embodiments shown, the alloy structure 160 extends into the heat dissipation cover 136. In some embodiments, the topmost surface of the alloy structure 160 is higher than the interface between the heat dissipation cover 136 and the inner adhesive structure 134.

[0080] The alloy structure 160 may be composed of or include a compound material including gold-indium, silver-indium, tin-indium, zinc-indium, another suitable material, or a combination thereof. In some embodiments, the alloy structure 160 includes an intermetallic compound material including a first metallization element (e.g., indium) from the thermally conductive layer 126 and a second metallization element (e.g., gold, silver, tin, or zinc) from the metallization structure 150.

[0081] In some embodiments, the metallization structure 150 and the thermally conductive layer 126 are heated for a long period of time to ensure a complete reaction between the metallization structure 150 and the thermally conductive layer 126. In some embodiments, the metallization structure 150 and the thermally conductive layer 126 are heated to approximately 200°C for more than 4 hours. In this way, all of the metallization structure 150 and all of the thermally conductive layer 126 are converted into the alloy structure 160.

[0082] However, the present invention is not limited thereto. The present invention may have many variations and / or modifications. In some other embodiments, the metallization structure 150 and the thermally conductive layer 126 are not heated for a long period of time. Thus, the metallization structure 150 and the thermally conductive layer 126 are partially converted into the alloy structure 160.

[0083] In some embodiments, a portion of the thermally conductive layer 126 and a portion of the metallization structure 150 are converted into an alloy structure 160. In some embodiments, a portion of the thermally conductive layer 126 and a portion of the metallization structure 150 near the initial interface between the thermally conductive layer 126 and the metallization structure 150 are converted into the alloy structure 160. In some embodiments, the alloy structure 160 is formed between the remaining portion of the thermally conductive layer 126 and the remaining portion of the metallization structure 150. In some other embodiments, a portion of the thermally conductive layer 126 and all of the metallization structure 150 together form the alloy structure 160. In some embodiments, the alloy structure 160 is formed between the remaining portion of the thermally conductive layer 126 and the heat dissipation cover 136.

[0084] In some embodiments, the metallization structure 150 and the thermally conductive layer 126 together form an alloy structure 160, significantly improving the adhesion between the heat dissipation lid 136 and the chip package 10. The alloy structure 160 prevents the thermally conductive layer 126 from flowing away from the chip package 10 during the thermal clamping process. Due to the good interface between the chip package 10 and the heat dissipation lid 136, heat generated by the chip structures 100A and 100B can be effectively dissipated through the heat dissipation lid 136. This significantly improves the performance and reliability of the package structure.

[0085] Afterwards Figure 1G In some embodiments shown, a plurality of bonding structures 210 are formed on the bottom of the substrate 20. The bonding structures 210 may include solder bumps containing tin. Thus, the package structure can be bonded to another unit via the bonding structures 210.

[0086] The embodiments of the present invention may have many variations and / or modifications. For example, the pattern of the metallization structure 150 may be varied as needed.

[0087] Figures 4A to 4C 1 is a cross-sectional view of various stages of a process for forming a portion of a package structure in some embodiments. Figure 4A As shown, the formation Figure 1D The heat dissipation cover 136 is located on the chip package 10 and is ready to be bonded to the substrate 20 and the chip package 10 .

[0088] Figure 3 is a plan view of an intermediate stage of a process for forming a portion of a package structure in some embodiments. Figure 3 yes Figure 4A A plan view of a portion of the structure is shown. Figure 3 is a plan view of a portion of the heat dissipation cover 136 proximate the metallization structure 150 . Figure 3 The groove 402 is not shown for simplicity and clarity of the drawing. Figure 3 In some embodiments shown, the metallization structure 150 is a ring structure. Figure 3 and Figure 4A In some embodiments shown, the metallization structure 150 extends beyond both side edges of the wafer structure 100A and both side edges of the wafer structure 100B.

[0089] Figure 4B Some of the embodiments shown are Figure 1E Similar to the embodiment shown, the heat dissipation cover 136 is lowered. In this way, the metallization structure 150 directly contacts the thermal conductive layer 126. In some embodiments, the heat dissipation cover 136 also directly contacts the thermal conductive layer 126. Figure 4B In some embodiments shown, the heat dissipation cover 136 directly contacts the inner adhesive structure 134 .

[0090] Afterwards Figure 1F Similar to the embodiment shown, Figure 4C Some embodiments shown heat up and press the heat dissipation cover 136 against the heat conducting layer 126 and the inner adhesive structure 134. For example, a thermal clamping process is used. Figure 4C In some embodiments shown, the metallization structure 150 and a portion of the thermally conductive layer 126 are converted into an alloy structure 160 under hot pressing. Figure 4C In some embodiments shown, the alloy structure 160 extends into the heat dissipation cover 136. In some embodiments, the topmost surface of the alloy structure 160 is higher than the interface between the heat dissipation cover 136 and the inner adhesive structure 134. In some embodiments, the topmost surface of the alloy structure 160 is higher than the topmost surface of the remaining portion of the thermally conductive layer 126.

[0091] In some embodiments, the metallization structure 150 and the thermally conductive layer 126 are heated for a long period of time to ensure a complete reaction between the metallization structure 150 and the portion of the thermally conductive layer 126 directly beneath the metallization structure 150. In some embodiments, the metallization structure 150 and the thermally conductive layer 126 are heated to approximately 200° C. for more than four hours. As a result, all of the metallization structure 150 and all of the portion of the thermally conductive layer 126 directly beneath the metallization structure 150 are converted into the alloy structure 160. In some embodiments, the thermal conductivity of the remaining portion of the thermally conductive layer 126 is higher than the thermal conductivity of the alloy structure 160. In some embodiments, the melting point of the thermally conductive layer 126 is lower than the melting point of the alloy structure 160. In some embodiments, the bond strength of the alloy structure 160 between the heat dissipation lid 136 and the chip package 10 is greater than the bond strength of the remaining portion of the thermally conductive layer 126 between the heat dissipation lid 136 and the chip package 10.

[0092] In some embodiments, the alloy structure 160 laterally surrounds the remaining portion of the thermally conductive layer 126. The alloy structure 160 can prevent the remaining portion of the thermally conductive layer 126 directly beneath the wafer structures 100A and 100B from flowing away during the thermal clamping process, thereby improving heat dissipation.

[0093] However, the present invention is not limited to this embodiment. Numerous variations and / or modifications are possible. In some other embodiments, the metallization structure 150 and the thermally conductive layer 126 are not heated for an extended period of time. As a result, the metallization structure 150 and the portion of the thermally conductive layer 126 directly below the metallization structure 150 are partially converted into the alloy structure 160.

[0094] In some embodiments, a portion of the thermally conductive layer 126 directly above the metallization structure 150 and a portion of the metallization structure 150 are converted into an alloy structure 160. In some embodiments, a portion of the thermally conductive layer 126 and a portion of the metallization structure 150 near the initial interface between the thermally conductive layer 126 and the metallization structure 150 are converted into an alloy structure 160. In some embodiments, the alloy structure 160 is formed between the remaining portion of the thermally conductive layer 126 and the remaining portion of the metallization structure 150. In some other embodiments, a portion of the thermally conductive layer 126 directly below the metallization structure 150 and all of the metallization structure 150 together form the alloy structure 160. In some embodiments, the alloy structure 160 is formed between the remaining portion of the thermally conductive layer 126 and the heat dissipation cover 136.

[0095] In some embodiments, the metallization structure 150 and the portion of the thermally conductive layer 126 located directly beneath the metallization structure 150 together form an alloy structure 160, significantly improving the adhesion between the heat dissipation lid 136 and the chip package 10. Because the alloy structure 160 laterally surrounds the remaining portion of the thermally conductive layer 126, it prevents the flowable thermally conductive layer 126 from flowing away from the chip package 10 during the thermal clamping process. Due to the good interface between the chip package 10 and the heat dissipation lid 136, heat generated by the chip structures 100A and 100B can be effectively dissipated through the heat dissipation lid 136. This significantly improves the performance and reliability of the package structure.

[0096] Afterwards Figure 1G Similar to the embodiment shown, Figure 4C In some embodiments shown, a plurality of bonding structures 210 are formed on the bottom of the substrate 20. The bonding structures 210 may include solder bumps containing tin. Thus, the package structure can be bonded to another unit via the bonding structures 210.

[0097] In some embodiments, the metallization structure 150 is a single piece. However, the present invention is not limited thereto. The present invention can have many variations and / or modifications. In some other embodiments, the metallization structure includes a plurality of metallization island structures separated from each other.

[0098] Figure 5A and Figure 5B 1 is a cross-sectional view of various stages of a process for forming a portion of a package structure in some embodiments. Figure 5A As shown, the formation Figure 1D The heat dissipation cover 136 is located on the chip package 10 and is ready to be bonded to the substrate 20 and the chip package 10. In some embodiments, a plurality of metallization structures 550 are embedded in the heat dissipation cover 136. Figure 5A As shown, the metallization structures 550 may be metallization island structures separated from each other. In some embodiments, each of the metallization structures 550 has a buried portion surrounded by the heat dissipation cover 136 and a protruding portion extending along the surface of the heat dissipation cover 136 facing the wafer package 10. In some embodiments, each of the metallization structures 550 has a protruding lower surface.

[0099] Figure 8 is a plan view of an intermediate stage of a process for forming a portion of a package structure in some embodiments. Figure 8 yes Figure 5A A plan view of a portion of the structure is shown. Figure 8 is a plan view of a portion of the heat dissipation cover 136 proximate the metallization structure 550 . Figure 8 The groove 402 is not shown for simplicity and clarity of the drawing. Figure 3 In some embodiments shown, the metallization structure 150 is a ring structure.

[0100] Afterwards Figure 1E and Figure 1F Similar to the embodiment shown, Figure 5B In some embodiments shown, the heat dissipation cover 136 is heated and pressed against the thermally conductive layer 126 and the inner adhesive structure 134. For example, a thermal clamping process is performed. In some embodiments, the metallized structure 550 under thermal compression penetrates the thermally conductive layer 126.

[0101] Afterwards Figure 5B As shown, the metallization structure 550 and the heat conducting layer 126 adjacent to the metallization structure 550 are transformed into a plurality of alloy structures 560. Figure 5B In some embodiments shown, the alloy structure 560 extends into the heat dissipation cover 136. In some embodiments, the topmost surface of the alloy structure 560 is higher than the interface between the heat dissipation cover 136 and the inner adhesive structure 134. In some embodiments, the topmost surface of the alloy structure 560 is higher than the topmost surface of the remaining portion of the thermally conductive layer 126.

[0102] In some embodiments, the metallization structure 550 and the thermally conductive layer 126 are heated for a long period of time to ensure that all of the metallization structure 550 is converted into the alloy structure 560. In some embodiments, the metallization structure 550 and the thermally conductive layer 126 are heated to approximately 200° C. for more than 4 hours. In this way, all of the metallization structure 550 is converted into the alloy structure 560.

[0103] In some embodiments, the thermal conductivity of the remaining portion of the thermal conductive layer 126 is greater than the thermal conductivity of the alloy structure 560. In some embodiments, the bonding strength of the alloy structure 560 between the heat dissipation cover 136 and the chip package 10 is greater than the bonding strength of the remaining portion of the thermal conductive layer 126 between the heat dissipation cover 136 and the chip package 10.

[0104] However, the present invention is not limited thereto. Numerous variations and / or modifications are possible. In some other embodiments, the metallization structure 550 is not heated for an extended period of time. As a result, the metallization structure is partially converted into the alloy structure 560. In some embodiments, one portion of the alloy structure 560 is located between the remaining portion of the thermally conductive layer 126 and the remaining portion of one portion of the metallization structure 550.

[0105] In some embodiments, the alloy structure 560 can significantly improve the adhesion between the heat dissipation lid 136 and the chip package 10. Because the alloy structure 560 is dispersed throughout the thermally conductive layer 126, the flow of the thermally conductive layer 126 away from the chip package 10 during the thermal clamping process can be prevented. Due to the good interface between the chip package 10 and the heat dissipation lid 136, heat generated by the chip structures 100A and 100B can be effectively dissipated through the heat dissipation lid 136. This significantly improves the performance and reliability of the package structure.

[0106] Afterwards Figure 1G Similar to the embodiment shown, Figure 5B In some embodiments shown, a plurality of bonding structures 210 are formed on the bottom of the substrate 20. The bonding structures 210 may include solder bumps containing tin. Thus, the package structure can be bonded to another unit via the bonding structures 210.

[0107] Many variations and / or modifications are possible in the embodiments of the present invention. Figure 6A and Figure 6B 1 is a cross-sectional view of various stages of a process for forming a portion of a package structure in some embodiments. Figure 6A As shown, the formation Figure 5A Some embodiments are similar to the structure shown in FIG. Figure 5A Similar to the embodiment shown, a plurality of metallization structures 650 are embedded in the heat dissipation cover 136. In some embodiments, each of the metallization structures 650 has a concave lower surface. A plurality of recesses are formed in the concave lower surface of the metallization structure 650.

[0108] Afterwards Figure 1E and Figure 1F Similar to the embodiment, Figure 6BSome embodiments heat up and press the heat dissipation cover 136 against the thermal conductive layer 126 and the inner adhesive structure 134. During the thermal clamping process, a portion of the thermal conductive layer 126 may extend into the recess formed in the concave lower surface of the metallized structure 650. In this way, after the heat dissipation cover 136 is pressed against the substrate 20, the metallized structure 650 directly contacts the thermal conductive layer 126. Figure 6B As shown, the metallization structure 650 and the portion of the thermal conductive layer 126 adjacent to the metallization structure 650 are transformed into a plurality of alloy structures 660 during the thermal clamping process.

[0109] In some embodiments, the metallization structure 650 and the thermally conductive layer 126 are heated for a long period of time to ensure that all of the metallization structure 650 is converted into the alloy structure 660. In some embodiments, the metallization structure 650 and the thermally conductive layer 126 are heated to approximately 200° C. for more than 4 hours. In this way, all of the metallization structure 650 is converted into the alloy structure 660.

[0110] However, the present invention is not limited to this embodiment. Numerous variations and / or modifications are possible. In some other embodiments, the metallization structure 650 is not heated for an extended period of time. As a result, the metallization structure 650 is partially converted into the alloy structure 660. In some embodiments, one portion of the alloy structure 660 is located between the remaining portion of the thermally conductive layer 126 and the remaining portion of one portion of the metallization structure 650.

[0111] Afterwards Figure 1G Similar to the embodiment shown, Figure 6B In some embodiments shown, a plurality of bonding structures 210 are formed on the bottom of the substrate 20. The bonding structures 210 may include solder bumps containing tin. Thus, the package structure can be bonded to another unit via the bonding structures 210.

[0112] Many variations and / or modifications are possible in the embodiments of the present invention. Figure 7A and Figure 7B 1 is a cross-sectional view of various stages of a process for forming a portion of a package structure in some embodiments. Figure 7A As shown, the formation Figure 5A Some embodiments are similar to the structure shown in FIG. Figure 5A Similar to the embodiment shown, a plurality of metallization structures 750 are formed on the heat dissipation cover 136. In some embodiments, each of the metallization structures 750 has a protruding lower surface. Figure 7A As shown, a plurality of recesses 702 are formed adjacent to the metallization structure 750 .

[0113] Afterwards Figure 1E and Figure 1F Similar to the embodiment shown, Figure 7BSome embodiments shown heat up and press the heat dissipation cover 136 against the thermal conductive layer 126 and the inner adhesive structure 134. During the hot clamping process, a portion of the thermal conductive layer 126 extends upward into the recess 702 and laterally surrounds the metallization structure 750. Figure 7B As shown, the metallization structure 750 during the thermal clamping process and the portion of the heat conducting layer 126 near the metallization structure 750 together form a plurality of alloy structures 760. Figure 7B In some embodiments shown, the topmost surface of the alloy structure 760 is vertically positioned between the topmost and bottommost surfaces of the thermally conductive layer 126 .

[0114] In some embodiments, the metallization structure 750 and the thermally conductive layer 126 are heated for a long period of time to ensure that all of the metallization structure 750 is converted into the alloy structure 760. In some embodiments, the metallization structure 750 and the thermally conductive layer 126 are heated to approximately 200° C. for more than 4 hours. In this way, all of the metallization structure 750 is converted into the alloy structure 760.

[0115] However, the present invention is not limited to this embodiment. Numerous variations and / or modifications are possible. In some other embodiments, the metallization structure 750 is not heated for an extended period of time. As a result, the metallization structure 750 may be partially converted into the alloy structure 760. In some embodiments, one or more alloy structures 760 are located between the remaining portion of the thermally conductive layer 126 and the remaining portion of the metallization structure 750.

[0116] Afterwards Figure 1G similar, Figure 7B In some embodiments shown, a plurality of bonding structures 210 are formed on the bottom of the substrate 20. The bonding structures 210 may include solder bumps containing tin. Thus, the package structure can be bonded to another unit via the bonding structures 210.

[0117] Figure 9A is a cross-sectional view of a portion of a package structure in some embodiments. Figure 9B is a cross-sectional view of a portion of a package structure in some embodiments. Figure 9B yes Figure 9A In some embodiments, the structure is formed with Figure 1G In some embodiments, the metallization structure 150 and the thermally conductive layer 126 are partially converted into an alloy structure 960 .

[0118] like Figure 9A In some embodiments shown, during the heat clamping process, the lower portion of the metallization structure 150 and the upper portion of the thermally conductive layer 126 react with each other to transform into an alloy structure 960. The alloy structure 960 is located between the remaining portions of the metallization structure 150 and the thermally conductive layer 126.

[0119] like Figure 9B In some embodiments shown, the interface between the alloy structure 960 and the thermally conductive layer 126 and the interface between the alloy structure 960 and the metallization structure 150 have uneven profiles. Figure 9B In some embodiments shown, the lower portion of the alloy structure 960 is lower than the topmost surface of the thermally conductive layer 126. Figure 9B In some embodiments shown, the upper portion of the alloy structure 960 is higher than the bottommost surface of the metallization structure 150 .

[0120] In some embodiments, one or more metallization structures composed of the same material are formed on or embedded in the heat dissipation cover. However, the present invention is not limited thereto. Numerous variations and / or modifications are possible. In other embodiments, two or more metallization structures composed of different materials are formed on or embedded in the heat dissipation cover.

[0121] Figures 11A to 11C 1 is a cross-sectional view of various stages of a process for forming a portion of a package structure in some embodiments. Figure 11A As shown, the formation Figure 1D The heat dissipation cover 136 is located on the chip package 10 and is ready to be bonded to the substrate 20 and the chip package 10. Figure 11A In some embodiments shown, a plurality of metallization structures 150A and 150B are embedded in the heat dissipation cover 136. In some embodiments, the metallization structures 150A and 150B are composed of different materials.

[0122] Figure 10A and Figure 10B is a plan view of various stages of a process for forming a portion of a package structure in some embodiments. Figure 10A In some embodiments, Figure 11A A plan view of a portion of the structure is shown. Figure 10A FIG. 1 is a plan view of a portion of the heat dissipation cover 136 adjacent to the metallization structures 150A and 150B.

[0123] Figure 10A The groove 402 is not shown for simplicity and clarity of the drawing. Figure 10A and Figure 11A In some embodiments shown, the metallization structure 150A includes a ring structure that laterally surrounds the metallization structure 150B. Figure 10A and Figure 11A In some embodiments shown, the metallization structures 150A and 150B extend beyond both side edges of the wafer structure 100A and both side edges of the wafer structure 100B.

[0124] Figure 11BSome of the embodiments shown are Figure 1E Similar to the embodiment shown, the heat dissipation cover 136 is lowered. In this way, the metallization structure 150A directly contacts the outer portion of the thermal conductive layer 126. The metallization structure 150B directly contacts the inner portion of the thermal conductive layer 126. Figure 11B In some embodiments shown, the heat dissipation cover 136 directly contacts the inner adhesive structure 134 .

[0125] Afterwards Figure 1F Similar to the embodiment shown, Figure 11C Some embodiments shown heat up and press the heat dissipation cover 136 against the heat conducting layer 126 and the inner adhesive structure 134. For example, a thermal clamping process is performed. Figure 10B and Figure 11C In some embodiments shown, a portion of the metallization structure 150A and a portion of the thermally conductive layer 126 are converted into an alloy structure 160A during thermal compression. In some embodiments, a portion of the metallization structure 150B and a portion of the thermally conductive layer 126 are converted into an alloy structure 160B.

[0126] like Figure 10B In some embodiments shown, alloy structure 160A laterally surrounds alloy structure 160B. In some embodiments, alloy structure 160B has a higher thermal conductivity than alloy structure 160A. In some embodiments, the bond strength between alloy structure 160A and chip package 10 is greater than the bond strength between alloy structure 160B and chip package 10.

[0127] In some embodiments, the conversion alloy structure 160A is faster than the conversion alloy structure 160B. For example, the alloy structure 160 may include indium and zinc. During the heat clamping process, the alloy structure 160A, which forms faster than the alloy structure 160B, can laterally surround the thermally conductive layer 126 directly below the metallization structure 150B and prevent the thermally conductive layer 126 from flowing away. This allows sufficient reaction time between the metallization structure 150B and the underlying thermally conductive layer 126. In this way, the alloy structure 160B is formed.

[0128] Afterwards Figure 1G Similar to the embodiment shown, Figure 11C In some embodiments shown, a plurality of bonding structures 210 are formed on the bottom of the substrate 20. The bonding structures 210 may include solder bumps containing tin. Thus, the package structure can be bonded to another unit via the bonding structures 210.

[0129] The embodiments of the present invention may have many variations and / or modifications. The pattern of the metallization structure embedded in or formed on the metal cover may be varied and / or designed according to the type of the underlying chip structure.

[0130] 13A to 13C 1 is a cross-sectional view of various stages of a process for forming a portion of a package structure in some embodiments. Figure 13A As shown, the formation Figure 11A The heat dissipation cover 136 is located on the chip package 10 and is ready to be bonded to the substrate 20 and the chip package 10. Figure 13A In some embodiments shown, a plurality of metallization structures 150A and 150B are embedded in the heat dissipation cover 136. In some embodiments, the metallization structures 150A and 150B are composed of different materials. In some embodiments, the metallization structures 150A and 150B are partially removed to form a recess 1302, exposing the heat dissipation cover 136.

[0131] Figure 12A and Figure 12B is a plan view of various stages of a process for forming a portion of a package structure in some embodiments. Figure 12A In some embodiments, Figure 13A A plan view of a portion of the structure is shown. Figure 12A FIG. 1 is a plan view of a portion of the heat dissipation cover 136 near the metallization structures 150A and 150B and the recess 1302 . Figure 12A The groove 402 is not shown for simplicity and clarity of the drawing. Figure 12A and Figure 13A In some embodiments shown, the metallization structure 150A includes a ring structure that laterally surrounds the metallization structure 150B. Figure 12A and Figure 13A In some embodiments shown, the metallization structure 150A extends over both side edges of the wafer structure 100A and both side edges of the wafer structure 100B. Figure 12A and Figure 13A In some embodiments shown, the metallization structure 150B extends beyond both side edges of the wafer structure 100B.

[0132] Figure 13B Some of the embodiments shown are Figure 11B Similar to the embodiment shown, the heat dissipation cover 136 is lowered. As a result, the metallization structure 150A directly contacts the outer portion of the thermally conductive layer 126. The metallization structure 150B directly contacts the portion of the thermally conductive layer 126 directly above the wafer structure 100B. Figure 13B In some embodiments shown, the heat dissipation cover 136 directly contacts the inner adhesive structure 134 .

[0133] Afterwards Figure 11C Similar to the embodiment shown, Figure 13C Some embodiments shown heat up and press the heat dissipation cover 136 against the heat conducting layer 126 and the inner adhesive structure 134. For example, a thermal clamping process is performed. Figure 12B and Figure 13CIn some embodiments, a portion of the metallization structure 150A and a portion of the thermal conductive layer 126 are converted into an alloy structure 160A during the thermal compression process. In some embodiments, the metallization structure 150B and a portion of the thermal conductive layer 126 directly above the wafer structure 100B are converted into an alloy structure 160B.

[0134] In some embodiments, the portion of the thermally conductive layer 126 that remains after being converted into the alloy structures 160A and 160B during the thermal clamping process extends upward to fill the recess 1302. In some embodiments, the thermally conductive layer 126 directly contacts the heat dissipation cover 136. In some embodiments, the thermally conductive layer 126 extends beyond both sidewalls of the wafer structure 100A.

[0135] like Figure 12B In some embodiments shown, alloy structure 160A laterally surrounds the remaining portion of alloy structure 160B and thermally conductive layer 126. Alloy structure 160A surrounds one or more corners of thermally conductive layer 126. In some embodiments, the thermal conductivity of thermally conductive layer 126 is greater than the thermal conductivity of alloy structure 160B. In some embodiments, the thermal conductivity of alloy structure 160B is greater than the thermal conductivity of alloy structure 160A. In some embodiments, the bond strength of alloy structure 160B between heat dissipation lid 136 and chip package 10 is greater than the bond strength of thermally conductive layer 126 between heat dissipation lid 136 and chip package 10. In some embodiments, the bond strength of alloy structure 160A between heat dissipation lid 136 and chip package 10 is greater than the bond strength of alloy structure 160B between heat dissipation lid 136 and chip package 10.

[0136] The thermally conductive layer 126 located directly above the chip structure 100A helps improve heat dissipation of the chip structure 100A (e.g., a logic chip structure). During operation, the chip structure 100A generates more heat than the chip structure 100B (e.g., a memory chip structure). The alloy structure 160B located directly above the chip structure 100B provides sufficient heat dissipation for the chip structure 100B. During operation, the chip structure 100B generates less heat than the chip structure 100A. The alloy structure 160B and the alloy structure 160A together improve the adhesion between the heat dissipation cover 136 and the chip package 10. This significantly improves the heat dissipation of the chip package 10. This significantly improves the performance and reliability of the package structure.

[0137] In some embodiments, the conversion alloy structure 160A is faster than the conversion alloy structure 160B. For example, the alloy structure 160 may contain indium and zinc. During the heat clamping process, the alloy structure 160A, which forms faster than the alloy structure 160B, can laterally surround the thermally conductive layer 126 directly below the metallization structure 150B or directly below the recess 1302 and prevent the thermally conductive layer 126 from flowing away. This allows sufficient reaction time between the metallization structure 150B and the underlying thermally conductive layer 126. In this way, the alloy structure 160B can be formed.

[0138] Afterwards Figure 11C Similar to the embodiment shown, Figure 13C In some embodiments shown, a plurality of bonding structures 210 are formed on the bottom of the substrate 20. The bonding structures 210 may include solder bumps containing tin. Thus, the package structure can be bonded to another unit via the bonding structures 210.

[0139] The embodiments of the present invention may have many variations and / or modifications. The pattern of the metallization structure embedded in or formed on the heat dissipation cover may be changed and / or designed according to the type of chip structure thereunder.

[0140] Figures 15A to 15C 1 is a cross-sectional view of various stages of a process for forming a portion of a package structure in some embodiments. Figure 15A As shown, the formation Figure 13A The heat dissipation cover 136 is located on the chip package 10 and is ready to be bonded to the substrate 20 and the chip package 10. Figure 15A In some embodiments shown, the metallization structure 150 is embedded in the heat dissipation cover 136. In some embodiments, the metallization structure 150 extends beyond both edges of the wafer structure 100B. In some embodiments, the metallization structure 150 is partially removed to form a recess 1302 to expose the heat dissipation cover 136.

[0141] Figure 14A and Figure 14B is a plan view of various stages of a process for forming a portion of a package structure in some embodiments. Figure 14A In some embodiments, Figure 15A A plan view of a portion of the structure is shown. Figure 14A A plan view of a portion of the heat spreader cover 136 proximate the metallization structure 150 and the recess 1302 is shown. Figure 14A The groove 402 is not shown for simplicity and clarity of the drawing. Figure 14A In some embodiments shown, the metallization structure includes a ring structure that laterally surrounds the recess 1302 .

[0142] like Figure 15B Some of the embodiments shown are Figure 13BSimilar to the embodiment shown, the heat dissipation cover 136 is lowered. In this way, the metallization structure 150 directly contacts the outer portion of the thermal conductive layer 126, and the outer portion of the thermal conductive layer 126 is located directly above the wafer structure 100B. Figure 15B In some embodiments shown, the heat dissipation cover 136 directly contacts the inner adhesive structure 134 .

[0143] Afterwards Figure 13C Similar to the embodiment shown, Figure 15C Some embodiments shown heat up and press the heat dissipation cover 136 against the heat conducting layer 126 and the inner adhesive structure 134. For example, a thermal clamping process is performed. Figure 14B and Figure 15C In some embodiments shown, all or part of the metallization structure 150 and a portion of the thermal conductive layer 126 are converted into an alloy structure 160 during the thermal compression process.

[0144] In some embodiments, the portion of the thermally conductive layer 126 that is not converted into the alloy structure 160 during the thermal clamping process extends upward to fill the recess 1302. In some embodiments, the thermally conductive layer 126 directly contacts the heat dissipation cover 136. In some embodiments, the thermally conductive layer 126 extends beyond both edges of the wafer structure 100A.

[0145] like Figure 14B and Figure 15C In some embodiments shown, the alloy structure 160 laterally surrounds the remaining portion of the thermally conductive layer 126. In some embodiments, the thermal conductivity of the thermally conductive layer 126 is greater than the thermal conductivity of the alloy structure 160. In some embodiments, the bond strength of the alloy structure 160 between the heat dissipation lid 136 and the chip package 10 is greater than the bond strength of the thermally conductive layer 126 between the heat dissipation lid 136 and the chip package 10.

[0146] The thermally conductive layer 126 located directly above the wafer structure 100A helps improve heat dissipation from the wafer structure 100A. During operation, the wafer structure 100A generates more heat than the wafer structure 100B. The alloy structure 160 located directly above the wafer structure 100B provides sufficient heat dissipation for the wafer structure 100B. During operation, the wafer structure 100B generates less heat than the wafer structure 100A. The alloy structure 160 further improves the adhesion between the heat dissipation cover 136 and the chip package 10. This significantly improves the heat dissipation of the chip package 10 and significantly enhances the performance and reliability of the package structure.

[0147] Afterwards Figure 13C Similar to the embodiment shown, Figure 15C In some embodiments shown, a plurality of bonding structures 210 are formed on the bottom of the substrate 20. The bonding structures 210 may include solder bumps containing tin. Thus, the package structure can be bonded to another unit via the bonding structures 210.

[0148] The embodiments of the present invention may have many variations and / or modifications. The metallization structure may have many variations. Figure 16A FIG1 is a plan view of an intermediate stage of a process for forming a portion of a package structure in some embodiments. In some embodiments, a plurality of metallization structures 150 are embedded in or formed on the heat dissipation cover 136. In some embodiments, the metallization structures 150 are located on corner portions of the wafer structure 10 below.

[0149] The embodiments of the present invention may have many variations and / or modifications. The pattern of the metallization structure may have many variations. Figure 16B FIG2 is a plan view of an intermediate stage of a process for forming a portion of a package structure in some embodiments. In some embodiments, a plurality of metallization structures 150 are embedded in or formed on the heat dissipation cover 136. In some embodiments, the metallization structures 150 cover corner portions of the chip package 10 below and extend over multiple edges of the chip structure in the chip package 10 below.

[0150] An embodiment of the present invention forms a packaging structure with a heat dissipation cover. A heat-conducting structure is formed between the heat dissipation cover and the chip structure in the packaging structure. A metallized structure having a designed pattern is embedded in the heat dissipation cover or formed on the heat dissipation cover, and faces the heat-conducting layer on the chip structure. During the thermal clamping process of joining the heat dissipation cover to the chip structure, the metallized structure and the heat-conducting layer are partially or completely converted into an alloy structure (or an intermetallic compound structure), which can improve the adhesion between the heat dissipation cover and the chip structure. Due to the formation of the alloy structure, the heat-conducting layer that may flow during the thermal clamping process can be prevented from flowing away from the chip structure. In this way, the heat generated by the chip structure can be effectively conducted away from the chip structure via the heat dissipation cover. This can greatly improve the performance and reliability of the packaging structure.

[0151] In some embodiments, a method for forming a package structure is provided. The method includes placing a chip-containing structure on a substrate and forming a thermally conductive layer on the chip-containing structure. The method also includes placing a heat dissipation cover over the chip-containing structure and the thermally conductive layer. A metallized structure is embedded in the heat dissipation cover, with the metallized structure facing the thermally conductive layer. The method also includes heating and pressing the thermally conductive cover against the chip-containing structure to convert at least a portion of the metallized structure and at least a portion of the thermally conductive layer into an intermetallic compound material.

[0152] In some embodiments, the metallization structure includes gold, silver, tin, zinc, or a combination thereof.

[0153] In some embodiments, the metallization structure extends beyond both side edges of the wafer-containing structure.

[0154] In some embodiments, the second metallization structure is embedded in the heat dissipation cover, and after heating and pressing the heat conductive cover toward the chip-containing structure, at least a portion of the second metallization structure and a second portion of the heat conductive layer are converted into a second intermetallic compound material.

[0155] In some embodiments, the method further includes placing a second chip-containing structure on the substrate, wherein the chip-containing structure generates more heat than the second chip-containing structure during operation, forming a protective layer to laterally surround the chip-containing structure and the second chip-containing structure; and forming a thermally conductive layer on the protective layer, the chip-containing structure, and the second chip-containing structure.

[0156] In some embodiments, the second metallization structure is embedded in the heat dissipation cover, the second metallization structure faces the heat conducting layer, the second metallization structure extends beyond the two side edges of the second chip-containing structure, the metallization structure and the second metallization structure are made of different materials, and the metallization structure laterally surrounds the second metallization structure.

[0157] In some embodiments, when the temperature is elevated and the thermally conductive cover is pressed against the wafer-containing structure, at least a portion of the second metallization structure and a second portion of the thermally conductive layer are converted into a second intermetallic compound material.

[0158] In some embodiments, the rate of conversion to the intermetallic compound material is faster than the rate of conversion to the second intermetallic compound material.

[0159] In some embodiments, the metallization structure extends beyond the edges of both sides of the second chip-containing structure, the metallization structure surrounds a recess directly above the chip-containing structure, the thermally conductive layer after the heat dissipation cover is pressed against the chip-containing structure extends into the recess, and the intermetallic compound material laterally surrounds the thermally conductive layer extending into the recess.

[0160] In some embodiments, an intermetallic material is formed between the remaining portion of the metallization structure and the remaining portion of the thermally conductive layer.

[0161] In some embodiments, a method for forming a package structure is provided. The method includes placing a logic chip structure and a memory chip structure on a substrate, and forming a metal adhesive layer on the logic chip structure and the memory chip structure. The method also includes forming an indium layer on the metal adhesive layer and placing a heat sink cover on the indium layer. A patterned metallization structure is embedded in the heat sink cover and directly contacts the indium layer. The method also includes heating and pressing the heat sink cover and the substrate together, so that at least a portion of the patterned metallization structure and at least a portion of the indium layer together form an indium-containing alloy.

[0162] In some embodiments, the patterned metallization structure includes a plurality of metallization island structures. When the heat dissipation cover and the substrate are pressed together, the metallization island structures penetrate into the indium layer and are converted into portions of an indium alloy.

[0163] In some embodiments, the topmost surface of the indium-containing alloy is vertically located between the topmost surface of the indium layer and the bottommost surface of the indium layer.

[0164] In some embodiments, the indium-containing alloy extends beyond both edges of the memory wafer structure, while the remaining portion of the indium layer extends beyond both edges of the logic wafer structure.

[0165] In some embodiments, the indium-containing alloy laterally surrounds the remaining portion of the indium layer.

[0166] In some embodiments, a packaging structure is provided. The packaging structure includes a substrate and a heat dissipation cover positioned on the substrate. The packaging structure also includes a chip-containing structure positioned between the substrate and the heat dissipation cover. The packaging structure also includes a thermally conductive structure positioned between the chip-containing structure and the heat dissipation cover. The thermally conductive structure includes an intermetallic compound material comprising a plurality of first metallization elements and a plurality of second metallization elements. The intermetallic compound material extends into the heat dissipation cover.

[0167] In some embodiments, the intermetallic compound material includes a first metallization element and a second metallization element, and the melting point of the first metallization element is lower than about 160°C.

[0168] In some embodiments, the package structure further includes a heat conducting layer located between the chip-containing structure and the heat dissipation cover, wherein the heat conducting layer is adjacent to the heat conducting structure and has a melting point lower than that of the heat conducting structure.

[0169] In some embodiments, the heat conducting structure surrounds at least one corner of the heat conducting layer.

[0170] In some embodiments, the package structure further includes a second chip-containing structure that is separate from the chip-containing structure; and a thermally conductive layer is located between the second chip-containing structure and the heat dissipation cover. The thermally conductive layer is adjacent to the thermally conductive structure, the thermally conductive layer is composed of indium, and the thermally conductive structure contains indium.

[0171] The features of the above-described embodiments will facilitate understanding of the present invention by those skilled in the art. Those skilled in the art will appreciate that the present invention can be used as a basis to design and modify other processes and structures to achieve the same objectives and / or advantages as the above-described embodiments. Those skilled in the art will also appreciate that these equivalent substitutions do not depart from the spirit and scope of the present invention and that changes, substitutions, or modifications may be made without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a package structure, comprising: placing a chip-containing structure on a substrate; forming a thermally conductive layer on the chip-containing structure; placing a heat dissipation cover on the chip-containing structure and the heat conductive layer, wherein a metallized structure is embedded in the heat dissipation cover and faces the heat conductive layer; as well as The heat is raised and the thermally conductive cover is pressed against the chip-containing structure to convert at least a portion of the metallization structure and at least a portion of the thermally conductive layer into an intermetallic compound material. 2 . The method for forming a package structure as claimed in claim 1 , wherein the metallization structure comprises gold, silver, tin, zinc, or a combination thereof. 3 . The method for forming a package structure as claimed in claim 1 , wherein the metallization structure extends beyond both side edges of the chip-containing structure.

4. The method for forming a package structure as claimed in claim 1 , wherein a second metallization structure is embedded in the heat dissipation cover, and after heating and pressing the heat conductive cover toward the chip-containing structure, at least a portion of the second metallization structure and the second portion of the heat conductive layer are converted into a second intermetallic compound material.

5. A method for forming a packaging structure, comprising: placing a logic chip structure and a memory chip structure on a substrate; forming a metal adhesion layer on the logic chip structure and the memory chip structure; forming an indium layer on the metal adhesion layer; placing a heat dissipation cover on the indium layer, wherein a patterned metallization structure is embedded in the heat dissipation cover and directly contacts the indium layer; as well as The heat dissipation cover and the substrate are pressed together to increase the temperature, so that at least a portion of the patterned metallization structure and at least a portion of the indium layer form an indium-containing alloy.

6. The method for forming a package structure according to claim 5, wherein: The patterned metallization structure includes a plurality of metallization island structures, When the heat dissipation cover and the substrate are pressed together at elevated temperatures, the metallized island structure penetrates the indium layer, and The metallized island structures are converted into portions of the indium-containing alloy. 7 . The method for forming a package structure as claimed in claim 6 , wherein a topmost surface of the indium-containing alloy is vertically located between a topmost surface of the indium layer and a bottommost surface of the indium layer.

8. A packaging structure comprising: a substrate; a heat dissipation cover, located on the substrate; a chip-containing structure located between the substrate and the heat dissipation cover; as well as A heat conducting structure is located between the chip-containing structure and the heat dissipation cover, wherein the heat conducting structure includes an intermetallic compound material including a plurality of first metallization elements and a plurality of second metallization elements, and the intermetallic compound material extends into the heat dissipation cover. 9 . The package structure of claim 8 , wherein the intermetallic compound material comprises the plurality of first metallization elements and the plurality of second metallization elements, and the melting points of the plurality of first metallization elements are lower than approximately 160° C.

10. The package structure according to claim 8, further comprising: A heat-conducting layer is located between the chip-containing structure and the heat-dissipating cover, wherein the heat-conducting layer is adjacent to the heat-conducting structure and has a melting point lower than that of the heat-conducting structure.

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