Fan-out wafer level chip packaging method

Abstract

The invention relates to the field of design and manufacturing of integrated circuit semiconductors, and particularly provides a fan-out wafer level chip packaging method. The method comprises the following technological processes of wafer coating, ball mounting, PI coating, wafer cutting, crystal grain mounting, primary plastic packaging, primary grinding, primary hole rotating, laser drilling, primary RDL copper plating, secondary plastic packaging, carrier plate stripping, secondary hole rotating, secondary laser drilling, secondary RDL copper plating, bonding pad copper plating, third plastic packaging, secondary grinding, laser printing, pre-cutting, tin plating, chip cutting and braid testing. And packaging. According to the invention, a Fanout process is adopted to replace a traditional ceramic packaging process, and more I / O points can be arranged in a limited space by'fanout 'the I / O points out of the boundary of the chip; the I / O points are rearranged on a larger carrier, so that the overall packaging size can be reduced; the design and layout of the RDL can optimize signal transmission and improve electrical performance.

Description

Technical Field

[0001] The present invention relates to the field of design and manufacturing of integrated circuit semiconductors, and in particular to a fan-out wafer-level chip packaging method. Background Art

[0002] In the current semiconductor industry, electronic packaging has become a crucial aspect of industry development. Increasing global supply chain security concerns are prompting countries to strengthen their domestic supply chains and reduce external reliance. China, likewise, faces increasingly severe external sanctions and supply chain instability. Furthermore, China is the world's largest semiconductor market, with its scale continuously expanding. Driven particularly by the application of cutting-edge technologies such as 5G communications, artificial intelligence, and the Internet of Things, demand for high-performance, low-power, and highly integrated semiconductor products is growing, while the need to reduce costs and increase efficiency is also pressing.

[0003] Ceramic packaging is commonly used in electronic products in the international market due to its advantages, including excellent high-frequency performance, good insulation, and high thermal conductivity. However, ceramic packaging is complex to manufacture and more expensive than plastic encapsulation. Furthermore, ceramic materials are brittle and prone to cracking due to stress damage. Process automation and thinness are not as good as plastic encapsulation, and the thermal expansion coefficient is not fully matched with the chip, which can lead to solder joint fatigue. A new packaging type, the Fanout process, is currently being introduced in the domestic market to replace the high-cost ceramic packaging methods used abroad. The Fanout process is divided into two main types: Fan-in and Fan-out. Traditional WLP packaging mostly uses the Fan-in type, which is suitable for low-pin-count ICs. However, as the number of IC signal output pins increases, the requirements for solder ball spacing become more stringent. Coupled with the need for PCB assembly to adjust the size of the IC package and the position of the signal output pins, the Fan-out process has emerged. The Fanout process deposits metal and dielectric layers on the chip surface to form a redistribution layer (RDL), connecting the chip's I / O points to the carrier surface, thereby achieving higher I / O density and better electrical performance.

[0004] A published Chinese patent, publication number CN105390471B, discloses a fan-out wafer-level packaging structure comprising: a carrier plate, a chip loaded within a first opening on the carrier plate; a first redistribution layer formed on the carrier plate and positioned around the first opening; conductive pillars formed on the first redistribution layer, the top surface of the conductive pillars being higher than the top surface of the chip; a first sealing layer formed on the carrier plate, the surface of the first sealing layer exposing the connection between the top surface of the conductive pillars and the chip; a second redistribution layer formed on the first sealing layer connecting the conductive pillars to the chip; a second sealing layer formed on the second redistribution layer, the second sealing layer exposing the connection area of ​​the second redistribution layer; and solder balls formed on the connection area. This invention utilizes a flow-blocking structure fanout process to form a fence-like pillar area to limit the expansion and contraction of the resin during curing, thereby limiting chip displacement. The first redistribution layer is disposed above the carrier plate and below the conductive pillars to increase bonding strength and improve heat dissipation performance. The chip product packaged by the disclosed invention has the following deficiencies: 1) it needs to be formed based on a carrier board, and the thickness is still relatively large; 2) the formed product is a single-sided structure, and the design flexibility of the chip product with a single-sided structure is low.

[0005] A published Chinese patent, publication number CN114171507B, discloses a wafer-level fan-out packaging method and structure, relating to the field of chip packaging technology. This method involves preparing a carrier board with a relief protrusion and forming a plastic encapsulation body directly on the carrier board. After removing the carrier board, a plastic encapsulation body with a relief groove is obtained. The relief groove is then directly encapsulated using a plastic encapsulation compound. The chip is then embedded in the relief groove, and a passivation layer is formed on the surface of the plastic encapsulation body to cover the relief groove. Finally, wafer-level processes such as the wiring layer and solder balls are completed. This method leverages the plastic encapsulation compound's plasticity and low cost, utilizing established plastic encapsulation molding processes and combining them with the carrier board's relief protrusions to precisely shape the relief groove and other structures. The process is simple and low in complexity. Furthermore, by embedding the chip in the relief groove and then rewiring the signal contacts on the front side to fan out to the outside of the plastic encapsulation body, the reliability of the plastic encapsulation is improved. The disclosed invention adopts a method of first forming a clearance groove and then loading the chip. This method causes the problem of insufficient fit between the chip and the clearance groove. Specifically, when the size of the clearance groove is larger than the size of the chip, the chip is easy to load but easy to fall off after loading; when the size of the clearance groove is smaller than the size of the chip, the chip is not easy to load, and if the chip is forced to load, the edge is easily damaged; when the size of the clearance groove is equal to the size of the chip, the processing accuracy requirements for the clearance groove are extremely high, and the molding difficulty is extremely great, which will affect the packaging effect. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a fan-out wafer-level chip packaging method. This process, by setting three plastic sealing steps, three copper plating steps, two grinding steps and two laser drilling steps, can sequentially package RDL copper plating, pads and back pads based on the grain chip. The plastic sealing and the particle chip have a better bonding effect, and have a better packaging effect; after packaging and molding, the carrier plate can be removed, so that the chip product has a double-sided structure, and the thickness of the finished chip product is thinned on the basis of retaining or even enhancing the existing chip function, meeting the market demand for high-density, small-size chip packaging; it can solve the problems of large chip thickness and single-sided structure of the chip packaged using the fanout process in the prior art, as well as the problem of insufficient fit between the chip and the clearance groove by first forming the clearance groove and then loading the chip

[0007] To achieve the above-mentioned and other related objectives, the present invention provides a fan-out wafer-level chip packaging method, which includes the following process:

[0008] Step 1: Wafer Coating: Apply a layer of highly thermally conductive silver glue on the back of the entire wafer.

[0009] Step 2: Bumping: Bumping the pads of each chip on the wafer.

[0010] Step 3: PI Coating: Apply a layer of PI insulating glue on the front of the wafer to insulate the front of the chips on the entire wafer.

[0011] Step 4: Wafer Saw: Cut the entire wafer into independent chips.

[0012] Step 5, Die Attaching: Prepare a carrier board with a pre-attached adhesive film (DOF) and evenly bond the die chips one by one to the carrier board using backside bonding.

[0013] Step 6: DOF Molding: Use the molding material to perform a molding process on the carrier board, so that the molding material completely covers the die chip to form a molding product.

[0014] Step 7: Panel Grinding: Grind the plastic-sealed product to expose the top of the implant ball on the die.

[0015] Step 8: Rotating holes: Rotate holes on the primary plastic-encapsulated product according to the RDL trace drawing to generate the RDL trace pattern. At the same time, rotate positioning holes at the four corners near the edge of the primary plastic-encapsulated product.

[0016] Step 9: Laser Drilling: Use laser drilling technology to drill holes on the plastic-sealed product to make the upper and lower circuits conductive;

[0017] Step 10: 1ST RDL CuPlating: Copper is plated on the RDL trace pattern to complete the RDL copper plating operation, and copper is plated on the top of the ball to form a pad.

[0018] Step 11, Secondary Molding (DOF Molding 2): Use molding material to perform secondary molding on the front of the primary molding product, so that the molding material completely covers the exposed part of the top of the implant ball and the RDL copper area to form a secondary molding product;

[0019] Step 12: Panel stripping: remove the panel of the secondary plastic encapsulated product;

[0020] Step 13, Rotating Hole 2: Rotate holes at the four corners near the edge of the secondary plastic-sealed product so that the positioning holes connect to the front of the secondary plastic-sealed product.

[0021] Step 14: Secondary laser drilling (Laser Drilling 2): Use laser drilling technology to drill holes on the secondary plastic-encapsulated product so that the RDL trace pattern generated by the primary hole transfer is connected to the back of the secondary plastic-encapsulated product;

[0022] Step 15, Secondary RDL Copper Plating (2ND RDL Cu Plating): Make RDL on the back of the secondary plastic encapsulated product corresponding to the pad and RDL copper area to manufacture the pad area on the back of the secondary plastic encapsulated product;

[0023] Step 16: Lead Cu Plating: Copper is plated on the pad area on the back of the secondary plastic package product to create an outer lead area with a jagged edge.

[0024] Step 17, DOF Molding 3: Use the molding material to perform a third molding on the back of the second-molded product. The molding material completely wraps the pad area and the outer lead area to form a third-molded product.

[0025] Step 18, Secondary Grinding (Panel Grinding 2): Grind the back of the triple-molded product to expose the outer lead area;

[0026] Step 19: Laser Marking: Laser marking the front of the triple-laminated product.

[0027] Step 20: Pre-cut: Pre-cut the triple-molded product. This involves cutting a portion of the back of the triple-molded product to create a step and expose the side metal of the pad area and outer lead area.

[0028] Step 21, tin plating (E less Sn): tin plating is performed on the back and side exposed parts of the pad area and outerlead area;

[0029] Step 22: Package Saw: Continue cutting the triple-molded product along the pre-cut outline to form a single independent chip product, with steps formed on the side of the product;

[0030] Step 23: Test and Tape: Test the tape of the chip product;

[0031] Step 24: Packaging: Chip product packaging.

[0032] In one embodiment of the present invention, in step 2, the number of implant balls on a single die chip is four, and the diameter of each implant ball is ≥60 um.

[0033] In one embodiment of the present invention, in step 15, the thickness of the pad region is manufactured to be ≥30 um.

[0034] In one embodiment of the present invention, in step sixteen, the thickness of the outer lead region is manufactured to be greater than or equal to 75 μm.

[0035] In one embodiment of the present invention, in step 20, the depth of the pre-cutting is no more than half of the width of the thrice-molded product.

[0036] In one embodiment of the present invention, in step 21, the thickness of the tin layer of the tin plating is 0.8-1.5 μm.

[0037] In one embodiment of the present invention, the plastic encapsulation materials used in step six, step eleven, and step seventeen are all EMC materials, which are powdered molding compounds composed of epoxy resin as a base resin, high-performance phenolic resin as a curing agent, silica powder as a filler, and a variety of additives.

[0038] In one embodiment of the present invention, in step 23, the test tape items include checking for open or short circuit (Open / short test), DC parameter test (DC test), embedded flash function and performance test (Eflash test), logic function test (Function test), AC specification test (AC test), and radio frequency module function test (RF test).

[0039] As described above, the fan-out wafer-level chip packaging method of the present invention has the following beneficial effects:

[0040] 1. This process sets three plastic sealing steps, three copper plating steps, two grinding steps and two laser drilling steps. It can encapsulate RDL copper plating, pads and back pads in sequence based on the grain chip. The plastic sealing and particle chip have better bonding effect and better packaging effect. After packaging molding, the carrier plate can be removed, so that the chip product has a double-sided structure. The double-sided chip product has higher design flexibility. The present invention reduces the thickness of the finished chip product while retaining or even enhancing the existing chip function, meeting the market demand for high-density and small-size chip packaging.

[0041] 2. By setting up two hole-turning steps, one hole-turning step can not only generate the RDL routing pattern, but also turn out positioning holes at the four corners near the edge of the chip product. The second hole-turning step can connect the positioning holes to the back of the chip product, thereby improving the positioning effect of the chip product and thus improving the processing effect of the chip product.

[0042] 3. By setting up a pre-cutting step, pre-cutting can disperse the stress during cutting by pre-forming cutting lines on the wafer, reduce stress concentration at the edge of the chip product, and reduce cracks and breakage; pre-cutting also helps to more accurately control the cutting path, make the cutting lines clearer, improve the cutting accuracy of the chip product and simplify subsequent cutting steps.

[0043] 4. By setting up a tin plating step, the tin plating step can be performed on the back and side leakage parts of the pad area and outerlead area. The tin layer can melt at a lower temperature and form a good alloy layer with the solder, thereby improving the quality and efficiency of welding; the tin layer, as a protective film, is not only smooth, flat and dense, but also can effectively isolate the copper layer from oxygen and moisture in the air, preventing the occurrence of oxidation reaction; and tin, as a metal with high resistivity, can effectively reduce the contact resistance after being evenly attached to the surface of the copper layer through electroplating technology, thereby enhancing the current conduction capability.

[0044] 5. The present invention adopts the Fanout process to replace the traditional ceramic packaging process. By "fanning out" the I / O points beyond the chip boundary, more I / O points can be arranged in a limited space; and because the I / O points are rearranged on a larger carrier, the overall package size can be reduced; the design and layout of the RDL can optimize signal transmission and improve electrical performance; the present invention is based on the grain chip for packaging. Compared with the existing technology of first forming a clearance groove and then loading the chip, the present invention is packaged based on the grain chip, and the plastic package and the particle chip have a better bonding effect, which has a better packaging effect; compared with the existing technology relying on the carrier board molding method, the present invention only uses the carrier board as the carrier, and the carrier board is removed after the packaging molding, so that the chip product has a double-sided structure, and the thickness of the finished chip product is thinned on the basis of retaining or even enhancing the existing chip function, meeting the market demand for high-density, small-size chip packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 Shown is a product manufacturing process flow chart of the present invention.

[0046] Figure 2 Shown is a process schematic diagram of step 1 in Example 1.

[0047] Figure 3 Shown is a process schematic diagram of step 2 in Example 1.

[0048] Figure 4 Shown is a process schematic diagram of step 4 in Example 1.

[0049] Figure 5 Shown is a process schematic diagram of step five in Example 1.

[0050] Figure 6 Shown is a process schematic diagram of step six in Example 1.

[0051] Figure 7 Shown is a process schematic diagram of step seven in Example 1.

[0052] Figure 8 Shown is a process schematic diagram of step eight in Example 1.

[0053] Figure 9 Shown is a process schematic diagram of step nine in Example 1.

[0054] Figure 10 Shown is a process schematic diagram of step ten in Example 1.

[0055] Figure 11 It shows the process schematic diagram of step 11 in Example 1.

[0056] Figure 12It is a process schematic diagram of step twelve in Example 1.

[0057] Figure 13 It shows the process schematic diagram of step thirteen in Example 1.

[0058] Figure 14 It is a process schematic diagram of step fourteen in Example 1.

[0059] Figure 15 It is a process schematic diagram of step 15 in Example 1.

[0060] Figure 16 It is a process schematic diagram of step 16 in Example 1.

[0061] Figure 17 Display as Figure 16 A magnified view of the local structure.

[0062] Figure 18 It is a process schematic diagram of step seventeen in Example 1.

[0063] Figure 19 It is a process schematic diagram of step 18 in Example 1.

[0064] Figure 20 It is a process schematic diagram of step nineteen in Example 1.

[0065] Figure 21 It shows the process schematic diagram of step 20 in Example 1.

[0066] Figure 22 Shown is a process schematic diagram of step 21 in Example 1.

[0067] Figure 23 It is a process schematic diagram of step 22 in Example 1.

[0068] Figure 24 It shows the process schematic diagram of step 23 in Example 1.

[0069] Figure 25 Shown as the present invention Figure 23 Schematic diagram of the cross-sectional structure of a single chip.

[0070] Figure 26 The figure shows a perspective view of a chip product packaged by the present invention from the front, viewed from above.

[0071] Component number description

[0072] 1. Wafer; 2. Chip; 3. Ball planting; 4. Carrier; 5. Plastic packaging material; 6. Positioning hole; 7. Pad; 8. Outer lead; 9. Tin layer; 10. Silver glue; 11. Solder pad. DETAILED DESCRIPTION

[0073] The following describes the implementation of the present invention through specific embodiments. People skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0074] See also Figures 1 to 26 It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so that people familiar with this technology can understand and read them. They are not used to limit the conditions under which the present invention can be implemented. Therefore, they have no technical significance. Any structural modification, change in proportion or adjustment of size should still fall within the scope of the technical content disclosed in the present invention without affecting the efficacy and purpose that can be achieved by the present invention.

[0075] See also Figure 1-Figure 26 This embodiment provides a fan-out wafer-level chip packaging method, which includes the following process:

[0076] Step 1, Wafer Coating: Apply a layer of highly thermally conductive silver paste 10 on the back of the entire wafer 1. This step can reduce the risk of chip 2 cracking due to stress and tension in the chip 2.

[0077] Step 2, bumping: bumping a ball 3 in the pad 11 area of ​​each chip 2 on the wafer 1 . The number of bumps 3 on a single die chip 2 is four, and the diameter of each bump 3 is ≥60 μm.

[0078] Step 3, PI Coating: Apply a layer of PI insulating glue on the front of wafer 1 to insulate the front of chip 2 on the entire wafer 1. This step can protect the bumping and prevent the impact of subsequent electroplating / flash etching solutions.

[0079] Step 4: Wafer Saw: Cut the entire wafer 1 into independent crystal chips 2 .

[0080] Step 5, DOF Die Attaching: Prepare a carrier board 4 with a pre-attached adhesive film (DOF), and evenly bond the die chips 2 one by one to the carrier board 4 by back-bonding.

[0081] Step 6: DOF Molding: Use the molding material 5 to perform a molding process on the carrier 4, so that the molding material 5 completely wraps the die chip 2 to form a molding product.

[0082] Step 7: Panel Grinding: Grind the plastic-encapsulated product to expose the top of the implant balls 3 on the die chip 2. In this step, the top diameter of each exposed implant ball 3 is controlled to be ≥30 μm, and the overall thickness of the product after grinding is controlled to be between 439 μm and 459 μm.

[0083] Step 8: Rotating holes: Rotate holes on the primary encapsulated product according to the RDL trace drawing to generate the RDL trace pattern, preparing for subsequent RDL process exposure and development. At the same time, positioning holes 6 are rotated at the four corners of the primary encapsulated product near the edge for positioning.

[0084] Step 9. Laser Drilling: This product has a double-sided structure and uses laser drilling technology to drill holes on the plastic-sealed product at one time, which can make the upper and lower circuits conductive. In this step, the shape of the drilled hole is a trapezoid that is wide at the top and narrow at the bottom. The trapezoidal drilling includes a hole mouth and a hole bottom. The outer diameter of the hole mouth is controlled in the range of 1000um to 1040um, and the minimum inner diameter of the hole mouth is controlled to be 970um; the outer diameter of the hole bottom is controlled in the range of 200um to 240um, and the minimum inner diameter of the hole bottom is controlled to be 170um.

[0085] Step 10: First RDL copper plating: Copper is plated on the RDL trace pattern to complete the RDL copper plating process. Copper is also plated on the top of the bump 3 to form the pad 11. The RDL width is controlled between 512um and 768um, and the RDL pitch is controlled between 1430um and 1470um.

[0086] Step 11, Secondary Molding (DOF Molding 2): Use molding material 5 to perform secondary molding on the front of the primary molding product, so that the molding material 5 completely covers the exposed portion of the top of the implant ball 3 and the RDL copper area to form a secondary molding product; the thickness of the secondary molding product is controlled to be 639μm to 679μm.

[0087] Step 12, Panel Stripping: The panel 4 of the secondary plastic encapsulation product is stripped and removed. The present invention only uses the panel 4 as a carrier. After the encapsulation is completed, the panel 4 is removed, so that the chip 2 product has a double-sided structure. While retaining or even enhancing the existing chip 2 functions, the thickness of the finished chip 2 product is reduced, meeting the market demand for high-density, small-size chip 2 packaging.

[0088] Step 13, Rotating Hole 2: Rotate holes at the four corners near the edge of the secondary plastic package product so that the positioning holes 6 are connected to the front of the secondary plastic package product, which can improve the positioning effect of the chip 2 product and further improve the processing effect of the chip 2 product.

[0089] Step 14, Secondary Laser Drilling (Laser Drilling 2): Use laser drilling technology to drill holes on the secondary plastic-encapsulated product so that the RDL trace pattern generated by the first hole transfer is connected to the back of the secondary plastic-encapsulated product; the drilling shape in this step is also a trapezoid with a larger top and a smaller bottom, including the hole mouth and the hole bottom. The outer diameter of the hole mouth is controlled in the range of 200um to 240um, and the minimum inner diameter of the hole mouth is controlled to be 170um; the outer diameter of the hole bottom is controlled in the range of 140um to 180um, and the minimum inner diameter of the hole bottom is controlled to be 110um.

[0090] Step 15, Secondary RDL Copper Plating (2ND RDL Cu Plating): RDL is made on the area corresponding to the pad 11 and RDL copper plating on the back of the secondary plastic package product to manufacture the pad 7 area on the back of the secondary plastic package product. The RDL width is controlled at 216um to 324um, the RDL spacing is controlled at 480um to 720um, and the thickness of the pad 7 area is ≥30um.

[0091] Step 16: Copper plating of pad 11 (Lead Cu Plating): Copper is plated on the pad 7 area on the back of the secondary plastic package product to produce an outer lead 8 area with a jagged edge. The thickness of the outer lead 8 area is ≥75um, the width of the outer lead 8 is controlled at 200um~300um, and the spacing of the outer lead 8 is controlled at 750um~850um.

[0092] In this step, the serrated edge design of the outer lead 8 area has the following advantages: 1) It increases the contact circumference between the pad and the solder, and the actual pad contact area can be increased by 20% to 40% compared with the smooth pad; the serrated structure can form a "mechanical lock", and the solder fills the grooves between the teeth and solidifies, preventing the lateral displacement of the solder joint, effectively enhancing the welding strength and mechanical reliability of the product; 2) The tooth-shaped gap is used to block the excessive flow of molten solder to avoid short circuits between adjacent pads; the serrated edge can destroy the continuous tension of the solder paste, promote the uniform separation of the solder paste after printing, and effectively improve the welding processability; 3) By increasing the current path, the impedance is dispersed and the trend effect at high frequencies is reduced; at the same time, the larger contact area and metallurgical bonding interface reduce current crowding and effectively improve the electrical performance of the product; 4) The heat conduction path between the pad and the PCB copper layer is increased to improve the heat diffusion efficiency; and the stress caused by the CTE (coefficient of thermal expansion) mismatch is dispersed by the serrated edge, delaying the propagation of thermal fatigue cracks.

[0093] Step 17, DOF Molding 3: Use molding material 5 to perform tertiary molding on the back of the secondary molding product. The molding material 5 completely wraps the pad 7 area and the outer lead 8 area to form a tertiary molding product. The thickness of the tertiary molding product is controlled at 872um to 912um.

[0094] Step 18, Secondary Grinding (Panel Grinding 2): Grind the back of the triple-molded product to expose the outer lead 8 area. After grinding, the product thickness is controlled at 540um to 560um.

[0095] This process sets three plastic sealing steps, three copper plating steps, two grinding steps and two laser drilling steps, and can encapsulate RDL copper plating, pads 11 and back pad 7 in sequence based on the grain chip 2. The plastic sealing and the particle chip 2 have a better bonding effect and a better packaging effect. After the packaging is formed, the carrier board 4 can be removed, so that the chip 2 product has a double-sided structure. The double-sided structure of the chip 2 product has higher design flexibility. The present invention reduces the thickness of the finished chip 2 product on the basis of retaining or even enhancing the existing chip 2 function, meeting the market demand for high-density and small-size chip 2 packaging.

[0096] Step 19: Laser Marking: Laser marking is performed on the front of the triple-laminated product, and the laser depth of the printing is controlled at 10um to 20um.

[0097] Step 20, Pre-cut: Use a 0.2mm wide blade to pre-cut the three-times plastic-sealed product, that is, cut a part on the back of the three-times plastic-sealed product with a cutting depth of 0.165mm, leaving a step and exposing the side metal of the pad 7 area and the outer lead 8 area to facilitate subsequent soldering and formal cutting of the product; the depth of the pre-cutting is not more than half of the width of the three-times plastic-sealed product. Reasonable control of the pre-cutting depth has multiple advantages in the chip 2 packaging process, including preventing the plastic sealing layer from cracking, protecting the chip 2 and the internal structure, improving the yield, optimizing the cutting efficiency, reducing stress concentration, adapting to subsequent processes and reducing costs. These advantages together ensure the reliability and efficiency of the packaging process, while improving the quality of the final product.

[0098] This step can disperse the stress during cutting by pre-forming cutting lines on the wafer, reduce stress concentration at the edge of chip 2 product, and reduce cracks and breakage; pre-cutting also helps to more accurately control the cutting path, make the cutting lines clearer, improve the cutting accuracy of chip 2 product and simplify subsequent cutting steps.

[0099] Step 21, tin plating (Eless Sn): Tin plating is performed on the back and side leaking parts of the pad 7 area and the outer lead 8 area, and the thickness of the tin layer 9 is 0.8-1.5μm; the main functions of tin plating in the pad 7 area and the outer lead 8 area in this step include improving welding performance, enhancing corrosion resistance, improving conductivity and protecting the copper layer. Specifically, 1) the tin layer 9 can melt at a lower temperature and form a good alloy layer with the solder, thereby improving the quality and efficiency of welding. This is especially important for the pins and wire connections of electronic components; 2) the tin layer 9 acts as a protective film, which can effectively isolate the copper layer from oxygen and moisture in the air and prevent the occurrence of oxidation reactions. Especially in harsh environments such as humidity and salt spray, the tin-plated copper layer exhibits more excellent corrosion resistance, extending the service life of the circuit board; 3) tin, as a low-resistivity metal, can effectively reduce contact resistance after being evenly attached to the surface of the copper layer through electroplating technology, thereby enhancing the current conduction capability. This is particularly important for circuit boards that require efficient transmission of electrical energy or signals. 4) The tinned layer 9 is not only smooth, flat, and dense, but also less likely to form copper-tin intermetallic compounds than electroplated tin, effectively preventing oxidation and corrosion of the copper layer and protecting it from the external environment. Furthermore, the tin layer 9 formed by the immersion tin process has a thickness of 0.8-1.5 μm, which can withstand multiple lead-free soldering shocks, helping to maintain the electrical performance of the circuit board. This can reduce signal loss and interference, particularly in high-frequency and high-speed signal transmission applications.

[0100] Step 22: Package Saw: Use a 0.1mm wide blade to continue cutting the triple-molded product along the pre-cut outline to form a single independent chip 2 product, with steps formed on the side of the product.

[0101] In this step, the chip 2 product is designed to be stepped at the edge of the product pad after cutting, which has the following advantages: 1) Enhanced mechanical strength and impact resistance: (1) Dispersed stress concentration, the step structure disperses external stress (such as falling, vibration) through multi-level transition, avoids stress concentration on a single plane, and reduces the risk of cracking; (2) Improved anti-delamination ability: the step increases the contact area between the plastic packaging material and the substrate (such as PCB, lead frame), combined with the interface locking effect, inhibits delamination; 2. Optimized sealing and moisture-proof performance: (1) Extended moisture penetration path, the tortuous path formed by the step delays moisture intrusion, reduces moisture absorption rate, and improves moisture sensitivity level; (2) Enhanced interface sealing, the step structure and sealant (such as epoxy resin) form a multi-level bite, reducing capillary Leakage caused by the effect; 3. Improve assembly accuracy and compatibility: (1) Positioning guide function, the step serves as a mechanical positioning reference to simplify the alignment process of PCB mounting or shell assembly; (2) Compatibility with heterogeneous materials, the step excess particles alleviate the CTE (thermal expansion coefficient) mismatch of different materials (such as epoxy resin and metal frame); 4. Thermal management optimization: (1) Increase the heat dissipation surface area, the step structure enhances convection heat dissipation through multi-level exposure, which is especially suitable for compact designs without heat sinks; (2) Heat dissipation effect, the step disperses the heat flow path, avoids local overheating, and improves high-temperature reliability; 5. Electromagnetic shielding (EMI) enhancement: (1) Shielding continuity, the step edge can form a stepped overlap with the metal shell or shielding layer to reduce electromagnetic leakage gaps.

[0102] Step 23, Test and Tape: Test the tape of Chip 2. Test tape items include open / short test (checking for open or short circuits), DC test (DC parameter test), Eflash test (embedded flash function and performance test), Function test (logic function test), AC test (AC specification test), and RF test (RF module function test). Required test equipment: FT testing hardware includes test boards, test sockets, ATE (Automation Test Equipment) testers, and handlers.

[0103] Step 24: Packaging: Chip 2 product packaging.

[0104] Example 2, based on Example 1, the plastic encapsulation material 5 used in step 6, step 11, and step 17 of this embodiment is an EMC material, which is a powdered molding compound made of epoxy resin as a base resin, high-performance phenolic resin as a curing agent, silicon powder and the like as a filler, and a variety of additives. The use of EMC material as the plastic encapsulation material 5 in this embodiment has the following advantages: 1) EMC material has high mechanical strength and can provide good physical protection for the chip 2, preventing the chip 2 from being damaged by mechanical stress or impact during packaging, transportation, and use; 2) EMC material has a low coefficient of thermal expansion (CTE) and can match the chip 2 and substrate material, reducing thermal stress. When the temperature changes, it reduces the risk of package cracking or delamination caused by thermal expansion mismatch; 3) EMC material is an excellent insulator and can effectively isolate the electrical connections inside the chip 2, prevent short circuits and electrical interference, and ensure the reliable operation of the chip 2. 4) EMC materials are highly resistant to most chemicals and can maintain stable performance in harsh environments, such as high temperature, high humidity, and corrosive gas environments, extending the life of the chip 2. 5) EMC materials are relatively low-cost, suitable for large-scale production, reducing overall packaging costs and improving economic benefits. 6) EMC materials have good fluidity and can fill gaps between complex mold structures and the chip 2, ensuring that there are no voids or defects inside the package, thereby improving package reliability. 7) After optimization, EMC materials have good moisture resistance, preventing moisture from invading the chip 2 and avoiding moisture-induced corrosion or delamination problems. 8) The formulation of EMC materials can be adjusted according to specific needs, such as adjusting thermal conductivity, flame retardancy, CTE, etc., to meet the performance requirements of different application scenarios.

[0105] In summary, the present invention adopts the Fanout process to replace the traditional ceramic packaging process. By "fanning out" the I / O points outside the boundary of the chip 2, more I / O points can be arranged in a limited space. Moreover, since the I / O points are rearranged on a larger carrier, the overall package size can be reduced. The design and layout of the RDL can optimize signal transmission and improve electrical performance. The present invention is based on the crystal chip 2 for packaging. Compared with the method of first forming a clearance groove and then installing the chip 2 in the prior art, the crystal chip 2 in the present invention is more closely fitted with the plastic package and has a better molding effect. Compared with the prior art method of relying on the carrier board 4 for molding, the present invention only uses the carrier board 4 as a carrier. After the packaging molding, the carrier board 4 is removed, so that the chip 2 product has a double-sided structure. While retaining or even enhancing the existing chip 2 function, the thickness of the finished chip 2 product is reduced, meeting the market demand for high-density, small-size chip 2 packaging. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial utilization value.

[0106] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A fan-out wafer-level chip packaging method, characterized in that: The method comprises the following process: Step 1: Wafer Coating: Apply a layer of highly thermally conductive silver glue on the back of the entire wafer. Step 2: Bumping: Bumping the pads of each chip on the wafer. Step 3: PI Coating: Apply a layer of PI insulating glue on the front of the wafer to insulate the front of the chips on the entire wafer. Step 4: Wafer Saw: Cut the entire wafer into independent chips. Step 5, Die Attaching: Prepare a carrier board with a pre-attached adhesive film (DOF) and evenly bond the die chips one by one to the carrier board using backside bonding. Step 6: DOF Molding: Use the molding material to perform a molding process on the carrier board, so that the molding material completely covers the die chip to form a molding product. Step 7: Panel Grinding: Grind the plastic-sealed product to expose the top of the implant ball on the die. Step 8: Rotating holes: Rotate holes on the primary plastic-encapsulated product according to the RDL trace drawing to generate the RDL trace pattern. At the same time, rotate positioning holes at the four corners near the edge of the primary plastic-encapsulated product. Step 9: Laser Drilling: Use laser drilling technology to drill holes on the plastic-sealed product to make the upper and lower circuits conductive; Step 10: 1ST RDL CuPlating: Copper is plated on the RDL trace pattern to complete the RDL copper plating operation, and copper is plated on the top of the ball to form a pad. Step 11, Secondary Molding (DOF Molding 2): Use molding material to perform secondary molding on the front of the primary molding product, so that the molding material completely covers the exposed part of the top of the implant ball and the RDL copper area to form a secondary molding product; Step 12: Panel stripping: remove the panel of the secondary plastic encapsulated product; Step 13, Rotating Hole 2: Rotate holes at the four corners near the edge of the secondary plastic-sealed product so that the positioning holes connect to the front of the secondary plastic-sealed product. Step 14: Secondary laser drilling (Laser Drilling 2): Use laser drilling technology to drill holes on the secondary plastic-encapsulated product so that the RDL trace pattern generated by the primary hole transfer is connected to the back of the secondary plastic-encapsulated product; Step 15, Secondary RDL Copper Plating (2ND RDL Cu Plating): Make RDL on the back of the secondary plastic encapsulated product corresponding to the pad and RDL copper area to manufacture the pad area on the back of the secondary plastic encapsulated product; Step 16: Lead Cu Plating: Copper is plated on the pad area on the back of the secondary plastic package product to create an outer lead area with a jagged edge. Step 17, DOF Molding 3: Use the molding material to perform a third molding on the back of the second-molded product. The molding material completely wraps the pad area and the outer lead area to form a third-molded product. Step 18, Secondary Grinding (Panel Grinding 2): Grind the back of the triple-molded product to expose the outer lead area; Step 19: Laser Marking: Laser marking the front of the triple-laminated product. Step 20: Pre-cut: Pre-cut the triple-molded product. This involves cutting a portion of the back of the triple-molded product to create a step and expose the side metal of the pad area and outer lead area. Step 21: Tin plating (E less Sn): Tin plating is performed on the back and side exposed portions of the pad area and outer lead area; Step 22: Package Saw: Continue cutting the triple-molded product along the pre-cut outline to form a single independent chip product, with steps formed on the side of the product; Step 23: Test and Tape: Test the tape of the chip product; Step 24: Packaging: Chip product packaging.

2. The fan-out wafer-level chip packaging method according to claim 1, wherein: In step 2, the number of implant balls on a single die chip is four, and the diameter of each implant ball is ≥60 um.

3. The fan-out wafer-level chip packaging method according to claim 1, wherein: In step fifteen, the thickness of the pad region is manufactured to be ≥30 μm.

4. The fan-out wafer-level chip packaging method according to claim 3, wherein: In step sixteen, the thickness of the outerlead region is manufactured to be ≥75 μm.

5. The fan-out wafer-level chip packaging method according to claim 1, wherein: In step 20, the depth of the pre-cutting is no more than half of the width of the thrice-molded product.

6. The fan-out wafer-level chip packaging method according to claim 1, wherein: In step twenty-one, the thickness of the tin layer of the tin plating is 0.8-1.5 μm.

7. The fan-out wafer-level chip packaging method according to claim 1, wherein: The plastic encapsulation materials used in step six, step eleven, and step seventeen are all EMC materials, which are powdered molding compounds made of epoxy resin as a base resin, high-performance phenolic resin as a curing agent, silica powder as a filler, and a variety of additives.

8. The fan-out wafer-level chip packaging method according to claim 1, wherein: In step 23, the test tape items include open circuit or short circuit check (Open / short test), DC parameter test (DC test), embedded flash function and performance test (Eflashtest), logic function test (Function test), AC specification test (ACtest), and radio frequency module function test (RF test).

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