Chip packaging method and test substrate
By performing multiple tests and interconnections during the chip packaging process, the problem of difficulty in identifying chip packaging failures in the existing technology has been solved, low-cost and high-efficiency packaging verification has been achieved, the yield of finished products has been improved, and the verification cycle has been shortened.
Patent Information
- Application Number
- CN202510759123.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-06
- Publication Date
- 2025-09-12
AI Technical Summary
In the existing technology, it is difficult to determine the causes of chip packaging failures and failures, the testing cost is high, and the packaging verification cycle before mass production is long.
By receiving multiple wafers and packaging interposers, testing and dicing, the chip units with normal performance are processed by adding lead structures, and then electrically connected to the test substrate for chip testing, and finally interconnected with the packaging interposer to form a packaging structure.
It reduces production costs, improves finished product yield, shortens the packaging verification cycle before mass production, and reduces the difficulty of determining the causes of chip packaging faults and failures.
Smart Images
Figure CN120637255A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chip packaging, and in particular to a chip packaging method and a test substrate. Background Art
[0002] With the rapid development of integrated circuits in the post-Moore era, packaging technology has become a key enabler for breakthroughs in chip performance. The core of packaging technology is to integrate chips with different functions and manufacturing processes into a single package through a packaging process, thereby achieving high performance and low cost. This packaging process is typically 3D stacking, which vertically stacks multiple chips (dies) with different functions and interconnects them through bonding technology.
[0003] Currently, there is no unified standard for the 3D stacked package verification process. Conventional verification tests focus on the overall package structure. When a failure occurs, it is impossible to precisely identify which chip or pin has failed. Physical testing, such as X-rays, is usually required to determine the cause of the failure.
[0004] Therefore, how to determine the causes of chip packaging failures and failures at low cost and high efficiency, and shorten the packaging verification cycle before mass production, is an urgent problem to be solved by those skilled in the art. Summary of the Invention
[0005] The purpose of the present invention is to provide a chip packaging method and a test substrate to solve the problems in the prior art of chip packaging failure, difficulty in determining the cause of failure, high testing cost, and long packaging verification cycle before mass production.
[0006] To solve the above technical problems, the present invention provides a chip packaging method, comprising:
[0007] Receive multiple wafers and package interposers;
[0008] Testing the chip units on the entire wafer to obtain wafer chip test results;
[0009] Slicing the entire wafer to obtain multiple independent chip units;
[0010] Performing lead structure addition processing on chip units with normal performance in the wafer chip test results to obtain lead-completed chips;
[0011] Electrically connecting the lead-out completed chip to a test substrate, and performing a chip test on the lead-out completed chip through the test substrate to obtain a test result of the lead-out completed chip;
[0012] The lead-out completed chip with normal performance in the lead-out completed chip test result is interconnected with the packaging interposer to obtain a packaging structure.
[0013] Optionally, in the chip packaging method, performing lead structure addition processing on chip units with normal performance in the wafer chip test results to obtain lead-completed chips includes:
[0014] Perform at least one of ball planting, BUMP or TSV processing on chip units with normal performance in the wafer chip test results to obtain a lead-out completed chip.
[0015] Optionally, in the chip packaging method, before interconnecting the lead-out completed chip with normal performance in the lead-out completed chip test results with the packaging interposer, the method further includes:
[0016] Electrically connecting the packaging interposer to a test substrate, and performing a packaging interposer function test on the packaging interposer through the test substrate to obtain a packaging interposer test result;
[0017] Accordingly, the lead-out completed chip with normal performance in the lead-out completed chip test result is interconnected with the package interposer to obtain a package structure, including:
[0018] The lead-out completed chip with normal performance in the lead-out completed chip test result and the packaging interposer with normal performance in the packaging interposer test result are interconnected to obtain a packaging structure.
[0019] Optionally, in the chip packaging method, electrically connecting the lead-out chip to a test substrate, and performing a chip test on the lead-out chip through the test substrate includes:
[0020] The plurality of lead-out completed chips are electrically connected to a test substrate, and chip testing is performed on the plurality of lead-out completed chips at once through the test substrate.
[0021] Optionally, in the chip packaging method, the chip test includes at least one of open circuit detection, short circuit detection, chip functional integrity detection and chip performance detection.
[0022] Optionally, in the chip packaging method, before interconnecting the lead-out completed chip with normal performance in the lead-out completed chip test results with the packaging interposer, the method further includes:
[0023] Stacking and bonding the lead-out completed chips with normal performance among the test results of the multiple lead-out completed chips to obtain a stacked chip unit;
[0024] Electrically connecting the stacked chip unit to a test substrate, and performing a chip test on the stacked chip unit through the test substrate to obtain a chip stacking test result;
[0025] Accordingly, the lead-out completed chip with normal performance in the lead-out completed chip test result is interconnected with the package interposer to obtain a package structure, including:
[0026] The stacked chip units with normal performance in the chip stacking test results are interconnected with the packaging interposer to obtain a packaging structure.
[0027] Optionally, in the chip packaging method, after obtaining the packaging structure, the method further includes:
[0028] Electrically connecting the package structure to a test substrate, and performing a chip test on the package structure through the test substrate to determine whether the package structure has a fault;
[0029] When there is a fault in the package structure, the package structure is marked as a failed package.
[0030] Optionally, in the chip packaging method, interconnecting the lead-out completed chip with normal performance in the lead-out completed chip test results with the packaging interposer to obtain a packaging structure includes:
[0031] The lead-out completed chip with normal performance in the lead-out completed chip test result is interconnected with the packaging intermediary layer through BUMP or bonding to obtain a packaging structure.
[0032] A test substrate, used in any one of the above chip packaging methods, comprising a plurality of functional test modules;
[0033] The functional testing module is used to perform corresponding chip testing on the lead-out completed chip;
[0034] The functional test module includes a surface connection terminal, and the lead-out completion chip is electrically connected to the corresponding functional test module via the surface connection terminal.
[0035] Optionally, in the test substrate, the packaging structure includes a plurality of different lead-out completed chips;
[0036] The test substrate includes a plurality of functional test modules for different lead-out completed chips, which can simultaneously connect all the lead-out completed chips constituting the package structure and perform chip tests on all the lead-out completed chips constituting the package structure.
[0037] The chip packaging method provided by the present invention receives multiple wafers and a packaging interposer; tests the chip units on the entire wafer to obtain wafer chip test results; dices the entire wafer to obtain multiple independent chip units; performs lead-out structure addition processing on the chip units with normal performance in the wafer chip test results to obtain lead-out completed chips; electrically connects the lead-out completed chips to a test substrate, and performs chip testing on the lead-out completed chips through the test substrate to obtain lead-out completed chip test results; interconnects the lead-out completed chips with normal performance in the lead-out completed chip test results with the packaging interposer to obtain a packaging structure. In the prior art, the chip is usually tested when it is still on the whole wafer and has not been diced. At this stage, the failed chip units or faulty chip units are eliminated, leaving only the chip units with normal functions. The entire process of subsequent chip unit packaging assumes that the chip unit itself will not have any more faults or problems. However, in fact, during the chip packaging process, the chip unit itself is very likely to be structurally damaged in the process of adding the lead-out structure, causing the chip unit to fail. In the present invention, by performing an additional chip test on the chip units that have been diced and the lead-out structure added, the chip units that have failed due to the addition of the lead-out structure can be judged as early as possible. After that, the chip units that failed during the lead-out structure addition process are eliminated, and only the chip units that are still functional are packaged. This can greatly reduce production costs, improve the yield of finished products, and greatly reduce the difficulty of determining the causes of chip packaging failures and failures, shortening the packaging verification cycle before mass production. The present invention also provides a test substrate with the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0039] Figure 1 A schematic flow chart of a specific embodiment of the chip packaging method provided by the present invention;
[0040] Figure 2 A schematic structural diagram of a test substrate in a specific embodiment of the chip packaging method provided by the present invention;
[0041] Figure 3 A schematic structural diagram of a packaging structure of a specific embodiment of the chip packaging method provided by the present invention;
[0042] Figure 4A schematic flow chart of another specific embodiment of the chip packaging method provided by the present invention;
[0043] Figure 5 This is a structural schematic diagram of a specific embodiment of the test substrate provided by the present invention.
[0044] Reference numerals:
[0045] 100-test substrate; 110-functional test module; 200-lead-out completed chip; 300-packaging interposer. DETAILED DESCRIPTION
[0046] In order to enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the embodiments described are only some of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.
[0047] The core of the present invention is to provide a chip packaging method, a flow chart of a specific embodiment of the invention is as follows: Figure 1 As shown, it is called specific implementation method one, including:
[0048] S101: receiving multiple wafers and packaging interposers.
[0049] The packaging interposer 300 is used to finally carry the plurality of chip units and is connected to an external circuit.
[0050] A plurality of identical chip units are arranged in an array on the entire wafer.
[0051] S102: Testing the chip units on the entire wafer to obtain wafer chip test results.
[0052] In this step, each chip unit on the entire wafer is tested, which is equivalent to obtaining the functional status of the chip units on the entire wafer.
[0053] S103: Slicing the entire wafer to obtain multiple independent chip units.
[0054] The independent chip units obtained after dicing are chip units that can be freely assembled.
[0055] S104: performing lead-out structure adding processing on chip units with normal performance in the wafer chip test results to obtain lead-out completed chips.
[0056] The lead-out structure adding process is a process of adding a lead-out structure to the chip unit. Since this process is a post-processing after the chip unit is formed, it is usually not a change to the internal logic circuit of the chip unit, but usually an addition to the electrical connection structure.
[0057] As a specific implementation, the chip units with normal performance in the wafer chip test results are subjected to lead structure addition processing to obtain a lead-completed chip 200, including:
[0058] At least one of ball planting, BUMP (bump) or TSV (through silicon via) processing is performed on the chip units with normal performance in the wafer chip test results to obtain a lead-out completed chip 200.
[0059] Among them, the ball planting process and BUMP process are usually processes performed on the surface of the chip unit to electrically connect the chip unit to the external circuit, while the TSV process requires opening a hole in the chip unit, which includes both the connection between the chip unit and the external circuit board and the electrical connection between different chip units, or the chip unit with a hole only provides an electrical connection channel, and itself does not have an electrical connection with the TSV inside it. The above three lead-out structure addition processes are all processes with high destructive power on the chip unit. Therefore, after the above-mentioned lead-out structure addition process is performed, the lead-out completed chip 200 needs to be inspected.
[0060] S105: electrically connecting the lead-out completed chip to a test substrate, and performing a chip test on the lead-out completed chip through the test substrate to obtain a test result of the lead-out completed chip.
[0061] The test substrate 100 is a substrate that sends an excitation signal to the lead-out chip 200 and determines the functional integrity of the lead-out chip through the output signal returned by the lead-out chip 200. Figure 2 , Figure 2 This is a schematic diagram of the ports on the surface of the test substrate 100, which may include a TP (test stimulus) port, a DUT (Device Under Test) output port, a POWER (power) port, and a GND (ground) port. Of course, by adding different test modules to the test substrate 100, the test substrate 100 can also test other components in the package structure, which is not limited by the present invention. This step can eliminate failed or faulty chip units as early as possible, improve the yield of finished products, and directly obtain the percentage of chip units with process failures and failed samples, assisting in subsequent process adjustments and shortening the package verification cycle.
[0062] S106: interconnecting the lead-out completed chip with normal performance in the lead-out completed chip test results with the packaging interposer to obtain a packaging structure.
[0063] As a preferred embodiment, before interconnecting the lead-out completed chip 200 with normal performance in the test results of the lead-out completed chip 200 with the packaging interposer 300, the method further includes:
[0064] A1: electrically connecting the packaging interposer 300 to the test substrate 100 , and performing a packaging interposer function test on the packaging interposer 300 through the test substrate 100 to obtain a packaging interposer test result.
[0065] Accordingly, the lead-out completed chip 200 with normal performance in the test results of the lead-out completed chip 200 is interconnected with the package interposer 300 to obtain a package structure, including:
[0066] A2: interconnecting the lead-out completed chip 200 with normal performance in the test results of the lead-out completed chip 200 and the packaging interposer 300 with normal performance in the test results of the packaging interposer to obtain a packaging structure.
[0067] In this preferred embodiment, on the premise that the lead-out completed chip 200 is tested as mentioned above and chips with normal functions are screened out, the packaging interposer 300 is further tested for its functionalities, thereby avoiding the interconnection between the faulty packaging interposer 300 and the lead-out completed chip 200 with good functions, which may result in failure of the final new packaging structure. This further improves the yield, avoids rework, and reduces costs. At the same time, it also helps to further identify the process stages that need to be improved in the packaging process, helps to clarify the causes of chip packaging failures and failures, assists in subsequent process adjustments, and shortens the packaging verification cycle.
[0068] Furthermore, electrically connecting the lead-out completed chip 200 to the test substrate 100 and performing a chip test on the lead-out completed chip 200 through the test substrate 100 includes:
[0069] The plurality of lead-out completed chips 200 are electrically connected to the test substrate 100 , and chip testing is performed on the plurality of lead-out completed chips 200 at the same time through the test substrate 100 .
[0070] In this preferred embodiment, a plurality of the lead-out completion chips 200 are connected to the test substrate 100 at the same time, which can greatly improve the test efficiency of the packaging structure and shorten the early packaging verification time. Of course, the types of the lead-out completion chips 200 connected to the test substrate 100 at the same time can be the same or different, and can be adjusted according to actual needs.
[0071] Preferably, the test substrate 100 can simultaneously test all the lead-out completed chips 200 that constitute the packaging structure, further improving the test efficiency. Furthermore, the test substrate 100 can also perform packaging interposer function testing on the packaging interposer 300 while testing the lead-out completed chips 200.
[0072] Specifically, the chip test includes at least one of open circuit detection, short circuit detection, chip functional integrity detection, and chip performance detection. Of the four chip test items described above, the open circuit detection, short circuit detection, chip functional integrity detection, and chip performance detection cover the vast majority of test items, further enhancing the versatility of the present invention.
[0073] As another preferred embodiment, before interconnecting the lead-out completed chip 200 with normal performance in the test results of the lead-out completed chip 200 with the packaging interposer 300, the method further includes:
[0074] B1: Stack and bond the lead-out completed chips 200 with normal performance in the test results of multiple lead-out completed chips 200 to obtain a stacked chip unit.
[0075] For reference Figure 3 In the package structure, not all of the lead-out chips 200 are directly soldered on the surface of the package interposer 300. Some of the lead-out chips 200 are first stacked and bonded to form the stacked chip unit, and then soldered on the surface of the package interposer 300 in the form of the stacked chip unit. Figure 3 Die1 and Die2 are stacked and bonded to form a stacked chip unit, Die3 and Die4 are directly interconnected on the packaging interposer 300 , and Die1 , Die2 , Die3 , and Die4 are all lead-out completed chips 200 .
[0076] B2: electrically connecting the stacked chip unit to the test substrate 100 , and performing a chip test on the stacked chip unit through the test substrate 100 to obtain a chip stacking test result.
[0077] Accordingly, the lead-out completed chip 200 with normal performance in the test results of the lead-out completed chip 200 is interconnected with the package interposer 300 to obtain a package structure, including:
[0078] B3: interconnecting the stacked chip units with normal performance in the chip stacking test results with the packaging interposer 300 to obtain a packaging structure.
[0079] In other words, in this preferred embodiment, the existence of a stacked chip unit structure in the new packaging structure is taken into consideration, and during the stack bonding process of the lead-out completed chip 200, faults caused by bonding failure may also occur. After completing the stack bonding to obtain the stacked chip unit, the stacked chip unit is directly tested through the test substrate 100 to eliminate failed and faulty stacked chip units as early as possible, thereby improving the yield of finished products. At the same time, the number of stacked chip units with failed stack bonding and the number of failed samples can be directly obtained to assist in subsequent process adjustments and shorten the packaging verification cycle.
[0080] In addition, the lead-out completed chip 200 with normal performance in the test results of the lead-out completed chip 200 is interconnected with the package interposer 300 to obtain a package structure, including:
[0081] The lead-out completed chips 200 with normal performance in the test results of the lead-out completed chips 200 are interconnected with the packaging interposer 300 through a BUMP (bump) or bonding method to obtain a packaging structure.
[0082] In this specific embodiment, a means of interconnecting the lead-out chip 200 and the packaging interposer 300 is provided. BUMP interconnection and bonding interconnection are highly efficient, have a mature process, a high yield rate, and are cost-controllable. Of course, interconnection can also be achieved through other means, which are not limited in the present invention.
[0083] The chip packaging method provided by the present invention receives multiple wafers and a packaging interposer 300; tests the chip units on the entire wafer to obtain wafer chip test results; dices the entire wafer to obtain multiple independent chip units; performs lead-out structure addition processing on the chip units with normal performance in the wafer chip test results to obtain lead-out completed chips 200; electrically connects the lead-out completed chips 200 to a test substrate 100, and performs chip testing on the lead-out completed chips 200 through the test substrate 100 to obtain lead-out completed chip 200 test results; interconnects the lead-out completed chips 200 with normal performance in the lead-out completed chip 200 test results with the packaging interposer 300 to obtain a packaging structure. In the prior art, chips are usually tested when they are still on the whole wafer and have not been diced. At this stage, failed chip units or faulty chip units are eliminated, leaving only chip units with normal functions. The entire process of subsequent chip unit packaging assumes that the chip unit itself will not have any faults or problems. However, in fact, during the chip packaging process, the chip unit itself is very likely to be structurally damaged during the process of adding the lead-out structure, causing the chip unit to fail. In the present invention, an additional chip test is performed on the chip units that have been diced and the lead-out structure added, so that the chip units that have failed due to the addition of the lead-out structure can be judged as early as possible, and then the chip units that failed during the process of adding the lead-out structure are eliminated, and only the chip units that are still functionally intact are packaged. This can greatly reduce production costs, improve the yield of finished products, and greatly reduce the difficulty of determining the causes of chip packaging failures and failures, thereby shortening the packaging verification cycle before mass production.
[0084] On the basis of the specific embodiment 1, the chip packaging method is further improved to obtain the specific embodiment 2, and the corresponding flow chart is as follows: Figure 4 As shown, including:
[0085] S201: receiving multiple wafers and packaging interposers.
[0086] S202: Testing the chip units on the entire wafer to obtain wafer chip test results.
[0087] S203: Slicing the entire wafer to obtain multiple independent chip units.
[0088] S204: performing lead-out structure adding processing on chip units with normal performance in the wafer chip test results to obtain lead-out completed chips.
[0089] S205: electrically connecting the lead-out completed chip to a test substrate, and performing a chip test on the lead-out completed chip through the test substrate to obtain a test result of the lead-out completed chip.
[0090] S206: interconnecting the lead-out completed chip with normal performance in the lead-out completed chip test results with the packaging interposer to obtain a packaging structure.
[0091] S207: electrically connecting the package structure to a test substrate, and performing a chip test on the package structure through the test substrate to determine whether the package structure has a fault.
[0092] S208: When there is a fault in the package structure, mark the package structure as a failed package.
[0093] The difference between this specific embodiment and the above specific embodiment is that, in this specific embodiment, after completing the interconnection between the lead-out chip 200 and the packaging interposer 300, the chip test is performed on the packaging structure. The remaining steps are the same as the above specific embodiment and will not be repeated here.
[0094] In this preferred embodiment, the chip test is performed again on the packaged packaging structure after packaging, which not only ensures the yield rate of the final product packaging structure in one step, but also further determines the failure cause of the packaging structure that fails at this time, that is, the failure at this time must be due to the chip failure caused by the interconnection process during the interconnection process between the lead-out completed chip 200 and the packaging interposer 300. The number of interconnection failures and failed samples can be directly obtained to assist in subsequent process adjustments and shorten the packaging verification cycle.
[0095] The present invention also provides a test substrate 100, a structural diagram of a specific embodiment of which is shown in FIG. Figure 5 As shown, it is called specific embodiment three, the test substrate 100 is used in any of the above-mentioned chip packaging methods, including multiple functional test modules 110;
[0096] The functional testing module 110 is used to perform corresponding chip testing on the lead-out completed chip 200;
[0097] The functional test module 110 includes a surface connection terminal, and the lead-out chip 200 is electrically connected to the corresponding functional test module 110 via the surface connection terminal.
[0098] The test substrate 100 in this specific embodiment is used in any of the chip packaging methods described above, so the specific technical details can be referred to above, and the present invention will not be repeated here.
[0099] Figure 5The test substrate 100 includes a plurality of functional test modules 110, and different functional test modules 110 perform different test items. Each functional test module 110 includes a surface connection terminal interconnected with the lead-out completion chip 200. The structural diagram of the surface connection terminal on a single functional test module 110 is shown in FIG. Figure 2 shown.
[0100] Of course, in some specific embodiments, the test substrate 100 may also perform corresponding tests on the packaging interposer 300 or the packaging structure or the stacked chip unit, and the functional test module 110 may also perform different test items on the above-mentioned structures.
[0101] As a specific embodiment, the package structure includes a plurality of different lead-out completed chips 200;
[0102] The test substrate 100 includes a plurality of functional test modules 110 for different lead-out completed chips 200 , and can simultaneously connect all lead-out completed chips 200 constituting the package structure and perform chip tests on all lead-out completed chips 200 constituting the package structure.
[0103] In this specific embodiment, the test substrate 100 can test all the lead-out chips 200 constituting one package structure at one time, thereby greatly improving the test efficiency and shortening the verification cycle.
[0104] The test substrate 100 provided by the present invention is used in any of the chip packaging methods described above, and includes multiple functional test modules 110; the functional test modules 110 are used to perform corresponding chip tests on the lead-out completed chip 200; the functional test modules 110 include surface connection terminals, and the lead-out completed chip 200 is electrically connected to the corresponding functional test modules 110 through the surface connection terminals. In the prior art, chips are usually tested when they are still on the whole wafer and have not been diced. At this stage, failed chip units or faulty chip units are eliminated, leaving only chip units with normal functions. The entire process of subsequent chip unit packaging assumes that the chip unit itself will not have any faults or problems. However, in fact, during the chip packaging process, the chip unit itself is very likely to be structurally damaged during the process of adding the lead-out structure, causing the chip unit to fail. In the present invention, an additional chip test is performed on the chip units that have been diced and the lead-out structure added, so that the chip units that have failed due to the addition of the lead-out structure can be judged as early as possible, and then the chip units that failed during the process of adding the lead-out structure are eliminated, and only the chip units that are still functionally intact are packaged. This can greatly reduce production costs, improve the yield of finished products, and greatly reduce the difficulty of determining the causes of chip packaging failures and failures, thereby shortening the packaging verification cycle before mass production.
[0105] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.
[0106] It should be noted that, in this specification, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.
[0107] The chip packaging method and test substrate 100 provided by the present invention are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only intended to help understand the method and core concept of the present invention. It should be noted that, for those skilled in the art, various improvements and modifications may be made to the present invention without departing from the principles of the present invention, and such improvements and modifications also fall within the scope of protection of the present invention.
Claims
1. A chip packaging method, characterized in that: include: Receive multiple wafers and package interposers; Testing the chip units on the entire wafer to obtain wafer chip test results; Slicing the entire wafer to obtain multiple independent chip units; Performing lead structure addition processing on chip units with normal performance in the wafer chip test results to obtain lead-completed chips; Electrically connecting the lead-out completed chip to a test substrate, and performing a chip test on the lead-out completed chip through the test substrate to obtain a test result of the lead-out completed chip; The lead-out completed chip with normal performance in the lead-out completed chip test result is interconnected with the packaging interposer to obtain a packaging structure.
2. The chip packaging method according to claim 1, wherein: Performing lead structure addition processing on chip units with normal performance in the wafer chip test results to obtain lead-completed chips, including: Perform at least one of ball planting, BUMP or TSV processing on chip units with normal performance in the wafer chip test results to obtain a lead-out completed chip.
3. The chip packaging method according to claim 1, wherein: Before interconnecting the lead-out completed chip with normal performance in the lead-out completed chip test results with the package interposer, the method further includes: Electrically connecting the packaging interposer to a test substrate, and performing a packaging interposer function test on the packaging interposer through the test substrate to obtain a packaging interposer test result; Accordingly, the lead-out completed chip with normal performance in the lead-out completed chip test result is interconnected with the package interposer to obtain a package structure, including: The lead-out completed chip with normal performance in the lead-out completed chip test result and the packaging interposer with normal performance in the packaging interposer test result are interconnected to obtain a packaging structure.
4. The chip packaging method according to claim 1, wherein: Electrically connecting the lead-out completed chip to a test substrate, and performing a chip test on the lead-out completed chip through the test substrate includes: The plurality of lead-out completed chips are electrically connected to a test substrate, and chip testing is performed on the plurality of lead-out completed chips at once through the test substrate.
5. The chip packaging method according to claim 1, wherein: The chip test includes at least one of open circuit detection, short circuit detection, chip functional integrity detection and chip performance detection.
6. The chip packaging method according to claim 1, wherein: Before interconnecting the lead-out completed chip with normal performance in the lead-out completed chip test results with the package interposer, the method further includes: Stacking and bonding the lead-out completed chips with normal performance among the test results of the multiple lead-out completed chips to obtain a stacked chip unit; Electrically connecting the stacked chip unit to a test substrate, and performing a chip test on the stacked chip unit through the test substrate to obtain a chip stacking test result; Accordingly, the lead-out completed chip with normal performance in the lead-out completed chip test result is interconnected with the package interposer to obtain a package structure, including: The stacked chip units with normal performance in the chip stacking test results are interconnected with the packaging interposer to obtain a packaging structure.
7. The chip packaging method according to claim 1, wherein: After obtaining the package structure, it also includes: Electrically connecting the package structure to a test substrate, and performing a chip test on the package structure through the test substrate to determine whether the package structure has a fault; When there is a fault in the package structure, the package structure is marked as a failed package.
8. The chip packaging method according to claim 1, wherein: Interconnecting the lead-out completed chip with normal performance in the lead-out completed chip test results with the package interposer to obtain a package structure, including: The lead-out completed chip with normal performance in the lead-out completed chip test result is interconnected with the packaging intermediary layer through BUMP or bonding to obtain a packaging structure.
9. A test substrate, characterized in that: The test substrate is used in the chip packaging method according to any one of claims 1 to 8, comprising a plurality of functional test modules; The functional testing module is used to perform corresponding chip testing on the lead-out completed chip; The functional test module includes a surface connection terminal, and the lead-out completion chip is electrically connected to the corresponding functional test module via the surface connection terminal.
10. The test substrate according to claim 9, wherein The packaging structure includes a variety of different lead-out completed chips; The test substrate includes a plurality of functional test modules for different lead-out completed chips, which can simultaneously connect all the lead-out completed chips constituting the package structure and perform chip tests on all the lead-out completed chips constituting the package structure.