Wafer surface defect scanning arrangement method and system

Abstract

The application discloses a wafer surface defect scanning arrangement method and system, wherein the method comprises the following steps: calculating the number of chips covered by a scanning machine in a first direction as Nx and the number of chips covered in a second direction as Ny according to the one-time projection exposure range of the scanning machine on a wafer; judging whether the size of the chip is within a preset scanning threshold range, if yes, the chip does not need to be scanned in combination; if not, calculating the minimum number of chips N1 that need to be combined in the first direction and the minimum number of chips N2 that need to be combined in the second direction according to the preset scanning threshold range, wherein N1 and N2 are both less than a preset value, N1 can be divided by Nx, and N2 can be divided by Ny; setting the scanning parameters of the scanning machine according to N1 and N2, and automatically drawing a wafer defect scanning arrangement diagram to scan the wafer surface. The wafer defect scanning arrangement diagram can be automatically drawn, the best sensitivity of scanning defects is realized, and the best defect detection capability is realized.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method and system for scanning and arranging wafer surface defects. Background Art

[0002] During the wafer manufacturing process, various defects may appear on the wafer, such as surface defects, structural defects, and chemical defects. These defects can affect the function and performance of the chip and even cause chip failure. Therefore, effective detection and analysis of wafer defects is extremely necessary.

[0003] The scanning machine is one of the key equipment used in the semiconductor manufacturing process. It is mainly used to detect defects on the surface and inside of the wafer to ensure the quality and reliability of the wafer. The scanning machine usually uses an optical system for detection, scanning the surface of the wafer with a light beam, and then determines the detection result of the wafer through optical signals such as reflection and interference of the light beam. During detection, the existing scanning machine mainly controls the mechanical motion platform to move the wafer under the image acquisition system, and at the same time adjusts the height of the imaging system up and down to ensure the focus of the wafer surface to achieve clear photography of each target position on the wafer surface. The computer then performs image defect detection on the wafer surface. Finally, the position of the defect on the wafer can be obtained based on the position of the wafer when taking the photo and the position of the defect in the image, thus completing the detection of the wafer to be tested. The wafer to be tested is usually a circular silicon wafer made of single crystal silicon. The wafer to be tested includes multiple chips (i.e., small dies, chips before packaging), and the multiple chips are usually the same. The size of the chip is determined before the manufacturing process based on the function, performance requirements, application requirements, etc. of the chip. Therefore, in the defect detection process, the width of the chip is known. Figure 1A As shown in the figure, when the machine scans, it generally scans in an "S" shape. After scanning in the X-axis direction, it will move one line (swath) in the Y-axis direction. The detection is mainly based on chip comparison (die to die) to achieve defect detection, and the defects on the wafer surface are identified by comparing the scanning signals.

[0004] In wafer production, die size continues to shrink due to application and cost considerations. However, due to the resolution limitations of scanning equipment, the scannable die size is limited to a certain range (e.g., 1.5mm to 43mm). Therefore, when setting scanning parameters, it is sometimes necessary to combine and calculate the die and then manually draw the defect scanning layout, which is inefficient and carries the risk of miscalculation. Summary of the Invention

[0005] The main purpose of the present invention is to propose an algorithm for calculating the scanning arrangement of wafer surface defects, select the optimal parameters through calculation and automatically draw a wafer surface defect scanning arrangement diagram.

[0006] The technical solution adopted in the present invention is:

[0007] A method for scanning and arranging wafer surface defects is provided, comprising the following steps:

[0008] According to the projection exposure range of the scanning machine on the wafer, the number of chips covered in the first direction is calculated as Nx, and the number of chips covered in the second direction is calculated as Ny;

[0009] Determine whether the chip size is within the preset scanning threshold range. If so, the chips do not need to be merged and scanned. If not, calculate the minimum number of chips to be merged in the first direction, N1, and the minimum number of chips to be merged in the second direction, N2, based on the preset scanning threshold range. Both N1 and N2 are smaller than the preset values, and N1 is divisible by Nx, and N2 is divisible by Ny.

[0010] Set the scanning parameters of the scanning machine according to N1 and N2, and automatically draw a wafer defect scanning arrangement map to scan defects on the wafer surface.

[0011] Following the above technical solution, if N1 exceeds the preset value, or N1 is not divisible by Nx, the minimum number of combined projection exposures N3 in the first direction is calculated, and Nx·N3 / N1 is an integer. If N2 exceeds the preset value, or N2 is not divisible by Ny, the minimum number of combined projection exposures N4 in the second direction is calculated, and Ny·N4 / N2 is an integer. The scanning parameters of the scanning machine are then set according to N1, N2, N3, and N4.

[0012] Following the above technical solution, the size of the chip in the first direction is multiplied by natural numbers greater than 1 in sequence until it meets the scanning threshold range, and the smallest natural number that can be divided by Nx is selected as N1.

[0013] Following the above technical solution, the calculation process of N1 is: multiply the size of the chip in the first direction by the minimum divisor a1 of Nx to obtain a first product value, and determine whether the first product value is within the preset scanning threshold range. If so, N1=a1, where a1≠1.

[0014] Following the above technical solution, if the first product value is outside the preset scanning threshold range, the smallest divisor a1 is multiplied by a natural number n greater than 1 in sequence to obtain the nth product value, until the nth product value is within the preset scanning threshold range, and it is judged whether the nth product value is greater than the next smallest divisor a2 of Nx and the size of a2 chips in the first direction is within the preset scanning threshold range. If so, N1=a2; if not, Nx·m / (a1·n) is calculated, where m is the smallest natural number that makes the calculation result an integer. At this time, the minimum number of combined projection exposures in the first direction is N3=m, and the number of chip mergers is N2=a1·n.

[0015] Following the above technical solution, the method for calculating the minimum number of chips merged or the minimum number of merged projection exposures in the second direction is the same as that in the first direction.

[0016] Following the above technical solution, the preset scanning threshold range is 1.5mm-43mm.

[0017] The present invention also provides a wafer surface defect scanning method, which specifically utilizes the wafer surface defect scanning arrangement method described in the above scheme to generate a wafer defect scanning arrangement diagram, and scans the wafer surface according to the wafer defect scanning arrangement diagram, compares the scanned images, and identifies wafer surface defects.

[0018] Following the above technical solution, the process of identifying wafer surface defects specifically includes: comparing the scanned image with the scanned images on both adjacent sides, and using subtraction operations between the images to mark the wafer surface defects.

[0019] The present invention also provides a wafer surface defect scanning and arranging system, comprising:

[0020] A calculation module is used to calculate the number of chips covered in the first direction as Nx and the number of chips covered in the second direction as Ny according to the exposure range of the scanning machine projected on the wafer in one time;

[0021] The scanning arrangement parameter generation module is used to determine whether the chip size is within the preset scanning threshold range. If so, the chips do not need to be merged for scanning. If not, the minimum number of chips to be merged in the first direction, N1, and the minimum number of chips to be merged in the second direction, N2, are calculated based on the preset scanning threshold range. The scanning parameters of the scanning machine are set based on N1 and N2, where N1 and N2 are both less than the preset values, N1 is divisible by Nx, and N2 is divisible by Ny.

[0022] The arrangement diagram automatic generation module is used to automatically draw the wafer defect scanning arrangement diagram of the scanning machine according to the scanning parameters to perform defect scanning on the wafer surface.

[0023] The beneficial effects of the present invention are as follows: the present invention calculates the number of chips scanned in a single scan (i.e., merged dies) from two directions of the wafer through a scanning arrangement algorithm, and scans the chips individually or merges the scans in different situations. If merged, the number of merged chips is limited so that the size of the merged chips scanned by the machine is within the scanning range, and multiple scans can just cover all the chips on the entire wafer, thereby obtaining the optimal machine scanning parameters and automatically drawing a circular defect scanning arrangement diagram. The unexpected effect is that the present invention automatically realizes the scanning of wafer surface defects by merging the number of chips as little as possible to achieve the maximum number of die and die comparisons, and ultimately achieves the optimal sensitivity of the scanning defect recipe and the optimal defect detection capability. Therefore, the present invention improves the scanning efficiency while ensuring the accuracy of defect recognition.

[0024] Furthermore, under the condition of the chip merging number limit, if multiple scans cannot just cover all the chips on the entire wafer, it can be achieved through the minimum merging projection exposure number (i.e. merging shot).

[0025] Furthermore, by multiplying the chip size in the first direction by the smallest divisor a1 of Nx (the number of chips covered in the first direction by a single projection exposure), if the product is within the preset scan threshold, the number of chips to be merged is a1. If not, the smallest divisor a1 is sequentially multiplied by a natural number n greater than 1 until the product value is within the preset scan threshold. A determination is then made as to whether the product value is greater than the next smallest divisor a2 of Nx and the sizes of a2 chips in the first direction are within the preset scan threshold. If so, the number of merges is a2. If not, the shots need to be merged, and Nx·m / (a1·n) is calculated, where m is the smallest natural number that makes the calculation result an integer. In this case, the minimum number of merged projection exposures in the first direction, N3, equals m. This algorithm can quickly determine the number of chip merges and the number of shot merges, thereby finding the optimal scan arrangement parameters.

[0026] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1A It is a schematic diagram of the machine scanning path;

[0029] Figure 1B It is a shot map diagram of the wafer;

[0030] Figure 1C This is a schematic diagram of multiple dies covered by a single shot;

[0031] Figure 2A This is a flow chart of a wafer surface defect scanning and arrangement method according to an embodiment of the present invention;

[0032] Figure 2B This is a flow chart of a wafer surface defect scanning and arrangement method according to an embodiment of the present invention;

[0033] Figure 3A 1 is a flow chart of a method for calculating the number N1 of die merges in the first direction according to an embodiment of the present invention;

[0034] Figure 3B 1 is a flow chart of a method for calculating the number of die merges N1 and the number of shot merges N3 in the first direction according to an embodiment of the present invention;

[0035] Figure 4 This is a flow chart of a wafer surface defect scanning method according to an embodiment of the present invention;

[0036] Figure 5 This is a schematic diagram of defect identification according to an embodiment of the present invention;

[0037] Figure 6 It is a schematic structural diagram of a wafer surface defect scanning and arrangement system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0039] It should be noted that the illustrations provided in the embodiments of the present invention are only schematic illustrations of the basic concept of the present invention. Therefore, the drawings only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0040] In the present invention, it should also be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" and the like are used to indicate positions or locations based on those shown in the accompanying drawings. These terms are intended solely to facilitate the description of the present application and to simplify the description. They are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present application. Furthermore, the terms "first" and "second" are used solely for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0041] In addition, it should be noted that the features of the various embodiments of the present invention may be combined or coupled in part or in whole, and, as will be appreciated by those skilled in the art, may interact and operate in different ways. Each embodiment may be implemented independently of one another or in an associated relationship.

[0042] like Figure 2A As shown, the wafer surface defect scanning and arrangement method according to an embodiment of the present invention includes the following steps:

[0043] S201, calculating the number of chips covered in the first direction as Nx and the number of chips covered in the second direction as Ny based on the single projection exposure range of the scanning machine on the wafer;

[0044] S202, determine whether the size of the chip is within a preset scanning threshold range, if so, execute step S203; if not, execute step S204;

[0045] S203: The chips do not need to be scanned together. The chips do not need to be scanned together. Each chip can be scanned separately.

[0046] S204, calculating the minimum number of chips N1 to be merged in the first direction and the minimum number of chips N2 to be merged in the second direction according to the preset scanning threshold range, that is, the size after merging meets the preset scanning threshold range;

[0047] S205, determine whether N1 and N2 are both less than the preset value, if so, execute step S206;

[0048] S206, determine whether N1 is divisible by Nx, whether N2 is divisible by Ny, if so, execute step S207;

[0049] S207 , setting the scanning parameters of the scanning machine according to the number of merges ( N1 , N2 ), and automatically drawing a wafer defect scan map (Scan Map) to perform defect scanning on the wafer surface.

[0050] Specifically, in step S201, the projection exposure distribution (shot map, such as Figure 1B Each projection exposure (each shot, as shown) Figure 1C The number and size of dies covered by the wafer (as shown) are as follows: Nx dies are covered in a first direction (e.g., along the X-axis) and Ny dies are covered in a second direction (e.g., along the Y-axis). In the present invention, the first direction may be the horizontal direction of the wafer, and the second direction may be the vertical direction of the wafer.

[0051] Further, if Figure 2B As shown, in step S205, if N1 and N2 exceed the preset value or cannot be divided evenly, step S208 is executed.

[0052] S208. If N1 exceeds the preset value, or N1 is not divisible by Nx, then the minimum number of combined projection exposures N3 in the first direction is calculated, and Nx·N3 / N1 is an integer; if N2 exceeds the preset value, or N2 is not divisible by Ny, then the minimum number of combined projection exposures N4 in the second direction is calculated, and Ny·N4 / N2 is an integer.

[0053] Finally, step S209 is executed to set the scanning parameters of the scanning machine according to the number of merges (N1, N2, N3, N4).

[0054] Specifically, when calculating N1, the chip size in the first direction can be multiplied by natural numbers greater than 1 until it meets the scanning threshold range. The smallest natural number that is divisible by Nx is selected as N1. It is understandable that N1 also needs to be less than the preset value in this case, because if the number of combined chips exceeds the preset value (e.g., no more than 4), the defect detection sensitivity cannot be met. Similarly, find a suitable N2. For example, if Nx = 24, and the chip die size in the first direction (horizontal direction) is 0.5mm, then multiply by 2, 3, 4, 6, and 8 in sequence. When multiplied by 2, the combined size is 1.0mm, which does not meet the machine scanning range (within 1.5mm-43mm). When multiplied by 3 or 4, both are within the machine scanning range, do not exceed the preset value, and are also divisible by Nx. In this case, the smallest natural number that meets the conditions is selected as N1, N1 = 3.

[0055] In order to better implement the above method embodiment and calculate the optimal parameters of the machine scanning, the specific algorithm can be implemented through the following three rules of merged scanning, including: (1) The first rule of merged scanning: if the size of the die is within the preset scanning threshold range of the machine, the die does not need to be merged and can be scanned and compared separately; (2) The second rule of merged scanning: the number of die merges is preferably the smallest divisor of Nx (not equal to 1); (3) The third rule of merged scanning: when the number of die merges cannot be greater than the preset value, if it is greater than the preset value, it is solved by merging shots at the same time.

[0056] In accordance with the above three merge scanning rules, in a preferred embodiment of the present invention, Figure 3A As shown, the calculation process of the merging method in the first direction is:

[0057] S301, calculating the number of chips covered in the first direction as Nx based on a single projection exposure range of the scanning machine on the wafer;

[0058] S302, determining whether the size of the chip in the first direction is within a preset scanning threshold range; if so, executing step S303; if not, executing step S304;

[0059] S303: The chips do not need to be scanned together. At this time, N1=1, and each chip can be scanned separately.

[0060] S304. List the divisors (a1, a2, ...) that are divisible by Nx and sort them (1≠a1<a2<...), and proceed to step S305.

[0061] S305 , multiplying the chip size in the first direction by the smallest divisor a1 of Nx to obtain a first product value, and proceeding to step S306 ;

[0062] S306, determining whether the first product value is within a preset scanning threshold range, if so, executing step S307; if not, executing step S308;

[0063] S307. At this time, N1=a1.

[0064] S308. If the first product value is outside the preset scanning threshold range (e.g., still less than the minimum threshold after merging), the smallest divisor a1 is sequentially multiplied by a natural number n greater than 1 to obtain an nth product value. The nth product value is obtained until it is within the preset scanning threshold range, and step S309 is continued.

[0065] S309: Determine whether the nth product value is greater than the next smallest divisor a2 of Nx and the size of the a2 chips in the first direction is within a preset scanning threshold. If so, execute step S310; if not, execute step S311.

[0066] S310, at this time N1=a2;

[0067] S311 , calculating Nx·m / (a1·n), where m is the minimum natural number that makes the calculation result an integer. In this case, the minimum number of combined projection exposures in the first direction is N3=m, and the number of combined chip dies is a1·n.

[0068] In steps S304-S307, Nx can be factored as Nx = a1 × b1 = a2 × b2 = a3 × b3 = .... All divisors of Nx (excluding 1 and itself) are listed and sorted. For example, Nx = 24 = 2 × 12 = 3 × 8 = 4 × 6, where its divisors include: a1 = 2, a2 ​​= 3, a3 = 4, b1 = 12, b2 = 8, and b3 = 6. If the chip die's size in the first direction (horizontal) is 0.8 mm, multiply it by the smallest dividend a1: 0.8 × 2 = 1.6. This is within the machine's scanning range (1.5 mm to 43 mm), so N1 = 2, meaning the number of dies merged in the first direction is 2.

[0069] Specifically, in steps S308-S310, still taking Nx=24 as an example, if the chip die size in the first direction (horizontal direction) is 0.5mm, first multiply it by the smallest dividend a1 (a1=2), then 0.5×2=1.0. This is not within the scanning range (1.5mm-43mm). Then set n=2, calculate a1×n=4, and determine whether it is greater than the next smallest divisor a2 of Nx (a2=3). In this case, a1×n=4>a2. Continue calculating 0.5×a2=0.5×3=1.5. Within the scanning range (1.5mm-43mm), select the number of die merges as a2 (a2=3).

[0070] In step S311, taking Nx=22 as an example, Nx is factored into Nx=a1×b1=2×11. The smallest divisor is 2, and the next smallest divisor is 11. If the chip die size in the first direction (horizontal direction) is 0.5 mm, first multiply it by the smallest dividend a1 (a1=2), resulting in 0.5×2=1.0. If it is not within the scanning range (1.5 mm-43 mm), then set n=2 and calculate 0.5×a1×n=0.5×2×2=2.0. If it is within the scanning range (1.5 mm-43 mm), a1×n=4<11. Then calculate Nx·m / (a1·n), where m is the minimum natural number that makes the calculation result an integer. When m=2, it can be an integer. In this case, the minimum number of combined projection exposures in the first direction is N3=m=2, and the number of chip die combined is a1·n=4.

[0071] Similarly, the method for calculating the minimum number of chip merging or the minimum number of combined projection exposures in the second direction is the same as that in the first direction, such as Figure 3B As shown, the calculation process of the merging method in the second direction is:

[0072] S401, calculating the number of chips covered in the second direction as Ny based on a single projection exposure range of the scanning machine on the wafer;

[0073] S402, determining whether the size of the chip in the second direction is within a preset scanning threshold range; if so, executing step S403; if not, executing step S404;

[0074] S403: The chips do not need to be scanned together. If the chips do not need to be scanned together, N2 = 1, and each chip can be scanned separately.

[0075] S404. List the divisors (c1, c2, ...) that are divisible by Ny and sort them (1≠c1<c2<...), and proceed to step S405.

[0076] S405 , multiplying the chip size in the second direction by the smallest divisor c1 of Ny to obtain a first product value, and proceeding to step S406 ;

[0077] S406, determining whether the first product value is within a preset scanning threshold range, if so, executing step S407; if not, executing step S408;

[0078] S407. At this time, N2=c1.

[0079] S408. If the first product value is outside the preset scanning threshold range (e.g., still less than the minimum threshold after merging), the smallest divisor c1 is sequentially multiplied by a natural number n greater than 1 to obtain an nth product value. The nth product value is obtained until it is within the preset scanning threshold range, and step S409 is continued.

[0080] S409: Determine whether the nth product value is greater than the next smallest divisor c2 of Nx and the size of the c2 chips in the second direction is within a preset scanning threshold range. If so, execute step S410; if not, execute step S411;

[0081] S410, at this time N2=c2;

[0082] S411. Calculate Ny·m / (c1·n), where m is the minimum natural number that makes the calculation result an integer. At this time, the minimum number of combined projection exposures in the second direction N4=m, and the number of combined chip dies is c1·n.

[0083] In steps S404-S407, Ny can be factored as Ny = c1 × d1 = c2 × d2 = c3 × d3 = .... All divisors of Ny (excluding 1 and itself) are listed and sorted. For example, Ny = 24 = 2 × 12 = 3 × 8 = 4 × 6, where its divisors include: c1 = 2, c2 = 3, c3 = 4, d1 = 12, d2 = 8, and d3 = 6. If the die size in the second direction (vertical direction) is 0.8 mm, multiply by the smallest dividend c1: 0.8 × 2 = 1.6. This is within the machine's scanning range (1.5 mm to 43 mm), so N2 = 2, meaning the number of dies merged in the second direction is 2.

[0084] Specifically, in steps S408-S410, still taking Ny=24 as an example, if the chip die size in the second direction (vertical direction) is 0.5mm, first multiply it by the smallest dividend c1 (c1=2), then 0.5×2=1.0. This is not within the scanning range (1.5mm-43mm). Then, set n=2, calculate c1×n=4, and determine whether it is greater than the next smallest divisor c2 of Ny (c2=3). In this case, c1×n=4>c2. Continue calculating 0.5×c2=0.5×3=1.5. This is within the scanning range (1.5mm-43mm), so the number of die merging is selected as c2 (c2=3).

[0085] In step S411, taking Ny=22 as an example, Ny is factored into Ny=c1×d1=2×11. The smallest divisor is 2, and the next smallest divisor is 11. If the chip die's size in the second direction (horizontal direction) is 0.5 mm, it is first multiplied by the smallest dividend c1 (c1=2), resulting in 0.5×2=1.0. If it is not within the scanning range (1.5 mm-43 mm), n is set to 2, and 0.5×c1×n=0.5×2×2=2.0 is calculated. If it is within the scanning range (1.5 mm-43 mm), c1×n=4<11. Then Ny·m / (c1·n) is calculated, where m is the minimum natural number that makes the calculation result an integer. When m=2, it can be an integer. In this case, the minimum number of combined projection exposures in the second direction is N4=m=2, and the number of chip die combined is c1·n=4.

[0086] The above embodiment can quickly calculate the optimal scanning parameters in the first direction and the second direction, thereby generating an effective defect scan distribution map.

[0087] Further, if Figure 4 As shown, a wafer surface defect scanning method according to an embodiment of the present invention is Figure 2AThe method further includes step S210: scanning the wafer surface according to the wafer defect scanning arrangement diagram; S211, comparing the scanned images to identify wafer surface defects.

[0088] Among them, such as Figure 5 As shown, in step S211, the process of identifying wafer surface defects specifically includes comparing scanned image A2 with adjacent scanned images A1 and A3, and marking the wafer surface defects using a subtraction operation between the images. Once the defect is identified, the specific location of the defect on the actual wafer can be found using the coordinates recorded by the scanning machine.

[0089] like Figure 6 As shown, in order to implement the wafer surface defect scanning and arranging method of the above embodiment, the present invention also provides an embodiment of a wafer surface defect scanning and arranging system, which mainly includes:

[0090] A calculation module is used to calculate the number of chips covered in the first direction as Nx and the number of chips covered in the second direction as Ny according to the exposure range of the scanning machine projected on the wafer in one time;

[0091] The scanning arrangement parameter generation module is used to determine whether the chip size is within the preset scanning threshold range. If so, the chips do not need to be merged for scanning; if not, the minimum number of chips to be merged in the first direction N1 and the minimum number of chips to be merged in the second direction N2 are calculated based on the preset scanning threshold range, and the size after merging meets the preset scanning threshold range. The scanning parameters of the scanning machine are set based on N1 and N2, where N1 and N2 are both less than the preset values, N1 is divisible by Nx, and N2 is divisible by Ny;

[0092] The arrangement diagram automatic generation module is used to automatically draw the wafer defect scanning arrangement diagram of the scanning machine according to the scanning parameters to perform defect scanning on the wafer surface.

[0093] In summary, the wafer surface defect scanning arrangement method of the present invention can calculate the optimal number of merged chips, so that the size of the merged chips scanned by each machine is within the scanning range, and multiple scans can just cover all the chips on the entire wafer. The unexpected effect is that the present invention can calculate and automatically draw a circular defect scanning arrangement diagram, and automatically realize the scanning of wafer surface defects by merging the least number of chips as possible to achieve the maximum number of die and die comparisons, and finally achieve the best sensitivity of the scanning defect program (Defect Recipe) and the best defect detection capability. Therefore, the present invention improves the scanning efficiency while ensuring the accuracy of defect recognition.

[0094] It should be pointed out that, according to the needs of implementation, the various steps / components described in this application can be split into more steps / components, or two or more steps / components or partial operations of steps / components can be combined into new steps / components to achieve the purpose of the present invention.

[0095] The size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0096] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all such improvements and changes should fall within the scope of protection of the appended claims of the present invention.

Claims

1. A wafer surface defect scanning and arrangement method, characterized in that: The following steps are involved: According to the projection exposure range of the scanning machine on the wafer, the number of chips covered in the first direction is calculated as Nx, and the number of chips covered in the second direction is calculated as Ny; Determine whether the chip size is within the preset scanning threshold range. If so, the chips do not need to be merged and scanned. If not, calculate the minimum number of chips to be merged in the first direction, N1, and the minimum number of chips to be merged in the second direction, N2, based on the preset scanning threshold range. Both N1 and N2 are smaller than the preset values, and N1 is divisible by Nx, and N2 is divisible by Ny. Set the scanning parameters of the scanning machine according to N1 and N2, and automatically draw a wafer defect scanning arrangement map to scan defects on the wafer surface.

2. The wafer surface defect scanning and arrangement method according to claim 1, characterized in that: If N1 exceeds a preset value, or N1 cannot be divided by Nx, then the minimum number of combined projection exposures N3 in the first direction is calculated, and Nx·N3 / N1 is an integer; If N2 exceeds the preset value, or N2 cannot be divided by Ny, the minimum number of combined projection exposures N4 in the second direction is calculated, and Ny·N4 / N2 is an integer; then the scanning parameters of the scanning machine are set according to N1, N2, N3, and N4.

3. The wafer surface defect scanning and arrangement method according to claim 1, characterized in that: The size of the chip in the first direction is multiplied by natural numbers greater than 1 in sequence until it meets the scanning threshold range, and the smallest natural number that can be divided by Nx is selected as N1.

4. The wafer surface defect scanning and arrangement method according to claim 1, characterized in that: The calculation process of N1 is: multiply the chip size in the first direction by the minimum divisor a1 of Nx to obtain a first product value, and determine whether the first product value is within the preset scanning threshold range. If so, N1=a1, where a1≠1.

5. The wafer surface defect scanning and arrangement method according to claim 4, characterized in that: If the first product value is outside the preset scanning threshold range, the smallest divisor a1 is multiplied by a natural number n greater than 1 in sequence to obtain the nth product value, until the nth product value is within the preset scanning threshold range, and it is determined whether the nth product value is greater than the next smallest divisor a2 of Nx and the sizes of a2 chips in the first direction are within the preset scanning threshold range. If so, N1=a2; if not, Nx·m / (a1·n) is calculated, where m is the smallest natural number that makes the calculation result an integer. At this time, the minimum number of combined projection exposures in the first direction is N3=m, and the number of chips combined is N2=a1·n.

6. The wafer surface defect scanning and arrangement method according to any one of claims 3 to 5, characterized in that: The method for calculating the minimum number of chips merged or the minimum number of merged projection exposures in the second direction is the same as that in the first direction.

7. The wafer surface defect scanning and arrangement method according to claim 1, characterized in that: The preset scanning threshold range is 1.5mm-43mm.

8. A wafer surface defect scanning method, characterized in that: Specifically, a wafer surface defect scanning arrangement method according to any one of claims 1 to 6 is used to generate a wafer defect scanning arrangement diagram, and the wafer surface is scanned according to the wafer defect scanning arrangement diagram, and the scanned images are compared to identify wafer surface defects.

9. The wafer surface defect scanning method according to claim 8, characterized in that: The process of identifying wafer surface defects specifically includes: comparing the scanned image with the scanned images on both sides, and using subtraction operations between the images to mark the wafer surface defects.

10. A wafer surface defect scanning and arrangement system, characterized in that: include: A calculation module is used to calculate the number of chips covered in the first direction as Nx and the number of chips covered in the second direction as Ny according to the exposure range of the scanning machine projected on the wafer in one time; The scanning arrangement parameter generation module is used to determine whether the chip size is within the preset scanning threshold range. If so, the chips do not need to be merged for scanning. If not, the minimum number of chips to be merged in the first direction, N1, and the minimum number of chips to be merged in the second direction, N2, are calculated based on the preset scanning threshold range. The scanning parameters of the scanning machine are set based on N1 and N2, where N1 and N2 are both less than the preset values, N1 is divisible by Nx, and N2 is divisible by Ny. The arrangement diagram automatic generation module is used to automatically draw the wafer defect scanning arrangement diagram of the scanning machine according to the scanning parameters to perform defect scanning on the wafer surface.

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