Semiconductor structure, forming method thereof and memory
By forming a signal blocking layer and a conductive layer in the semiconductor structure and blocking the signal interference of the metal interconnect structure during the grinding process, the problem of unstable eddy current signals is solved, and the grinding effect and product yield are improved.
Patent Information
- Application Number
- CN202510796039.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-13
- Publication Date
- 2025-09-12
AI Technical Summary
During the semiconductor packaging process, the eddy current signal stability of the signal lead wire is poor, resulting in low product yield.
A signal blocking layer and a conductive layer are formed in the dielectric layer of the semiconductor structure and are made flush with the dielectric layer through chemical mechanical polishing. The signal blocking layer is used to block signal interference from the metal interconnect structure below, and a metal silicide layer is formed to optimize contact resistance.
The stability of the eddy current signal is improved, the grinding endpoint is accurately determined, the risk of over- or under-grinding is reduced, and the grinding effect and product yield of the semiconductor structure are improved.
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Figure CN120637318A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same, and a memory. Background Art
[0002] During the semiconductor packaging process, multiple semiconductor units are typically stacked and connected together to increase the storage capacity of the package. After stacking, signal lead lines need to be formed on the upper semiconductor unit. However, during the polishing process of the signal lead lines, the eddy endpoint detect (EEPD) signal stability is poor, resulting in low product yield.
[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention
[0004] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, as well as a memory, which can improve the stability of eddy current signals during the grinding process and increase product yield.
[0005] According to one aspect of the present disclosure, a method for forming a semiconductor structure is provided, comprising:
[0006] forming a stacked structure, the stacked structure comprising at least two layers of semiconductor units stacked and connected in a vertical direction, each layer of the semiconductor units comprising a dielectric layer and a metal interconnection structure embedded in the dielectric layer; and a via hole being provided in the dielectric layer of the semiconductor unit located on the topmost layer in the vertical direction, the via hole exposing the metal interconnection structure in the semiconductor unit located on the topmost layer;
[0007] forming a signal blocking layer on the dielectric layer having the via hole, wherein the signal blocking layer is located on the top of the dielectric layer and on the inner wall of the via hole;
[0008] forming a conductive layer on the signal blocking layer, wherein the conductive layer fills the via hole;
[0009] Chemical mechanical polishing is performed on the conductive layer and the signal blocking layer, so that the top surface of the conductive layer and the top surface of the signal blocking layer are flush with the top surface of the dielectric layer.
[0010] In an exemplary embodiment of the present disclosure, the material of the signal blocking layer includes polysilicon, and the forming method further includes:
[0011] Before forming the conductive layer, forming a metal layer conformally covering the signal blocking layer, wherein the number of atoms in the metal layer is greater than the number of atoms in the signal blocking layer;
[0012] When chemical mechanical polishing is performed on the conductive layer and the signal blocking layer, chemical mechanical polishing is also performed on the metal layer, and the top surface of the metal layer is flush with the top surface of the dielectric layer. After the chemical mechanical polishing, the forming method further includes:
[0013] The signal blocking layer and the metal layer are subjected to a heat treatment so that the signal blocking layer reacts with at least a portion of the metal layer to form a metal silicide layer.
[0014] In an exemplary embodiment of the present disclosure, the thickness of the signal blocking layer is less than or equal to 100 nm.
[0015] In an exemplary embodiment of the present disclosure, the material of the metal layer includes cobalt and / or nickel.
[0016] In an exemplary embodiment of the present disclosure, forming a conductive layer on the signal blocking layer, wherein the conductive layer fills the via hole, includes:
[0017] forming a seed layer conformally covering the metal layer;
[0018] A conductive material layer is formed on the seed layer, the conductive material layer fills the via hole, and the seed layer and the conductive material layer together constitute the conductive layer.
[0019] In an exemplary embodiment of the present disclosure, the forming method further includes:
[0020] Before forming the signal blocking layer, forming a diffusion blocking layer on the dielectric layer having the via hole;
[0021] When chemical mechanical polishing is performed on the conductive layer and the signal blocking layer, chemical mechanical polishing is also performed on the diffusion blocking layer to make the top surface of the diffusion blocking layer flush with the top surface of the dielectric layer.
[0022] In an exemplary embodiment of the present disclosure, before forming the signal blocking layer, forming a diffusion blocking layer on the dielectric layer having the via hole includes:
[0023] forming a first barrier layer, wherein the first barrier layer conformally covers the top surface of the dielectric layer and the sidewalls of the via hole;
[0024] A second barrier layer is formed, wherein the second barrier layer conformally covers the surface of the first barrier layer and the metal interconnection structure exposed at the bottom of the via hole.
[0025] In an exemplary embodiment of the present disclosure, the material of the first barrier layer includes titanium nitride and / or tantalum nitride; and / or the material of the second barrier layer includes titanium and / or tantalum.
[0026] According to one aspect of the present disclosure, there is provided a semiconductor structure comprising:
[0027] A stacked structure comprising at least two layers of semiconductor units stacked and connected in a vertical direction, wherein each layer of the semiconductor units comprises a dielectric layer and a metal interconnection structure embedded in the dielectric layer; and a via is provided in the dielectric layer of the semiconductor unit located on the topmost layer in the vertical direction, wherein the via exposes the metal interconnection structure in the semiconductor unit located on the topmost layer;
[0028] a metal silicide layer, located on the sidewalls and bottom of the via hole and connected to the metal interconnect structure; a top surface of the metal silicide layer is flush with a top surface of the dielectric layer;
[0029] A conductive layer is located on the metal silicide layer and fills the via hole; and a top surface of the conductive layer is flush with a top surface of the dielectric layer.
[0030] In an exemplary embodiment of the present disclosure, the semiconductor structure further includes:
[0031] A diffusion barrier layer conformally covers the sidewalls and bottom of the via hole and is connected to the metal interconnect structure exposed at the bottom of the via hole; the top surface of the diffusion barrier layer is flush with the top surface of the dielectric layer, and the metal silicide layer is located on the surface of the diffusion barrier layer.
[0032] In an exemplary embodiment of the present disclosure, the diffusion barrier layer includes:
[0033] a first barrier layer conformally covering the sidewalls of the via hole;
[0034] The second barrier layer conformally covers the surface of the first barrier layer and the metal interconnection structure exposed at the bottom of the via hole.
[0035] In an exemplary embodiment of the present disclosure, the material of the first barrier layer includes titanium nitride and / or tantalum nitride; and / or the material of the second barrier layer includes titanium and / or tantalum.
[0036] In an exemplary embodiment of the present disclosure, the material of the metal silicide layer includes cobalt silicide and / or nickel silicide.
[0037] In an exemplary embodiment of the present disclosure, the thickness of the metal silicide layer is less than or equal to 100 nm.
[0038] According to one aspect of the present disclosure, a memory is provided, comprising any one of the semiconductor structures described above.
[0039] The semiconductor structure, its formation method, and memory disclosed herein are characterized by a via hole in the dielectric layer of the semiconductor unit located on the topmost layer in the vertical direction after at least two layers of semiconductor units (such as wafers) are stacked to form a stacked structure. A signal blocking layer is formed on the top of the dielectric layer and the inner wall of the via hole. During the chemical mechanical polishing of the conductive layer, the signal blocking layer can block the signal scattered by the metal interconnection structure in the underlying semiconductor units, thereby reducing the interference of the metal interconnection structure on the eddy current signal during the polishing process, improving the stability of the eddy current signal, enabling the polishing endpoint to be accurately determined during the polishing process, reducing problems such as over-polishing or under-polishing, and thereby improving the polishing effect and product yield of the semiconductor structure.
[0040] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.
[0042] Figure 1 Flowchart of a method for forming a semiconductor structure in an embodiment of the present disclosure.
[0043] Figure 2 FIG. 1 is a schematic diagram of a semiconductor unit located at the topmost layer of a stacked structure in an embodiment of the present disclosure.
[0044] Figure 3 Schematic diagram of the stacking structure in an embodiment of the present disclosure.
[0045] Figure 4 Schematic diagram of the embodiment of the present disclosure after forming a diffusion barrier layer, a signal barrier layer, a metal layer and a seed layer.
[0046] Figure 5 Schematic diagram of the structure after step S130 is completed in one embodiment of the present disclosure.
[0047] Figure 6 Schematic diagram of the structure after step S140 is completed in one embodiment of the present disclosure.
[0048] Figure 7Schematic diagram of the semiconductor structure after the signal blocking layer is converted into a metal silicide layer in an embodiment of the present disclosure.
[0049] Figure 8 Schematic diagram of the first barrier layer before reverse sputtering in an embodiment of the present disclosure.
[0050] Figure 9 A schematic diagram of the structure after step S410 is completed in one embodiment of the present disclosure.
[0051] Description of reference numerals:
[0052] 100. Stacked structure; 10. Semiconductor unit; 20. Substrate; 1. Dielectric layer; 11. First dielectric layer; 12. Second dielectric layer; 13. Third dielectric layer; 14. Metal interconnect structure; 101. Via; 2. Signal blocking layer; 3. Conductive layer; 31. Seed layer; 32. Conductive material layer; 4. Metal layer; 5. Metal silicide layer; 6. Diffusion barrier layer; 61. First barrier layer; 62. Second barrier layer. DETAILED DESCRIPTION
[0053] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
[0054] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.
[0055] The terms "a", "an", "the" and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.
[0056] As the number of stacked layers of semiconductor units increases, the number of metal interconnect structures inside the semiconductor structure also increases. As a result, in the subsequent process of making signal lead lines, the eddy current signal during the grinding process is affected by the scattered signals of each metal interconnect structure, and the stability is poor, which is prone to over-etching or under-etching.
[0057] Based on this, the present disclosure provides a method for forming a semiconductor structure, such as Figure 1 As shown, the forming method includes steps S110 to S140, wherein:
[0058] Step S110, forming a stack structure, the stack structure comprising at least two layers of semiconductor units stacked and connected in a vertical direction, each layer of semiconductor units comprising a dielectric layer and a metal interconnect structure embedded in the dielectric layer; the dielectric layer of the semiconductor unit located on the topmost layer in the vertical direction comprises a via, the via exposing the metal interconnect structure in the semiconductor unit located on the topmost layer;
[0059] Step S120, forming a signal blocking layer on the dielectric layer having the via hole, wherein the signal blocking layer is located on the top of the dielectric layer and on the inner wall of the via hole;
[0060] Step S130, forming a conductive layer on the signal blocking layer, wherein the conductive layer fills the via hole;
[0061] Step S140 , chemical mechanical polishing is performed on the conductive layer and the signal blocking layer, so that the top surface of the conductive layer and the top surface of the signal blocking layer are flush with the top surface of the dielectric layer.
[0062] The method for forming a semiconductor structure disclosed herein comprises the following steps: after at least two layers of semiconductor units (such as wafers) are stacked to form a stacked structure, a via is provided in the dielectric layer of the semiconductor unit located on the topmost layer in the vertical direction. A signal blocking layer is formed on the top of the dielectric layer and on the inner wall of the via. During chemical mechanical polishing of the conductive layer, the signal blocking layer can block signals scattered by metal interconnect structures in the underlying semiconductor units, thereby reducing interference of the metal interconnect structures with eddy current signals during the polishing process and improving the stability of the eddy current signals. This allows accurate determination of the polishing endpoint during the polishing process, reduces problems such as over-polishing or under-polishing, and thereby improves the polishing effect and product yield of the semiconductor structure.
[0063] The following is a detailed description of the steps and details of the method for forming a semiconductor structure disclosed herein:
[0064] like Figure 1As shown, in step S110, a stacked structure is formed, which includes at least two layers of semiconductor units stacked and connected in a vertical direction, each layer of semiconductor units including a dielectric layer and a metal interconnection structure embedded in the dielectric layer; and a via is provided in the dielectric layer of the semiconductor unit located on the top layer in the vertical direction, and the via exposes the metal interconnection structure in the semiconductor unit located on the top layer.
[0065] In an exemplary embodiment of the present disclosure, Figure 2 As shown, the semiconductor unit 10 may include a device layer (not shown in the figure), which may be provided with word lines, bit lines and capacitors, and the dielectric layer 1 is provided on the device layer; the metal interconnection structure 14 is embedded in the dielectric layer 1 and connected to the word lines, bit lines or capacitors, and the word lines, bit lines or capacitors can be electrically led out through the metal interconnection structure 14.
[0066] In some embodiments of the present disclosure, please continue to refer to Figure 2 As shown, dielectric layer 1 can be a single-layer structure or a composite structure composed of multiple layers, without specific limitation. For example, dielectric layer 1 can include a first dielectric layer 11, a second dielectric layer 12, and a third dielectric layer 13 stacked vertically from bottom to top. First dielectric layer 11, second dielectric layer 12, and third dielectric layer 13 are made of different materials and have different thicknesses. By configuring dielectric layers 1 of different materials and thicknesses, internal stresses in the structure can be balanced to facilitate subsequent bonding or lamination processes. Metal interconnect structure 14 can be embedded within first dielectric layer 11.
[0067] like Figure 3 As shown, the stacked structure 100 can be formed on a substrate 200. The number of semiconductor units 10 in the stacked structure 100 can be multiple, and the multiple semiconductor units 10 can be stacked and connected in a vertical direction. It should be noted that the vertical direction can be a direction perpendicular to the surface of the semiconductor unit 10, or the vertical direction can be a direction perpendicular to the surface of the substrate 200. In the stacked structure 100, adjacent semiconductor units 10 can be stacked and connected in the vertical direction by bonding.
[0068] For example, the number of semiconductor units 10 in the stacked structure 100 may be 2 to 12, for example, 2, 4, 6, 8, 10 or 12. Of course, other numbers are also possible and are not listed here one by one.
[0069] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 3As shown, the dielectric layer 1 of the semiconductor unit 10 located at the topmost layer in the vertical direction can be etched, thereby forming a via 101 within the dielectric layer 1. The via 101 can expose the metal interconnect structure 14 located within the topmost semiconductor unit 10. For example, when the dielectric layer 1 includes a first dielectric layer 11, a second dielectric layer 12, and a third dielectric layer 13 stacked in sequence from bottom to top along the vertical direction, and the metal interconnect structure 14 is embedded in the first dielectric layer 11, the via 101 can penetrate the second dielectric layer 12 and the third dielectric layer 13 and penetrate into the first dielectric layer 11, thereby exposing a portion of the surface of the metal interconnect structure 14 located in the first dielectric layer 11. In the present disclosure, the number of vias 101 can be one or more; when there are more than one vias 101, different vias 101 can respectively expose different areas of the metal interconnect structure 14.
[0070] like Figure 1 As shown, in step S120 , a signal blocking layer 2 is formed on the dielectric layer 1 having the via hole 101 . The signal blocking layer 2 is located on the top of the dielectric layer 1 and on the inner wall of the via hole 101 .
[0071] The material of the signal blocking layer 2 can be polysilicon, such as Figure 4 As shown, the signal blocking layer 2 can be formed on the top of the dielectric layer 1 and the sidewalls and bottom of the via 101 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the signal blocking layer 2 can also be formed by other methods. The formation method of the signal blocking layer 2 is not particularly limited here.
[0072] In an exemplary embodiment of the present disclosure, in order to facilitate the subsequent conversion of the signal blocking layer 2 into a metal silicide layer, the thickness of the signal blocking layer 2 should not be too large. For example, the thickness of the signal blocking layer 2 may be less than or equal to 100 nm. For example, the thickness of the signal blocking layer 2 may be 20 nm, 40 nm, 60 nm, 80 nm or 100 nm. Of course, the signal blocking layer 2 may also have other thicknesses, which are not listed here one by one.
[0073] like Figure 1 As shown, in step S130 , a conductive layer 3 is formed on the signal blocking layer 2 , and the conductive layer 3 fills the via hole 101 .
[0074] The conductive layer 3 may be made of a material with a relatively strong conductive property, for example, copper. Figure 5 As shown, a conductive layer 3 can be formed on the signal blocking layer 2 by electroplating or deposition. During this process, the conductive layer 3 can fill the remaining space in the via hole 101. For process convenience, the conductive layer 3 can be spread over the top area of the dielectric layer 1. That is, the electroplating or deposition can be stopped after the conductive layer 3 fills the via hole 101.
[0075] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 4 and Figure 5 As shown, before forming the conductive layer 3, a metal layer 4 may be formed to conformally cover the signal blocking layer 2. The material of the metal layer 4 may include cobalt and / or nickel. For example, the metal layer 4 may be formed on the signal blocking layer 2 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In some embodiments of the present disclosure, the thickness of the metal layer 4 may be greater than that of the signal blocking layer 2.
[0076] In an exemplary embodiment of the present disclosure, forming a conductive layer 3 on the signal blocking layer 2 and filling the via 101 with the conductive layer 3 (ie, step S130) may include steps S210 and S220, wherein:
[0077] Step S210 , forming a seed layer 31 conformally covering the metal layer 4 .
[0078] The material of the seed layer 31 can be copper or cobalt, please refer to Figure 4 As shown, the seed layer 31 can be formed on the metal layer 4 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the seed layer 31 can also be formed by other methods. For example, the seed layer 31 can also be formed by ion plating. The formation method of the seed layer 31 is not particularly limited here.
[0079] In step S220 , a conductive material layer 32 is formed on the seed layer 31 . The conductive material layer 32 fills the via hole 101 . The seed layer 31 and the conductive material layer 32 together constitute the conductive layer 3 .
[0080] The conductive material layer 32 may be made of a material with good conductive properties, for example, copper or tungsten. Figure 5 As shown, a conductive material layer 32 can be formed on the seed layer 31 by electroplating or deposition. During this process, the conductive material layer 32 can fill the remaining space in the via 101. For process convenience, the conductive material layer 32 can also cover the surface of the seed layer 31 located on the top of the dielectric layer 1, that is, the electroplating or deposition can be stopped after the conductive material layer 32 fills the via 101.
[0081] like Figure 1 As shown, in step S140 , chemical mechanical polishing is performed on the conductive layer 3 and the signal blocking layer 2 so that the top surfaces of the conductive layer 3 and the signal blocking layer 2 are flush with the top surface of the dielectric layer 1 .
[0082] The conductive layer 3 and the signal blocking layer 2 can be polished by chemical mechanical polishing process, thereby removing the signal blocking layer 2 and the conductive layer 3 located on the top of the dielectric layer 1; during the polishing process, the surface of the dielectric layer 1 can also be polished so that the remaining dielectric layer 1 meets the structural design requirements. In the present disclosure, the structure after completing step S140 is as follows Figure 6 shown.
[0083] It should be noted that during the chemical mechanical polishing process, the signal blocking layer 2 can block the signals scattered by the metal interconnection structures 14 in the semiconductor units 10 below, thereby reducing the interference of the metal interconnection structures 14 on the eddy current signals during the polishing process, improving the stability of the eddy current signals, and thus making it possible to accurately determine the polishing end point during the polishing process, which helps to reduce problems such as over-polishing or under-polishing, thereby improving the polishing effect and product yield of the semiconductor structure.
[0084] It should be noted that when a metal layer 4 is formed on the signal blocking layer 2, when the conductive layer 3 and the signal blocking layer 2 are subjected to chemical mechanical polishing, the metal layer 4 can also be subjected to chemical mechanical polishing at the same time, and the top surface of the remaining metal layer 4 after polishing is flush with the top surface of the dielectric layer 1.
[0085] In an exemplary embodiment of the present disclosure, Figure 7 As shown, after chemical mechanical polishing, the signal blocking layer 2 and the metal layer 4 may be heat treated to allow the signal blocking layer 2 to react with at least a portion of the metal layer 4 to form a metal silicide layer 5 .
[0086] In some embodiments of the present disclosure, the number of atoms in metal layer 4 can be greater than the number of atoms in signal blocking layer 2, so that during the heat treatment process, the signal blocking layer 2 can completely react with the metal ions in metal layer 4, thereby completely converting the polysilicon in signal blocking layer 2 into metal silicide. The signal blocking layer 2 after conversion into metal silicide can be defined as metal silicide layer 5. The metal silicide layer 5 can optimize the contact resistance between the metal interconnect structure 14 at the bottom of the via 101 and the conductive layer 3, thereby improving charge transfer efficiency and signal integrity, thereby enhancing conductivity.
[0087] For example, the ratio of the number of atoms in the metal layer 4 to the number of atoms in the signal blocking layer 2 may be greater than or equal to 1:1; for example, the ratio of the number of atoms in the metal layer 4 to the number of atoms in the signal blocking layer 2 may be 1:1, 1:1.5, 1:2, 1:2.5, or 1:3, etc. It should be noted that after the heat treatment, the signal blocking layer 2 may be completely converted into the metal silicide layer 5, while the metal layer 4 may not be completely reacted, and unreacted metal layer 4 may remain.
[0088] In the present disclosure, the heat treatment may be an annealing treatment. When the material of the metal layer 4 is cobalt, the material of the metal silicide layer 5 is cobalt silicide; when the material of the metal layer 4 is nickel, the material of the metal silicide layer 5 is nickel silicide. The annealing temperature in the present disclosure is very low, which can be 300-500°C, and will not cause damage to the device layer or other structures of the semiconductor unit.
[0089] In an exemplary embodiment of the present disclosure, the method for forming a semiconductor structure of the present disclosure may further include step S310 and step S320, wherein:
[0090] Step S310 , before forming the signal blocking layer 2 , forming a diffusion blocking layer 6 on the dielectric layer 1 having the via 101 .
[0091] The material of the diffusion barrier layer 6 may be a material having an ion barrier function. For example, the material of the diffusion barrier layer 6 may include tantalum, titanium, titanium nitride, tantalum nitride, or a combination thereof. Figure 4 As shown, a diffusion barrier layer 6 can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition to conformally cover the top surface of the dielectric layer 1 and the sidewalls and bottom of the via 101. During the heat treatment process, the diffusion barrier layer 6 can prevent metal ions from diffusing through the signal blocking layer 2 into the dielectric layer 1, thereby helping to improve device reliability.
[0092] In step S320 , when chemical mechanical polishing is performed on the conductive layer 3 and the signal blocking layer 2 , chemical mechanical polishing is also performed on the diffusion barrier layer 6 to make the top surface of the diffusion barrier layer 6 flush with the top surface of the dielectric layer 1 .
[0093] When the diffusion barrier layer 6 is formed before the signal blocking layer 2 is formed, the diffusion barrier layer 6 can be polished simultaneously during the subsequent chemical mechanical polishing process, thereby removing the diffusion barrier layer 6 located on the top of the dielectric layer 1 and making the top surface of the remaining diffusion barrier layer 6 flush with the top surface of the dielectric layer 1.
[0094] In an exemplary embodiment of the present disclosure, the diffusion barrier layer 6 may be a composite film structure composed of multiple film layers. Forming the diffusion barrier layer 6 (i.e., step S310) may include steps S410 and S420, wherein:
[0095] In step S410 , a first barrier layer 61 is formed. The first barrier layer 61 conformally covers the top surface of the dielectric layer 1 and the sidewalls of the via hole 101 .
[0096] The material of the first barrier layer 61 may include titanium nitride and / or tantalum nitride, such as Figure 8As shown, a first barrier layer 61 can be formed on the surface of the dielectric layer 1 having the via 101 by chemical vapor deposition, physical vapor deposition or atomic layer deposition, and then the first barrier layer 61 at the bottom of the via 101 can be removed by a reverse sputtering process, thereby exposing the surface of the metal interconnect structure 14 at the bottom of the via 101. It is understood that the first barrier layer 61 on the side wall of the via 101 is retained by the reverse sputtering process, but the thickness is reduced. In the present disclosure, the structure after completing step S410 is as follows Figure 9 shown.
[0097] In step S420 , a second barrier layer 62 is formed. The second barrier layer 62 conformally covers the surface of the first barrier layer 61 and the metal interconnect structure 14 exposed at the bottom of the via hole 101 .
[0098] Because the reverse sputtering process inevitably damages the first barrier layer 61 on the sidewalls of the via 101, reducing the thickness of the first barrier layer 61, it is necessary to continue depositing a material with ion-blocking functionality to ensure ion blocking effectiveness. For example, the material of the second barrier layer 62 may include titanium and / or tantalum. The second barrier layer 62 can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition to conformally cover the surface of the first barrier layer 61 and the bottom surface of the via 101.
[0099] It should be noted that although the steps of the method for forming a semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.
[0100] The present disclosure also provides a semiconductor structure, which is formed by the method for forming a semiconductor structure in any of the above embodiments. Figure 7 As shown, the semiconductor structure may include a stacked structure 100, a metal silicide layer 5 and a conductive layer 3, wherein:
[0101] The stacked structure 100 includes at least two layers of semiconductor units 10 stacked and connected in a vertical direction. Each layer of semiconductor units 100 includes a dielectric layer 1 and a metal interconnect structure 14 embedded in the dielectric layer 1. The dielectric layer 1 of the semiconductor unit 10 located on the topmost layer in the vertical direction has a via 101, and the via 101 exposes the metal interconnect structure 14 in the semiconductor unit 10 located on the topmost layer.
[0102] The metal silicide layer 5 is located on the sidewalls and bottom of the via hole 101 and is connected to the metal interconnect structure 14; the top surface of the metal silicide layer 5 is flush with the top surface of the dielectric layer 1;
[0103] The conductive layer 3 is located on the metal silicide layer 5 and fills the via hole 101 ; and the top surface of the conductive layer 3 is flush with the top surface of the dielectric layer 1 .
[0104] Compared with the prior art, the beneficial effects of the semiconductor structure provided by the present disclosure are the same as the beneficial effects of the semiconductor structure formation method provided by the above-mentioned example embodiments (for example, there are fewer problems such as over-grinding or under-grinding, and the product yield is higher), which will not be elaborated here.
[0105] The following describes in detail the various parts of the semiconductor structure disclosed herein and their specific details:
[0106] Please continue to see Figure 3 As shown, stacked structure 100 may include at least two layers of semiconductor units 10 stacked and connected in a vertical direction. Each layer of semiconductor units 100 includes a dielectric layer 1 and a metal interconnect structure 14. Semiconductor units 10 may also include a device layer (not shown), which may include word lines, bit lines, capacitors, etc. The dielectric layer 1 may be provided on the device layer. The metal interconnect structure 14 is embedded in the dielectric layer 1 and connected to the word lines, bit lines, or capacitors. The word lines, bit lines, or capacitors can be electrically led out through the metal interconnect structure 14.
[0107] In some embodiments of the present disclosure, the dielectric layer 1 may be a single-layer film structure or a composite film structure composed of multiple layers, which is not particularly limited here. Figure 2 Dielectric layer 1 may include a first dielectric layer 11, a second dielectric layer 12, and a third dielectric layer 13 stacked vertically from bottom to top. First dielectric layer 11, second dielectric layer 12, and third dielectric layer 13 are made of different materials and have different thicknesses. By configuring dielectric layers 1 of different materials and thicknesses, internal stress within the structure can be balanced to facilitate subsequent bonding or lamination processes. Metal interconnect structure 14 may be embedded within first dielectric layer 11.
[0108] Please continue to see Figure 3 As shown, the stacking structure 100 can be formed on a substrate 200. The number of semiconductor units 10 in the stacking structure 100 can be multiple, and the multiple semiconductor units 10 can be stacked and connected in a vertical direction. For example, in the vertical direction, adjacent semiconductor units 10 can be stacked and connected by bonding.
[0109] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 3As shown, a via 101 is provided in the dielectric layer 1 of the semiconductor unit 10 located at the topmost layer in the vertical direction. The via 101 can expose the metal interconnect structure 14 located at the topmost semiconductor unit 10. For example, when the dielectric layer 1 includes a first dielectric layer 11, a second dielectric layer 12, and a third dielectric layer 13 stacked in sequence from bottom to top along the vertical direction, and the metal interconnect structure 14 is embedded in the first dielectric layer 11, the via 101 can penetrate the second dielectric layer 12 and the third dielectric layer 13 and penetrate into the first dielectric layer 11, thereby exposing a portion of the surface of the metal interconnect structure 14 located in the first dielectric layer 11. In the present disclosure, the number of vias 101 can be one or more; when there are multiple vias 101, different vias 101 can respectively expose different areas of the metal interconnect structure 14.
[0110] In an exemplary embodiment of the present disclosure, the semiconductor structure of the present disclosure may further include a diffusion barrier layer 6. The material of the diffusion barrier layer 6 may be a material having ion blocking properties. For example, the material of the diffusion barrier layer 6 may include tantalum, titanium, titanium nitride, tantalum nitride, or a combination thereof. The diffusion barrier layer 6 may conformally cover the sidewalls and bottom of the via 101 and contact and connect with the metal interconnect structure 14 exposed at the bottom of the via 101. The top surface of the diffusion barrier layer 6 is flush with the top surface of the dielectric layer 1. The diffusion barrier layer 6 can prevent metal ions formed during the subsequent formation of the metal silicide layer 5 from diffusing into the dielectric layer 1, thereby helping to improve device reliability.
[0111] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 7 As shown, the diffusion barrier layer 6 may be a composite film layer structure composed of multiple film layers. For example, the diffusion barrier layer 6 may include a first barrier layer 61 and a second barrier layer 62, wherein the first barrier layer 61 may conformally cover the side wall of the via 101, and the material of the first barrier layer 61 may include titanium nitride and / or tantalum nitride.
[0112] In order to enhance the ion blocking effect between the dielectric layer 1 and the subsequently formed metal silicide layer 5 and / or conductive layer 3, a second barrier layer 62 may be formed in the via 101 having the first barrier layer 61. The material of the second barrier layer 62 may include titanium and / or tantalum. The second barrier layer 62 may conformally cover the surface of the first barrier layer 61 and the metal interconnect structure 14 exposed at the bottom of the via 101, that is, the second barrier layer 62 may be in contact with and connected to the metal interconnect structure 14.
[0113] The metal silicide layer 5 is located within the via 101. For example, the metal silicide layer 5 may be located on the sidewalls and bottom of the via 101 and connected to the metal interconnect structure 14 located at the bottom of the via 101. The top surface of the metal silicide layer 5 is flush with the top surface of the dielectric layer 1. The material of the metal silicide layer 5 may include cobalt silicide and / or nickel silicide. The provision of the metal silicide layer 5 can reduce the contact resistance between the metal interconnect structure 14 and the subsequently formed conductive layer 3, thereby improving charge transfer efficiency and signal integrity, thereby enhancing conductivity.
[0114] In an exemplary embodiment of the present disclosure, the thickness of the metal silicide layer 5 may be less than or equal to 100 nm. For example, its thickness may be 20 nm, 40 nm, 60 nm, 80 nm or 100 nm. Of course, the metal silicide layer 5 may also have other thicknesses, which are not listed here one by one.
[0115] It should be noted that when a diffusion barrier layer 6 is provided in the via 101 , the metal silicide layer 5 is located on the surface of the diffusion barrier layer 6 . For example, the metal silicide layer 5 can conformally cover the surface of the diffusion barrier layer 6 and be connected to the metal interconnect structure 14 through the diffusion barrier layer 6 .
[0116] Conductive layer 3 is located on metal silicide layer 5 and fills via 101. For example, conductive layer 3 may fill the remaining space in via 101, and the top surface of conductive layer 3 may be flush with the top surface of dielectric layer 1. Conductive layer 3 may be made of a highly conductive material, such as copper and / or tungsten. Signals in metal interconnect structure 14 may be led out through conductive layer 3.
[0117] The present disclosure also provides a memory, which may include the semiconductor structure in any of the above embodiments. Its specific details, formation process and beneficial effects have been described in detail in the corresponding semiconductor structure and the method for forming the semiconductor structure, and will not be repeated here.
[0118] For example, the memory may be a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, an electrically erasable programmable read-only memory (EEPROM), a phase change random access memory (PRAM), or a magnetoresistive random access memory (MRAM). Of course, other storage devices are also possible, which are not listed here one by one.
[0119] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: forming a stacked structure, the stacked structure comprising at least two layers of semiconductor units stacked and connected in a vertical direction, each layer of the semiconductor units comprising a dielectric layer and a metal interconnection structure embedded in the dielectric layer; and a via hole being provided in the dielectric layer of the semiconductor unit located on the topmost layer in the vertical direction, the via hole exposing the metal interconnection structure in the semiconductor unit located on the topmost layer; forming a signal blocking layer on the dielectric layer having the via hole, wherein the signal blocking layer is located on the top of the dielectric layer and on the inner wall of the via hole; forming a conductive layer on the signal blocking layer, wherein the conductive layer fills the via hole; Chemical mechanical polishing is performed on the conductive layer and the signal blocking layer, so that the top surface of the conductive layer and the top surface of the signal blocking layer are flush with the top surface of the dielectric layer.
2. The forming method according to claim 1, wherein: The material of the signal blocking layer includes polysilicon, and the forming method further includes: Before forming the conductive layer, forming a metal layer conformally covering the signal blocking layer, wherein the number of atoms in the metal layer is greater than the number of atoms in the signal blocking layer; When chemical mechanical polishing is performed on the conductive layer and the signal blocking layer, chemical mechanical polishing is also performed on the metal layer, and the top surface of the metal layer is flush with the top surface of the dielectric layer. After the chemical mechanical polishing, the forming method further includes: The signal blocking layer and the metal layer are subjected to a heat treatment so that the signal blocking layer reacts with at least a portion of the metal layer to form a metal silicide layer.
3. The forming method according to claim 2, wherein: The thickness of the signal blocking layer is less than or equal to 100 nm.
4. The forming method according to claim 2, wherein: The material of the metal layer includes cobalt and / or nickel.
5. The forming method according to claim 2, wherein: forming a conductive layer on the signal blocking layer, wherein the conductive layer fills the via hole, comprising: forming a seed layer conformally covering the metal layer; A conductive material layer is formed on the seed layer, the conductive material layer fills the via hole, and the seed layer and the conductive material layer together constitute the conductive layer.
6. The forming method according to any one of claims 1 to 5, characterized in that: The forming method further comprises: Before forming the signal blocking layer, forming a diffusion blocking layer on the dielectric layer having the via hole; When chemical mechanical polishing is performed on the conductive layer and the signal blocking layer, chemical mechanical polishing is also performed on the diffusion blocking layer to make the top surface of the diffusion blocking layer flush with the top surface of the dielectric layer.
7. The forming method according to claim 6, wherein: Before forming the signal blocking layer, forming a diffusion blocking layer on the dielectric layer having the via hole comprises: forming a first barrier layer, wherein the first barrier layer conformally covers the top surface of the dielectric layer and the sidewalls of the via hole; A second barrier layer is formed, wherein the second barrier layer conformally covers the surface of the first barrier layer and the metal interconnection structure exposed at the bottom of the via hole.
8. The forming method according to claim 7, wherein: The material of the first barrier layer includes titanium nitride and / or tantalum nitride; and / or the material of the second barrier layer includes titanium and / or tantalum.
9. A semiconductor structure, characterized in that include: A stacked structure comprising at least two layers of semiconductor units stacked and connected in a vertical direction, wherein each layer of the semiconductor units comprises a dielectric layer and a metal interconnection structure embedded in the dielectric layer; and a via is provided in the dielectric layer of the semiconductor unit located on the topmost layer in the vertical direction, wherein the via exposes the metal interconnection structure in the semiconductor unit located on the topmost layer; a metal silicide layer, located on the sidewalls and bottom of the via hole and connected to the metal interconnect structure; a top surface of the metal silicide layer is flush with a top surface of the dielectric layer; A conductive layer is located on the metal silicide layer and fills the via hole; and a top surface of the conductive layer is flush with a top surface of the dielectric layer.
10. The semiconductor structure according to claim 9, wherein: The semiconductor structure further comprises: A diffusion barrier layer conformally covers the sidewalls and bottom of the via hole and is connected to the metal interconnect structure exposed at the bottom of the via hole; the top surface of the diffusion barrier layer is flush with the top surface of the dielectric layer, and the metal silicide layer is located on the surface of the diffusion barrier layer.
11. The semiconductor structure according to claim 10, wherein: The diffusion barrier layer comprises: a first barrier layer conformally covering the sidewalls of the via hole; The second barrier layer conformally covers the surface of the first barrier layer and the metal interconnection structure exposed at the bottom of the via hole.
12. The semiconductor structure according to claim 11, wherein: The material of the first barrier layer includes titanium nitride and / or tantalum nitride; and / or the material of the second barrier layer includes titanium and / or tantalum.
13. The semiconductor structure according to any one of claims 9 to 12, characterized in that: The material of the metal silicide layer includes cobalt silicide and / or nickel silicide.
14. The semiconductor structure according to any one of claims 9 to 12, wherein: The thickness of the metal silicide layer is less than or equal to 100 nm.
15. A memory, characterized in that: The semiconductor structure comprises the semiconductor structure according to any one of claims 9 to 14.