A capacitance-enhanced ring isolator structure

Abstract

The application provides a kind of loop isolator structure of capacitance enhancement, common ground electrical connection is realized by forming ground metal boss structure, the distance between ground metal and multi-path rejection structure is significantly reduced, the ground capacitance of multi-path rejection structure is significantly improved, and bandwidth expansion is realized by capacitance-inductance cooperative tuning at the same time;2-order LC matching network is used in three radio frequency ports, the slotted part of matching capacitor can make matching inductor and matching capacitor share space to a certain extent, thereby effectively reducing the size of matching network, the absorbing port uses 1-order LC matching network, impedance matching of the absorbing port is realized under the condition of only increasing a single resistance, while realizing good absorption effect, the size of matching network can also be reduced, which helps to reduce the size of non-reciprocal central node structure;In addition, the first non-reciprocal central node structure and the second non-reciprocal central node structure use L-C-L type matching network for conjugate matching, so as to realize good isolation performance.

Description

Technical Field

[0001] This invention relates to the field of microwave integrated devices, and in particular to a capacitance-enhanced ring isolator structure. Background Technology

[0002] In wireless communication and radar systems, the loop isolator, as a core passive device, undertakes key functions such as signal channel isolation, impedance matching, antenna multiplexing, and same-frequency duplexing. Compared with RF switches, the loop isolator utilizes the non-reciprocal transmission characteristic of a gyromagnetic material under an applied bias magnetic field, enabling electromagnetic waves to propagate unidirectionally along a loop path. This effectively suppresses signal crosstalk between the transmitting and receiving channels. It achieves natural isolation without the need for dynamic control circuitry, avoiding the power amplifier (PA) load pulling effect caused by impedance mismatch, and greatly improving the stability and performance of the system.

[0003] Currently, common ring isolators are mainly of waveguide and microstrip types. Waveguide ring isolators operate on the principle of a metal waveguide cavity and ferrite loading structure, utilizing the non-reciprocal transmission characteristics of TE mode electromagnetic waves to achieve isolation. Their advantages include low insertion loss and high power capacity, but they are limited by the physical size constraints of waveguide structures in the millimeter-wave band, making it difficult to meet the miniaturization, lightweighting, and planar integration requirements of modern communication equipment. Microstrip ring isolators employ a planar design, achieving non-reciprocal transmission through electromagnetic coupling between the microstrip line and the ferrite substrate. Thanks to their compact planar layout, they are easier to integrate with low-temperature co-fired ceramic modules, gradually becoming the mainstream choice for miniaturized transceiver components.

[0004] However, most microstrip ring isolators are obtained by co-firing ferrite and high-dielectric ceramics, which has many defects and low microstrip line precision. At the same time, the vertical vias made by this process require mechanical drilling or laser ablation, which is difficult to form and the rough surface of the vias will introduce additional losses in high-frequency signal transmission. In addition, existing silicon-based ferrite ring isolators usually use planar substrate design. Due to the low dielectric constant of silicon-based materials, it is difficult to compress the size of the ring isolator and cannot meet the needs of miniaturization and integration.

[0005] Therefore, there is an urgent need for a new type of ring isolator design that can improve line accuracy without introducing additional losses, while also taking into account the smaller size design to meet the needs of miniaturization and integration, thereby meeting the requirements of communication systems and millimeter-wave radar systems for high-performance, highly integrated RF front-end modules.

[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating the understanding of those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because these solutions have been described in the background section of this application. Summary of the Invention

[0007] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a capacitance-enhanced ring isolator structure to solve the problems of numerous defects in the prior art of microstrip ring isolators, low microstrip line precision, difficulty in forming vertical vias, and difficulty in reducing the size of the ring isolator due to the low dielectric constant of silicon-based materials.

[0008] To achieve the above objectives, the present invention provides a capacitance-enhanced ring isolator structure, wherein the ring isolator structure comprises, from bottom to top:

[0009] Kovar metal layer and a first conductive layer disposed on the Kovar metal layer;

[0010] A first silicon substrate has a first metal layer on its front side and a second metal layer on its back side. The second metal layer and the first conductive layer are electrically connected. A ground metal boss structure is formed on the back side of the first silicon substrate. The ground metal boss includes a cavity and a third metal layer disposed inside the cavity.

[0011] The first through hole is disposed in the first silicon substrate on one side of the ground metal boss, and the two ends of the first through hole are respectively connected to the first metal layer and the second metal layer.

[0012] A resistive layer is located on the front side of the first silicon substrate, and the resistive layer and the first via are located on the same side of the ground metal boss.

[0013] The second through hole is coaxially arranged with the ground metal boss and is used to accommodate the ferrite substrate. One end of the ferrite substrate is in contact with the Kovar metal layer, and the other end of the ferrite substrate is in contact with the fourth metal layer.

[0014] A second silicon substrate has a fourth metal layer on its back side, which is bonded to the second metal layer. A cascaded first circulator and a second circulator are formed on the back side of the second silicon substrate.

[0015] A permanent magnet is disposed on the front side of the second silicon substrate, and an insulating pad is provided between the permanent magnet and the second silicon substrate.

[0016] Optionally, the ground metal boss includes a first ground metal boss and a second ground metal boss. The first ground metal boss is located below the first circulator and is coaxially arranged with the first circulator. The second ground metal boss is located below the second circulator and is coaxially arranged with the second circulator.

[0017] Optionally, both the first and second ground metal bosses include a central ring and ear pieces distributed circumferentially along the central ring.

[0018] Optionally, the first circulator includes a first non-reciprocal central node structure, the second circulator includes a second non-reciprocal central node structure, and the first non-reciprocal central node structure and the second non-reciprocal central node structure are connected by a fifth matching network.

[0019] Optionally, the first non-reciprocal central junction structure includes a first multi-path impedance structure, a first radio frequency port, a first matching network matched with the first radio frequency port, a second radio frequency port, and a second matching network matched with the second radio frequency port, wherein the first radio frequency port and the second radio frequency port are symmetrically distributed with respect to the first multi-path impedance structure.

[0020] Optionally, the second non-reciprocal central junction structure includes a second multiplexed impedance structure, a third radio frequency port, a third matching network matched with the third radio frequency port, and an absorption port of an integrated resistor, wherein the absorption port of the integrated resistor forms an electrical connection with the resistive layer.

[0021] Optionally, the first matching network includes a first-stage matching inductor, a second-stage matching inductor, a first-stage matching capacitor, and a second-stage matching capacitor. The first matching network, the second matching network, and the third matching network have the same structure, and the first matching network and the second matching network are symmetrically distributed about the first multi-channel reactance structure.

[0022] Optionally, both the first multi-path impedance structure and the second multi-path impedance structure include a central disk and a first microstrip line group, a second microstrip line group, and a third microstrip line group connected to the central disk. The central disk is located directly above the central ring, and the first microstrip line group, the second microstrip line group, and the third microstrip line group are located directly above the ear piece and are evenly distributed along the circumference.

[0023] Optionally, the first microstrip line group, the second microstrip line group, and the third microstrip line group each include 3 to 5 microstrip lines, which are distributed in parallel; and the first microstrip line group, the second microstrip line group, and the third microstrip line group contain the same number of microstrip lines.

[0024] Optionally, the diameter of the first through hole is in the range of 20 to 60 μm, and a connecting metal is formed inside the first through hole.

[0025] As described above, the present invention provides a capacitance-enhanced ring isolator structure, which has the following beneficial effects:

[0026] This invention reduces the spacing between the first and second multi-path reactance structures by forming a ground metal boss structure and a third metal layer electrically connected to the first metal layer in the first silicon substrate. This significantly improves the ground capacitance of the multi-path reactance structure, thereby greatly reducing the size of the non-reciprocal center junction structure. Simultaneously, bandwidth expansion is achieved through capacitor-inductor synergistic tuning. The first to third matching networks employ second-order LC matching networks, and the slotted portion of the matching capacitor allows for a certain degree of space sharing between the matching inductor and the matching capacitor, effectively reducing the size of the first to third matching networks. Furthermore, the absorption port employs a first-order LC network. The matching network, combined with resistor parasitic parameter tuning, achieves impedance matching at the absorption port by adding only a single resistor, achieving good absorption while reducing the size of the matching circuit. Furthermore, the first non-reciprocal center junction structure and the second non-reciprocal center junction structure are conjugate matched using an LCL-type matching network, thereby achieving good isolation performance. Compared with traditional multi-path impedance structures, the structure of this invention can significantly reduce size and lower the requirements for the surface roughness of the ferrite substrate, which helps to improve product assembly yield and product consistency. It has good application prospects in satellite communication, radar, electronic countermeasures and other fields. Attached Figure Description

[0027] Figure 1 The diagram shown is a cross-sectional view of the capacitor-enhanced annular isolator structure in an embodiment of the present invention.

[0028] Figure 2 The diagram shown is a top view of the first and second circulators in an embodiment of the present invention.

[0029] Figure 3 The diagram shown is a top view of the metal boss in an embodiment of the present invention.

[0030] Figures 4-6 The figure shown is a simulation data diagram of the S-parameters of the capacitor-enhanced ring isolator structure in an embodiment of the present invention.

[0031] Component designation explanation

[0032] 10. Kovar metal layer; 11. First conductive layer; 12. First silicon substrate; 13. Second metal layer; 14. First metal layer; 15. Ground metal boss; 151. Cavity; 152. Third metal layer; 153. First ground metal boss; 1531. Ear; 1532. Central ring; 154. Second ground metal boss; 16. First through-hole; 17. Resistive layer; 18. Fourth metal layer; 19. Second silicon substrate; 201. Second through-hole; 20. Ferrite substrate; 21. Insulating pad 22. Permanent magnet; 23. First circulator; 230. Second-stage matching capacitor; 231. First microstrip line group; 232. Second microstrip line group; 233. Third microstrip line group; 234. Central disk; 235. Second RF port; 236. First RF port; 237. First-stage matching inductor; 238. First-stage matching capacitor; 239. Second-stage matching inductor; 24. Second circulator; 241. Third RF port; 242. Absorption port; 243. Fourth matching network. Detailed Implementation

[0033] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0034] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0035] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the accompanying drawings for devices in use or operation.

[0036] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0037] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0038] like Figure 1 As shown, the present invention provides a capacitance-enhanced ring isolator structure, which comprises, from bottom to top, the following:

[0039] Kovar metal layer 10 and a first conductive layer 11 disposed on Kovar metal layer 10;

[0040] A first silicon substrate 12 has a first metal layer 14 on its front side and a second metal layer 13 on its back side. The second metal layer 13 is electrically connected to the first conductive layer 11. A ground metal boss 15 structure is formed on the back side of the first silicon substrate 12. The ground metal boss 15 includes a cavity 151 and a third metal layer 152 disposed inside the cavity 151.

[0041] The first through hole 16 is disposed in the first silicon substrate 12 on one side of the ground metal boss 15, and the two ends of the first through hole 16 are respectively connected to the first metal layer 14 and the second metal layer 13.

[0042] A resistive layer 17 is located on the front side of the first silicon substrate 12 and the resistive layer 17 and the first via 16 are located on the same side of the ground metal boss 15.

[0043] The second through hole 201 is coaxially arranged with the ground metal boss 15 and is used to accommodate the ferrite substrate 20. One end of the ferrite substrate 20 is in contact with the Kovar metal layer 10 and the other end of the ferrite substrate 20 is in contact with the fourth metal layer 18.

[0044] A second silicon substrate 19 has a fourth metal layer 18 on its back side, which is bonded to the second metal layer 13. A cascaded first circulator 23 and a second circulator 24 are formed on the back side of the second silicon substrate 19.

[0045] A permanent magnet 22 is disposed on the front side of the second silicon substrate 19, and an insulating pad 21 is provided between the permanent magnet 22 and the second silicon substrate 19.

[0046] In one embodiment, such as Figure 1As shown, the material forming the Kovar metal layer 10 is an Fe-Ni-Co alloy, which generally consists of Fe (54% wet), Ni (29% wet), Co (17% wet), and trace amounts of other components such as Si and Mn. The thickness of the Kovar metal layer 10 is 50–300 μm, for example, it can be 50 μm, 150 μm, 250 μm or 300 μm. The specific thickness of the Kovar metal layer 10 can be set according to the size of the annular isolator structure required by actual needs, and is not limited here.

[0047] In one embodiment, such as Figure 1 As shown, a first conductive layer 11 is formed above the Kovar metal layer 10. The materials forming the first conductive layer 11 include, but are not limited to, metal solder and conductive adhesive. The first conductive layer 11 and the Kovar metal layer 10 have good electrical and thermal conductivity and a low coefficient of thermal expansion. The thickness of the first conductive layer 11 is 10 to 50 μm, for example, it can be 10 μm, 30 μm or 50 μm, and there is no limitation here.

[0048] In some embodiments, such as Figure 1 As shown, a first metal layer 14 and a second metal layer 13 are respectively disposed on the front and back sides of the first silicon substrate 12. The material forming the first silicon substrate 12 is high-resistivity silicon. The materials of the first metal layer 14 and the second metal layer 13 include, but are not limited to, gold, copper, or tungsten. The second metal layer 13 and the first conductive layer 11 can be soldered together by gold-tin sintering to form an electrical connection. The thickness of the first silicon substrate 12 is 80-400 μm, for example, it can be 80 μm, 250 μm, or 400 μm. The thickness of the first metal layer 14 is 2-20 μm, and the thickness of the second metal layer 13 is 2-20 μm, for example, it can be 2 μm, 10 μm, or 20 μm, without limitation. A cavity 151 is formed by etching a second metal layer 13 and the first silicon substrate 12 from the back side of the first silicon substrate 12. The cavity 151 is used to fill a ferrite sheet (i.e., a ferrite substrate 20). A third metal layer 152 is also formed inside the cavity 151. The material forming the third metal layer 152 includes, but is not limited to, gold, copper, or tungsten. The third metal layer 152 and the second metal layer 13 are welded together by gold-tin sintering to form an electrical connection. The cavity 151 and the third metal layer 152 inside it form a ground metal boss 15 structure. Since the third metal layer 152, the second metal layer 13 and the first conductive layer 11 are connected to a common ground, the distance between the ground metal and the multi-path reactance structure is significantly reduced, thereby significantly improving the ground capacitance of the multi-path reactance structure.

[0049] In some embodiments, such as Figure 1As shown, a first via 16 is formed in the first silicon substrate 12. The first via 16 is located on one side of the ground metal boss 15 structure, for example, it can be located on the left or right side of the ground metal boss 15 structure. There is no limitation here, but it should be noted that the position of the first via 16 should be on the same side as the position of the resistive layer 17. The diameter of the first via 16 is in the range of 20 to 60 μm. Since the two ends of the first via 16 are respectively connected to the first metal layer 14 and the second metal layer 13, a connecting metal layer is also formed in the first via 16. The material of the connecting metal layer includes, but is not limited to, copper, gold or other metals. In addition, a resistive layer 17 is also formed on the front side of the first silicon substrate 12. The material of the resistive layer 17 includes, but is not limited to, TaN, NiCr, TiW. The thickness of the resistive layer 17 is 15 to 50 nm. The two ends of the resistive layer 17 are respectively connected to the circuit structure of the first circulator 23 and the second circulator 24 formed in the first metal layer 14.

[0050] like Figure 1 As shown, a photolithography process is performed on the front side of the first silicon substrate 12 to form a second via 201. The second via 201 is coaxially arranged with the ground metal boss 15 structure and the second via 201 is connected to the cavity 151 of the ground metal boss 15 to accommodate a ferrite substrate 20. One end of the ferrite substrate 20 is in contact with the Kovar metal layer 10.

[0051] In some embodiments, such as Figure 1 As shown, a second silicon substrate 19 and a fourth metal layer 18 disposed on the back side of the second silicon substrate 19 are disposed at the other end of the ferrite substrate 20. The fourth metal layer 18 is bonded to and interconnected with the second metal layer 13, and the fourth metal layer 18 is also connected to the other end of the ferrite substrate 20. Optionally, the material forming the second silicon substrate 19 is high-resistivity silicon, and the material forming the fourth metal layer 18 includes, but is not limited to, gold, copper, or tungsten. The thickness of the second silicon substrate 19 is 80 to 400 μm, for example, it can be 80 μm, 250 μm, or 400 μm, and the thickness of the fourth metal layer 18 is 2 to 20 μm, for example, it can be 2 μm, 10 μm, or 20 μm, without limitation here.

[0052] In one embodiment, a cascaded first circulator 23 and a second circulator 24 are also formed in the fourth metal layer 18 and the third metal layer 152, wherein the first circulator 23 includes a first non-reciprocal central node structure, the second circulator 24 includes a second non-reciprocal central node structure, and the first non-reciprocal central node structure and the second non-reciprocal central node structure are connected by a fifth matching network.

[0053] As an example, both the first ground metal boss 153 and the second ground metal boss 154 include a central ring 1532 and ear pieces 1531 distributed circumferentially along the central ring 1532.

[0054] Specifically, such as Figure 2 and Figure 3 As shown, the ground metal boss 15 includes a first ground metal boss 153 and a second ground metal boss 154. The first ground metal boss 153 is located below the first circulator 23 and is coaxially arranged with the first circulator 23. The second ground metal boss 154 is located below the second circulator 24 and is coaxially arranged with the second circulator 24. Both the first ground metal boss 153 and the second ground metal boss 154 include a central ring 1532 and ear pieces 1531 distributed circumferentially along the central ring 1532. Microstrip line groups are formed on the ear pieces 1531. Cascaded first circulator 23 and second circulator 24 are formed on the central ring 1532.

[0055] Specifically, the fifth matching network includes an LCL-type matching network, which enables the first circulator 23 and the second circulator 24 to perform conjugate matching, thereby achieving good signal isolation performance.

[0056] In one embodiment, the first non-reciprocal central junction structure includes a first multiplexed impedance structure, a first radio frequency (RF) port 236, a first matching network matching the first RF port 236, and a second RF port 235 and a second matching network matching the second RF port 235, wherein the first RF port 236 and the second RF port 235 are symmetrically distributed with respect to the first multiplexed impedance structure. Specifically, as shown... Figure 2 As shown, the first matching network includes a second-order LC matching network formed by a first-stage matching inductor 237, a second-stage matching inductor 239, a first-stage matching capacitor 238, and a second-stage matching capacitor 230. The first-stage matching inductors 237 and 239, and the first-stage matching capacitors 238 and 230 are interconnected. The first-stage matching inductors 237 and 239 are implemented using a microstrip structure, and the first-stage matching capacitors 238 and 230 are implemented using a slotted fan-shaped microstrip structure. The slotted portions of the first-stage matching capacitors 238 and 230 allow for a certain degree of space sharing between the first-stage matching inductors 237 and 239 and the first-stage matching capacitors 238 and 230, thereby effectively reducing the size of the first matching network. Furthermore, the ground metal boss 15 structure also increases the ground capacitance of the slotted fan-shaped microstrip structure, further reducing the size of the first-stage matching capacitors 238 and 230. Figure 2As shown, the structure of the second matching network is the same as that of the first matching network, and the first matching network and the second matching network are symmetrically distributed about the first multi-path additive structure. Based on the same principle, the size of the second matching network can also be effectively reduced.

[0057] In one embodiment, the first multi-path impedance structure includes a central disk 234 and a first microstrip line group 231, a third microstrip line group 233, and the first microstrip line group 231 connected to the central disk 234. Specifically, as shown... Figure 2 and Figure 3 As shown, the central disk 234 is located directly above the central ring 1532. The first microstrip line group 231, the second microstrip line group 232, and the third microstrip line group 233 are located directly above the lug 1531 and are evenly distributed along the circumference, i.e., the first microstrip line group 231, the second microstrip line group 232, and the third microstrip line group 233 are distributed at an angle of 120°. Each of these groups includes 3 to 5 microstrip lines, and the number of microstrip lines in each group is the same. Preferably, in this embodiment, each of the first microstrip line group 231, the second microstrip line group 232, and the third microstrip line group 233 includes 3 microstrip lines, and the 3 microstrip lines are distributed parallel to each other.

[0058] In one embodiment, the second non-reciprocal central junction structure includes a second multiplexed impedance structure, a third RF port 241, a third matching network matched with the third RF port 241, an absorption port 242 of the integrated resistor, and a fourth matching network 243 matched with the absorption port 242 of the integrated resistor. The fourth matching network 243 forms an electrical connection with the resistor layer 17. Specifically, as shown... Figure 2As shown, the structure of the third matching network is the same as that of the first matching network, both comprising a second-order LC matching network formed by a first-stage matching inductor 237, a second-stage matching inductor 239, a first-stage matching capacitor 238, and a second-stage matching capacitor 230. The first-stage matching inductors 237, 239, 238, and 230 are interconnected. The first-stage matching inductors 237 and 239 are implemented using a microstrip structure, while the first-stage matching capacitors 238 and 230 are implemented using a slotted fan-shaped microstrip structure. The slotted portions of the first-stage matching capacitors 238 and 230 allow for a certain degree of space sharing between the first-stage matching inductors 237 and 239 and the first-stage matching capacitors 238 and 230, thereby effectively reducing the size of the third matching network.

[0059] like Figure 2 As shown, a fourth matching network 243 matching the absorption port 242 of the integrated resistor is provided. The fourth matching network 243 uses a first-order LC matching network to adjust the impedance to a specific point, and then uses the parasitic parameters of the resistor layer 17 itself to achieve matching. This not only achieves good absorption of the isolation signal, but also reduces the size of the fourth matching network 243.

[0060] In one embodiment, a permanent magnet 22 is further disposed on the front side of the second silicon substrate 19, and an insulating pad 21 is provided between the permanent magnet 22 and the second silicon substrate 19. The permanent magnet 22, the insulating pad 21, and the ferrite substrate 20 are coaxially arranged in the vertical direction. The thickness of the insulating pad 21 is 50-400 μm; the permanent magnet 22 is made of samarium cobalt and has a thickness of 400-3000 μm. The permanent magnet 22 provides a constant bias magnetic field, thereby achieving a signal circulation effect and ultimately enabling low-loss signal transmission.

[0061] like Figures 4 to 6 As shown, it displays the S-parameter simulation results obtained after performing a three-dimensional electromagnetic simulation of the capacitor-enhanced ring isolator structure of the present invention. Figure 4 It can be seen that within the 8.8–10.5 GHz frequency band, the insertion loss is less than 0.7 dB, the isolation is better than 30 dB, and the return loss is better than 20 dB.

[0062] In summary, this invention achieves a common ground connection by forming a ground metal boss structure and a third metal layer electrically connected to the first metal layer in the first silicon substrate. This significantly reduces the spacing between the ground metal and the multi-path reactance structure, significantly improves the ground capacitance of the multi-path reactance structure, and simultaneously achieves bandwidth expansion through capacitor-inductor synergistic tuning. The first to third matching networks adopt a second-order LC matching network, where the first-stage matching inductor and the second-stage matching inductor are implemented using a microstrip structure, and the first-stage matching capacitor and the second-stage matching capacitor are implemented using a slotted fan-shaped microstrip structure. The slotted portions of the first-stage matching capacitor and the second-stage matching capacitor allow for a certain degree of space sharing between the first-stage matching inductor and the first-stage matching capacitor, thereby effectively reducing the size of the first matching network. Furthermore, The ground metal boss structure also increases the ground capacitance of the slotted fan-shaped microstrip structure, effectively reducing the size of the first to third matching networks. Furthermore, the absorption port uses a first-order LC matching network combined with resistor parasitic parameter tuning, achieving impedance matching at the absorption port with only a single added resistor. This achieves good absorption while reducing the size of the matching network, thus helping to reduce the size of the non-reciprocal center junction structure. In addition, the first and second non-reciprocal center junction structures use an LCL-type matching network for conjugate matching, achieving good isolation performance. Compared to traditional multi-path impedance structures, the structure of this invention reduces the requirements for the surface roughness of the ferrite substrate, helping to improve product assembly yield and product consistency, and has good application prospects in satellite communication, radar, electronic countermeasures, and other fields.

[0063] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0064] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A capacitor-enhanced ring isolator structure, characterized in that, The ring isolator structure comprises, from bottom to top: Kovar metal layer and a first conductive layer disposed on the Kovar metal layer; A first silicon substrate has a first metal layer on its front side and a second metal layer on its back side. The second metal layer and the first conductive layer are electrically connected. A ground metal boss structure is formed on the back side of the first silicon substrate. The ground metal boss includes a cavity and a third metal layer disposed inside the cavity. The first through hole is disposed in the first silicon substrate on one side of the ground metal boss, and the two ends of the first through hole are respectively connected to the first metal layer and the second metal layer. A resistive layer is located on the front side of the first silicon substrate, and the resistive layer and the first via are located on the same side of the ground metal boss. The second through hole is coaxially arranged with the ground metal boss and is used to accommodate the ferrite substrate. One end of the ferrite substrate is in contact with the Kovar metal layer. A second silicon substrate has a fourth metal layer on its back side, which is bonded to and interconnected with the second metal layer. The fourth metal layer is also in contact with the other end of the ferrite substrate. A cascaded first circulator and a second circulator are formed on the back side of the second silicon substrate. A permanent magnet is disposed on the front side of the second silicon substrate, and an insulating pad is provided between the permanent magnet and the second silicon substrate.

2. The capacitance-enhanced ring isolator structure according to claim 1, characterized in that, The ground metal protrusion includes a first ground metal protrusion and a second ground metal protrusion. The first ground metal protrusion is located below the first circulator and is coaxially arranged with the first circulator. The second ground metal protrusion is located below the second circulator and is coaxially arranged with the second circulator.

3. The capacitance-enhanced ring isolator structure according to claim 2, characterized in that, Both the first and second ground metal bosses include a central ring and ear pieces distributed circumferentially along the central ring.

4. The capacitance-enhanced ring isolator structure according to claim 3, characterized in that, The first circulator includes a first non-reciprocal central node structure, and the second circulator includes a second non-reciprocal central node structure. The first non-reciprocal central node structure and the second non-reciprocal central node structure are connected by a fifth matching network.

5. The capacitance-enhanced ring isolator structure according to claim 4, characterized in that, The first non-reciprocal central junction structure includes a first multi-path impedance structure, a first radio frequency port, a first matching network matching the first radio frequency port, a second radio frequency port, and a second matching network matching the second radio frequency port, wherein the first radio frequency port and the second radio frequency port are symmetrically distributed with respect to the first multi-path impedance structure.

6. The capacitance-enhanced ring isolator structure according to claim 5, characterized in that, The second non-reciprocal central junction structure includes a second multiplexed impedance structure, a third radio frequency port, a third matching network matched with the third radio frequency port, and an absorption port of an integrated resistor, wherein the absorption port of the integrated resistor forms an electrical connection with the resistor layer.

7. The capacitance-enhanced ring isolator structure according to claim 6, characterized in that, The first matching network includes a first-stage matching inductor, a second-stage matching inductor, a first-stage matching capacitor, and a second-stage matching capacitor. The first matching network, the second matching network, and the third matching network have the same structure, and the first matching network and the second matching network are symmetrically distributed about the first multi-channel reactance structure.

8. The capacitance-enhanced ring isolator structure according to claim 7, characterized in that, Both the first and second multi-path impedance structures include a central disk and a first microstrip line group, a second microstrip line group, and a third microstrip line group connected to the central disk. The central disk is located directly above the central ring, and the first, second, and third microstrip line groups are located directly above the ear piece and are evenly distributed along the circumference.

9. The capacitor-enhanced ring isolator structure according to claim 8, characterized in that, The first microstrip line group, the second microstrip line group, and the third microstrip line group each include 3 to 5 microstrip lines, which are distributed in parallel; and the first microstrip line group, the second microstrip line group, and the third microstrip line group contain the same number of microstrip lines.

10. The capacitance-enhanced ring isolator structure according to claim 1, characterized in that: The diameter of the first through hole is in the range of 20~60μm, and a connecting metal is formed inside the first through hole.

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