Level shifter for power electronic circuit

Abstract

The invention relates to a level shifter for a power electronic circuit. A level shifter includes a current pulse generation circuit coupled to a first power rail and a first (ground) reference rail and configured to output non-overlapping first and second current pulses based on opposite edges of a logic input signal; a latch and a current mirror circuit coupled to the second power rail and the second reference rail, the current mirror circuit configured to mirror non-overlapping first and second current pulses such that the latch is set when the first current pulse is active and reset when the second current pulse is active; and a voltage clearance circuit configured to mitigate a voltage clearance loss between the second power rail and the first reference rail independent of a potential difference of the second reference rail. A power electronic circuit including the level shifter is also described.

Description

Technical Field

[0001] The present disclosure relates to level shifters, and more particularly to level shifters for power electronic circuits. Background Art

[0002] Power converters, such as half-bridge and full-bridge converters, typically use a bootstrap technique that includes a bootstrap capacitor to create a floating voltage domain to drive one or more high-side power switches of the power converter. In a typical DC-DC buck converter application, there is a deadtime between the activation of the high-side power switch and the activation of the low-side power switch, during which all power switches are off. During this deadtime, the output inductor forces current to flow, forcing the power converter's switch node to a negative value. If silicon transistors are used to implement the power switches, the low-side power switch has a body diode that limits the negative voltage at the switch node to approximately -0.7V. If GaN transistors are used to implement the low-side power switch, the low-side power switch does not have a body diode, but can conduct current if the voltage between the drain and gate creates a channel. In this case, the power converter's switch node is forced to a more negative voltage (such as in the range of -2V to -5V).

[0003] Due to the presence of the bootstrap capacitor, the bootstrap node, which serves as the positive supply voltage for the high-side driver, follows the power converter's switch node down to near ground. To exit deadtime mode, the high-side driver's input control triggers, sending the signal from the low-voltage input domain to the high-side domain through the level shifter, ultimately triggering the driver for the high-side power switch. When the high-side input is activated to trigger the high-side power switch, the power converter's switch node goes negative. Because there is a floating supply (e.g., 5V) and the level shifter is referenced to a fixed 0V, there is insufficient voltage headroom to power the level shifter to propagate the current signal.

[0004] Therefore, there is a need for a level shifter design with improved voltage headroom for power converter applications. Summary of the Invention

[0005] According to an embodiment of a level shifter, the level shifter includes: a current pulse generating circuit coupled to a first power rail and a first reference rail and configured to output non-overlapping first and second current pulses based on opposite edges of a logic input signal, the first reference rail being grounded; a latch and current mirror circuit coupled to a second power rail and a second reference rail, the current mirror circuit being configured to mirror the non-overlapping first and second current pulses such that the latch is set when the first current pulse is valid and reset when the second current pulse is valid; and a voltage headroom circuit configured to mitigate voltage headroom loss between the second power rail and the first reference rail independent of a potential difference of the second reference rail.

[0006] According to an embodiment of a power electronic circuit, the power electronic circuit includes: a power converter circuit including a high-side GaN switching device coupled in series with a low-side GaN switching device at a switching node; a first gate driver configured to drive a gate of the low-side GaN switching device; and a second gate driver configured to drive a gate of the high-side GaN switching device, wherein the second gate driver includes: a current pulse generation circuit coupled to a first power rail and a first reference rail and configured to output non-overlapping first and second current pulses based on opposite edges of a logic input signal, the first reference rail being grounded; a latch and current mirror circuit coupled to a second power rail and a second reference rail, the current mirror circuit configured to mirror the non-overlapping first and second current pulses such that the latch is set when the first current pulse is valid and reset when the second current pulse is valid, the second reference rail corresponding to the switching node of the power converter circuit; and a voltage headroom circuit configured to mitigate voltage headroom loss between the second power rail and the first reference rail independent of a potential difference of the second reference rail.

[0007] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The elements of the drawings are not necessarily to scale with respect to each other. The same reference numerals denote corresponding similar parts. The features of the various illustrated embodiments may be combined unless they are mutually exclusive. The embodiments are depicted in the drawings and described in detail in the following description.

[0009] Figure 1 A schematic diagram of an embodiment of a power electronics circuit including a level shifter with a voltage headroom circuit for mitigating voltage headroom losses is illustrated.

[0010] Figure 2 FIG2 shows a circuit diagram of a level shifter according to an embodiment.

[0011] Figure 3 FIG. 1 is a circuit diagram of a level shifter according to another embodiment. DETAILED DESCRIPTION

[0012] Embodiments described herein provide a level shifter having a voltage headroom circuit for mitigating voltage headroom losses. The level shifter can be used in power electronics applications such as half-bridge and full-bridge converters. The level shifter also includes a current pulse generating circuit, a latch, and a current mirror circuit. The current pulse generating circuit is coupled to a first power rail and a first reference rail and outputs non-overlapping first (set) current pulses and second (reset) current pulses based on opposing edges of a logic input signal, wherein the first reference rail is grounded. The latch and current mirror circuit are coupled to a second power rail and a second reference rail. The current mirror circuit mirrors the non-overlapping set current pulses and reset current pulses such that the latch is set when the first current pulse is active and reset when the second current pulse is active. The second reference rail is designed to be coupled to a switch node of a power converter circuit so that the power converter circuit has a variable potential difference when in use. The voltage headroom circuit mitigates voltage headroom losses between the second power rail and the first reference rail independently of the potential difference of the second reference rail. This allows the level shifter to propagate a current signal used to drive the high-side GaN switching device of the power converter circuit even when the switch node of the power converter circuit is at a negative potential, such as -2V, -5V, or even -8V.

[0013] Exemplary embodiments of a level shifter and a power electronic circuit including the level shifter are described below with reference to the accompanying drawings.

[0014] Figure 1 A schematic diagram of an embodiment of a power electronic circuit 100 including a level shifter 102 is illustrated. The power electronic circuit 100 may be part of a power electronic circuit assembly used in various power applications, such as in a DC / AC converter, a DC / DC converter, an AC / DC converter, a DC / AC converter, an AC / AC converter, a multiphase converter, an H-bridge, etc. For example, the power electronic circuit 100 may be configured as a buck, a boost, or a buck-boost converter by coupling an output inductor (not shown) to a switching node Vsw of the power electronic circuit 100.

[0015] The switching node Vsw of the power electronic circuit 100 is formed by coupling the high-side GaN switching device GaN1 in series with the low-side GaN switching device GaN2, and the switching node Vsw has a variable potential difference when the power electronic circuit 100 is in use. Depending on the DC bus voltage Vin+ and Vin- applied across the series-connected GaN switching devices GaN1 and GaN2, the voltage Vsw at the switching node can drop from 400V (e.g., 100V) to 0V, -2V, -5V, or even -8V. For example, depending on the current requirements of the load (not shown), the high-side GaN switching device GaN1 and the low-side GaN switching device GaN2 can each be implemented by a single GaN power transistor or by two or more GaN power transistors coupled in parallel.

[0016] The power electronics circuit 100 also includes a high-side (HS) gate driver 104 for driving the gate of the high-side GaN switch device GaN1 and a low-side (LS) gate driver 106 for driving the gate of the low-side GaN switch device GaN2. For example, the gate drive signal may be a current signal. A high-side deadtime circuit 108 and a low-side deadtime circuit 110 ensure that the high-side GaN switch device GaN1 and the low-side GaN switch device GaN2 are not turned on simultaneously. The on / off control of the high-side GaN switch device GaN1 and the low-side GaN switch device GaN2 is directed by a logic input signal (such as a PWM (pulse width modulation) signal) generated by a controller 112. A power supply 114 provides power, such as 5V, to the power electronics circuit 100. An isolated DC-DC converter 116 receives a power supply input (e.g., +5V or other voltage level) and provides two isolated outputs (e.g., 8V or other voltage level) to the gate drivers 104 and 106.

[0017] In a typical DC-DC buck converter application, deadtime circuits 108 and 110 impose a deadtime during the interval between the activation of the high-side GaN switch device GaN1 and the activation of the low-side GaN switch device GaN2. During this deadtime, both GaN switch devices GaN1 and GaN2 are off. During this deadtime, the output inductor (not shown) forces current to flow, and as a result, the switch node Vsw of the power electronic circuit 100 is forced to a negative value. Because GaN transistors are used to implement the power switches GaN1 and GaN2, the low-side GaN switch device GaN2 does not have a body diode. However, if the voltage between the drain and gate creates a channel, the low-side GaN switch device GaN2 can conduct current. Therefore, the switch node Vsw of the power electronic circuit 100 can be forced to a more negative voltage (such as in the range of -2V to -5V or even more negative (e.g., -8V)).

[0018] If left unmitigated, the voltage headroom loss caused by this negative voltage at the switch node Vsw of the power electronic circuit 100 typically means that the high-side GaN switch device GaN1 cannot be properly driven. At switch node voltages of -2V or more negative, there is little to no voltage headroom, and the gate drive current signal cannot reliably propagate from the high-side gate driver 104 to the high-side GaN switch device GaN1, where voltage headroom is the minimum voltage required by the level shifter 102 to ensure gate drive current signal propagation. Without sufficient voltage headroom, the gate drive current signal cannot reliably propagate to the driver 104 for the high-side GaN switch device GaN1.

[0019] However, the level shifter 102 described herein has a voltage headroom circuit that mitigates voltage headroom losses independently of the potential difference of the switch node Vsw. Therefore, even when the switch node Vsw of the power electronic circuit 100 is at a negative voltage, the high-side gate driver 104 is still able to robustly drive the gate of the high-side GaN switch device GaN1. In one embodiment, the potential difference of the switch node Vsw can drop to a voltage in the range of 0V to -8V (e.g., -2V to -5V), and the level shifter 102 still ensures that the high-side gate driver 104 properly drives the gate of the high-side GaN switch device GaN1.

[0020] Figure 2 The figure shows a circuit diagram of a level shifter 102 according to an embodiment. The level shifter 102 includes a current pulse generating circuit 200, a latch 202, and a current mirror circuit 204. The current pulse generating circuit 200 is coupled to a first power rail VDD and a first reference rail VSS, which is connected to ground (gnd). The current pulse generating circuit 200 has two current injection paths that output non-overlapping first (set) current pulses Iset and second (reset) current pulses Irst based on opposite edges of a logic input signal PWM. These two paths are used to set or reset the latch 202.

[0021] The latch 202 and the current mirror circuit 204 are coupled to a second power rail HB and a second reference rail HS, wherein the voltage of the second power rail HB may correspond to the voltage of the bootstrap capacitor Cboot. The current mirror circuit 204 mirrors the non-overlapping first current pulse Iset and second current pulse Irst output by the current pulse generating circuit 200, so that the latch 202 is set when the first current pulse Iset is valid and is reset when the second current pulse Irst is valid. The second reference rail HS corresponds to Figure 1The switching node Vsw of the power electronic circuit 100 is shown and has a variable potential difference when using the power electronic circuit 100. The level shifter 102 includes a voltage headroom circuit that mitigates voltage headroom losses between the second power rail HB and the first reference rail VSS independently of the potential difference of the second reference rail HS.

[0022] If the voltage headroom circuit is omitted, the voltage headroom loss between the second power rail HB and the first reference rail VSS may prevent the current pulse generating circuit 200 from generating sufficient set pulse current Iset and reset pulse current Irst for shifting between the VDD and HB voltage domains. For example, when the second reference rail HS is at 0V, there may be a 5V potential difference between the second power rail HB and the first reference rail VSS. In this example, the 5V headroom is sufficient for the current pulse generating circuit 200 to generate robust set pulse current Iset and reset pulse current Irst, and thus shift between the VDD and HB voltage domains. However, if the second reference rail HS is at -2V, only 3V of headroom is available between the second power rail HB and the first reference rail VSS. At 3V of headroom, the set pulse current Iset and reset pulse current Irst generated by the current pulse generating circuit 200 may not be strong enough to adequately shift between the VDD and HB voltage domains. When the second reference rail HS is at -5V or even -8V, the voltage headroom loss becomes even greater. Under these conditions, there is no voltage headroom for proper operation of the level shifter 102. The voltage headroom circuit advantageously mitigates the voltage headroom loss between the second power rail HB and the first reference rail VSS, regardless of the potential difference of the second reference rail HS.

[0023] exist Figure 2 In FIG, the voltage headroom circuit includes a first diode D1 and a second diode D2. The cathode of the first diode D1 is coupled to the first reference rail VSS, and the anode of the first diode D1 is coupled to the reference node Lsftgnd of the current pulse generating circuit 200. The cathode of the second diode D1 is coupled to the second reference rail HS, and the anode of the second diode D2 is coupled to the reference node Lsftgnd of the current pulse generating circuit 200.

[0024] According to this embodiment, when the second reference rail HS is more positive than the first reference rail VSS, the first diode D1 of the voltage headroom circuit couples the reference node Lsftgnd of the current pulse generating circuit 200 to the first reference rail VSS. Similarly, when the second reference rail HS is more negative than the first reference rail VSS by at least one diode voltage drop, the second diode D2 of the voltage headroom circuit couples the reference node Lsftgnd of the current pulse generating circuit 200 to the second reference rail HS. In other words, the first diode D1 and the second diode D2 of the voltage headroom circuit form a minimum selector between the two reference nodes VSS and HS by selecting the lower of the two reference nodes VSS and HS as the reference node Lsftgnd of the current pulse generating circuit 200. Thus, when the second reference rail HS goes negative, the reference node Lsftgnd of the current pulse generating circuit 200 is pulled below ground, ensuring that sufficient voltage headroom is maintained for the current pulse generating circuit 200 to generate robust set pulse current Iset and reset pulse current Irst, and thus shift between the VDD and HB voltage domains.

[0025] exist Figure 2 In the embodiment of the present invention, the voltage headroom circuit of the level shifter 102 may further include a local voltage source VDDLsftgnd generated from the first power rail VDD and a signal level shifter 206. The signal level shifter 206 shifts the logic input signal PWM from a first domain defined by the first power rail VDD (e.g., 5V or another level) and ground (gnd) to a second domain defined by the local voltage source VDDLsftgnd (e.g., 5V or another level) and the potential at the reference node Lsftgnd of the current pulse generating circuit 200. As described above, the potential at the reference node Lsftgnd of the current pulse generating circuit 200 is at the lower limit of VSS or HS. The corresponding exclusive OR (XOR) logic gates 208 and 210 for the set and reset branches of the current pulse generating circuit 200 output a logic set signal Xor_s or a reset signal Xor_r based on the output of the signal level shifter 206.

[0026] The set branch of the current pulse generation circuit 200 includes a pulse generator 212 (such as a positive-edge pulse generator that generates a set pulse based on the output of the set XOR logic gate 208) and a driver 214 that is also controlled by the output of the set XOR logic gate 208. When the output of the set XOR logic gate 208 goes high (e.g., a logic 1 level), the NMOS transistor M1s, together with the NMOS boost transistor M2s, pulls current through the resistor R1s. The current path including the NMOS transistor M1s, the NMOS boost transistor M2s, and the resistor R1s outputs the set current Iset for the set branch of the current mirror circuit 204.

[0027] The reset branch of the current pulse generation circuit 200 can be symmetrical, having a pulse generator 216 (such as a positive-edge pulse generator for generating pulses based on the output of the reset XOR logic gate 210) and a driver 218 that is also controlled by the output of the reset XOR logic gate 210. When the output of the reset XOR logic gate 210 goes high (e.g., a logic 1 level), the NMOS transistor M1r, in conjunction with the NMOS boost transistor M2r, pulls current through the resistor R1r. The current path including the NMOS transistor M1r, the NMOS boost transistor M2r, and the resistor R1r outputs the reset current Irst for the reset branch of the current mirror circuit 204.

[0028] In one embodiment, the local voltage source VDDLsftgnd of the voltage headroom circuit includes a resistor R2 and a Zener diode DZ1. Resistor R2 is coupled between the first power rail VDD and a voltage node 207 of the current pulse generation circuit 200, which is at a voltage higher than 1sftgnd. The anode of Zener diode DZ1 is coupled to the reference node Lsftgnd of the current pulse generation circuit 200. The cathode of Zener diode DZ1 is coupled to the voltage node 207 of the current pulse generation circuit 200, which is at a voltage higher than 1sftgnd. In this embodiment, Zener diode DZ1 generates the local voltage source VDDLsftgnd by acting as a local regulator. Diode DZ1 of the current pulse generation circuit 200 can be an actual Zener diode or a diode device with a Zener clamp-like function.

[0029] The current mirror circuit 204 has a mirror path for mirroring the first current pulse Iset and the second current pulse Irst generated by the current pulse generating circuit 200. In one embodiment, the mirror paths of the current mirror circuit 204 are symmetrical. For example, both current mirror paths of the current mirror circuit 204 may include PMOS transistors "M3s-M5s" and "M3r-M5r", where the PMOS transistors M3s-M5s of the first (set) current mirror path and the PMOS transistors M3r-M5r of the second (reset) current mirror path have matching transconductances.

[0030] The source of each PMOS transistor M3s-M5s in the first current mirror path is coupled to the second power rail 11B. The gate of each PMOS transistor M3s-M5 in the first current mirror path is driven by the first current pulse Iset generated by the current pulse generation circuit 200. Similarly, the source of each PMOS transistor M3r-M5r in the second current mirror path is coupled to the second power rail HB. The gate of each PMOS transistor M3r-M5r in the second current mirror path is driven by the second current pulse Irst generated by the current pulse generation circuit 200.

[0031] The drain of the first PMOS transistor M3s of the first current mirror path can be coupled to a node 220 of the first current mirror path, into which the first current pulse Iset flows. Similarly, the drain of the first PMOS transistor M3r of the second current mirror path can be coupled to a node 222 of the second current mirror path, into which the second current pulse Irst flows. The first PMOS transistors M3s and M3r of the two current mirror paths are master devices of the corresponding mirror paths, wherein the current of each first PMOS transistor M3s and M3r is set by the corresponding current pulse Iset and Irst generated by the current pulse generation circuit 200 in the low voltage (VDD) domain.

[0032] The drain of the third PMOS transistor M5 of the first current mirror path may be cross-coupled to a node 222 of the second current mirror path, into which the second current pulse Irst flows. The drain of the third PMOS transistor M5r of the second current mirror path may be cross-coupled to a node 220 of the first current mirror path, into which the first current pulse Iset flows.

[0033] The drain of the second PMOS transistor M3s of the first current mirror path can drive the gate of the NMOS transistor M7s of the latch 202. Similarly, the drain of the second PMOS transistor M3r of the second current mirror path can drive the gate of the NMOS transistor M7r of the latch 202. The NMOS transistors M7s and M7r can have sources coupled to the second reference rail HS. The PMOS transistor M6s of the latch 202 can have a drain coupled to the drain of the NMOS transistor M7s and a source coupled to the second power rail HB. Similarly, the PMOS transistor M6r of the latch 202 can have a drain coupled to the drain of the NMOS transistor M7r and a source coupled to the second power rail HB. The latch 202 may have a symmetrical arrangement of buffers 1v1, 1v2, 1v3s, 1v3r, which are cross-coupled via NMOS transistors M7s and M7r and PMOS transistors M6s and M6r to form a memory bit Q and its complement. The latch circuit. The latch output is provided to the high-side gate driver 104, which is used to drive Figure 1 The gate of the high-side GaN switch device GaN1 is shown. Other latch and current mirror circuits can be used.

[0034] Figure 3FIG2 shows a circuit diagram of a level shifter 102 according to another embodiment. According to this embodiment, when the second reference rail HS is more negative than the first reference rail VSS by at least one diode drop, the voltage headroom circuit of the level shifter 102 activates an additional current injection path for setting or resetting the latch 202.

[0035] exist Figure 3 In the embodiment of the present invention, the voltage headroom circuit of the level shifter 102 includes a first additional current injection path 300 and a second additional current injection path 302. When the second reference rail HS is more negative than the first reference rail VSS by at least one diode voltage drop and a first (rising or falling) edge of the logic input signal PWM is detected, for example, by the set XOR logic gate 208 of the current pulse generation circuit 200, the first additional current injection path 300 of the voltage headroom circuit injects an additional current pulse Iset2 into the first (set) branch of the current mirror circuit 204 that mirrors the first (set) current pulse Iset. When the second reference rail HS is more negative than the first reference rail VSS by at least one diode voltage drop and a second (falling or rising) edge of the logic input signal PWM is detected, for example, by the reset XOR logic gate 210 of the current pulse generation circuit 200, the second additional current injection path 302 of the voltage headroom circuit injects an additional current pulse Irst2 into the second (reset) branch of the current mirror circuit 204 that mirrors the second current pulse Irst.

[0036] When the variable potential difference of the second reference rail HS is in the range of 0V to -8V (for example, in the range of -2V to -5V), Figure 3 The amplitudes of the first current pulse Iset and the second current pulse Irst generated by the current pulse generation circuit 200 in the circuit are proportionally reduced according to the potential difference of the second reference rail HS. When the current pulse generation circuit 200 detects a first (rising or falling) edge of the logic input signal PWM, the first additional current injection path 300 of the voltage headroom circuit injects an additional set current pulse Iset2 into the first (set) branch of the current mirror circuit 204. When the current pulse generation circuit 200 detects a second (falling or rising) edge of the logic input signal PWM, the second additional current injection path 302 of the voltage headroom circuit injects an additional reset current pulse Irst2 into the second (reset) branch of the current mirror circuit 204.

[0037] exist Figure 3In the voltage headroom circuit, a first additional current injection path 300 includes an NMOS transistor M8s having a drain coupled to the first (set) branch of the current mirror circuit 204 and a source coupled to the second reference rail HS. A first gate driver 304 is coupled to the gate of the NMOS transistor M8s. A first resistor R3s is coupled between the input of the first gate driver 304 and the second reference rail HS. The cathode of a diode D1 is coupled to the input of the first gate driver 304. A second gate driver formed by a PMOS transistor M9s and an NMOS transistor M10s is coupled between the first power rail VDD and the first reference rail VSS and has an input controlled based on the first (rising or falling) edge of a logic input signal PWM, such as indicated by the first pulse generator 212 of the current pulse generation circuit 200. A PMOS transistor M11s has a source coupled to the first power rail VDD and a gate coupled to the output of the second gate driver formed by the PMOS transistor M9s and the NMOS transistor M10s. A second resistor R2s is coupled between the drain of PMOS transistor M11s and the anode of diode D1s. The first additional current injection path 300 of the voltage headroom circuit may further include a Zener protection diode Dz1 having a cathode coupled to the input of the first gate driver 304 and an anode coupled to the second reference rail HS.

[0038] When the gate of PMOS transistor M11s is activated by the second gate driver (M9s and M10s) and the second reference rail HS is more negative than the first reference rail VSS by at least one diode D1s voltage drop, the PMOS transistor M11s, the second resistor R2s, and the diode D1s of the first additional current injection path 300 inject current Ig1 into the first resistor R3s. The first additional current injection path 300 of the voltage headroom circuit activates the additional current pulse Iset2 only when the potential of the second reference rail HS drops below the value required to generate a voltage across the first resistor R3s that is above the threshold of the first gate driver 304. Activation of the first (set) additional current pulse Iset2 is accomplished by the diode D1s of the first additional current injection path 300, which behaves like a switch that allows the first (set) additional current pulse Iset2 only when the second reference rail HS drops below the first power rail VDD by at least one forward diode voltage drop. When this occurs, the branch of the first additional current injection path 300, which includes NMOS transistor M8s, second resistor R2s, and diode D1s, passes a voltage across first resistor R3s. When the voltage of the second reference rail HS drops below the first power rail VDD enough to cross the threshold of the first gate driver 304, NMOS transistor M8s injects current Iset2 into the current mirror formed by PMOS transistors M3s and M4s. These currents Iset1 and Iset2 then set latch 202.

[0039] Similarly, a second additional current injection path 302 of the voltage headroom circuit includes an NMOS transistor M8r having a drain coupled to the second (reset) branch of the current mirror circuit 204 and a source coupled to the second reference rail HS. A first gate driver 306 is coupled to the gate of the NMOS transistor M8r. A first resistor R3r is coupled between the input of the first gate driver 306 and the second reference rail HS. The cathode of a diode D1r is coupled to the input of the first gate driver 306. A second gate driver formed by a PMOS transistor M9r and an NMOS transistor M10r is coupled between the first power rail VDD and the first reference rail VSS and has an input controlled based on the second (falling or rising) edge of the logic input signal PWM, for example, as indicated by the second pulse generator 216 of the current pulse generation circuit 200. The PMOS transistor M11r has a source coupled to the first power rail VDD and a gate coupled to the output of the second gate driver formed by the PMOS transistor M9r and the NMOS transistor M10r. A second resistor R2r is coupled between the drain of PMOS transistor M11r and the anode of diode D1r.The second additional current injection path 302 of the voltage headroom circuit may also include a Zener protection diode Dz1r having a cathode coupled to the input of the first gate driver 306 and an anode coupled to the second reference rail HS.

[0040] When the gate of PMOS transistor M11r is activated by the second gate driver (M9r and M10r) and the second reference rail HS is more negative than the first reference rail VSS by at least one diode D1r voltage drop, the PMOS transistor M11r, the second resistor R2r, and the diode D1r of the second additional current injection path 302 inject current Ig2 into the first resistor R3r. The second additional current injection path 302 of the voltage headroom circuit activates the additional current pulse Irst2 only when the potential of the second reference rail HS drops below the value required to generate a voltage across the first resistor R3r that is above the threshold of the first gate driver 306. The activation of the second (reset) additional current pulse Irst2 is accomplished by the diode D1r of the second additional current injection path 302, which behaves like a switch that allows the second (reset) additional current pulse Irst2 only when the second reference rail HS drops to at least one forward diode voltage drop below the first power rail VDD. When this occurs, the branch of the second additional current injection path 302, which includes NMOS transistor M8r, second resistor R2r, and diode D1r, passes a voltage across first resistor R3r. When the voltage of the second reference rail HS drops sufficiently below the first power rail VDD to cross the threshold of the first gate driver 306, NMOS transistor M8r injects current Irst2 into the current mirror formed by PMOS transistors M3r and M4r. These currents Irst1 and Irst2 then reset latch 202.

[0041] In the following example, the first (set) branch of the current pulse generation circuit 200 is activated by the positive (rising) edge of the logic input signal PWM, while the second (reset) branch of the current pulse generation circuit 200 is activated by the negative (falling) edge of the logic input signal PWM. At a positive PWM edge, a current pulse Iset is injected into the current mirror formed by PMOS transistors M3s and M4s. The mirror output pulse sets the latch 202. At a negative PWM edge, a current pulse Irst is injected into the current mirror formed by PMOS transistors M3r and M4r. The mirror output pulse resets the latch 202. When the second reference rail HS is at a positive potential, the additional current injection paths 300, 302 of the voltage headroom circuit are inactive, and the set and reset current pulses Iset, Irst for setting and resetting the latch 202 are generated exclusively by the current pulse generation circuit 200. More specifically, when the second reference rail HS is higher than the ground potential, the NMOS transistor M1s, the NMOS boost transistor M2s, the resistor R1s, the pulse generator 212 and the driver 214 exclusively generate the set current pulse Iset, while the NMOS transistor M1r, the NMOS boost transistor M2r, the resistor R1r, the pulse generator 216 and the driver 218 exclusively generate the reset current pulse Irst.

[0042] When the second reference rail HS is more negative than at least one forward diode drop, at least a portion of the set and reset current pulses Iset and Irst for setting and resetting the latch 202 are generated by the additional current injection paths 300 and 302 of the voltage headroom circuit. More specifically, the NMOS transistor M8s, gate driver 304, resistor R3s, diode D1s, resistor R2s, and PMOS transistor M11s of the first additional current injection path 300 generate additional current Iset2 for helping set the latch 202, while the NMOS transistor M8r, gate driver 306, resistor R3r, diode D1r, resistor R2r, and PMOS transistor M11r of the second additional current injection path 302 generate additional current Irst2 for helping reset the latch 202. If the second reference rail HS becomes sufficiently negative, for example, more negative than -3V, the voltage headroom loss is significant, so that the current pulse generation circuit 200 no longer contributes to the set current Iset and the reset current Irst. Under these conditions, the additional current injection paths 300 , 302 of the voltage headroom circuit generate the full amplitude of the set and reset current pulses Iset, Irst for setting and resetting the latch 202 .

[0043] Although the present disclosure is not limited in this regard, the following numbered examples illustrate one or more aspects of the present disclosure.

[0044] Example 1. A level shifter comprising: a current pulse generating circuit coupled to a first power rail and a first reference rail and configured to output non-overlapping first and second current pulses based on opposite edges of a logic input signal, the first reference rail being grounded; a latch and current mirror circuit coupled to a second power rail and a second reference rail, the current mirror circuit being configured to mirror the non-overlapping first and second current pulses such that the latch is set when the first current pulse is valid and reset when the second current pulse is valid; and a voltage headroom circuit configured to mitigate voltage headroom loss between the second power rail and the first reference rail independent of a potential difference of the second reference rail.

[0045] Example 2. The level shifter of Example 1, wherein the potential difference of the second reference rail is configured to drop to a negative voltage in the range of 0V to -8V.

[0046] Example 3. The level shifter of Example 1 or 2, wherein the voltage headroom circuit is configured to couple the reference node of the current pulse generating circuit to the first reference rail when the second reference rail is more positive than the first reference rail, and wherein the voltage headroom circuit is configured to couple the reference node of the current pulse generating circuit to the second reference rail when the second reference rail is more negative than the first reference rail by at least one diode drop.

[0047] Example 4. The level shifter of any of Examples 1 to 3, wherein the voltage headroom circuit comprises: a first diode having a cathode coupled to the first reference rail and an anode coupled to the reference node of the current pulse generating circuit; and a second diode having a cathode coupled to the second reference rail and an anode coupled to the reference node of the current pulse generating circuit.

[0048] Example 5. The level shifter of Example 4, wherein the voltage headroom circuit further comprises: a local voltage source generated from a first power rail; and a signal level shifter that transforms a logic input signal from a first domain defined by the first power rail and ground to a second domain defined by the local voltage source and a potential at a reference node of the current pulse generating circuit.

[0049] Example 6. The level shifter of Example 5, wherein the local voltage source comprises: a resistor coupled between the first power rail and the high voltage node of the current pulse generating circuit; and a Zener diode having an anode coupled to the reference node of the current pulse generating circuit and a cathode coupled to the high voltage node of the current pulse generating circuit.

[0050] Example 7. The level shifter of any of Examples 1 to 6, wherein the voltage headroom circuit is configured to activate an additional current injection path for setting or resetting the latch when the second reference rail is more negative than the first reference rail by at least one diode drop.

[0051] Example 8. The level shifter of any of Examples 1 to 7, wherein the voltage headroom circuit comprises: a first additional current injection path configured to inject an additional current pulse into a first branch of the current mirror circuit that mirrors the first current pulse when the second reference rail is more negative than the first reference rail by at least one diode voltage drop and a first edge of the logic input signal is detected; and a second additional current injection path configured to inject an additional current pulse into a second branch of the current mirror circuit that mirrors the second current pulse when the second reference rail is more negative than the first reference rail by at least one diode voltage drop and a second edge of the logic input signal is detected.

[0052] Example 9. The level shifter of Example 8, wherein for a potential difference of a second reference rail in the range of 0 V to -8 V: the amplitudes of the first current pulse and the second current pulse are reduced proportionally according to the potential difference of the second reference rail; the first additional current injection path is configured to: inject the additional current pulse into the first branch of the current mirror circuit when a first edge of the logic input signal is detected; and the second additional current injection path is configured to: inject the additional current pulse into the second branch of the current mirror circuit when a second edge of the logic input signal is detected.

[0053] Example 10. The level shifter of Example 8 or 9, wherein the first additional current injection path includes: an NMOS transistor having a drain coupled to the first branch of the current mirror circuit and a source coupled to the second reference rail; a first gate driver coupled to the gate of the NMOS transistor; a first resistor coupled between the input of the first gate driver and the second reference rail; a diode having a cathode coupled to the input of the first gate driver; a second gate driver coupled between the first power rail and the first reference rail and having an input controlled based on a first edge of a logic input signal; a PMOS transistor having a source coupled to the first power rail and a gate coupled to the output of the second gate driver; and a second resistor coupled between the drain of the PMOS transistor and the anode of the diode.

[0054] Example 11. The level shifter of Example 10, wherein the PMOS transistor, the second resistor, and the diode inject current into the first resistor when the gate of the PMOS transistor is activated by the second gate driver and the second reference rail is more negative than the first reference rail by at least one diode voltage drop.

[0055] Example 12. The level shifter of Example 10 or 11, wherein the first additional current injection path further comprises: a Zener diode having a cathode coupled to the input of the first gate driver and an anode coupled to the second reference rail.

[0056] Example 13. The level shifter of any of Examples 8 to 12, wherein the second additional current injection path comprises: an NMOS transistor having a drain coupled to the second branch of the current mirror circuit and a source coupled to the second reference rail; a first gate driver coupled to the gate of the NMOS transistor; a first resistor coupled between an input of the first gate driver and the second reference rail; a diode having a cathode coupled to the input of the first gate driver; a second gate driver coupled between the first power rail and the first reference rail and having an input controlled based on a second edge of a logic input signal; a PMOS transistor having a source coupled to the first power rail and a gate coupled to the output of the second gate driver; and a second resistor coupled between the drain of the PMOS transistor and the anode of the diode.

[0057] Example 14. The level shifter of Example 13, wherein the PMOS transistor, the second resistor, and the diode inject current into the first resistor when the gate of the PMOS transistor is activated by the second gate driver and the second reference rail is more negative than the first reference rail by at least one diode voltage drop.

[0058] Example 15. The level shifter of Example 13 or 14, wherein the second additional current injection path further comprises: a Zener diode having a cathode coupled to the input of the first gate driver and an anode coupled to the second reference rail.

[0059] Example 16. A power electronic circuit comprising: a power converter circuit including a high-side GaN switching device coupled in series with a low-side GaN switching device at a switching node; a first gate driver configured to drive the gate of the low-side GaN switching device; and a second gate driver configured to drive the gate of the high-side GaN switching device, wherein the second gate driver comprises: a current pulse generating circuit coupled to a first power rail and a first reference rail and configured to output non-overlapping first and second current pulses based on relative edges of a logic input signal, the first reference rail being grounded; a latch and current mirror circuit coupled to a second power rail and a second reference rail, the current mirror circuit being configured to mirror the non-overlapping first and second current pulses such that the latch is set when the first current pulse is valid and reset when the second current pulse is valid, the second reference rail corresponding to the switching node of the power converter circuit; and a voltage headroom circuit configured to mitigate voltage headroom losses between the second power rail and the first reference rail independent of a potential difference of the second reference rail.

[0060] Example 17. The power electronic circuit of Example 16, wherein the voltage headroom circuit comprises: a first diode having a cathode coupled to a first reference rail and an anode coupled to a reference node of the current pulse generating circuit; and a second diode having a cathode coupled to a second reference rail and an anode coupled to the reference node of the current pulse generating circuit.

[0061] Example 18. The power electronic circuit of Example 16 or 17, wherein the voltage headroom circuit comprises: a first additional current injection path configured to inject an additional current pulse into a first branch of the current mirror circuit that mirrors the first current pulse when the second reference rail is more negative than the first reference rail by at least one diode voltage drop and a first edge of the logic input signal is detected; and a second additional current injection path configured to inject an additional current pulse into a second branch of the current mirror circuit that mirrors the second current pulse when the second reference rail is more negative than the first reference rail by at least one diode voltage drop and a second edge of the logic input signal is detected.

[0062] Example 19. The power electronic circuit of Example 18, wherein the first additional current injection path includes: an NMOS transistor having a drain coupled to the first branch of the current mirror circuit and a source coupled to the second reference rail; a first gate driver coupled to the gate of the NMOS transistor; a first resistor coupled between the input of the first gate driver and the second reference rail; a diode having a cathode coupled to the input of the first gate driver; a second gate driver coupled between the first power rail and the first reference rail and having an input controlled based on a first edge of a logic input signal; a PMOS transistor having a source coupled to the first power rail and a gate coupled to the output of the second gate driver; and a second resistor coupled between the drain of the PMOS transistor and the anode of the diode.

[0063] Example 20. The power electronic circuit of Example 18 or 19, wherein the second additional current injection path includes: an NMOS transistor having a drain coupled to the second branch of the current mirror circuit and a source coupled to the second reference rail; a first gate driver coupled to the gate of the NMOS transistor; a first resistor coupled between the input of the first gate driver and the second reference rail; a diode having a cathode coupled to the input of the first gate driver; a second gate driver coupled between the first power rail and the first reference rail and having an input controlled based on a second edge of a logic input signal; a PMOS transistor having a source coupled to the first power rail and a gate coupled to the output of the second gate driver; and a second resistor coupled between the drain of the PMOS transistor and the anode of the diode.

[0064] Terms such as "first", "second", etc. are used to describe various elements, regions, sections, etc., and are not intended to be limiting. Throughout the specification, the same terms refer to the same elements.

[0065] As used herein, the terms "having," "containing," "including," "comprising," and the like are open-ended terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. The articles "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0066] The expression "and / or" should be interpreted as including all possible combinations and disjunctions, unless expressly stated otherwise. For example, the expression "A and / or B" should be interpreted as meaning only A, only B, or both A and B. The expression "at least one" should be interpreted in the same manner as "and / or," unless expressly stated otherwise. For example, the expression "at least one of A and B" should be interpreted as meaning only A, only B, or both A and B.

[0067] It will be understood that the features of the various embodiments described herein may be combined with each other, unless specifically stated otherwise.

[0068] Although specific embodiments have been illustrated and described herein, it will be understood by those skilled in the art that various alternatives and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any modifications or variations of the specific embodiments discussed herein. Therefore, the present invention is limited only by the claims and their equivalents.

Claims

1. A level shifter, comprising: a current pulse generating circuit coupled to a first power rail and a first reference rail, the first reference rail being grounded, and configured to output non-overlapping first and second current pulses based on opposite edges of a logic input signal; a latch and a current mirror circuit coupled to a second power rail and a second reference rail, the current mirror circuit configured to mirror the non-overlapping first current pulse and the second current pulse such that the latch is set when the first current pulse is valid and is reset when the second current pulse is valid; as well as A voltage headroom circuit is configured to mitigate voltage headroom losses between the second power rail and the first reference rail independent of a potential difference of the second reference rail. 2 . The level shifter of claim 1 , wherein the potential difference of the second reference rail is configured to drop to a negative voltage within a range of 0V to −8V.

3. The level shifter of claim 1 , wherein the voltage headroom circuit is configured to couple the reference node of the current pulse generating circuit to the first reference rail when the second reference rail is more positive than the first reference rail, and wherein the voltage headroom circuit is configured to couple the reference node of the current pulse generating circuit to the second reference rail when the second reference rail is more negative than the first reference rail by at least one diode drop.

4. The level shifter according to claim 1 , wherein the voltage headroom circuit comprises: a first diode having a cathode coupled to the first reference rail and an anode coupled to a reference node of the current pulse generating circuit; as well as A second diode has a cathode coupled to the second reference rail and an anode coupled to the reference node of the current pulse generating circuit.

5. The level shifter according to claim 4 , wherein the voltage headroom circuit further comprises: a local voltage source generated from the first power rail; as well as A signal level shifter transforms the logic input signal from a first domain defined by the first power rail and ground to a second domain defined by the local voltage source and the potential at the reference node of the current pulse generating circuit.

6. The level shifter of claim 5 , wherein the local voltage source comprises: a resistor coupled between the first power rail and a high voltage node of the current pulse generating circuit; as well as A Zener diode has an anode coupled to the reference node of the current pulse generating circuit and a cathode coupled to a high voltage node of the current pulse generating circuit.

7. The level shifter of claim 1 , wherein the voltage headroom circuit is configured to activate an additional current injection path for setting or resetting the latch when the second reference rail is more negative than the first reference rail by at least one diode voltage drop.

8. The level shifter of claim 1 , wherein the voltage headroom circuit comprises: a first additional current injection path configured to inject an additional current pulse into a first branch of the current mirror circuit that mirrors the first current pulse when the second reference rail is more negative than the first reference rail by at least one diode voltage drop and a first edge of the logic input signal is detected; as well as a second additional current injection path configured to inject an additional current pulse into a second branch of the current mirror circuit that mirrors the second current pulse when the second reference rail is more negative than the first reference rail by at least one diode voltage drop and a second edge of the logic input signal is detected.

9. The level shifter of claim 8 , wherein for the potential difference of the second reference rail in the range of 0 V to −8 V: the amplitudes of the first current pulse and the second current pulse decrease in proportion to the potential difference of the second reference rail; The first additional current injection path is configured to: inject the additional current pulse into the first branch of the current mirror circuit when the first edge of the logic input signal is detected; as well as The second additional current injection path is configured to inject the additional current pulse into the second branch of the current mirror circuit when the second edge of the logic input signal is detected.

10. The level shifter according to claim 8, wherein the first additional current injection path comprises: an NMOS transistor having a drain coupled to the first branch of the current mirror circuit and a source coupled to the second reference rail; a first gate driver coupled to the gate of the NMOS transistor; a first resistor coupled between an input of the first gate driver and the second reference rail; a diode having a cathode coupled to the input of the first gate driver; a second gate driver coupled between the first power rail and the first reference rail and having an input controlled based on a first edge of the logic input signal; a PMOS transistor having a source coupled to the first power rail and a gate coupled to the output of the second gate driver; as well as A second resistor is coupled between the drain of the PMOS transistor and the anode of the diode.

11. The level shifter of claim 10 , wherein the PMOS transistor, the second resistor, and the diode inject current into the first resistor when the gate of the PMOS transistor is activated by the second gate driver and the second reference rail is more negative than the first reference rail by at least one voltage drop of the diode.

12. The level shifter according to claim 10 , wherein the first additional current injection path further comprises: A Zener diode has a cathode coupled to the input of the first gate driver and an anode coupled to the second reference rail.

13. The level shifter according to claim 8, wherein the second additional current injection path comprises: an NMOS transistor having a drain coupled to the second branch of the current mirror circuit and a source coupled to the second reference rail; a first gate driver coupled to the gate of the NMOS transistor; a first resistor coupled between an input of the first gate driver and the second reference rail; a diode having a cathode coupled to the input of the first gate driver; a second gate driver coupled between the first power rail and the first reference rail and having an input controlled by a second edge of the logic input signal; a PMOS transistor having a source coupled to the first power rail and a gate coupled to the output of the second gate driver; as well as A second resistor is coupled between the drain of the PMOS transistor and the anode of the diode.

14. The level shifter of claim 13 , wherein the PMOS transistor, the second resistor, and the diode inject current into the first resistor when the gate of the PMOS transistor is activated by the second gate driver and the second reference rail is more negative than the first reference rail by at least one voltage drop of the diode.

15. The level shifter according to claim 13 , wherein the second additional current injection path further comprises: A Zener diode has a cathode coupled to the input of the first gate driver and an anode coupled to the second reference rail.

16. A power electronic circuit comprising: a power converter circuit including a high-side GaN switching device coupled in series with a low-side GaN switching device at a switching node; a first gate driver configured to drive a gate of the low-side GaN switching device; as well as a second gate driver configured to drive a gate of the high-side GaN switching device, The second gate driver comprises: a current pulse generating circuit coupled to a first power rail and a first reference rail, the first reference rail being grounded, and configured to output non-overlapping first and second current pulses based on opposite edges of a logic input signal; a latch and current mirror circuit coupled to a second power rail and a second reference rail, the current mirror circuit configured to mirror non-overlapping first and second current pulses such that the latch is set when the first current pulse is valid and reset when the second current pulse is valid, the second reference rail corresponding to the switch node of the power converter circuit; and A voltage headroom circuit is configured to mitigate voltage headroom losses between the second power rail and the first reference rail independent of a potential difference of the second reference rail.

17. The power electronic circuit of claim 16, wherein the voltage headroom circuit comprises: a first diode having a cathode coupled to the first reference rail and an anode coupled to a reference node of the current pulse generating circuit; as well as A second diode has a cathode coupled to the second reference rail and an anode coupled to the reference node of the current pulse generating circuit.

18. The power electronic circuit of claim 16, wherein the voltage headroom circuit comprises: a first additional current injection path configured to inject an additional current pulse into a first branch of the current mirror circuit that mirrors the first current pulse when the second reference rail is more negative than the first reference rail by at least one diode voltage drop and a first edge of the logic input signal is detected; as well as a second additional current injection path configured to inject an additional current pulse into a second branch of the current mirror circuit that mirrors the second current pulse when the second reference rail is more negative than the first reference rail by at least one diode voltage drop and a second edge of the logic input signal is detected.

19. The power electronic circuit according to claim 18, wherein the first additional current injection path comprises: an NMOS transistor having a drain coupled to the first branch of the current mirror circuit and a source coupled to the second reference rail; a first gate driver coupled to the gate of the NMOS transistor; a first resistor coupled between an input of the first gate driver and the second reference rail; a diode having a cathode coupled to the input of the first gate driver; a second gate driver coupled between the first power rail and the first reference rail and having an input controlled based on a first edge of the logic input signal; a PMOS transistor having a source coupled to the first power rail and a gate coupled to the output of the second gate driver; as well as A second resistor is coupled between the drain of the PMOS transistor and the anode of the diode.

20. The power electronic circuit of claim 18, wherein the second additional current injection path comprises: an NMOS transistor having a drain coupled to the second branch of the current mirror circuit and a source coupled to the second reference rail; a first gate driver coupled to the gate of the NMOS transistor; a first resistor coupled between an input of the first gate driver and the second reference rail; a diode having a cathode coupled to the input of the first gate driver; a second gate driver coupled between the first power rail and the first reference rail and having an input controlled by a second edge of the logic input signal; a PMOS transistor having a source coupled to the first power rail and a gate coupled to the output of the second gate driver; as well as A second resistor is coupled between the drain of the PMOS transistor and the anode of the diode.

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