Method of fabricating variable resistance memory device

Abstract

According to the method of manufacturing a variable resistance memory device, a difference between etch profiles occurring during simultaneous formation of a first contact hole and a second contact hole in a cell region and a peripheral region may be reduced by forming a molded insulating layer from a material having similar etch selectivity in the cell region and the peripheral region.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priority from Korean Patent Application No. 10-2024-0033865 filed on March 11, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The inventive concept relates to a method of manufacturing a variable resistance memory device, and more particularly, to a method of manufacturing a variable resistance memory device including a magnetic tunnel junction (MTJ) structure. Background Art

[0003] Recently, as electronic products have become increasingly high-speed and low-power, the demand for fast read / write operations and low operating voltages in semiconductor devices embedded in these products has increased. To meet this growing demand, highly integrated variable resistance memory devices are becoming the next generation of memory devices due to their ability to achieve high-speed read and write operations and their non-volatile nature. In particular, research is underway into variable resistance memory devices that utilize the magnetoresistive properties of magnetic tunnel junctions (MTJs). Summary of the Invention

[0004] The inventive concept provides a method of manufacturing a variable resistance memory device capable of reducing a difference between etching profiles occurring during simultaneous formation of contact holes in a cell region and a peripheral region by forming a mold insulating layer using a material having similar etching selectivity in the cell region and the peripheral region.

[0005] In addition, technical objectives to be achieved by the embodiments of the present inventive concept are not limited to the above-mentioned technical objectives, and a person of ordinary skill in the art can clearly understand other technical objectives based on the following description.

[0006] According to one aspect of the present invention, a method for manufacturing a variable resistance memory device is provided, the method comprising: preparing a substrate having a cell region and a peripheral region surrounding the cell region in a plan view; forming a first plug including a first cell plug and a first via plug in the cell region, and forming a second plug in the peripheral region; forming a lower insulating layer on the first plug and the second plug over the cell region and the peripheral region; forming a magnetic tunnel junction (MTJ) structure, the MTJ structure extending through the lower insulating layer in the cell region and electrically connected to the first cell plug; conformally forming a capping layer on the MTJ structure and the lower insulating layer over the cell region and the peripheral region; and conformally etching the capping layer in the cell region to form a magnetic tunnel junction. forming a capping pattern on both side walls of the structure; forming a buried insulating layer on the MTJ structure in the cell area, and removing the capping layer from the peripheral area; forming an interlayer insulating layer on the lower insulating layer in the peripheral area; forming an upper insulating layer on the buried insulating layer in the cell area and on the interlayer insulating layer in the peripheral area; forming a first through hole overlapping with the first plug in the cell area in a direction perpendicular to the upper surface of the substrate, and forming a second through hole overlapping with the second plug in the peripheral area in a direction perpendicular to the upper surface of the substrate; and forming a first contact hole by etching a bottom surface of the first through hole overlapping with the first via plug in the cell area in a direction perpendicular to the substrate, and forming a second contact hole by etching a bottom surface of the second through hole in the peripheral area.

[0007] According to another aspect of the present invention, a method for manufacturing a variable resistance memory device is provided, the method comprising: preparing a substrate having a cell region and a peripheral region surrounding the cell region in a plan view; forming a first plug including a first cell plug and a first via plug in the cell region, and forming a second plug in the peripheral region; forming a lower insulating layer on the first plug and the second plug over the cell region and the peripheral region; forming a magnetic tunnel junction (MTJ) structure, the MTJ structure extending through the lower insulating layer in the cell region and electrically connected to the first cell plug; conformally forming a capping layer on the MTJ structure and the lower insulating layer over the cell region and the peripheral region; forming a mask pattern over the cell region and the peripheral region to at least partially expose a region overlapping with the first via plug in a direction perpendicular to an upper surface of the substrate; etching the cell region by using the mask pattern as an etching mask etching a portion of the capping layer to at least partially expose the lower insulating layer in a region overlapping with the first via plug in a direction perpendicular to the upper surface of the substrate; removing the mask pattern; forming a buried insulating layer on the MTJ structure in the cell region, and removing the capping layer from the peripheral region; forming an interlayer insulating layer on the lower insulating layer in the peripheral region; forming an upper insulating layer on the buried insulating layer in the cell region and on the interlayer insulating layer in the peripheral region; forming a first through hole overlapping with the first plug in the cell region in a direction perpendicular to the upper surface of the substrate, and forming a second through hole overlapping with the second plug in the peripheral region in a direction perpendicular to the upper surface of the substrate; and forming a first contact hole by etching the bottom surface of the first through hole overlapping with the first via plug in the cell region in a direction perpendicular to the upper surface of the substrate, and forming a second contact hole by etching the bottom surface of the second through hole in the peripheral region.

[0008] According to another aspect of the present invention, there is provided a method for manufacturing a variable resistance memory device, the method comprising: preparing a substrate having a cell region and a peripheral region surrounding the cell region in a plan view; forming a first plug including a first cell plug and a first via plug in the cell region, and forming a second plug in the peripheral region; forming a lower insulating layer on the first plug and the second plug over the cell region and the peripheral region; forming a magnetic tunnel junction (MTJ) structure, the MTJ structure extending through the lower insulating layer in the cell region and electrically connected to the first cell plug; conformally forming a capping layer on the MTJ structure and the lower insulating layer over the cell region and the peripheral region; etching a portion of the capping layer to at least partially expose the lower insulating layer in a region overlapping with the first via plug in a direction perpendicular to an upper surface of the substrate; forming a buried insulating layer on the MTJ structure in the cell region, and removing the capping layer from the peripheral region; forming a lower insulating layer on the lower insulating layer in the peripheral region; an interlayer insulating layer; forming an upper insulating layer on the buried insulating layer in the cell area and on the interlayer insulating layer in the peripheral area; forming a first through hole overlapping with the first plug in the cell area in a direction perpendicular to the upper surface of the substrate, and forming a second through hole overlapping with the second plug in the peripheral area in a direction perpendicular to the upper surface of the substrate; forming a first contact hole by etching the bottom surface of the first through hole overlapping with the first via plug in the cell area in a direction perpendicular to the upper surface of the substrate, and forming a second contact hole by etching the bottom surface of the second through hole in the peripheral area; forming a metal layer, the metal layer at least partially filling the first through hole and the first contact hole in the cell area, and at least partially filling the second through hole and the second contact hole in the peripheral area; and separating the metal layer into nodes to form a first contact portion in contact with the MTJ structure and a cell via in contact with the first via plug in the cell area, and a second contact portion in contact with the second plug in the peripheral area. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a circuit diagram showing a cell array of a variable resistance memory device according to an embodiment;

[0011] Figure 2 It shows Figure 1 A circuit diagram of a magnetoresistive memory unit;

[0012] Figure 3 yes Figure 2 A perspective view of a magnetoresistive memory cell;

[0013] Figure 4is a plan view showing a variable resistance memory device according to an embodiment;

[0014] Figure 5 is a flowchart of a method for manufacturing a variable resistance memory device according to an embodiment;

[0015] Figures 6 to 16 is a cross-sectional view illustrating a method of manufacturing a variable resistance memory device according to an embodiment according to a process sequence;

[0016] Figure 17 is a flow chart of a method for manufacturing a variable resistance memory device according to another embodiment;

[0017] Figures 18 to 22 is a cross-sectional view illustrating a method of manufacturing a variable resistance memory device according to another embodiment according to a process sequence;

[0018] Figure 23 is a configuration diagram showing a data processing system including a variable resistance memory element according to an embodiment; and

[0019] Figure 24 is a diagram showing a configuration of a data processing system including a variable resistance memory element according to an embodiment. DETAILED DESCRIPTION

[0020] Some embodiments of the present invention will be described below with reference to the accompanying drawings. Throughout this specification, the same reference numerals may indicate the same components. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be understood that although the terms "first," "second," "upper," "lower," etc. may be used herein to describe various elements or components, these elements or components should not be limited by these terms. These terms are only used to distinguish one element or component from another. Therefore, the first element or component discussed below may be referred to as the second element or component. It should be noted that the various aspects described for an embodiment may be incorporated into different embodiments, although not specifically described in this regard. That is, the features of all embodiments and / or any embodiment can be combined in any manner and / or combination.

[0021] Figure 1 is a diagram illustrating a cell array of a variable resistance memory device according to an embodiment. Figure 2 It shows Figure 1 Circuit diagram of a magnetoresistive memory cell. Figure 3 yes Figure 2 A perspective view of a magnetoresistive memory cell. Figure 4 is a plan view showing a variable resistance memory device according to an embodiment.

[0022] Reference together Figures 1 to 4, the variable resistance memory device VRM may be a magnetoresistive memory device according to an embodiment.

[0023] like Figure 1 As shown, the variable resistance memory device may be a magnetoresistive RAM (MRAM). The variable resistance memory device VRM may include a magnetic tunnel junction (MTJ), which is a variable resistance layer.

[0024] The variable resistance memory device VRM may include a magnetoresistive memory cell array 10. The magnetoresistive memory cell array 10 may also be referred to as a cell array 10. The magnetoresistive memory cell array 10 may be electrically connected to a write driver 12, a selection circuit 14, a source line voltage generator 18, and a sense amplifier 16.

[0025] The magnetoresistive memory cell array 10 may include a plurality of magnetoresistive memory cells 10u. The magnetoresistive memory cell 10u may be simply referred to as a memory cell. The magnetoresistive memory cell array 10 may include a plurality of word lines WL1 to WLm and a plurality of bit lines BL1 to BLn. The magnetoresistive memory cell array 10 may have a magnetoresistive memory cell 10u between each of the word lines WL1 to WLm and each of the bit lines BL1 to BLn.

[0026] The magnetoresistive memory cell array 10 may include a plurality of cell transistors MN11 to MNmn having gates connected to a plurality of word lines WL1 to WLm, and a plurality of MTJs MTJ11 to MTJmn respectively connected between the plurality of cell transistors MN11 to MNmn and a plurality of bit lines BL1 to BLn and constituting variable resistance layers.

[0027] The write driver 12 is connected to the plurality of bit lines BL1 to BLn, generates a program current based on write data, and supplies the program current to the plurality of bit lines BL1 to BLn.

[0028] The selection circuit 14 may selectively connect the plurality of bit lines BL1 to BLn to the sense amplifier 16 in response to a plurality of column selection signals CSL_s1 to CSL_sn. The sense amplifier 16 may generate output data DOUT by amplifying a difference between an output voltage signal of the selection circuit 14 and a reference voltage VREF.

[0029] The source terminals of the plurality of cell transistors MN11 to MNmn may be connected to a source line SL. To magnetize the plurality of MTJs MTJ11 to MTJmn in the magnetoresistive memory cell array 10, a voltage higher than the voltage applied to the plurality of bit lines BL1 to BLn may be applied to the source line SL. The source line voltage generator 18 may generate a source line drive voltage VSL and provide the source line drive voltage VSL to the source line SL of the magnetoresistive memory cell array 10.

[0030] like Figure 2As shown, the magnetoresistive memory cell 10u may include a cell transistor MN11 configured as an NMOS transistor and a MTJ MTJ11. The cell transistor MN11 has a gate connected to a word line WL1 and a source connected to a source line SL. The MTJ MTJ11 is connected between the drain of the cell transistor MN11 and the bit line BL1.

[0031] like Figure 3 As shown, the MTJ MTJ11 includes a pinned layer PL having a fixed magnetization direction, a free layer FL magnetized in a direction of a magnetic field applied from the outside, and a tunnel barrier layer TBL formed as an insulating layer between the pinned layer PL and the free layer FL.

[0032] According to some embodiments, the fixed layer PL may include any one of iron manganese (FeMn), iridium manganese (IrMn), platinum manganese (PtMn), manganese oxide (MnO), manganese sulfide (MnS), manganese telluride (MnTe), manganese fluoride (MnF2), iron fluoride (FeF2), iron chloride (FeCl2), iron oxide (FeO), cobalt chloride (CoCl2), cobalt oxide (CoO), nickel chloride (NiCl2), nickel oxide (NiO), chromium (Cr), iron (Fe), nickel (Ni), cobalt (Co), ruthenium (Ru), iridium (Ir) and / or rhodium (Rh).

[0033] According to some embodiments, the free layer FL may be a ferromagnetic material including iron (Fe), nickel (Ni), and / or cobalt (Co).

[0034] According to some embodiments, the tunnel barrier layer TBL may include aluminum oxide (AlO) and / or magnesium oxide (MgO).

[0035] The MTJ MTJ11 may be included in a memory cell constituting a spin transfer torque (STT)-MRAM.

[0036] For a write operation of the STT-MRAM, a logic high voltage may be applied to the word line WL1 to turn on the cell transistor MN11 , and a write current may be applied between the bit line BL1 and the source line SL.

[0037] For a read operation of the STT-MRAM, a logic high voltage may be applied to the word line WL1 to turn on the cell transistor MN11, and a read current may be applied from the bit line BL1 to the source line SL, thereby determining the data stored in the magnetoresistive memory cell 10u based on the resistance value of the MTJ MTJ11 relative to the read current.

[0038] The resistance value of the MTJ MTJ11 varies depending on the magnetization direction of the free layer FL. For example, in the MTJ MTJ11, the magnetization directions of the free layer FL and the fixed layer PL may be arranged parallel to each other. In this case, the MTJ MTJ11 can have a low resistance value and can read data (e.g., 0). Alternatively, the MTJ MTJ11 can be arranged so that the magnetization direction of the free layer FL is antiparallel to the magnetization direction of the fixed layer PL. In this case, the MTJ MTJ11 has a high resistance value and can read data (e.g., 1).

[0039] Here, the MTJ MTJ11 is shown as a horizontal magnetic element including a free layer FL and a pinned layer PL having a horizontal magnetization direction. However, according to other embodiments, a vertical magnetic element including a free layer FL and a pinned layer PL having a vertical magnetization direction may also be used.

[0040] like Figure 4 As shown, in a plan view, the variable resistance memory device VRM may include a cell area CA and a peripheral area PA surrounding the cell area CA. According to some embodiments, the variable resistance memory device VRM may include a boundary area between the cell area CA and the peripheral area PA.

[0041] The unit area CA may include Figure 1 In addition, the cell area CA may be provided with a reference Figure 1 and Figure 2 The region of the magnetoresistive memory cell 10u is described.

[0042] In the peripheral area PA, peripheral circuits and peripheral transistors of the magnetoresistive memory cell array 10 in the cell area CA may be arranged. In other words, the peripheral area PA may be an area where core / peripheral circuits are arranged.

[0043] Figure 5 is a flowchart of a method of manufacturing a variable resistance memory device according to an embodiment.

[0044] refer to Figure 5 , the method S100 of manufacturing a variable resistance memory device may include first to ninth operations S110 to S190 .

[0045] In other embodiments, specific operations may be performed in an order different from the order described below. For example, two operations described in succession may be performed substantially simultaneously, or may be performed in an order opposite to the order described below.

[0046] The method S100 for manufacturing a variable resistance memory device according to the present invention may include: a first operation S110 of forming a first plug including a first cell plug and a first via plug in a cell region, and forming a second plug in a peripheral region; a second operation S120 of forming a lower insulating layer, the lower insulating layer being on the first plug and the second plug and at least partially covering the first plug and the second plug; a third operation S130 of forming an MTJ structure penetrating or extending through the lower insulating layer and connected to the first cell plug; a fourth operation S140 of forming a capping layer, the capping layer being conformally located on the MTJ structure and the lower insulating layer and at least partially covering the MTJ structure and the lower insulating layer; a fifth operation S150 of forming a capping pattern on both sidewalls of the MTJ structure by anisotropically etching the capping layer in the cell region; and a sixth operation S151 of etching the capping layer in the cell region. Operation S160, forming a buried insulating layer on the MTJ structure in the cell area, and removing the capping layer in the peripheral area and forming an interlayer insulating layer; a seventh operation S170, forming an upper insulating layer, which is on the buried insulating layer and the interlayer insulating layer and at least partially covers the buried insulating layer and the interlayer insulating layer; an eighth operation S180, forming a first through hole overlapping with the first plug in the vertical direction (i.e., a direction perpendicular to the upper surface of the substrate, on which the variable resistance memory device is formed, and the cell area is distinguished from the peripheral area), and a second through hole overlapping with the second plug in the vertical direction; and a ninth operation S190, forming a first contact hole by etching the bottom surface of the first through hole overlapping with the first via plug in the vertical direction, and forming a second contact hole by etching the bottom surface of the second through hole.

[0047] The following will refer to Figures 6 to 16 Technical features of the first to ninth operations S110 to S190 are described in detail.

[0048] Figures 6 to 16 2 is a cross-sectional view illustrating a method of manufacturing a variable resistance memory device according to an embodiment according to process sequence.

[0049] refer to Figure 6 , a substrate 101 in which the cell area CA is separated from the peripheral area PA may be prepared.

[0050] The substrate 101 may be a semiconductor wafer including silicon (Si), germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and / or indium phosphide (InP). According to some embodiments, the substrate 101 may include a conductive region, for example, a well doped with impurities or a structure doped with impurities.

[0051] Although not shown, cell transistors may be formed on the substrate 101 in the cell region CA. The cell transistors may be configured as buried-gate transistors. In addition, peripheral circuit transistors may be formed on the substrate 101 in the peripheral region PA. The peripheral circuit transistors may be configured as planar transistors.

[0052] A base insulating layer 110 may be formed on the substrate 101 , and a plurality of first plugs 111 and a plurality of second plugs 112 penetrating or extending through the base insulating layer 110 may be formed.

[0053] Specifically, a plurality of first plugs 111 connected to cell transistors or lower metal lines (not shown) may be formed in the cell area CA. The plurality of first plugs 111 may include cell plugs 111 a and via plugs 111 b. The cell plugs 111 a may be electrically connected to the cell transistors, and the via plugs 111 b may be electrically connected to the lower metal lines. Furthermore, a plurality of second plugs 112 electrically connected to peripheral circuit transistors may be formed in the peripheral area PA.

[0054] refer to Figure 7 A lower insulating layer 120 may be formed over the cell area CA and the peripheral area PA, on the plurality of first plugs 111 and the plurality of second plugs 112 , and at least partially covering the plurality of first plugs 111 and the plurality of second plugs 112 .

[0055] The lower insulating layer 120 may include a first lower insulating layer 121 and a second lower insulating layer 123 formed on the first lower insulating layer 121. The first lower insulating layer 121 and the second lower insulating layer 123 may include different materials.

[0056] According to some embodiments, the first lower insulating layer 121 may include a SiCN film, a SiOC film, a SiOF film, a SiCH film, a SiOCH film, or a combination thereof.

[0057] According to some embodiments, the second lower insulating layer 123 may include a tetraethoxysilane (TEOS) film, but is not limited thereto.

[0058] Next, in the cell region CA, a pad electrode 113 may be formed that penetrates or extends through the lower insulating layer 120 and contacts and is electrically connected to the cell plug 111a. Here, the pad electrode 113 is formed only on the cell plug 111a among the plurality of first plugs 111, and may not be formed on the via plug 111b and the plurality of second plugs 112 among the plurality of first plugs 111.

[0059] refer to Figure 8In the cell area CA, an MTJ structure 130 contacting and electrically connected to the pad electrode 113 may be formed.

[0060] The MTJ structure 130 may be disposed at the intersection of the first direction X and the second direction Y in the mesh structure. Furthermore, the MTJ structure 130 may constitute a memory cell. The MTJ structure 130 may be formed only on the cell plug 111a among the plurality of first plugs 111 in the cell area CA. In other words, the MTJ structure 130 may be electrically connected to the cell plug 111a through the pad electrode 113.

[0061] According to some embodiments, the MTJ structure 130 may have a structure in which a lower electrode 131, an MTJ pattern 133, and an upper electrode 135 are stacked. The MTJ pattern 133 constitutes a variable resistance layer, and as described above with reference to FIG. Figure 2 and Figure 3 As described above, the MTJ pattern 133 may include a fixed layer PL, a tunnel barrier layer TBL, and a free layer FL. The lower electrode 131 and the upper electrode 135 may include metal or metal nitride.

[0062] According to some embodiments, a portion of the second lower insulating layer 123 may be etched together during a process of forming the MTJ structure 130 , and thus the second lower insulating layer 123 may have an inverted dome surface.

[0063] refer to Figure 9 , a capping layer 140 may be formed over the cell area CA and the peripheral area PA, the capping layer 140 conformally on the top surface of the entire MTJ structure 130 and the lower insulating layer 120 , and at least partially covering the top surface of the entire MTJ structure 130 and the lower insulating layer 120 .

[0064] A capping layer 140 may be formed to protect the MTJ structure 130. The capping layer 140 is on and at least partially covers both the top and side surfaces of the MTJ structure 130, and may extend between adjacent MTJ structures 130. Therefore, the capping layer 140 may be referred to as an encapsulation layer.

[0065] The capping layer 140 may include an insulating material, for example, silicon nitride (SiN).

[0066] refer to Figure 10 , a mask layer ML may be formed in the peripheral area PA, and a capping pattern 141 may be formed on both sidewalls of the MTJ structure 130 in the cell area CA through a full-surface etching process.

[0067] By forming the mask layer ML in the peripheral area PA, the peripheral area PA may not be etched by the full-surface etching process. In contrast, since the mask layer ML is not formed in the cell area CA, the capping layer 140 may be etched by the full-surface etching process (see FIG. Figure 9 ) is located at a large portion of the top of the unit area CA.

[0068] When the full-surface etching process is anisotropic etching (e.g., dry etching), the capping pattern 141 may be formed on both sidewalls of the MTJ structure 130. Through the full-surface etching process, in the cell area CA, the top surface of the MTJ structure 130 and the inverted rounded top surface of the second lower insulating layer 123 may be at least partially exposed to the outside.

[0069] By removing the capping layer 140 (see Figure 9 ), while retaining only the capping patterns 141 on both sidewalls of the MTJ structure 130, it is possible to reduce the need to simultaneously form the first contact hole CH1 and the second contact hole CH2 in the cell area CA and the peripheral area PA (see Figure 15 ) in subsequent processes.

[0070] In addition, by etching the capping layer 140 extending between the MTJ structures 130 adjacent to each other (see Figure 9 ), the capping layer 140 (see Figure 9 ), thereby preventing or reducing the flow of leakage current between the MTJ structures 130.

[0071] Next, the mask layer ML may be completely removed through ashing and stripping processes.

[0072] refer to Figure 11 , a buried insulating layer 151 may be formed over the cell area CA and the peripheral area PA.

[0073] The buried insulating layer 151 may include a first buried insulating layer 151a and a second buried insulating layer 151b formed on the first buried insulating layer 151a. The first buried insulating layer 151a and the second buried insulating layer 151b may include different materials.

[0074] In the cell area CA, the first buried insulating layer 151a may at least partially fill the space between the MTJ structures 130 without a void. In addition, the second buried insulating layer 151b may be formed on and at least partially cover the top surface of the MTJ structure 130.

[0075] According to some embodiments, the first buried insulating layer 151 a may include silicon oxide (SiO) formed by a high density plasma (HDP) chemical vapor deposition process, but is not limited thereto.

[0076] According to some embodiments, the second buried insulating layer 151 b may include a SiCN film, a SiOC film, a SiOF film, a SiCH film, a SiOCH film, or a combination thereof.

[0077] refer to Figure 12 , the buried insulating layer 151 and the capping layer 140 may be removed from the peripheral area PA (refer to Figure 11 ).

[0078] Although not shown, a mask layer (not shown) may be formed on and at least partially cover the entire cell area CA. By forming the mask layer in the cell area CA, the buried insulating layer 151 may not be removed from the cell area CA.

[0079] In contrast, by not forming a mask layer in the peripheral area PA, the capping layer 140 (see FIG. Figure 11 ) as an etch stop layer to remove the second buried insulating layer 151b and the first buried insulating layer 151a.

[0080] Next, the capping layer 140 (see FIG. 1 ) used as an etch stop layer in the peripheral area PA may be removed. Figure 11 ). Therefore, in the peripheral area PA, the flat top surface of the second lower insulating layer 123 may be at least partially exposed to the outside.

[0081] refer to Figure 13 , an interlayer insulating layer 152 may be formed in the peripheral area PA, the interlayer insulating layer 152 being on the top surface of the second lower insulating layer 123 and at least partially covering the top surface of the second lower insulating layer 123 .

[0082] The interlayer insulating layer 152 formed in the peripheral area PA may include a material different from a material constituting the buried insulating layer 151 in the cell area CA.

[0083] According to some embodiments, interlayer insulating layer 152 may include a material having a low dielectric constant lower than that of silicon oxide. Interlayer insulating layer 152 may include a material having a low dielectric constant less than 3.9, such as a low-k (LK) dielectric, an ultra-low-k (ULK) dielectric, an extremely low-k (ELK) dielectric, etc.

[0084] refer to Figure 14, an upper insulating layer 160 may be formed on the buried insulating layer 151 in the cell area CA and at least partially covering the buried insulating layer 151 , and on the interlayer insulating layer 152 in the peripheral area PA and at least partially covering the interlayer insulating layer 152 .

[0085] The upper insulating layer 160 may include a first upper insulating layer 161, a second upper insulating layer 163 formed on the first upper insulating layer 161, and a third upper insulating layer 165 formed on the second upper insulating layer 163. The first upper insulating layer 161, the second upper insulating layer 163, and the third upper insulating layer 165 may include different materials from each other.

[0086] According to some embodiments, the first upper insulating layer 161 may include a tetraethoxysilane (TEOS) film, but is not limited thereto.

[0087] According to some embodiments, the second upper insulating layer 163 and the third upper insulating layer 165 may each include a SiON film, a SiOC film, a SiOF film, a SiCH film, a SiOCH film, or a combination thereof.

[0088] Next, a plurality of first via holes VH1 overlapping the plurality of first plugs 111 in the vertical direction Z are formed in the cell area CA, and a plurality of second via holes VH2 overlapping the plurality of second plugs 112 in the vertical direction Z are formed in the peripheral area PA.

[0089] The plurality of first through holes VH1 and the plurality of second through holes VH2 may each have a tapered shape in which a horizontal width gradually decreases toward the substrate 101 in the vertical direction Z.

[0090] The plurality of first through holes VH1 include a first shallow through hole VH1 a overlapping the cell plug 111 a in the vertical direction Z, and a first deep through hole VH1 b overlapping the via plug 111 b in the vertical direction Z.

[0091] Here, the depth of the first shallow via hole VH1a may be less than that of the first deep via hole VH1b because etching of the first shallow via hole VH1a is stopped by the top surface of the MTJ structure 130. In other words, the top surface of the MTJ structure 130 may be exposed to the outside through the first shallow via hole VH1a.

[0092] The plurality of second through holes VH2 may have horizontal widths different from each other in the first direction X. In other words, some of the plurality of second through holes VH2 may have horizontal widths greater than the remaining second through holes VH2 .

[0093] refer to Figure 15, the first contact hole CH1 may be formed by etching the bottom surface of the first deep via hole VH1b in the cell area CA, and the second contact hole CH2 may be formed by etching the bottom surfaces of the plurality of second via holes VH2 in the peripheral area PA.

[0094] The first contact hole CH1 at least partially exposing the top surface of the via plug 111 b may be formed by etching a portion of the bottom surface of the first deep through hole VH1 b overlapping the via plug 111 b in the vertical direction Z in the cell area CA.

[0095] Since the bottom surface of the first shallow via hole VH1 a overlapping the cell plug 111 a in the vertical direction Z in the cell area CA is the top surface of the MTJ structure 130 , the bottom surface of the first shallow via hole VH1 a may not be etched.

[0096] In the cell area CA, the first via hole VH1 alone may at least partially expose the top surface of the MTJ structure 130 , or the first via hole VH1 may at least partially expose the top surface of the via plug 111 b together with the first contact hole CH1 .

[0097] Second contact holes CH2 that at least partially expose the top surfaces of the plurality of second plugs 112 may be formed by etching the bottom surfaces of the plurality of second through holes VH2 in the peripheral area PA. One second contact hole CH2 may be formed in each of some of the plurality of second through holes VH2, and two second contact holes CH2 may be formed in each of the remaining second through holes VH2. However, embodiments of the present inventive concept are not limited thereto.

[0098] In the peripheral area PA, the second through holes VH2 may expose top surfaces of the second plugs 112 together with the second contact holes CH2 .

[0099] Here, the capping layer 140 (see Figure 9 ) may not exist on the inner sidewall of the first contact hole CH1 and the inner sidewall of the second contact hole CH2.

[0100] refer to Figure 16 , a metal layer may be formed that at least partially fills the plurality of first through holes VH1 in the cell area CA (see Figure 15 ) and the first contact hole CH1 (see Figure 15 ), and at least partially fill the plurality of second through holes VH2 in the peripheral area PA (see Figure 15 ) and the second contact hole CH2 (see Figure 15 ).

[0101] After the metal layer is formed, the metal layer may be separated into nodes, thereby forming a first contact portion 171 in contact with the MTJ structure 130 and a cell via 173 in contact with the via plug 111b in the cell area CA. Simultaneously, a second contact portion 172 in contact with the second plug 112 may be formed in the peripheral area PA.

[0102] Here, in the cell region CA, the cell via 173 may be formed between adjacent MTJ structures 130. In addition, the vertical (ie, Z-direction) length of the cell via 173 may be substantially the same as the vertical length of the second contact portion 172, and the vertical length of the first contact portion 171 may be smaller than the vertical length of the second contact portion 172.

[0103] Through the above-described manufacturing process, the variable resistance memory device 100 according to some embodiments of the inventive concept may be manufactured.

[0104] According to the demand for high-integration variable resistance memory devices 100 and the development of manufacturing process technology, adjacent magnetoresistive memory cells 10u (see Figure 1 Therefore, in order to reduce the metal line resistance and cell resistance in the variable resistance memory device 100, there is a trend to form cell vias 173 between the MTJ structures 130.

[0105] A difference between the molded insulating layers (eg, the lower insulating layer, the buried insulating layer, the interlayer insulating layer, and the upper insulating layer) constituting the cell area CA and the peripheral area PA, and in particular, constituting the capping layer 140 (see Figure 11 ) may not exist in the peripheral area PA. Therefore, when the first contact hole CH1 and the second contact hole CH2 are simultaneously etched in the cell area CA and the peripheral area PA, it may be difficult to form the same etching profile.

[0106] To solve this problem, the method of manufacturing the variable resistance memory device 100 according to some embodiments of the present inventive concept includes removing the capping layer 140 in advance from the region where the cell via hole 173 is to be formed (see Figure 11 ) process.

[0107] Finally, according to the method of manufacturing the variable resistance memory device 100 of some embodiments conceived by the present invention, by forming the mold insulating layer from a material having similar etching selectivity in the cell area CA and the peripheral area PA, the difference between the etching profiles occurring during the simultaneous formation of the first contact hole CH1 and the second contact hole CH2 in the cell area CA and the peripheral area PA can be reduced.

[0108] Figure 17is a flowchart of a method of manufacturing a variable resistance memory device according to another embodiment.

[0109] refer to Figure 17 , the method S200 of manufacturing a variable resistance memory device may include first to ninth operations S210 to S290.

[0110] The method S200 for manufacturing a variable resistance memory device according to an embodiment of the present invention may include: a first operation S210 of forming a first plug including a first cell plug and a first via plug in a cell region, and forming a second plug in a peripheral region; a second operation S220 of forming a lower insulating layer, the lower insulating layer being on the first plug and the second plug and at least partially covering the first plug and the second plug; a third operation S230 of forming an MTJ structure penetrating or extending through the lower insulating layer and connected to the first cell plug; a fourth operation S240 of forming a capping layer, the capping layer being conformally located on the MTJ structure and the lower insulating layer and at least partially covering the MTJ structure and the lower insulating layer; and a fifth operation S250 of etching a portion of the capping layer to at least partially expose the MTJ structure and the lower insulating layer. a lower insulating layer in an area overlapping with the first via plug in the vertical or Z direction; a sixth operation S260, forming a buried insulating layer on the MTJ structure in the cell area, and removing the capping layer in the peripheral area and forming an interlayer insulating layer; a seventh operation S270, forming an upper insulating layer, which is on the buried insulating layer and the interlayer insulating layer, and at least partially covers the buried insulating layer and the interlayer insulating layer; an eighth operation S280, forming a first through hole overlapping with the first plug in the vertical or Z direction, and a second through hole overlapping with the second plug in the vertical or Z direction; and a ninth operation S290, forming a first contact hole by etching the bottom surface of the first through hole overlapping with the first via plug in the vertical or Z direction, and forming a second contact hole by etching the bottom surface of the second through hole.

[0111] The following will refer to Figures 18 to 22 Technical features of each of the first to ninth operations S210 to S290 are described in detail.

[0112] Figures 18 to 22 is a cross-sectional view illustrating a method of manufacturing a variable resistance memory device according to another embodiment in order of processes.

[0113] The formation methods of most components included in the method of manufacturing the variable resistance memory device 200 described below are similar to those previously described with reference to FIG. Figures 6 to 16 The described forming methods are substantially the same or similar. Therefore, for ease of explanation, the following description will focus on the differences from the above-described method of manufacturing the variable resistance memory device 100.

[0114] refer to Figure 18, a capping layer 240 may be formed over the cell area CA and the peripheral area PA, the capping layer 240 conformally on the top surface of the entire MTJ structure 130 and the lower insulating layer 120 , and at least partially covering the top surface of the entire MTJ structure 130 and the lower insulating layer 120 .

[0115] A capping layer 240 may be formed to protect the MTJ structure 130. The capping layer 240 is on and at least partially covers both the top and side surfaces of the MTJ structure 130, and may extend between adjacent MTJ structures 130. Therefore, the capping layer 240 may be referred to as an encapsulation layer.

[0116] The capping layer 240 may include an insulating material, for example, silicon nitride (SiN).

[0117] refer to Figure 19 , a mask pattern MP may be formed over the cell area CA and the peripheral area PA to at least partially expose a region overlapping the via plug 111 b in the Z direction.

[0118] By performing an etching process in the cell area CA using a mask pattern MP having a pattern hole MPH exposing only the area overlapping with the via plug 111b as an etching mask to remove a portion of the capping layer 240, the top surface of the second lower insulating layer 123 can be at least partially exposed to the outside only in the area overlapping with the via plug 111b in the Z direction.

[0119] By removing the capping layer 240 from the region overlapping the via plug 111 b , a difference between etching profiles occurring during a subsequent process of simultaneously forming the first and second contact holes CH1 and CH2 in the cell area CA and the peripheral area PA may be reduced.

[0120] Although not shown, according to other embodiments, the mask pattern MP may be formed to expose the capping layer 240 at the edge region of the substrate 101. Therefore, popping defects that may occur in the edge region of the substrate 101 during the etching process may be simultaneously removed.

[0121] Next, the mask pattern MP may be completely removed through ashing and stripping processes.

[0122] refer to Figure 20 , a buried insulating layer 151 may be formed over the cell area CA and the peripheral area PA.

[0123] The buried insulating layer 151 may include a first buried insulating layer 151a and a second buried insulating layer 151b formed on the first buried insulating layer 151a. The first buried insulating layer 151a and the second buried insulating layer 151b may include different materials.

[0124] In the cell area CA, the first buried insulating layer 151a may at least partially fill the space between the MTJ structures 130 without a void. In addition, the second buried insulating layer 151b may be formed on the top surface of the capping layer 240 and at least partially cover the top surface of the capping layer 240.

[0125] refer to Figure 21 , an upper insulating layer 160 may be formed on the buried insulating layer 151 in the cell area CA and at least partially covering the buried insulating layer 151 , and on the interlayer insulating layer 152 in the peripheral area PA and at least partially covering the interlayer insulating layer 152 .

[0126] The upper insulating layer 160 may include a first upper insulating layer 161, a second upper insulating layer 163 formed on the first upper insulating layer 161, and a third upper insulating layer 165 formed on the second upper insulating layer 163. The first upper insulating layer 161, the second upper insulating layer 163, and the third upper insulating layer 165 may include different materials from each other.

[0127] Next, a plurality of first via holes VH1 overlapping the plurality of first plugs 111 in the vertical direction Z are formed in the cell area CA, and a plurality of second via holes VH2 overlapping the plurality of second plugs 112 in the vertical direction Z are formed in the peripheral area PA.

[0128] Next, the first contact hole CH1 may be formed by etching the bottom surface of the first deep via hole VH1 b in the cell area CA, and the second contact hole CH2 may be formed by etching the bottom surfaces of the plurality of second via holes VH2 in the peripheral area PA.

[0129] Here, the capping layer 240 may not exist on the inner sidewalls of the first contact hole CH1 and the inner sidewalls of the second contact hole CH2 .

[0130] refer to Figure 22 , a metal layer may be formed that at least partially fills the plurality of first through holes VH1 in the cell area CA (see Figure 21 ) and the first contact hole CH1 (see Figure 21 ), and at least partially fill the plurality of second through holes VH2 in the peripheral area PA (see Figure 21 ) and the second contact hole CH2 (see Figure 21 ).

[0131] After the metal layer is formed, the metal layer may be separated into nodes, thereby forming a first contact portion 171 in contact with the MTJ structure 130 and a cell via 173 in contact with the via plug 111b in the cell area CA. Simultaneously, a second contact portion 172 in contact with the second plug 112 may be formed in the peripheral area PA.

[0132] Here, in the cell region CA, the cell via 173 may be formed between adjacent MTJ structures 130. In addition, the vertical (ie, Z-direction) length of the cell via 173 may be substantially the same as the vertical length of the second contact portion 172, and the vertical length of the first contact portion 171 may be smaller than the vertical length of the second contact portion 172.

[0133] The capping layer 240 continuously extends between the MTJ structures 130 adjacent to each other in the cell area CA, but the capping layer 240 may discontinuously extend in a region where the cell via hole 173 is formed.

[0134] Through the above-described manufacturing process, the variable resistance memory device 200 according to some embodiments of the inventive concept may be manufactured.

[0135] Figure 23 is a diagram showing a configuration of a data processing system including a variable resistance memory element according to an embodiment.

[0136] refer to Figure 23 , the data processing system 1000 may include a memory controller 1010 connected between a host and a variable resistance memory device VRM.

[0137] The memory controller 1010 may be configured to access the variable resistance memory device VRM in response to a request of a host.

[0138] The variable resistance memory device VRM may include any one of the variable resistance memory devices 100 and 200 manufactured according to the above-described methods S100 and S200 of manufacturing a variable resistance memory device. The memory controller 1010 may include a processor 1011 , a working memory 1013 , a host interface 1015 , and a memory interface 1017 .

[0139] The processor 1011 controls the overall operation of the memory controller 1010, and the working memory 1013 may store applications, data, and control signals required for the operation of the memory controller 1010. The host interface 1015 may perform protocol conversion for data / control signal exchange between the host and the memory controller 1010.

[0140] The memory interface 1017 may perform protocol conversion for data / control signal exchange between the memory controller 1010 and the variable resistance memory device VRM. Since the configuration and operating characteristics of the variable resistance memory device VRM are the same as those described above, a detailed description thereof is omitted.

[0141] The data processing system 1000 according to an embodiment may be a memory card, but is not limited thereto.

[0142] Figure 24 is a diagram showing a configuration of a data processing system including a variable resistance memory element according to an embodiment.

[0143] refer to Figure 24 The data processing system 1100 may include a variable resistance memory device VRM, a processor 1110 , a working memory 1120 , and a user interface 1130 , and may further include a communication module 1140 as needed.

[0144] The variable resistance memory device VRM may include any one of the variable resistance memory devices 100 and 200 manufactured according to the above-described methods S100 and S200 of manufacturing a variable resistance memory device.

[0145] The processor 1110 may be a central processing unit. The working memory 1120 stores applications, data, control signals, and the like required for the operation of the data processing system 1100. The user interface 1130 provides an environment through which a user can access the data processing system 1100 and provides the user with the data processing process and processing results of the data processing system 1100. Because the configuration and operating characteristics of the variable resistance memory device VRM are the same as those described above, a detailed description thereof will be omitted.

[0146] The data processing system 1100 may be used as a magnetic disk device, an internal / external memory card of a portable electronic device, an image processor, or an application chipset.

[0147] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method for manufacturing a variable resistance memory device, comprising: preparing a substrate having a unit area and a peripheral area surrounding the unit area in a plan view; forming a first plug including a first cell plug and a first via plug in the cell region, and forming a second plug in the peripheral region; forming a lower insulating layer on the first plug and the second plug over the cell region and the peripheral region; forming a magnetic tunnel junction (MTJ) structure extending through the lower insulating layer in the cell region and electrically connected to the first cell plug; conformally forming a capping layer on the MTJ structure and the lower insulating layer over the cell region and the peripheral region; forming capping patterns on both sidewalls of the MTJ structure by anisotropically etching the capping layer in the cell region; forming a buried insulating layer on the MTJ structure in the cell region and removing the capping layer from the peripheral region; forming an interlayer insulating layer on the lower insulating layer in the peripheral region; forming an upper insulating layer on the buried insulating layer in the cell region and on the interlayer insulating layer in the peripheral region; forming a first through hole overlapping with the first plug in the cell region in a direction perpendicular to an upper surface of the substrate, and forming a second through hole overlapping with the second plug in the peripheral region in the direction perpendicular to the upper surface of the substrate; as well as A first contact hole is formed by etching a bottom surface of the first through hole overlapping the first via plug in the cell region in the direction perpendicular to the upper surface of the substrate, and a second contact hole is formed by etching a bottom surface of the second through hole in the peripheral region.

2. The method according to claim 1, wherein When forming the first contact hole and the second contact hole, the capping layer does not exist on the inner sidewall of the first contact hole in the cell region and the inner sidewall of the second contact hole in the peripheral region.

3. The method according to claim 1, wherein When forming the first contact hole and the second contact hole, in the cell region, the first through hole alone exposes at least a portion of the top surface of the MTJ structure, or the first through hole and the first contact hole together expose at least a portion of the top surface of the first via plug, and In the peripheral region, the second via hole, together with the second contact hole, exposes at least a portion of a top surface of the second plug.

4. The method according to claim 3, further comprising: After forming the first and second contact holes, a metal layer is formed that at least partially fills the first through-hole and the first contact hole in the cell region and at least partially fills the second through-hole and the second contact hole in the peripheral region.

5. The method according to claim 4, wherein After forming the metal layer, the metal layer is separated into nodes to form a first contact portion contacting the MTJ structure and a cell via contacting the first via plug in the cell region, and a second contact portion contacting the second plug in the peripheral region.

6. The method according to claim 5, wherein: A vertical length of the unit via in the direction perpendicular to the upper surface of the substrate is the same as a vertical length of the second contact portion in the direction perpendicular to the upper surface of the substrate, and A vertical length of the first contact portion is smaller than a vertical length of the second contact portion.

7. The method according to claim 5, wherein: The cell via is formed between MTJ structures adjacent to each other in the cell region.

8. The method according to claim 1, wherein When forming the capping pattern, A portion of the capping layer is removed from the cell region to at least partially expose a top surface of the MTJ structure and a top surface of the lower insulating layer, but the capping layer is protected by the mask pattern in the peripheral region.

9. The method according to claim 8, wherein The capping layer functions as an etch stop layer in the peripheral region.

10. The method according to claim 1, wherein The buried insulating layer in the cell region and the interlayer insulating layer in the peripheral region are formed at the same vertical height with respect to the upper surface of the substrate as a reference plane, and the buried insulating layer includes a different material from the interlayer insulating layer.

11. A method for manufacturing a variable resistance memory device, the method comprising: preparing a substrate having a unit area and a peripheral area surrounding the unit area in a plan view; forming a first plug including a first cell plug and a first via plug in the cell region, and forming a second plug in the peripheral region; forming a lower insulating layer on the first plug and the second plug over the cell region and the peripheral region; forming a magnetic tunnel junction (MTJ) structure extending through the lower insulating layer in the cell region and electrically connected to the first cell plug; conformally forming a capping layer on the MTJ structure and the lower insulating layer over the cell region and the peripheral region; forming a mask pattern over the cell region and the peripheral region to at least partially expose a region overlapping the first via plug in a direction perpendicular to an upper surface of the substrate; etching a portion of the capping layer by using the mask pattern as an etching mask to at least partially expose the lower insulating layer in the region overlapping the first via plug in the direction perpendicular to the upper surface of the substrate; removing the mask pattern; forming a buried insulating layer on the MTJ structure in the cell region and removing the capping layer from the peripheral region; forming an interlayer insulating layer on the lower insulating layer in the peripheral region; forming an upper insulating layer on the buried insulating layer in the cell region and on the interlayer insulating layer in the peripheral region; forming a first through hole overlapping with the first plug in the cell region in the direction perpendicular to the upper surface of the substrate, and forming a second through hole overlapping with the second plug in the peripheral region in the direction perpendicular to the upper surface of the substrate; as well as A first contact hole is formed by etching a bottom surface of the first through hole overlapping the first via plug in the cell region in the direction perpendicular to the upper surface of the substrate, and a second contact hole is formed by etching a bottom surface of the second through hole in the peripheral region.

12. The method according to claim 11, wherein When forming the first and second vias, in the cell region, the first via is formed by removing a portion of the capping layer to at least partially expose a top surface of the MTJ structure.

13. The method according to claim 12, wherein: When forming the first contact hole and the second contact hole, in the cell region, the first through hole alone at least partially exposes the top surface of the MTJ structure, or the first through hole and the first contact hole together at least partially expose the top surface of the first via plug, and In the peripheral region, the second through hole together with the second contact hole at least partially exposes a top surface of the second plug.

14. The method according to claim 13, further comprising: After forming the first and second contact holes, a metal layer is formed that at least partially fills the first through-hole and the first contact hole in the cell region and at least partially fills the second through-hole and the second contact hole in the peripheral region.

15. The method according to claim 14, wherein After forming the metal layer, the metal layer is separated into nodes to form a first contact portion contacting the MTJ structure and a cell via contacting the first via plug in the cell region, and a second contact portion contacting the second plug in the peripheral region.

16. The method according to claim 15, wherein The cell via is formed between MTJ structures adjacent to each other in the cell region.

17. The method according to claim 16, wherein The capping layer continuously extends between the MTJ structures adjacent to each other in the cell region, but the capping layer discontinuously extends in a region where the cell via is formed.

18. The method according to claim 11, wherein When forming the mask pattern, the mask pattern at least partially exposes the capping layer at an edge region of the substrate.

19. A method for manufacturing a variable resistance memory device, the method comprising: preparing a substrate having a unit area and a peripheral area surrounding the unit area in a plan view; forming a first plug including a first cell plug and a first via plug in the cell region, and forming a second plug in the peripheral region; forming a lower insulating layer on the first plug and the second plug over the cell region and the peripheral region; forming a magnetic tunnel junction (MTJ) structure extending through the lower insulating layer in the cell region and electrically connected to the first cell plug; conformally forming a capping layer on the MTJ structure and the lower insulating layer over the cell region and the peripheral region; etching a portion of the capping layer to at least partially expose the lower insulating layer in a region overlapping the first via plug in a direction perpendicular to an upper surface of the substrate; forming a buried insulating layer on the MTJ structure in the cell region and removing the capping layer from the peripheral region; forming an interlayer insulating layer on the lower insulating layer in the peripheral region; forming an upper insulating layer on the buried insulating layer in the cell region and on the interlayer insulating layer in the peripheral region; forming a first through hole overlapping with the first plug in the cell region in the direction perpendicular to the upper surface of the substrate, and forming a second through hole overlapping with the second plug in the peripheral region in the direction perpendicular to the upper surface of the substrate; forming a first contact hole by etching a bottom surface of the first through hole overlapping with the first via plug in the cell region in the direction perpendicular to the upper surface of the substrate, and forming a second contact hole by etching a bottom surface of the second through hole in the peripheral region; forming a metal layer, the metal layer at least partially filling the first through hole and the first contact hole in the cell region, and at least partially filling the second through hole and the second contact hole in the peripheral region; as well as The metal layer is separated into nodes to form a first contact portion contacting the MTJ structure and a cell via contacting the first via plug in the cell region, and a second contact portion contacting the second plug in the peripheral region.

20. The method according to claim 19, wherein When forming the first contact hole and the second contact hole, the first contact hole and the second contact hole are formed simultaneously. wherein the first contact hole and the second contact hole have the same profile, and The capping layer does not exist on the inner sidewall of the first contact hole in the cell area and the inner sidewall of the second contact hole in the peripheral area.

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