Epitaxial wafer, epitaxial wafer test equipment and test method

Abstract

The invention provides an epitaxial wafer, epitaxial wafer testing equipment and an epitaxial wafer testing method. The epitaxial wafer comprises a substrate, and an N semiconductor layer, a light-emitting layer, a P semiconductor layer and a contact layer which are sequentially stacked on one side of the substrate, the contact layer comprises a plurality of patterned contact regions; at least one notch is further included; the gap penetrates through the P semiconductor layer, the light-emitting layer and at least part of the N semiconductor layer, and / or the gap penetrates through the contact region, the P semiconductor layer, the light-emitting layer and at least part of the N semiconductor layer. According to the epitaxial wafer provided by the embodiment of the invention, the contact layer is deposited and patterned above the P semiconductor layer, so that the contact resistance during testing is small, a fixed and accurate light-emitting area can be realized, the accuracy of test data is high, the data has high repeatability and stability, the test and data feedback period is short, and the test efficiency is high. And the time cost and the process cost are greatly reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of epitaxial wafer testing, and in particular to an epitaxial wafer, epitaxial wafer testing equipment and a testing method. Background Art

[0002] Epiwafer performance parameters are crucial data guides during epiwafer selection and subsequent processing and testing. Therefore, non-destructive epiwafer characterization is essential before light-emitting diode (LED) fabrication. The precision and accuracy of these characterization methods are crucial for semiconductor chip manufacturing. EL (electroluminescence) is widely used to test the optoelectronic parameters of LED epiwafers. EL uses an electric field to excite carriers and measure the spectrum of the emitted light, thereby obtaining electrical and optical data at different locations on the epiwafer for further chip fabrication. Summary of the Invention

[0003] The present invention provides an epitaxial wafer, an epitaxial wafer testing device, and a testing method. By depositing and patterning a contact layer above a P semiconductor layer, not only can the contact resistance be reduced during testing, but a fixed and precise light-emitting area can also be achieved. Compared with the current epitaxial wafer EL testing method (indium ball ohmic contact), the present invention has the advantages of high test data accuracy, high repeatability, and stability, and is not overly dependent on the probe stability of the testing machine. Compared with chip-on-wafer photonic testing (COW), the present invention has a short test and data feedback cycle (the data feedback time of this EL testing method is less than 16 hours, while conventional COW testing requires more than 5 days, and COW test wafers are usually wasted), and the time cost and process cost are greatly reduced.

[0004] According to a first aspect of the present invention, there is provided an epitaxial wafer comprising a substrate and an N semiconductor layer, a light emitting layer, a P semiconductor layer and a contact layer stacked in sequence on one side of the substrate;

[0005] The contact layer includes a plurality of patterned contact regions;

[0006] Also includes at least one notch;

[0007] The notch passes through the P semiconductor layer, the light emitting layer and at least a portion of the N semiconductor layer, and / or the notch passes through the contact region, the P semiconductor layer, the light emitting layer and at least a portion of the N semiconductor layer.

[0008] Optionally, the contact layer forms an ohmic contact with the P semiconductor layer; the transmittance of the contact layer is greater than or equal to 70%; and the thickness of the contact layer is 10 nm-1.5 μm.

[0009] Optionally, multiple test groups are also included;

[0010] The test group includes a first test unit and a second test unit;

[0011] The first test unit includes at least one N semiconductor layer gap; the second test unit includes at least one P contact region; and the areas of the plurality of P contact regions are the same or different.

[0012] Optionally, the projection pattern of the contact area on the substrate includes at least one of the following shapes: circle, rectangle, triangle, polygon and ellipse.

[0013] Optionally, the notch is formed by at least one of voltage breakdown, mechanical drilling or laser breakdown.

[0014] Optionally, the material of the contact layer includes indium tin oxide or nickel gold alloy.

[0015] Optionally, the coating process of the contact layer includes physical vapor deposition or chemical vapor deposition; and the patterning process of the contact layer includes photolithography.

[0016] Optionally, the area of ​​the contact zone is 0.001 mm 2 -10mm 2 The test current density of the contact area is 0.001A / cm 2 -500A / cm 2 .

[0017] Optionally, the electrical conductivity of the contact layer is greater than or equal to 10 times the electrical conductivity of the P semiconductor layer.

[0018] Optionally, the light-emitting layer includes a multi-quantum well layer or a quantum well layer.

[0019] According to a second aspect of the present invention, there is provided an epitaxial wafer testing device for testing the epitaxial wafer according to any one of the first aspects of the present invention, the testing device comprising: a carrier, at least one P probe and at least one N probe;

[0020] The carrier is used to carry the epitaxial wafer to be tested;

[0021] The test ends of the P probe and the N probe are used to contact the epitaxial wafer to be tested during testing;

[0022] The power supply end of the P probe is connected to the positive electrode of the power supply, and the power supply end of the N probe is connected to the negative electrode of the power supply.

[0023] Optionally, it further comprises at least one breakdown head;

[0024] The breakdown head is used to penetrate the P semiconductor layer, the light-emitting layer and at least part of the N semiconductor layer of the epitaxial wafer to be tested to form a gap, and / or the breakdown head is used to penetrate the contact area of ​​the epitaxial wafer to be tested, the P semiconductor layer, the light-emitting layer and at least part of the N semiconductor layer to form a gap.

[0025] Optionally, the gap is formed by the N probe and / or the P probe through at least one of voltage breakdown, mechanical drilling or laser breakdown.

[0026] Optionally, the breakdown head forms the gap by at least one of voltage breakdown, mechanical drilling or laser breakdown.

[0027] Optionally, the breakdown voltage of the voltage breakdown is 80V-300V, the breakdown current is 0.1mA-100mA, and the breakdown time is 1s-10s.

[0028] According to a third aspect of the present invention, a method for testing an epitaxial wafer is provided, which is applicable to any of the epitaxial wafer testing equipment described in the second aspect of the present invention, and the testing method comprises:

[0029] Provide epitaxial wafers to be tested;

[0030] preparing at least one notch in the epitaxial wafer to be tested;

[0031] The test end of the P probe contacts the contact area of ​​the epitaxial wafer to be tested, and the test end of the N probe contacts the notch of the epitaxial wafer to be tested to form a test loop to test the epitaxial wafer to be tested.

[0032] Optionally, the test end of the P probe contacts the contact area of ​​the epitaxial wafer to be tested, and the test end of the N probe contacts the notch of the epitaxial wafer to be tested to form a test loop to test the epitaxial wafer to be tested, further comprising:

[0033] The testing end of the P probe contacts the Mth contact area of ​​the epitaxial wafer to be tested, and the testing end of the N probe contacts the Mth notch of the epitaxial wafer to be tested to form a testing loop to test the epitaxial wafer to be tested;

[0034] preparing an M+1th notch in the epitaxial wafer to be tested;

[0035] The testing end of the P probe contacts the M+1th contact area of ​​the epitaxial wafer to be tested, and the testing end of the N probe contacts the M+1th notch of the epitaxial wafer to be tested to form a testing loop to test the epitaxial wafer to be tested;

[0036] Wherein, M is a positive integer greater than or equal to 1.

[0037] Optionally, the test end of the P probe contacts the P contact area of ​​the epitaxial wafer to be tested, and the test end of the N probe contacts the notch of the epitaxial wafer to be tested to form a test loop to test the epitaxial wafer to be tested, further comprising:

[0038] The test end of the P probe sequentially contacts the first P contact area to the Mth P contact area of ​​the epitaxial wafer to be tested; the test end of the N probe contacts one of the notches of the epitaxial wafer to be tested, forming a test loop to test the epitaxial wafer to be tested;

[0039] Wherein, M is a positive integer greater than or equal to 2. Optionally, the test end of the P probe contacts the contact area of ​​the epitaxial wafer to be tested, and the test end of the N probe contacts the notch of the epitaxial wafer to be tested to form a test loop to test the epitaxial wafer to be tested, and further includes:

[0040] The test end of the P probe sequentially contacts the first contact area to the Mth contact area of ​​the epitaxial wafer to be tested; the test end of the N probe sequentially contacts the first notch to the Mth notch of the epitaxial wafer to be tested to form a test loop to test the epitaxial wafer to be tested;

[0041] Wherein, M is a positive integer greater than or equal to 2.

[0042] Optionally, the test end of the P probe contacts the contact area of ​​the epitaxial wafer to be tested, and the test end of the N probe contacts the notch of the epitaxial wafer to be tested to form a test loop to test the epitaxial wafer to be tested, further comprising:

[0043] The test end of the P probe and the test end of the N probe respectively contact different contact areas to form a test loop to test the resistance of the P semiconductor layer of the epitaxial wafer to be tested.

[0044] Optionally, the test end of the P probe contacts the contact area of ​​the epitaxial wafer to be tested, and the test end of the N probe contacts the notch of the epitaxial wafer to be tested to form a test loop to test the epitaxial wafer to be tested, further comprising:

[0045] Prepare the Mth notch and the M+1th notch of the epitaxial wafer to be tested

[0046] The testing end of the P probe contacts the Mth notch of the epitaxial wafer to be tested, and the testing end of the N probe contacts the M+1th notch of the epitaxial wafer to be tested to form a testing loop to test the resistance of the N semiconductor layer of the epitaxial wafer to be tested;

[0047] Preparing the M+2th notch and the M+3th notch of the epitaxial wafer to be tested;

[0048] The testing end of the P probe contacts the M+2th notch of the epitaxial wafer to be tested, and the testing end of the N probe contacts the M+3th notch of the epitaxial wafer to be tested to form a testing loop to test the resistance of the N semiconductor layer of the epitaxial wafer to be tested;

[0049] Wherein, M is a positive integer greater than or equal to 1.

[0050] Optionally, the test end of the P probe contacts the contact area of ​​the epitaxial wafer to be tested, and the test end of the N probe contacts the notch of the epitaxial wafer to be tested to form a test loop to test the epitaxial wafer to be tested, further comprising:

[0051] The test end of the P probe and the test end of the N probe respectively contact different notches to form a test loop to test the resistance of the N semiconductor layer of the epitaxial wafer to be tested.

[0052] Optionally, before preparing at least one notch in the epitaxial wafer to be tested, the method further includes:

[0053] The contact layer of the epitaxial wafer to be tested is patterned to form a plurality of contact regions.

[0054] The present invention provides an epitaxial wafer, epitaxial wafer testing equipment, and testing method, comprising a substrate and an N semiconductor layer, a light-emitting layer, a P semiconductor layer, and a contact layer stacked in sequence on one side of the substrate; the contact layer comprises a plurality of patterned contact regions; and further comprises at least one notch; the notch penetrates the P semiconductor layer, the light-emitting layer, and at least a portion of the N semiconductor layer, and / or the notch penetrates the contact region, the P semiconductor layer, the light-emitting layer, and at least a portion of the N semiconductor layer. The epitaxial wafer provided by the embodiment of the present invention deposits and patterns the contact layer on top of the P semiconductor layer, which not only reduces the contact resistance during testing but also provides a fixed and precise light-emitting area. Compared with the current epitaxial wafer EL testing method (indium ball ohmic contact), it has the advantages of high test data accuracy, high repeatability, and stability, and is not overly dependent on the probe stability of the test machine. Compared with COW testing, it has a short test and data feedback cycle (the data feedback time of this EL testing method is less than 16 hours, while conventional COW testing requires more than 5 days, and COW test wafers are usually wasted), and the time cost and process cost are greatly reduced.

[0055] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0057] Figure 1 This is a schematic structural diagram of an epitaxial wafer provided by an embodiment of the present invention;

[0058] Figure 2 is a schematic structural diagram of another epitaxial wafer provided by an embodiment of the present invention;

[0059] Figure 3 1 is a schematic diagram of a test group of an epitaxial wafer provided in an embodiment of the present invention;

[0060] Figure 4 1 is a schematic diagram of another epitaxial wafer test group provided by an embodiment of the present invention;

[0061] Figure 5 1 is a schematic structural diagram of an epitaxial wafer testing device provided by an embodiment of the present invention;

[0062] Figure 6 1 is a schematic structural diagram of another epitaxial wafer testing device provided by an embodiment of the present invention;

[0063] Figure 7 This is a schematic diagram of voltage breakdown in an epitaxial wafer testing device provided by an embodiment of the present invention;

[0064] Figure 8 This is a flow chart of an epitaxial wafer testing method provided by an embodiment of the present invention;

[0065] Figure 9 This is a test sequence diagram of an epitaxial wafer testing method provided by an embodiment of the present invention;

[0066] Figure 10 This is a flow chart of another epitaxial wafer testing method provided by an embodiment of the present invention;

[0067] Figure 11 This is a flow chart of another epitaxial wafer testing method provided by an embodiment of the present invention;

[0068] Figure 12 This is a flow chart of another epitaxial wafer testing method provided by an embodiment of the present invention;

[0069] Figure 13 Schematic diagram of another epitaxial wafer testing method provided by an embodiment of the present invention;

[0070] Figure 14This is a flow chart of another epitaxial wafer testing method provided by an embodiment of the present invention;

[0071] Figure 15 Schematic diagram of another epitaxial wafer testing method provided by an embodiment of the present invention;

[0072] Figure 16 Schematic diagram of another epitaxial wafer testing method provided by an embodiment of the present invention;

[0073] Figure 17 This is a flow chart of another epitaxial wafer testing method provided by an embodiment of the present invention;

[0074] Figure 18 This is a flow chart of another epitaxial wafer testing method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0075] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0076] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0077] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0078] In the prior art, there are basically three ways to test epitaxial wafers:

[0079] 1. Indium ball pressing. The existing indium pressing method is difficult to form a good ohmic contact with the front of the epitaxial wafer, resulting in high contact resistance. In addition, the operation of the indium pressing method is subject to human interference, resulting in the inability to accurately calculate the actual contact area with the front of the epitaxial wafer. This, in turn, leads to large errors in the test results of photoelectric parameters, poor reliability, and low accuracy. In addition, in order to improve the accuracy of EL testing, the diameter of the indium ball must be very small. However, small-diameter indium balls are difficult to manufacture, resulting in high difficulty and high cost in preparing P-type contact points.

[0080] 2. Bruker tester. The P probe of this tester directly contacts the P semiconductor layer of the epitaxial wafer, resulting in high contact resistance and large errors in test results. Forming contact with the N semiconductor layer requires a fixture, which is very inconvenient and costly.

[0081] 3. Chip on Wafer (COW) testing: The long preparation process leads to high time and process costs, and generates additional material and process costs, resulting in unnecessary waste of production line resources. The waste accounts for about 5% of the total production capacity. This is a common situation for all LED companies.

[0082] In order to solve the problems existing in the above-mentioned prior art, an embodiment of the present invention provides an epitaxial wafer. Figure 1 is a structural diagram of an epitaxial wafer provided by an embodiment of the present invention, Figure 2 This is a schematic diagram of the structure of another epitaxial wafer provided by an embodiment of the present invention, with reference to Figure 1 and Figure 2 The epitaxial wafer 100 includes: a substrate 1 and an N semiconductor layer 2, a light emitting layer 3, a P semiconductor layer 4 and a contact layer 5 stacked in sequence on one side of the substrate 1; the contact layer 5 includes a plurality of patterned contact areas 51; and further includes at least one notch 6; the notch 6 penetrates the P semiconductor layer 4, the light emitting layer 3 and at least a portion of the N semiconductor layer 2 (such as Figure 1 As shown), and / or the gap 6 passes through the contact region 51, the P semiconductor layer 4, the light emitting layer 3 and at least part of the N semiconductor layer 2 (as shown Figure 2 shown).

[0083] Among them, epitaxial wafers are a type of semiconductor material formed on a single crystal substrate through epitaxial growth technology, and are widely used in the manufacture of semiconductor devices such as integrated circuits, power devices, and optoelectronic devices.

[0084] Specifically, the epitaxial wafer 100 provided in the embodiment of the present invention includes a substrate 1 and an N semiconductor layer 2, a light emitting layer 3, a P semiconductor layer 4 and a contact layer 5 stacked in sequence on one side of the substrate 1 (for example, it can be deposited on the upper side); the contact layer 5 is deposited on the upper side of the P semiconductor layer 4, and the contact layer 5 is patterned to form a plurality of patterned contact areas 51, and further includes at least one notch 6, the notch 6 penetrates the P semiconductor layer 4, the light emitting layer 3 and at least a portion of the N semiconductor layer 2 (for example, Figure 1 As shown), and / or the gap 6 passes through the contact region 51, the P semiconductor layer 4, the light emitting layer 3 and at least part of the N semiconductor layer 2 (as shown Figure 2 As shown), more preferably, under the premise of ensuring that the notch 6 penetrates the N semiconductor layer 2, the notch 6 can be set to penetrate half of the total thickness of the N semiconductor layer 2, so that during the test process, the notch 6 is not set too shallow, resulting in an inability to accurately contact the N semiconductor layer 2 and affecting the test results, and the notch 6 is not set too deep, resulting in the probe piercing the N semiconductor layer 2 and affecting the test results. The setting conditions of the contact layer 5 include:

[0085] 1. A good ohmic contact should be formed between the contact layer 5 and the P semiconductor layer 4.

[0086] 2. The contact layer 5 has good conductivity, which should be at least one order of magnitude higher than the conductivity of the P semiconductor layer 4.

[0087] 3. The transmittance of the contact layer 5 is good, at least guaranteed to be above 70%.

[0088] The epitaxial wafer provided in the embodiment of the present invention, by depositing and patterning a contact layer above the P semiconductor layer, can not only reduce the contact resistance during testing, but also have a fixed and precise light-emitting area. The test data is highly accurate and the data is highly repeatable and stable. The test and data feedback cycle is short, and the time cost and process cost are greatly reduced.

[0089] Optionally, the contact layer 5 forms an ohmic contact with the P semiconductor layer 4 ; the transmittance of the contact layer 5 is greater than or equal to 70%, and the thickness of the contact layer 5 is 10 nm-1.5 μm.

[0090] Ohmic contact refers to a very low contact resistance between the metal (or contact layer 5) and the P semiconductor layer 4, with a linear relationship between current and voltage (in accordance with Ohm's law). This contact does not introduce additional potential barriers and can efficiently transmit carriers (electrons or holes). Transmittance refers to the efficiency of light transmission through the contact layer. The higher the transmittance, the less light is absorbed or reflected by the contact layer 5.

[0091] Specifically, the material selection of the contact layer 5 in the embodiment of the present invention must ensure good ohmic contact between the contact layer 5 and the P semiconductor layer 4, so that the resistance between the contact layer 5 and the P semiconductor layer is very low, thereby ensuring high accuracy of the test data and small error; the transmittance of the contact layer 5 is greater than or equal to 70% to further ensure the accuracy of the test data, and the thickness of the contact layer is between 10nm-1.5μm.

[0092] The contact layer is patterned to form a plurality of contact regions, and the contact regions at least include P contact regions. It is understood that the contact regions may include only P contact regions, or may include P contact regions and contact regions where notches may be formed.

[0093] Figure 3 1 is a schematic diagram of a test group of an epitaxial wafer provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of another epitaxial wafer test group provided by an embodiment of the present invention, with reference to Figure 3 or Figure 4 Optionally, the epitaxial wafer provided in an embodiment of the present invention further includes multiple test groups X, the test group X includes a first test unit and a second test unit; the first test unit includes at least one N semiconductor layer gap X1; the second test unit includes at least one P contact area X2, and the areas of the multiple P contact areas are the same or different.

[0094] Specifically, the epitaxial wafer provided in the embodiment of the present invention further includes a design of multiple test groups X, for example, referring to Figure 3 , Figure 3 The diagram shows that the test group X includes two N semiconductor layer notches X1 and one P contact region X2. The two N semiconductor layer notches X1 on the left are formed by high-voltage breakdown, mechanical drilling, or laser breakdown. The circular portion on the right is the P contact region X2 formed by depositing and patterning a contact layer. The two N semiconductor layer notches X1 can penetrate the contact layer, the P semiconductor layer, the light-emitting layer, and at least a portion of the N semiconductor layer (i.e., on the contact layer), or can penetrate the P semiconductor layer, the light-emitting layer, and at least a portion of the N semiconductor layer (i.e., not on the contact layer).

[0095] or reference Figure 4 , Figure 4It is shown that the test group X includes two N semiconductor layer gaps X1 and four P contact areas X2. The two N semiconductor layer gaps X1 on the left are formed by high-voltage breakdown, mechanical drilling or laser breakdown. The four rectangles on the right are P contact areas X2 formed by depositing a contact layer and patterning the contact layer. The two N semiconductor layer gaps X1 can penetrate the contact layer, the P semiconductor layer, the light-emitting layer and at least part of the N semiconductor layer (i.e., on the contact layer), or penetrate the P semiconductor layer, the light-emitting layer and at least part of the N semiconductor layer (i.e., not on the contact layer); the areas of the four rectangles in the P contact area X2 can be the same or different (i.e., Figure 4 The four rectangles shown in FIG. 5 have different areas). The present embodiment does not limit the number of N semiconductor layer notches X1 and P contact regions X2. Flexible modifications of the N semiconductor layer notches X1 and P contact regions X2 according to actual needs by those skilled in the art should also fall within the scope of protection of the present invention. This is not an exhaustive list. Optionally, the projection pattern of contact region 51 on substrate 1 includes at least one of the following shapes: circular, rectangular, triangular, polygonal, and elliptical.

[0096] Specifically, the projection pattern of the contact area 51 of the patterned contact layer 5 on the substrate 1 can be one or more of a circle, a rectangle, a triangle, a polygon and an ellipse. The specific projection pattern can be set as needed.

[0097] Optionally, the notch 6 is formed by at least one of voltage breakdown, mechanical drilling or laser breakdown.

[0098] Among them, voltage breakdown refers to the situation where the voltage applied to the insulating material or semiconductor device exceeds its tolerance limit, causing the material or device to suddenly lose its insulation performance, resulting in a sharp increase in current, thereby achieving the preparation of the gap 6;

[0099] Mechanical drilling: refers to a processing method of making holes in various materials (including semiconductor devices) by mechanical equipment to complete the preparation of the gap 6;

[0100] Laser breakdown: Laser-induced breakdown spectroscopy (LIBS) is used to directly utilize high-energy-density ultrashort pulse laser to focus on the surface of the epitaxial wafer 100 to complete the preparation of the gap 6 .

[0101] Specifically, the gap 6 can be formed by voltage breakdown, mechanical punching or laser breakdown. The embodiment of the present invention does not limit this. As long as the gap 6 can penetrate the P semiconductor layer 4, the light-emitting layer 3 and at least part of the N semiconductor layer 2, and / or the gap 6 penetrates the contact area 51, the P semiconductor layer 4, the light-emitting layer 3 and at least part of the N semiconductor layer 2, the preparation method is within the protection scope of the embodiment of the present invention.

[0102] Optionally, the material of the contact layer 5 includes indium tin oxide or nickel gold alloy.

[0103] Specifically, indium tin oxide (ITO) has good electrical conductivity and optical properties with a transparency of more than 85%; nickel-gold alloy (NiAu) is an alloy composed of nickel as a matrix and appropriate additions of gold and other elements, and has good electrical conductivity and thermal conductivity. The material of the contact layer 5 includes indium tin oxide or nickel-gold alloy, thereby ensuring that the contact layer 5 meets the requirements of good ohmic contact with the P semiconductor layer 4, an electrical conductivity one order of magnitude higher than the P semiconductor layer 4, and a transmittance of more than 70%.

[0104] Optionally, the coating process of the contact layer 5 includes physical vapor deposition or chemical vapor deposition; and the patterning process of the contact layer 5 includes photolithography.

[0105] Among them, physical vapor deposition (PVD) refers to the use of physical methods under vacuum conditions to vaporize the surface of a material source (solid or liquid) into gaseous atoms, molecules or partially ionize them into ions, and deposit a thin film with certain special functions on the surface of a substrate through a low-pressure gas (or plasma) process; chemical vapor deposition (CVD) is a process that uses one or more gaseous precursor reactants containing thin film elements to form a solid thin film on the surface of a substrate through a chemical reaction at a certain temperature; the photolithography process uses optical principles to accurately transfer circuit patterns to silicon wafers.

[0106] Specifically, the method of depositing the contact layer 5 on the P semiconductor layer 5 includes physical vapor deposition or chemical vapor deposition; the process of patterning the contact layer 5 to form the plurality of contact regions 51 includes a photolithography process.

[0107] Optionally, the area of ​​the contact area 51 is 0.001 mm 2 -10mm 2 , the test current density of the contact area 51 is 0.001A / cm 2 -500A / cm 2 .

[0108] Specifically, the design area of ​​the contact layer 5 is 0.001mm 2 -10mm 2 The test current density that the contact layer 5 can accept is 0.001A / cm 2 -500A / cm 2 , thus making the test results more accurate.

[0109] Optionally, the electrical conductivity of the contact layer 5 is greater than or equal to 10 times the electrical conductivity of the P semiconductor layer 4 .

[0110] Optionally, the light-emitting layer 3 includes a multi-quantum well layer or a quantum well layer.

[0111] Among them, the multi-quantum well layer is a thin film structure formed by alternating arrangements of two or more materials. The thickness of each layer of material is about several nanometers to tens of nanometers, which is much smaller than the wavelength of light. For example, the multi-quantum well layer is composed of material systems such as GaAs / AlGaAs and InGaAs / InP. The quantum well layer is composed of a barrier layer of material with a larger band gap and a well layer with a smaller band gap.

[0112] Figure 5 1 is a schematic structural diagram of an epitaxial wafer testing device provided by an embodiment of the present invention. Figure 6 This is a schematic diagram of the structure of another epitaxial wafer testing device provided by an embodiment of the present invention, with reference to Figure 5 and Figure 6 According to the same inventive concept, an embodiment of the present invention provides an epitaxial wafer testing device for testing any of the epitaxial wafers in the above-mentioned embodiments of the invention. The testing device 200 includes: a carrier 7, at least one P probe 8, and at least one N probe 9;

[0113] The carrier 7 is used to carry the epitaxial wafer to be tested;

[0114] During testing, the test ends of the P probe 8 and the N probe 9 contact the epitaxial wafer under test; the power supply end of the P probe 8 is connected to the positive terminal of the power supply, and the power supply end of the N probe 9 is connected to the negative terminal of the power supply. Specifically, the epitaxial wafer testing device 200 provided in an embodiment of the present invention is used to test the epitaxial wafer described in any of the above-mentioned embodiments of the invention. The testing device 200 includes: a carrier 7, at least one P probe 8, and at least one N probe 9. The P probe 8 and the N probe 9 form a test loop with the power supply to test the epitaxial wafer under test, and the carrier 7 is used to support the epitaxial wafer under test.

[0115] The testing equipment 200 breaks down or mechanically punches at least one extremely small point on the epitaxial wafer to expose the N semiconductor layer 2. The N probe 9 contacts the point to form a stable electrical connection. The P probe 8 forms a stable electrical connection with the contact area of ​​the epitaxial wafer. The N probe 9 and the P probe 8 form a test loop for testing. It can be understood that the P probe 8 and the N probe 9 are connected to the power supply. When there is a test requirement, it is only necessary to perform a contact operation on the test ends of the P probe 8 and the N probe 9 to complete the test. There is no need to connect to the power supply, which greatly reduces the time cost and preparation cost.

[0116] Optionally, the test device 200 further comprises at least one breakdown head (not shown in the figure); the breakdown head is used to penetrate the P semiconductor layer 4, the light emitting layer 3 and at least part of the N semiconductor layer 2 of the epitaxial wafer to be tested to form a gap 6 (such as Figure 5As shown), and / or the breakdown head is used to penetrate the contact area 51 of the epitaxial wafer to be tested, the P semiconductor layer 4, the light emitting layer 3 and at least part of the N semiconductor layer 2 to form a gap 6 (as shown Figure 6 shown).

[0117] Specifically, the test end of the P probe is pressed against one of the contact areas 51 of the epitaxial wafer to be tested, the test end of the N probe is pressed against the notch 6 of the epitaxial wafer to be tested, the power end of the P probe 8 is connected to the positive pole of the power supply, and the power end of the N probe 9 is connected to the negative pole of the power supply to form a test circuit to test the optoelectronic parameters of the epitaxial wafer to be tested.

[0118] Figure 7 This is a schematic diagram of a voltage breakdown in an epitaxial wafer testing device provided by an embodiment of the present invention, with reference to Figure 7 , the test device 200 can directly apply high voltage to the N probe 9 and the P probe 8 to form the gap 6, so that the P probe 8 and the N probe 9 directly have a breakdown function, thereby reducing the weight of the test device 200 and reducing the cost of manufacturing the test device 200. Figure 7 As shown, two notches 6 can be punched through simultaneously or only one notch 6 can be punched through.

[0119] Optionally, the breakdown head forms the notch 6 by at least one of voltage breakdown, mechanical drilling or laser breakdown.

[0120] Specifically, the testing device 200 may be provided with a breakdown head, which has a breakdown function and may be movable or fixed; the mechanical punching head may be movable or fixed.

[0121] The defects are prepared by a breakdown head based on at least one of voltage breakdown, mechanical drilling or laser breakdown.

[0122] In one embodiment of the present invention, the testing device 200 has two breakdown heads, which are respectively connected to the positive and negative poles of a power supply. The power supply applies high voltage to the two breakdown heads to form the notch 6 .

[0123] Optionally, the breakdown voltage of the voltage breakdown is 80V-300V, the breakdown current is 0.1mA-100mA, and the breakdown time is 1s-10s.

[0124] Specifically, the voltage breakdown designed for the test equipment 200 is 80V-300V, the breakdown current is 0.1mA-100mA, and the breakdown time is 1s-10s. The embodiment of the present invention does not limit this, and the breakdown voltage, breakdown current, and breakdown time can be adjusted according to actual needs.

[0125] Figure 8 This is a flow chart of an epitaxial wafer testing method provided by an embodiment of the present invention. Figure 9This is a test sequence diagram of an epitaxial wafer testing method provided by an embodiment of the present invention, with reference to Figure 5-9 According to the same inventive concept, an embodiment of the present invention provides a method for testing an epitaxial wafer, which is applicable to any epitaxial wafer testing device in the above-mentioned inventive embodiments. The testing method includes:

[0126] S101. Provide an epitaxial wafer to be tested.

[0127] Specifically, the epitaxial wafer to be tested for optoelectronic parameters is obtained and placed on a carrier of a test device. Before the test, the following steps may also be performed:

[0128] The test equipment 200 performs a standard film test. If the test is accurate, no calibration is required. If it is inaccurate, calibration is performed. A test program is designed for the test equipment 200 so that it can perform optoelectronic tests on relevant areas according to requirements.

[0129] The test procedures include (the order can be changed according to needs):

[0130] a) Test template setting: setting of the relative position of the gap to be made and the contact area, etc.

[0131] b) Target point capture

[0132] c) Notch breakdown data setting

[0133] d) Test path settings

[0134] e) Test condition setting: such as constant current source design (designed according to the contact area, range 1mA-1A), downward movement distance of the N probe and / or P probe, etc.

[0135] Specifically, the test path may be ACIG, etc., and the embodiment of the present invention does not limit the test order, wherein Q1 is the point when the N probe collides with the N semiconductor layer, and AL is the point when the P probe collides with different contact areas.

[0136] S102, preparing at least one notch in the epitaxial wafer to be tested.

[0137] Specifically, the gap 6 is prepared on the epitaxial wafer to be tested by the testing equipment 200. The gap 6 can be formed by applying a high voltage signal through the P probe 8 and the N probe 9 to break down the epitaxial wafer to be tested. The gap 6 can also be formed by a breakdown head. It can also be prepared by mechanical drilling or laser breakdown.

[0138] S103 , the test end of the P probe 8 contacts the contact area of ​​the epitaxial wafer to be tested; the test end of the N probe 9 contacts the notch of the epitaxial wafer to be tested to form a test loop to test the epitaxial wafer to be tested.

[0139] Specifically, the test end of the P probe 8 contacts the contact area of ​​the epitaxial wafer to be tested. It can be understood that since the epitaxial wafer provided in the embodiment of the present invention has multiple contact areas 51, the test end of the P probe 8 contacts one of the contact areas 51 of the epitaxial wafer to be tested to form a test loop, thereby testing the epitaxial wafer to be tested.

[0140] The epitaxial wafer testing method provided in the embodiment of the present invention can achieve the same technical effects as the epitaxial wafer testing equipment in the above-mentioned invention embodiment, and the embodiment of the present invention will not be described in detail here.

[0141] Based on the above-mentioned embodiment of the invention, the embodiment of the present invention further refines the method of forming a test loop by contacting the test end of the P probe with the contact area of ​​the epitaxial wafer to be tested and the test end of the N probe with the notch of the epitaxial wafer to be tested to test the epitaxial wafer to be tested. Figure 10 This is another flow chart of an epitaxial wafer testing method provided by an embodiment of the present invention, refer to Figure 10 , the testing method provided by the embodiment of the present invention includes:

[0142] S201. Provide an epitaxial wafer to be tested.

[0143] S202, preparing at least one notch in the epitaxial wafer to be tested.

[0144] S203 , the test end of the P probe contacts the Mth contact area of ​​the epitaxial wafer to be tested, and the test end of the N probe contacts the Mth notch of the epitaxial wafer to be tested to form a test loop to test the epitaxial wafer to be tested.

[0145] Specifically, a notch can be prepared on the epitaxial wafer to be tested, and then the test end of the P probe is pressed against the Mth (here can be the first) contact area of ​​the epitaxial wafer to be tested, and the test end of the N probe is pressed against the Mth (here can be the first) notch of the epitaxial wafer to be tested. The power supply end of the P probe is connected to the positive pole of the power supply, and the power supply end of the N probe is connected to the negative pole of the power supply to form a test loop to test the epitaxial wafer to be tested. Specifically, in the above step S203, after the test end of the P probe is pressed against the first contact area, the power supply end of the P probe is connected to the positive pole of the power supply, and after the test end of the N probe is pressed against the first notch, the power supply end of the N probe is connected to the negative pole of the power supply to form a test loop to test the first test point (i.e., the first contact area and the first notch) of the epitaxial wafer to be tested.

[0146] S204 , preparing the M+1th notch of the epitaxial wafer to be tested.

[0147] Specifically, after the first test point of the epitaxial wafer to be tested is tested in the above step S204, an M+1th (here, the second) notch is prepared in the epitaxial wafer to be tested.

[0148] S205 , the testing end of the P probe contacts the M+1 th contact area of ​​the epitaxial wafer to be tested, and the testing end of the N probe contacts the M+1 th notch of the epitaxial wafer to be tested.

[0149] Specifically, after preparing the M+1th (here can be the second) notch of the epitaxial wafer to be tested, the test end of the P probe is sequentially touched to the M+1th contact area (here can be the second) of the epitaxial wafer to be tested, and the test end of the N probe is sequentially touched to the M+1th (here can be the second) notch of the epitaxial wafer to be tested to form a test loop to test the epitaxial wafer to be tested.

[0150] Specifically, in step S206, the test ends of the P probe and the N probe are brought into contact with the second contact area and the second notch of the epitaxial wafer to be tested, respectively, to form a test loop, where M is a positive integer greater than or equal to 1. The epitaxial wafer to be tested is tested via the test loop. It can be understood that this embodiment of the present invention is a specific technical solution of "testing while preparing notches," i.e., preparing a first notch and testing the first test point; then preparing a second notch and testing the second test point; and finally preparing an Mth notch and testing the Mth test point.

[0151] Optionally, the test end of the P probe contacts the P contact area of ​​the epitaxial wafer to be tested, and the test end of the N probe contacts the notch of the epitaxial wafer to be tested to form a test loop to test the epitaxial wafer to be tested, further comprising:

[0152] The test end of the P probe sequentially contacts the first P contact area to the Mth P contact area of ​​the epitaxial wafer to be tested; the test end of the N probe contacts one of the notches of the epitaxial wafer to be tested, forming a test loop to test the epitaxial wafer to be tested; wherein M is a positive integer greater than or equal to 2.

[0153] Specifically, refer to Figure 4 In the embodiment of the present invention, the test end of the P probe sequentially contacts the first P contact area X2 to the M-th contact area X2 (in Figure 4 In the example, M is 4), the test end of the N probe contacts one of the gaps in the epitaxial wafer to be tested (i.e. Figure 4 One of the N semiconductor layer gaps X1 on the left forms a test loop for testing, for example, continue to refer to Figure 4 , place the N probe against one of the N semiconductor layer gaps X1, and place the P probe against the first P contact area X2 in sequence to form a test loop for testing. After the test is complete, move the P probe to the second P contact area X2, and the N and P probes form a test loop for testing, and so on. The test steps can be sequentially: the upper left corner P contact area X2, the lower P contact area X2, the upper right corner P contact area X2, and the largest area P contact area X2. The present embodiment does not limit the order in which the P probes contact the P contact areas X2.

[0154] Based on the above-mentioned embodiment of the invention, the embodiment of the present invention further refines the method of forming a test loop by contacting the test end of the P probe with the contact area of ​​the epitaxial wafer to be tested and the test end of the N probe with the notch of the epitaxial wafer to be tested to test the epitaxial wafer to be tested. Figure 11 This is another flow chart of an epitaxial wafer testing method provided by an embodiment of the present invention, refer to Figure 11 , the testing method provided by the embodiment of the present invention includes:

[0155] S301. Provide an epitaxial wafer to be tested.

[0156] S302 , preparing at least one notch in the epitaxial wafer to be tested.

[0157] S303 , the test end of the P probe sequentially contacts the first contact area to the Mth contact area of ​​the epitaxial wafer to be tested; the test end of the N probe sequentially contacts the first notch to the Mth notch of the epitaxial wafer to be tested to form a test loop to test the epitaxial wafer to be tested.

[0158] Specifically, the test end of the P probe sequentially contacts the first contact area of ​​the epitaxial wafer to be tested (such as Figure 7 A) to the Mth contact area (such as Figure 7 L), the test end of the N probe successively touches the first notch of the epitaxial wafer to be tested (such as Figure 7 Q1) to the Mth gap (such as Figure 7 In QM), the order of testing can also be adaptively adjusted according to the testing requirements, and the embodiment of the present invention does not limit this.

[0159] Specifically, after the test end of the P probe and the test end of the N probe are respectively brought into contact with the corresponding contact area and the notch in the above step S303, the epitaxial wafer to be tested is tested. It can be understood that the difference between the embodiment of the present invention and the above-mentioned embodiment of the invention is that the embodiment of the present invention is to test the epitaxial wafer after all the notches of the epitaxial wafer to be tested are prepared, where M is a positive integer greater than or equal to 2.

[0160] Based on the above-mentioned embodiment of the invention, the embodiment of the present invention further refines the method of testing the epitaxial wafer to be tested by contacting the testing end of the P probe with the contact area of ​​the epitaxial wafer to be tested and contacting the testing end of the N probe with the notch of the epitaxial wafer to be tested to form a test loop. Figure 12 This is a flow chart of another epitaxial wafer testing method provided by an embodiment of the present invention. Figure 13 Schematic diagram of another epitaxial wafer testing method provided by an embodiment of the present invention; Figure 12 and Figure 13 , the testing method provided by the embodiment of the present invention includes:

[0161] S401. Provide an epitaxial wafer to be tested.

[0162] S402 , preparing at least one notch in the epitaxial wafer to be tested.

[0163] S403 , the test end of the P probe and the test end of the N probe respectively contact different contact areas to form a test loop to test the resistance of the P semiconductor layer of the epitaxial wafer to be tested.

[0164] Specifically, the test end of the P probe 8 and the test end of the N probe 9 contact different contact areas 51 respectively, so that the probe and the contact area 51 have a good current loop, thereby testing the resistance of the P semiconductor layer 4 of the epitaxial wafer to be tested.

[0165] Based on the above-mentioned embodiment of the invention, the embodiment of the present invention further refines the method of forming a test loop by contacting the test end of the P probe with the contact area of ​​the epitaxial wafer to be tested and the test end of the N probe with the notch of the epitaxial wafer to be tested to test the epitaxial wafer to be tested. Figure 14 This is a flow chart of another epitaxial wafer testing method provided by an embodiment of the present invention. Figure 15 Schematic diagram of another epitaxial wafer testing method provided by an embodiment of the present invention; Figure 16 Schematic diagram of another epitaxial wafer testing method provided by an embodiment of the present invention; Figure 14 、 Figure 15 and Figure 16 , the epitaxial wafer testing method provided by the embodiment of the present invention includes:

[0166] S501. Provide an epitaxial wafer to be tested.

[0167] S502 , preparing at least one notch in the epitaxial wafer to be tested.

[0168] S503 , preparing the Mth notch and the M+1th notch of the epitaxial wafer to be tested.

[0169] Specifically, the Mth notch and the M+1th notch of the epitaxial wafer to be tested are prepared by a breakdown probe, a P probe, or an N probe.

[0170] S504 , the test end of the P probe contacts the Mth notch of the epitaxial wafer to be tested, and the test end of the N probe contacts the M+1th notch of the epitaxial wafer to be tested to form a test loop to test the resistance of the N semiconductor layer of the epitaxial wafer to be tested.

[0171] Specifically, the test end of the P probe is placed against the Mth notch of the epitaxial wafer to be tested, and the test end of the N probe is placed against the M+1th notch of the epitaxial wafer to be tested. For example, M=1, the test end of the P probe is placed against the first notch of the epitaxial wafer to be tested, and the test end of the N probe is placed against the second notch of the epitaxial wafer to be tested, so as to test the resistance of the N semiconductor layer of the epitaxial wafer to be tested. The power supply end of the P probe is connected to the positive pole of the power supply, and the power supply end of the N probe is connected to the negative pole of the power supply. A test loop is formed to test the resistance of the N semiconductor layer of the epitaxial wafer to be tested.

[0172] S505 , preparing the M+2 th notch and the M+3 th notch of the epitaxial wafer to be tested.

[0173] Specifically, after the test in step S504 is completed, the M+2 th notch and the M+3 th notch are prepared in the epitaxial wafer to be tested by using a breakdown probe, a P probe, or an N probe.

[0174] S506 , the test end of the P probe contacts the M+2th notch of the epitaxial wafer to be tested, and the test end of the N probe contacts the M+3th notch of the epitaxial wafer to be tested to form a test loop to test the resistance of the N semiconductor layer of the epitaxial wafer to be tested.

[0175] Specifically, on the test equipment, the power supply end of the P probe is connected to the positive pole of the power supply, and the power supply end of the N probe is connected to the negative pole of the power supply. After the test ends of the P probe and the N probe touch the notch of the epitaxial wafer, a test loop is formed to test the resistance of the N semiconductor layer of the epitaxial wafer to be tested, wherein M is a positive integer greater than or equal to 1. The embodiment of the present invention provides a test method for the resistance of the N semiconductor layer of the epitaxial wafer to be tested, which can achieve the technical effect of "testing while preparing notches", that is, preparing the first and second notches for testing; then preparing the third and fourth notches for testing; then preparing the Mth and M+1th notches for testing, and so on. Or prepare the first and second notches for testing; then prepare the third notch, and test between the second notch and the third notch, and so on. Or after making the third notch, it is also possible to test between the first notch and the third notch, that is, the polarity of one notch and any other notch on the epitaxial wafer can be tested, wherein M is a positive integer greater than or equal to 1.

[0176] Based on the above-mentioned embodiment of the invention, the embodiment of the present invention further refines the method of forming a test loop by contacting the test end of the P probe with the contact area of ​​the epitaxial wafer to be tested and the test end of the N probe with the notch of the epitaxial wafer to be tested to test the epitaxial wafer to be tested. Figure 17 This is another flow chart of an epitaxial wafer testing method provided by an embodiment of the present invention, refer to Figure 17 , the testing method provided by the embodiment of the present invention includes:

[0177] S601. Provide an epitaxial wafer to be tested.

[0178] S602 , preparing at least one notch in the epitaxial wafer to be tested.

[0179] S603 , the test end of the P probe and the test end of the N probe respectively contact different notches to form a test loop to test the resistance of the N semiconductor layer of the epitaxial wafer to be tested.

[0180] Specifically, the test end of the P probe 8 and the test end of the N probe 9 contact different notches 6, respectively, so that the P probe 8 and the N probe 9 form a good current loop with the different notches 6. The power supply end of the P probe is connected to the positive pole of the power supply, and the power supply end of the N probe is connected to the negative pole of the power supply to form a test loop to test the resistance of the N semiconductor layer of the epitaxial wafer to be tested.

[0181] Specifically, on the test equipment, the power supply end of the P probe is connected to the positive pole of the power supply, and the power supply end of the N probe is connected to the negative pole of the power supply. After the P probe and N probe test ends touch the notch of the epitaxial wafer, the resistance of the N semiconductor layer 2 of the epitaxial wafer to be tested is tested.

[0182] Based on the above-mentioned embodiment of the invention, the embodiment of the present invention further refines the process before preparing at least one notch in the epitaxial wafer to be tested. Figure 18 This is another flow chart of an epitaxial wafer testing method provided by an embodiment of the present invention, refer to Figure 18 , the epitaxial wafer testing method provided by the embodiment of the present invention includes:

[0183] S701. Provide an epitaxial wafer to be tested.

[0184] S702 , patterning the contact layer of the epitaxial wafer to be tested to form a plurality of contact regions.

[0185] Specifically, a contact layer is deposited on the P semiconductor layer of the epitaxial wafer to be tested by physical vapor deposition or chemical vapor deposition, and the contact layer is patterned to form a plurality of contact areas, for example, by photolithography.

[0186] S703 , preparing at least one notch in the epitaxial wafer to be tested.

[0187] S704 , the test end of the P probe contacts the contact area of ​​the epitaxial wafer to be tested; the test end of the N probe contacts the notch of the epitaxial wafer to be tested to form a test loop to test the epitaxial wafer to be tested.

[0188] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. An epitaxial wafer, characterized in that: include: A substrate and an N semiconductor layer, a light-emitting layer, a P semiconductor layer and a contact layer stacked in sequence on one side of the substrate; The contact layer includes a plurality of patterned contact regions; Also includes at least one notch; The notch passes through the P semiconductor layer, the light emitting layer and at least a portion of the N semiconductor layer, and / or the notch passes through the contact region, the P semiconductor layer, the light emitting layer and at least a portion of the N semiconductor layer.

2. The epitaxial wafer according to claim 1, characterized in that include: The contact layer forms an ohmic contact with the P semiconductor layer; the transmittance of the contact layer is greater than or equal to 70%; and the thickness of the contact layer is 10 nm-1.5 μm.

3. The epitaxial wafer according to claim 1, characterized in that Also included are multiple test groups; The test group includes a first test unit and a second test unit; The first test unit includes at least one N semiconductor layer gap; the second test unit includes at least one P contact region; and the areas of the plurality of P contact regions are the same or different.

4. The epitaxial wafer according to claim 1, characterized in that The projection pattern of the contact area on the substrate includes at least one of the following shapes: a circle, a rectangle, a triangle, a polygon, and an ellipse.

5. The epitaxial wafer according to claim 1, characterized in that The notch is formed by at least one of voltage punching, mechanical punching, or laser punching.

6. The epitaxial wafer according to claim 1, characterized in that The material of the contact layer includes indium tin oxide or nickel gold alloy.

7. The epitaxial wafer according to claim 1, characterized in that The coating process of the contact layer includes physical vapor deposition or chemical vapor deposition; the patterning process of the contact layer includes photolithography.

8. The epitaxial wafer according to claim 1, characterized in that: The area of ​​the contact zone is 0.001 mm 2 -10mm 2 The test current density of the contact area is 0.001A / cm 2 -500A / cm 2 .

9. The epitaxial wafer according to claim 1, characterized in that: The electrical conductivity of the contact layer is greater than or equal to 10 times the electrical conductivity of the P semiconductor layer.

10. The epitaxial wafer according to claim 1, characterized in that The light emitting layer includes a multi-quantum well layer or a quantum well layer.

11. An epitaxial wafer testing device, characterized in that: Used for testing the epitaxial wafer according to any one of claims 1 to 10, the testing equipment comprising: a carrier, at least one P probe and at least one N probe; The carrier is used to carry the epitaxial wafer to be tested; The test ends of the P probe and the N probe contact the epitaxial wafer to be tested during testing; The power supply end of the P probe is connected to the positive electrode of the power supply, and the power supply end of the N probe is connected to the negative electrode of the power supply.

12. The epitaxial wafer testing device according to claim 11, characterized in that: Also comprising at least one breakdown head; The breakdown head is used to penetrate the P semiconductor layer, the light-emitting layer and at least part of the N semiconductor layer of the epitaxial wafer to be tested to form a gap, and / or the breakdown head is used to penetrate the contact area of ​​the epitaxial wafer to be tested, the P semiconductor layer, the light-emitting layer and at least part of the N semiconductor layer to form a gap.

13. The epitaxial wafer testing device according to claim 11, characterized in that: The N-probe and / or the P-probe form the notch by at least one of voltage breakdown, mechanical drilling, or laser breakdown.

14. The epitaxial wafer testing device according to claim 12, characterized in that: The breakdown head forms the notch by at least one of voltage breakdown, mechanical drilling, or laser breakdown.

15. The epitaxial wafer testing device according to claim 13 or 14, characterized in that: The voltage breakdown has a breakdown voltage of 80V-300V, a breakdown current of 0.1mA-100mA, and a breakdown time of 1s-10s.

16. A method for testing an epitaxial wafer, characterized in that: A test device for an epitaxial wafer according to any one of claims 11 to 15, wherein the test method comprises: Provide epitaxial wafers to be tested; preparing at least one notch in the epitaxial wafer to be tested; The test end of the P probe contacts the contact area of ​​the epitaxial wafer to be tested, and the test end of the N probe contacts the notch of the epitaxial wafer to be tested to form a test loop to test the epitaxial wafer to be tested.

17. The epitaxial wafer testing method according to claim 16, characterized in that: The test end of the P probe contacts the contact area of ​​the epitaxial wafer to be tested, and the test end of the N probe contacts the notch of the epitaxial wafer to be tested to form a test loop to test the epitaxial wafer to be tested, further comprising: The testing end of the P probe contacts the Mth contact area of ​​the epitaxial wafer to be tested, and the testing end of the N probe contacts the Mth notch of the epitaxial wafer to be tested to form a testing loop to test the epitaxial wafer to be tested; preparing an M+1th notch in the epitaxial wafer to be tested; The testing end of the P probe contacts the M+1th contact area of ​​the epitaxial wafer to be tested, and the testing end of the N probe contacts the M+1th notch of the epitaxial wafer to be tested to form a testing loop to test the epitaxial wafer to be tested; Wherein, M is a positive integer greater than or equal to 1.

18. The epitaxial wafer testing method according to claim 16, characterized in that: The test end of the P probe contacts the P contact area of ​​the epitaxial wafer to be tested, and the test end of the N probe contacts the notch of the epitaxial wafer to be tested to form a test loop to test the epitaxial wafer to be tested, further comprising: The test end of the P probe sequentially contacts the first P contact area to the Mth P contact area of ​​the epitaxial wafer to be tested; the test end of the N probe contacts one of the notches of the epitaxial wafer to be tested, forming a test loop to test the epitaxial wafer to be tested; Wherein, M is a positive integer greater than or equal to 2.

19. The epitaxial wafer testing method according to claim 16, characterized in that: The test end of the P probe contacts the contact area of ​​the epitaxial wafer to be tested, and the test end of the N probe contacts the notch of the epitaxial wafer to be tested to form a test loop to test the epitaxial wafer to be tested, further comprising: The test end of the P probe sequentially contacts the first contact area to the Mth contact area of ​​the epitaxial wafer to be tested; the test end of the N probe sequentially contacts the first notch to the Mth notch of the epitaxial wafer to be tested to form a test loop to test the epitaxial wafer to be tested; Wherein, M is a positive integer greater than or equal to 2.

20. The epitaxial wafer testing method according to claim 16, characterized in that: The test end of the P probe contacts the contact area of ​​the epitaxial wafer to be tested, and the test end of the N probe contacts the notch of the epitaxial wafer to be tested to form a test loop to test the epitaxial wafer to be tested, further comprising: The test end of the P probe and the test end of the N probe respectively contact different P contact areas to test the resistance of the P semiconductor layer of the epitaxial wafer to be tested.

21. The epitaxial wafer testing method according to claim 16, characterized in that: The test end of the P probe contacts the contact area of ​​the epitaxial wafer to be tested, and the test end of the N probe contacts the notch of the epitaxial wafer to be tested to form a test loop to test the epitaxial wafer to be tested, further comprising: Preparing the Mth notch and the M+1th notch of the epitaxial wafer to be tested; The testing end of the P probe contacts the Mth notch of the epitaxial wafer to be tested, and the testing end of the N probe contacts the M+1th notch of the epitaxial wafer to be tested to form a testing loop to test the resistance of the N semiconductor layer of the epitaxial wafer to be tested; Preparing the M+2th notch and the M+3th notch of the epitaxial wafer to be tested; The testing end of the P probe contacts the M+2th notch of the epitaxial wafer to be tested, and the testing end of the N probe contacts the M+3th notch of the epitaxial wafer to be tested to form a testing loop to test the resistance of the N semiconductor layer of the epitaxial wafer to be tested; Wherein, M is a positive integer greater than or equal to 1.

22. The epitaxial wafer testing method according to claim 16, characterized in that: The test end of the P probe contacts the contact area of ​​the epitaxial wafer to be tested, and the test end of the N probe contacts the notch of the epitaxial wafer to be tested to form a test loop to test the epitaxial wafer to be tested, further comprising: The test end of the P probe and the test end of the N probe respectively contact different notches to form a test loop to test the resistance of the N semiconductor layer of the epitaxial wafer to be tested.

23. The epitaxial wafer testing method according to claim 16, wherein: Before preparing at least one notch in the epitaxial wafer to be tested, the method further comprises: The contact layer of the epitaxial wafer to be tested is patterned to form a plurality of contact regions.

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