Quantum chip bottom layer circuit preparation method and quantum chip

Abstract

The invention discloses a chip bottom layer circuit preparation method and a quantum chip, and the method comprises the steps: sequentially growing a superconducting metal layer and a hard material layer on a clean substrate, coating photoresist on the hard material layer for photoetching to obtain a bottom layer circuit pattern, etching the hard material layer to transfer the pattern, removing the photoresist, and polishing and grinding the superconducting metal layer to transfer the pattern through chemical mechanical polishing. And removing the hard material layer and cleaning to obtain the superconducting bottom layer circuit. The quantum chip comprises a substrate layer, a superconducting metal layer and a bottom layer circuit pattern. According to the method, the superconductive metal layer is patterned by combining the hard material layer with the CMP process, so that the problems of substrate damage and defect increase caused by traditional dry etching and poor undercutting and side wall steepness caused by wet etching are solved, two-energy-level defects are reduced, and the cost and the process complexity are reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip preparation, and specifically relates to a method for preparing a quantum chip bottom circuit and a quantum chip. Background Art

[0002] Superconducting quantum computing is one of the quantum computing solutions with the greatest potential for practical application, and superconducting quantum chips are the core hardware component. Superconducting quantum chips primarily consist of two components: the underlying circuitry and the Josephson junction. The underlying circuitry includes a resonant cavity, transmission lines, control lines, and bit capacitors. The processing and fabrication of superconducting quantum chips is largely compatible with the materials and processes of traditional semiconductors. Therefore, the current mainstream quantum chip fabrication methods utilize thin-film fabrication, photolithography, and etching to fabricate chip circuits and devices on a substrate. For example, in Chinese patents CN116782752A, CN117279484A, and CN117750872A, the underlying circuitry is typically fabricated by first growing a superconducting metal thin film, such as Al, Ta, or Nb, approximately 100-300 nm thick, on a clean semiconductor substrate. Subsequently, the metal film surface is subjected to photolithography, development, and plasma dry or wet etching to transfer the circuit pattern to the metal film.

[0003] However, in actual applications, the bit performance of superconducting quantum chips is extremely sensitive to two-level defects (a type of microscopic defect state that exists naturally in the material or is introduced during the process, and its behavior can be approximated as a two-level quantum system, which has a significant negative impact on the coherence and stability of the quantum bit). During dry etching, although the sidewalls are relatively steep, the plasma will damage the substrate, significantly increasing the system's two-level defect pole, reducing the quality factor of the resonant cavity, and causing a decrease in bit performance. When wet etching is used, although there is no obvious damage to the substrate, the etching solution will have a more obvious undercutting phenomenon on the photoresist. At the same time, because wet etching is isotropic etching, the sidewall morphology is less steep, and the quality factor of the resonant cavity is also poor, which will also lead to a decrease in bit performance. Summary of the Invention

[0004] The purpose of the present invention is to propose a method for preparing the underlying circuit of a quantum chip and a quantum chip to solve the problems in the prior art.

[0005] To this end, the present invention provides a method for preparing the underlying circuit of a quantum chip, the steps comprising:

[0006] growing a superconducting metal layer on a clean substrate;

[0007] growing a hard material layer on the superconducting metal layer;

[0008] Coating photoresist on the hard material layer and performing photolithography to obtain a bottom layer circuit pattern;

[0009] Etching the hard material layer, transferring the underlying circuit pattern to the hard material layer and cleaning and removing the photoresist;

[0010] Continue grinding the hard material layer and the exposed superconducting metal layer using a grinding process to transfer the bottom circuit pattern to the superconducting metal layer;

[0011] The hard material layer is removed and cleaned to obtain a superconducting bottom layer circuit.

[0012] Optionally, the hardness of the hard material layer is greater than the hardness of the superconducting metal layer.

[0013] Optionally, the grinding liquid used in the grinding process has a higher corrosion rate on the superconducting metal layer than on the hard material layer.

[0014] Optionally, during the grinding, chemical etching and mechanical grinding are performed simultaneously;

[0015] The chemical etching generates corrosion products by the reaction between the grinding liquid and the superconducting metal layer, and the mechanical grinding removes the corrosion products by the polishing pad and grinds the surface of the superconducting metal layer.

[0016] Optionally, a surface of the polishing pad in contact with the superconducting metal layer has a plurality of micron-scale peaks.

[0017] Optionally, the substrate is made of at least sapphire or intrinsic silicon.

[0018] Optionally, the material of the hard material layer includes at least silicon dioxide or silicon nitride.

[0019] Optionally, the material of the superconducting metal layer includes at least any one of an Al-based superconductor, a Nb-based superconductor, a Ta-based superconductor or a TiN-based superconductor.

[0020] Optionally, when growing a superconducting metal layer on a clean substrate, the clean substrate is placed in a superconducting metal growth device, and the vacuum degree inside the superconducting metal growth device is greater than 1×10 -9 torr.

[0021] Optionally, when growing the superconducting metal layer on the clean substrate, the thickness of the grown superconducting metal layer is 100-500 nm.

[0022] Optionally, when growing the hard material layer on the superconducting metal layer, the thickness of the grown superconducting hard material layer is 50-200 nm.

[0023] Optionally, before removing the hard material layer, the hard material layer may be etched at least by using gaseous hydrogen fluoride.

[0024] Also provided is a quantum chip prepared according to the method for preparing a quantum chip bottom circuit, comprising a substrate layer;

[0025] a superconducting metal layer, wherein the superconducting metal layer is formed on the surface of the substrate layer;

[0026] The bottom circuit pattern is formed on the surface of the superconducting metal layer.

[0027] Beneficial effects:

[0028] 1. The present invention achieves superconducting metal layer patterning by growing a harder hardness material layer on the superconducting metal layer and combining it with a chemical mechanical polishing process, thereby avoiding the problems of traditional dry etching damaging the substrate, increasing two-level defects, and wet etching undercutting and poor sidewall steepness.

[0029] 2. The high hardness of the hard material layer and the high corrosion selectivity of the grinding fluid to the superconducting metal layer and the hard material layer in the present invention ensure that polishing only acts on the metal layer, effectively improving the steepness and roughness of the metal sidewall, reducing damage to the substrate, and reducing two-level defects. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 Flowchart of the method for preparing the underlying circuit of the quantum chip provided by the present invention.

[0032] Figure 2 This is a schematic diagram of growing a superconducting metal layer in the method for preparing the underlying circuit of a quantum chip provided by the present invention.

[0033] Figure 3 This is a schematic diagram of growing a hard material layer in the method for preparing the underlying circuit of a quantum chip provided by the present invention.

[0034] Figure 4 This is a schematic diagram of the bottom-layer circuit pattern obtained after photolithography in the method for preparing the bottom-layer circuit of a quantum chip provided by the present invention.

[0035] Figure 5 This is a schematic diagram of transferring the bottom-layer circuit pattern to the hard material layer in the quantum chip bottom-layer circuit preparation method provided by the present invention.

[0036] Figure 6 This is a schematic diagram of transferring the bottom-layer circuit pattern to the superconducting metal layer in the quantum chip bottom-layer circuit preparation method provided by the present invention.

[0037] Figure 7 Schematic diagram of a quantum chip with a superconducting underlying circuit obtained by the quantum chip underlying circuit preparation method provided by the present invention.

[0038] In the figure: 1. substrate; 2. superconducting metal layer; 3. hard material layer; 4. photoresist. DETAILED DESCRIPTION

[0039] The present invention may be more readily understood by referring to the following detailed description of preferred embodiments of the present invention and the included Examples. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention pertains. In the event of a conflict, the definitions in this specification shall prevail.

[0040] This invention provides a method for fabricating the underlying circuitry of a quantum chip and a quantum chip, addressing existing issues with substrate damage and the adverse effects on the steepness of the sidewalls after etching caused by dry or wet etching. By using a hard dielectric material as a mask and combining it with a CMP (chemical mechanical polishing) process, the present invention achieves patterning of the superconducting metal layer, effectively avoiding damage to the substrate material caused by conventional dry or wet etching, while ensuring the steepness and smoothness of the sidewalls.

[0041] like Figure 1-7 As shown, in one embodiment, a method for preparing a quantum chip bottom circuit comprises the following steps:

[0042] like Figure 2 As shown, a superconducting metal layer 2 is grown on a clean substrate 1, wherein the substrate 1 can be cleaned by pre-cleaning with an organic solvent to remove organic matter, and then oxidizing and cleaning with a piranha solution to deeply remove the organic matter again, and finally treating the surface oxide with hydrofluoric acid to obtain a clean substrate 1, providing a basis for the subsequent growth of the superconducting metal layer 2 and reducing the negative impact of pollutants on subsequent process links.

[0043] like Figure 3As shown, a hard material layer 3 is grown on a superconducting metal layer 2. The superconducting metal layer 2 is then placed in a CVD (chemical vapor deposition) device to grow the hard material layer 3 to a specific thickness. It should be noted that the hardness of the selected hard material layer 3 needs to be greater than that of the superconducting metal layer 2. At the same time, the polishing liquid in the subsequent CMP process has a large etching selectivity for the superconducting metal layer 2 and the hard material layer 3. This allows the superconducting metal layer 2 to be quickly removed while the hard material layer 3 is retained during the polishing process. The high hardness and low etching rate of the hard material ensure that polishing only acts on the metal layer, reducing two-level defects. The high etching liquid selectivity ensures that the metal layer has a uniform thickness and steep sidewalls (e.g., a steepness greater than 85°).

[0044] like Figure 4 As shown, a photoresist 4 is coated on the surface of the hard material layer 3 and photolithography is performed to define the underlying circuit pattern. Specifically, the coated photoresist 4 is photolithographically formed into a hollowed-out underlying circuit pattern to facilitate subsequent transfer of the underlying circuit pattern to the hard material layer 3.

[0045] like Figure 5 As shown, the hard material layer 3 is etched by dry or wet methods to transfer the underlying circuit pattern to the hard material layer 3 and then clean and remove the adhesive. Specifically, through the previous step, the photoresist 4 layer forms a hollowed-out underlying circuit pattern. The area of ​​the hard material layer 3 not covered by the adhesive film (photoresist 4) (i.e., the target underlying circuit pattern) is exposed and ready for etching. Then, the etching method is selected based on the material type of the hard material layer 3, and a high-selectivity etchant is determined (the etchant has a much higher corrosion rate for hard materials than the photoresist 4). Then, dry or wet etching is performed to transfer the underlying circuit to the hard material layer 3. Cleaning and removing the adhesive shell is performed by plasma debonding and then ultrasonic cleaning with acetone and ethanol for 5 minutes each to remove polymer residue.

[0046] like Figure 6 As shown, the superconducting metal layer 2 is polished using a CMP process to transfer the underlying circuit pattern to the superconducting metal layer 2. Since the hardness of the hard material layer 3 is greater than that of the superconducting metal layer 2, it can be confirmed that the superconducting metal layer 2 is limitedly polished during polishing. At the same time, the corrosion rate of the grinding liquid on the metal superconducting layer is much greater than that of the hard material layer 3, which can achieve rapid removal of the superconducting metal layer 2 while stably retaining the hard material layer 3. During the grinding process, the chemical reagents in the grinding liquid react with the exposed metal layer to generate easily removable corrosion products. The corrosion products are mechanically scraped off by the abrasive particles in the grinding liquid, revealing a fresh metal surface, and the reaction continues. At the same time, the micron-sized peaks of the polishing pad rub against the metal surface, physically removing the corrosion products and raised particles. Due to the high hardness of the hard mask, the mechanical wear of the polishing pad on it is negligible, ensuring the clear boundaries of the underlying circuit pattern.

[0047] At the same time, during the CMP process, the hard material layer 3 is deposited on the superconducting metal layer 2 , and the superconducting metal layer 2 grows on the surface of the substrate 1 , forming a sandwich structure of the substrate 1 , the superconducting metal layer 2 , and the hard material layer 3 .

[0048] During the CMP polishing process, since the hardness of the substrate 1 is greater than that of the superconducting metal layer 2 and the substrate 1 has a strong corrosion resistance to the grinding liquid, the degree of damage to the substrate 1 during the polishing process is very small.

[0049] During the CMP polishing process, the hard material layer 3 acts as a mold to limit the polishing range. Only the exposed superconducting metal layer 2, that is, the area outside the pattern of the hard material layer 3, is ground away, while the metal layer below the hard material layer 3 is completely retained. Finally, the sidewall shape of the superconducting metal layer 2 is completely determined by the pattern of the hard material layer 3, ensuring that the metal sidewall is highly consistent with the mask sidewall, avoiding the problem of sidewall roughness caused by plasma scattering or solution diffusion in traditional etching.

[0050] like Figure 7 As shown, the hard material layer 3 is removed and cleaned to obtain a superconducting bottom circuit. The cleaning in this step can be carried out by treating with liquid hydrofluoric acid.

[0051] In one embodiment, taking the preparation of a 20-bit superconducting quantum planar chip as an example, the specific implementation steps are as follows:

[0052] Place the clean sapphire substrate 1 into a multi-cavity electron beam evaporation device, and when the vacuum degree is better than 1×10-9 torr, evaporate an aluminum film with a thickness of 150nm.

[0053] The above samples were placed in a CVD device to grow a SiO2 film with a thickness of 100 nm.

[0054] The above samples were subjected to photolithography, using AZ6112 photoresist 4, a rotation speed of 4000rpm, a thickness of about 1.2um, and baked on a hot plate at 100℃ for about 2 minutes. Then, a stepper photolithography machine was used to expose for about 0.2s, develop with a 2.38% TMAH solution for about 40s, and hard bake on a hot plate at 100℃ for about 2 minutes to define the underlying circuit structure.

[0055] The above samples were etched using an etching process to prepare the underlying circuit of the chip on the SiO2 film, and then the photoresist was removed by cleaning.

[0056] The above samples were treated with CMP to completely remove the exposed Al film and transfer the underlying circuit structure to the Al film.

[0057] The above samples were subjected to gaseous HF etching treatment to completely remove the SiO2 film, and then cleaned to obtain clean samples.

[0058] It should be noted that there are no specific limitations on substrate 1, materials, or equipment. In some embodiments, substrate 1 may be sapphire or intrinsic silicon, and the superconducting metal material may be an Al-based superconductor, a Nb-based superconductor, a Ta-based superconductor, or a TiN-based superconductor. In some embodiments, the superconducting metal growth equipment may be a multi-cavity evaporation device or a multi-cavity magnetron device. In some embodiments, the etching process for etching the SiO2 film may be dry etching, wet etching, or a combination of multiple processes. The SiO2 dielectric material may also be other materials.

[0059] In this embodiment, the thickness of the superconducting metal layer 2 is in the range of 100-500 nm, preferably 150 nm; the thickness of the SiO2 film is in the range of 50-200 nm, preferably 100 nm.

[0060] Optionally, the hardness of the hard material layer 3 is greater than the hardness of the superconducting metal layer 2, and the corrosion rate of the grinding liquid used for the chemical mechanical polishing on the superconducting metal layer 2 is greater than the corrosion rate of the hard material layer 3. The hardness of the hard material layer 3 is greater than the hardness of the superconducting metal layer 2, so that the hard material layer 3 can be used as a grinding stop layer. When CMP polishing is performed, the polishing pad rubs against the material surface. Since the hard material is harder, under the same pressure, the superconducting metal will be preferentially ground away, while the hard material is hardly worn. When the superconducting metal layer 2 is ground to be flush with the hard material layer 3, the hard material will "block" the polishing pad from continuing to move downward, avoiding excessive grinding and damaging the circuit structure. At the same time, the high hardness of the hard material enables it to accurately retain the edge contour of the circuit pattern during the photolithography and etching process, effectively avoiding the hard material from being insufficiently hard (such as close to metal) and being worn during polishing, causing the underlying circuit pattern to deform and affecting the circuit performance. The abrasive used in chemical mechanical polishing has a higher corrosion rate for the superconducting metal layer 2 than for the hard material layer 3, allowing the exposed superconducting metal layer 2 to be quickly polished away. Simultaneously, due to the lower corrosion rate, the hard material layer 3 is barely consumed, preserving the underlying circuit pattern defined by the photolithography.

[0061] like Figure 7 As shown, in one embodiment, a quantum chip prepared according to the above method is also provided, the chip includes a substrate 1 layer;

[0062] a superconducting metal layer 2, wherein the superconducting metal layer 2 is formed on the surface of the substrate 1;

[0063] The bottom circuit pattern is formed on the surface of the superconducting metal layer 2.

[0064] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for preparing the underlying circuit of a quantum chip, characterized in that the steps include: growing a superconducting metal layer on a clean substrate; growing a hard material layer on the superconducting metal layer; Coating photoresist on the hard material layer and performing photolithography to obtain a bottom layer circuit pattern; Etching the hard material layer, transferring the underlying circuit pattern to the hard material layer and cleaning and removing the photoresist; Continue grinding the hard material layer and the exposed superconducting metal layer using a grinding process to transfer the bottom circuit pattern to the superconducting metal layer; The hard material layer is removed and cleaned to obtain a superconducting bottom layer circuit.

2. The method for preparing the underlying circuit of a quantum chip according to claim 1, characterized in that: The hardness of the hard material layer is greater than the hardness of the superconducting metal layer.

3. The method for preparing the underlying circuit of a quantum chip according to claim 1, characterized in that: The grinding liquid used in the grinding process has a higher corrosion rate on the superconducting metal layer than on the hard material layer.

4. The method for preparing the underlying circuit of a quantum chip according to claim 1, characterized in that: When grinding, chemical etching and mechanical grinding are carried out simultaneously; The chemical etching generates corrosion products by the reaction between the grinding liquid and the superconducting metal layer, and the mechanical grinding removes the corrosion products by the polishing pad and grinds the surface of the superconducting metal layer.

5. The method for preparing the underlying circuit of a quantum chip according to claim 4, characterized in that: The surface of the polishing pad on the side in contact with the superconducting metal layer has a plurality of micron-level peaks.

6. The method for preparing the underlying circuit of a quantum chip according to claim 1, characterized in that: The hard material layer is made of at least silicon dioxide or silicon nitride.

7. The method for preparing the underlying circuit of a quantum chip according to claim 1, characterized in that: The material of the superconducting metal layer includes at least any one of an Al-based superconductor, a Nb-based superconductor, a Ta-based superconductor or a TiN-based superconductor.

8. The method for preparing the underlying circuit of a quantum chip according to claim 1, characterized in that: When growing a superconducting metal layer on a clean substrate, the clean substrate is placed in a superconducting metal growing device, and the vacuum degree inside the superconducting metal growing device is greater than 1×10 -9 torr.

9. The method for preparing the underlying circuit of a quantum chip according to claim 1, characterized in that: When a superconducting metal layer is grown on a clean substrate, the thickness of the grown superconducting metal layer is 100-500 nm.

10. The method for preparing the underlying circuit of a quantum chip according to claim 1, characterized in that: When the hard material layer is grown on the superconducting metal layer, the thickness of the grown superconducting hard material layer is 50-200 nm.

11. The method for preparing the bottom circuit of a quantum chip according to claim 1, characterized in that: When removing the hard material layer, the hard material layer may be etched at least by using gaseous hydrogen fluoride.

12. A quantum chip prepared according to the method for preparing a quantum chip bottom circuit according to any one of claims 1 to 11, characterized in that: including a substrate layer; a superconducting metal layer, wherein the superconducting metal layer is formed on the surface of the substrate layer; The bottom circuit pattern is formed on the surface of the superconducting metal layer.

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