Resistive random access memory, preparation method and electronic equipment
By using a three-layer oxide dielectric layer structure in the resistive random access memory, especially the second oxide dielectric layer with a high oxygen vacancy concentration, a prefabricated path is formed, which solves the problem of randomness of the conductive filaments, improves the uniformity and stability of the device, simplifies the process steps and reduces costs.
Patent Information
- Application Number
- CN202410278769.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-12
- Publication Date
- 2025-09-12
AI Technical Summary
The formation and breaking of conductive filaments in existing resistive memory devices are highly random, affecting the uniformity of device performance. It is difficult to form a thinner resistive layer between electrodes, and dislocations, defects and other undesirable factors exist in the resistive layer, leading to problems such as performance unevenness and current leakage.
A three-layer oxide dielectric layer structure is adopted, including the first oxide dielectric layer, the second oxide dielectric layer and the third oxide dielectric layer arranged in sequence from bottom to top. The oxygen vacancy concentration of the second oxide dielectric layer is higher than that of the other two layers. The electrode layer is connected to the resistive dielectric layer to form a prefabricated path to solidify the movement path of the conductive wire and suppress the randomness of the conductive wire in the prefabricated path.
The performance uniformity of the resistive random access memory is improved, the randomness of the conductive filament is reduced, the stability and consistency of the device are improved, the process steps are simplified and the cost is reduced.
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Figure CN120640965A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of resistive random access memory, and in particular to a resistive random access memory, a preparation method thereof, and an electronic device. Background Art
[0002] The emergence of resistive random access memory (RRAM) has opened up new avenues for innovation in information storage, processing, and transmission, promising broad applications in neuromorphic devices, scalable hardware systems, ultra-low-power devices, and high-performance materials engineering devices. Currently, most RRAMs are based on a sandwich-like capacitor structure: metal electrodes at either end sandwich a dielectric layer of insulator or semiconductor material. Applying a forward or reverse voltage to the electrodes creates or breaks a conductive filament in the dielectric layer, switching the device between two resistance states: low resistance or high resistance. When a conductive filament forms between the electrodes, the device is in a low-resistance state; when it breaks, it is in a high-resistance state. However, due to the difficulty of forming a thin resistive layer between the electrodes and the presence of various imperfect factors such as dislocations and defects in the resistive layer, the formation and breaking of the conductive filament is highly random. Summary of the Invention
[0003] The embodiments of the present application provide a resistive random access memory, a preparation method, and an electronic device, which can improve the performance uniformity of the resistive random access memory.
[0004] In a first aspect, an embodiment of the present application provides a resistive random access memory, comprising:
[0005] substrate;
[0006] a resistive dielectric layer, disposed on the substrate, comprising a first oxidizing dielectric layer, a second oxidizing dielectric layer, and a third oxidizing dielectric layer disposed sequentially from bottom to top, wherein the second oxidizing dielectric layer has a higher oxygen vacancy concentration than the first oxidizing dielectric layer and the third oxidizing dielectric layer;
[0007] The electrode layer is provided on the substrate and connected to the resistive dielectric layer, and is used to form a prefabricated path in the resistive dielectric layer.
[0008] In a second aspect, an embodiment of the present application provides a method for preparing a resistive random access memory, comprising:
[0009] Spin coating photoresist on the substrate to form a preparation area;
[0010] Prepare a resistive dielectric layer in the preparation area, wherein the resistive dielectric layer includes, from bottom to top, a first oxidizing dielectric layer, a second oxidizing dielectric layer, and a third oxidizing dielectric layer, wherein the second oxidizing dielectric layer has an oxygen vacancy concentration higher than that of the first oxidizing dielectric layer and the third oxidizing dielectric layer;
[0011] An electrode layer is deposited on the resistive dielectric layer, and the electrode layer is used to form a prefabricated path in the resistive dielectric layer.
[0012] In a third aspect, an embodiment of the present application provides an electronic device, comprising the resistive random access memory as described in the first aspect above; or, the electronic device comprises a resistive random access memory prepared using the resistive random access memory preparation method as described in the second aspect above.
[0013] The resistive memory in the embodiment of the present application includes a substrate, a resistive dielectric layer and an electrode layer. The resistive dielectric layer is arranged on the substrate, including a first oxide dielectric layer, a second oxide dielectric layer and a third oxide dielectric layer arranged in sequence from bottom to top. The oxygen vacancy concentration of the second oxide dielectric layer is higher than that of the first oxide dielectric layer and the third oxide dielectric layer. The electrode layer is arranged on the substrate and connected to the resistive dielectric layer to form a prefabricated path in the resistive dielectric layer. Since the oxygen vacancy concentration of the second oxide dielectric layer is higher than that of the first oxide dielectric layer and the third oxide dielectric layer, the conductive filament is mainly formed in the second oxide dielectric layer and can solidify the movement path of the conductive filament, thereby suppressing the randomness of the conductive filament in the prefabricated path and improving the uniformity of the performance of the resistive memory. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] The accompanying drawings are used to provide a further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.
[0015] Figure 1 1 is a schematic diagram of a top view of a resistive random access memory provided by an embodiment of the present application;
[0016] Figure 2 This is a resistive memory provided by the embodiment of the present application. Figure 1 A schematic diagram of the longitudinal cross-sectional structure of line AB is shown;
[0017] Figure 3 This is a resistive memory provided by the embodiment of the present application. Figure 1 Schematic diagram of the longitudinal cross-section structure of line CD shown;
[0018] Figure 4 1 is a schematic top view of a resistive random access memory provided by another embodiment of the present application;
[0019] Figure 5 Another embodiment of the present invention provides a resistive memory device. Figure 4 A schematic diagram of the longitudinal cross-sectional structure of line AB is shown;
[0020] Figure 6 Another embodiment of the present invention provides a resistive memory device. Figure 4 Schematic diagram of the longitudinal cross-section structure of line CD shown;
[0021] Figure 7 This is a flow chart of a method for preparing a resistive random access memory provided in an embodiment of the present application. DETAILED DESCRIPTION
[0022] In order to enable those skilled in the art to better understand the technical solution of the present application, the technical solution provided by the present application is described in detail below with reference to the accompanying drawings.
[0023] Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, but the described example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the scope of this application to those skilled in the art.
[0024] The terms used herein are used only to describe specific embodiments and are not intended to limit this application. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, they specify the presence of features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.
[0025] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.
[0026] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present application, and will not be interpreted as having an idealized or overly formal meaning, unless clearly defined in the examples of the present application.
[0027] The invention of resistive random access memory (RRAM) has opened up new avenues for innovation in information storage, processing, and transmission, with broad application prospects in areas such as neuromorphic devices, scalable hardware systems, ultra-low-power devices, and high-performance materials engineering devices. Currently, most RRAMs are based on a sandwich-like capacitor structure: metal electrodes at either end sandwich a dielectric layer of insulating or semiconductor material. Applying a positive or negative voltage to the electrodes creates or breaks a conductive filament in the dielectric layer, switching the device between two resistance states: low resistance or high resistance. When the conductive filament forms between the electrodes, the device is in the low-resistance state; when it breaks, it is in the high-resistance state. Compared to traditional vertical RRAMs, planar RRAMs offer advantages such as a simpler structure, fewer processing steps, lower power consumption, and lower cost. However, due to the difficulty of forming a thin resistive layer between the electrodes and the presence of various imperfect factors such as dislocations and defects in the resistive layer, the formation and breaking of the conductive filaments are subject to significant randomness. This randomness affects the performance uniformity of the same device in different cycles and of different devices in the same cycle, which may lead to performance disturbances in a single device, current leakage in large-scale resistive memory arrays, and even physical failure. This seriously restricts the performance improvement and application scale of planar resistive memory.
[0028] Traditional solutions have few technical approaches to improving the performance uniformity of planar resistive random access memory, and they mainly focus on solutions that introduce nanostructures. These solutions primarily utilize micro-nanostructures such as nanowires as the resistive dielectric layer of planar resistive random access memory, confining the migration of active metal ions or oxygen vacancies in the electrode to the interior or surface of low-dimensional nanostructures, thereby strengthening the orderly growth of conductive filaments and improving the uniformity of resistive random access memory. However, this type of solution involves the growth, collection, selection, transfer, and adhesion of nanostructures, with many process steps, low yield, incompatibility with CMOS processes, and difficulty in industrialization. This solution has many problems, such as the tendency for thin nanowires to break easily, and the inability to effectively restrict the disordered growth of conductive filaments if the nanowires are too thick.
[0029] Based on this, an embodiment of the present application provides a resistive random access memory, which includes a substrate, a resistive random access dielectric layer, and an electrode layer; the resistive random access dielectric layer is arranged on the substrate, including a first oxide dielectric layer, a second oxide dielectric layer, and a third oxide dielectric layer arranged in sequence from bottom to top, and the second oxide dielectric layer has an oxygen vacancy concentration higher than the first oxide dielectric layer and the third oxide dielectric layer; the electrode layer is arranged on the substrate and connected to the resistive random access dielectric layer, and is used to form a prefabricated path in the resistive random access dielectric layer. Because the conductive filament is mainly formed in the second oxide dielectric layer, and the oxygen vacancies in the resistive random access dielectric layer show a concentration gradient in the vertical direction with a high center and a low top and bottom, the conductive filament is confined to the second oxide dielectric layer with a higher oxygen vacancy concentration. This can solidify the movement path of the conductive filament, suppress the randomness of the conductive filament in the prefabricated path, and improve the uniformity of the performance of the resistive random access memory.
[0030] In order to make the technical solution of the present application clearer and easier to understand, the resistive memory device of the embodiment of the present application is described in detail below with reference to a top view structural diagram and a cross-sectional structural diagram.
[0031] See Figure 1 , is a schematic diagram of a top view of a resistive random access memory provided by an embodiment of the present application. Figure 1 As shown, the resistive memory includes a substrate 100, a resistive dielectric layer 200 and an electrode layer 300; and the resistive memory is symmetrically cross-sectioned along the CD line and the AB line respectively to form a longitudinal cross section of the resistive memory along the AB line and a longitudinal cross section along the CD line.
[0032] Figure 2 Shown along Figure 1 The longitudinal cross-sectional structure diagram of the AB line is as follows: Figure 2 As shown, the resistive dielectric layer 200 is disposed on the substrate 100, including a first oxidizing dielectric layer 210, a second oxidizing dielectric layer 220, and a third oxidizing dielectric layer 230 arranged in sequence from bottom to top. The concentration of oxygen vacancies 400 in the second oxidizing dielectric layer 220 is higher than that in the first oxidizing dielectric layer 210 and the third oxidizing dielectric layer 230; the electrode layer 300 is disposed on the substrate 100 and connected to the resistive dielectric layer 200, and is used to form a prefabricated path in the resistive dielectric layer 200.
[0033] Figure 3 Shown along Figure 1 Schematic diagram of the longitudinal cross-section structure of the CD line, as shown in Figure 3 As shown, the resistive dielectric layer 200 is disposed on the substrate 100 and includes a first oxidizing dielectric layer 210, a second oxidizing dielectric layer 220, and a third oxidizing dielectric layer 230 disposed sequentially from bottom to top. The cross-section of the resistive dielectric layer 200 along the CD line is an inverted isosceles trapezoid or an inverted isosceles triangle, and the angle formed between the resistive dielectric layer 200 and the substrate 100 is θ.
[0034] It should be noted that the first oxide dielectric layer 210 is a dry-process oxide dielectric layer with a relatively slow oxidation rate, high oxide lattice quality, low oxygen vacancy concentration, and a thickness of 1 to 30 nanometers. The second oxide dielectric layer 220 is a wet-process oxide dielectric layer with a relatively fast oxidation rate, low oxide lattice quality, high oxygen vacancy concentration 400, and a thickness of 1 to 80 nanometers. The third oxide dielectric layer 230 is a dry-process oxide dielectric layer with a relatively slow oxidation rate, high oxide lattice quality, low oxygen vacancy concentration, and a thickness of 1 to 30 nanometers. Because the oxygen vacancy concentration 400 in the second oxide dielectric layer 220 is higher than that in the first and third oxide dielectric layers 210, 230, the conductive filaments are primarily formed in the second oxide dielectric layer 220, solidifying the conductive filament movement path. This suppresses randomness in the conductive filaments' prefabricated paths and improves the uniformity of resistive random access memory performance. The device of the present application has a simple structure, consisting of only three parts: a substrate 100, a resistive dielectric layer 200, and an electrode layer 300. It does not require process steps such as epitaxial growth and requires less equipment, thereby shortening the production cycle and reducing costs.
[0035] The main constituent material of the substrate 100 may be silicon Si, silicon nitride SiN, silicon carbide SiC, or compounds thereof, or may be diamond or the like.
[0036] The resistive dielectric layer 200 is arranged on the upper surface of the substrate 100 and can be formed by thermal oxidation technology. The material can be silicon dioxide (SiO2), aluminum oxide (Al2O3) or other oxides, with a thickness of 1 nanometer to 100 nanometers and a length of 1 nanometer to 100 microns. Its top view shape includes but is not limited to rectangle, circle, triangle, "hourglass shape", etc. Its cross-sectional shape along the CD line includes but is not limited to inverted triangle, inverted trapezoid, etc. Its lower side width can be 1 nanometer to 100 nanometers, and its upper side width can be 1 nanometer to 1000 nanometers.
[0037] The electrode layer 300 is disposed on the upper surface of the substrate 100 and is located on both sides of the prefabricated path in the resistive dielectric layer 200, covering a portion of the resistive dielectric layer 200. The shape of the electrode layer 300 may include, but is not limited to, a triangle, a circle, a rectangle, a trapezoid, a polygon, or a combination thereof.
[0038] The main constituent materials of the electrode layer can be platinum (Pt), gold (Au), titanium nitride (TiN), tantalum nitride (TaN), palladium (Pd), ruthenium (Ru), iridium (Ir), tungsten (W), aluminum (Al), hafnium (Hf), titanium (Ti), tantalum (Ta), vanadium (V), chromium (Cr), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), niobium (Nb), zirconium (Zr) single substances and one or more combination stacks of metal compounds.
[0039] In the embodiment of the present application, the electrode layer 300 includes a first electrode layer 310 and a second electrode layer 320. The first electrode layer 310 is located at the first end of the resistive dielectric layer 200, and the second electrode layer 320 is located at the second end of the resistive dielectric layer 200. Both the first electrode layer 310 and the second electrode layer 320 are in contact with the second oxidizing dielectric layer 220.
[0040] It is understood that the electrode layer 300 includes a first electrode layer 310 and a second electrode layer 320, and the first electrode layer 320 and the second electrode layer 320 are used to form a prefabricated path in the resistive dielectric layer 200. Since the first oxidizing dielectric layer 210 and the third oxidizing dielectric layer 230 are both dry-process oxidizing dielectric layers with a slow oxidation rate, while the second oxidizing dielectric layer 220 is a wet-process oxidizing dielectric layer with a fast oxidation rate and a high oxygen vacancy concentration, the oxygen vacancy 400 concentration in the second oxidizing dielectric layer 220 is higher than that in the first oxidizing dielectric layer 210 and the third oxidizing dielectric layer 230. The first electrode layer 310 and the second electrode layer 320 are respectively in contact with the second oxidizing dielectric layer, so that the conductive filaments are mainly formed in the second oxidizing dielectric layer 220. This can solidify the movement path of the conductive filaments, thereby suppressing the randomness of the conductive filaments in the prefabricated path and improving the uniformity of the resistive memory performance.
[0041] It should be noted that the first electrode layer 310 and the second electrode layer 320 may be a combination of one or more metal elements and metal compounds, with a thickness of 100 nanometers to 1000 nanometers.
[0042] like Figure 1 As shown, the width of the prefabricated path is narrow in the middle and wide at both ends in the direction from the first end to the second end, so as to prevent the conductive wire from breaking at the narrowest part in the middle of the prefabricated path.
[0043] As an example, the length of the prefabricated path may be 1000 nanometers, the width at the widest point may be 100 nanometers, and the width at the narrowest point may be 30 nanometers.
[0044] It can be understood that the width of the prefabricated path is narrower in the middle and wider at both ends, with the width of the prefabricated path near the first and second ends being wider than the width of the prefabricated path in the middle. This prevents the conductive filaments from breaking at the narrowest point in the middle of the prefabricated path. The narrowest point in the middle is the break point of the conductive filaments. By solidifying the break point of the conductive filaments, the randomness of the conductive filaments in the prefabricated path is suppressed, thereby improving the uniformity of the performance of the resistive random access memory.
[0045] It should also be noted that in actual production, the width of the prefabricated path can be adjusted according to specific needs and the structure of the resistive random access memory, as long as the conductive wire is limited to breaking at the narrowest point in the middle of the prefabricated path. The embodiments of the present application do not impose specific restrictions on this.
[0046] like Figure 1 As shown, the first electrode layer 310 and the second electrode layer 320 respectively have a tip portion, and the tip portion is in contact with the second oxidizing medium layer 220 .
[0047] It can be understood that the ends of the first electrode layer and the second electrode layer are the starting points of the conductive filaments. The embodiment of the present application designs the ends of the first electrode layer and the second electrode layer into a pointed shape, which can enhance the probability of forming a conductive filament at this point through the pointed electric field, thereby realizing the starting point of the solidified conductive filament, suppressing the randomness of the conductive filament in the prefabricated path, and improving the uniformity of the performance of the resistive random access memory.
[0048] like Figure 2 As shown, the first oxidizing medium layer 210, the second oxidizing medium layer 220 and the third oxidizing medium layer 230 in the embodiment of the present application are stacked in sequence to form a layered structure, which are the first oxidizing medium layer 210, the second oxidizing medium layer 220 and the third oxidizing medium layer 230 from bottom to top.
[0049] In the embodiment of the present application, the second oxidizing medium layer 220 may be in an inverted trapezoidal shape.
[0050] like Figure 3 As shown, the longitudinal cross-section of the second oxidizing medium layer 220 along the CD line is in an inverted trapezoidal shape, and the longitudinal cross-section of the first oxidizing medium layer 210 , the second oxidizing medium layer 220 and the third oxidizing medium layer 230 along the CD line is in an inverted trapezoidal shape.
[0051] It should be noted that the longitudinal cross-sectional shape of the first oxidizing medium layer 210 , the second oxidizing medium layer 220 and the third oxidizing medium layer 230 as a whole along the CD line may also be an inverted triangle shape or other similar shapes.
[0052] The longitudinal cross-sectional shape of the first oxidizing medium layer 210, the second oxidizing medium layer 220, and the third oxidizing medium layer 230 along the CD line is designed to be an inverted trapezoid or an inverted triangle, so that the oxygen vacancies in the second oxidizing medium layer 220 (wet oxidizing medium layer) can only be located in the middle part. The wet oxidizing medium layer is thick in the middle with many oxygen vacancies and thin on both sides with few oxygen vacancies, further confining the conductive filaments to the middle of the second oxidizing medium layer, thereby helping to suppress the randomness of the conductive filaments in the prefabricated path.
[0053] In the embodiment of the present application, the third oxidizing medium layer 230 wraps the second oxidizing medium layer 220 to form a composite nanowire structure 500. In a specific implementation, a composite thermal oxidation technique can be used, where the third oxidizing medium layer wraps the second oxidizing medium layer to form a composite nanowire structure. This confines oxygen vacancies within the nanowires, creates a prefabricated path for the conductive filaments, and optimizes device uniformity.
[0054] See Figure 4, is a schematic diagram of a top view of a resistive random access memory provided by an embodiment of the present application. Figure 4 As shown, the resistive memory includes a substrate 100, a resistive dielectric layer 200 and an electrode layer 300; and the resistive memory is symmetrically cross-sectioned along the CD line and the AB line respectively to form a longitudinal cross section of the resistive memory along the AB line and a longitudinal cross section along the CD line.
[0055] Figure 5 Shown along Figure 4 The longitudinal cross-sectional structure diagram of the AB line is as follows: Figure 5 As shown, the resistive dielectric layer 200 is arranged on the substrate 100, including a first oxide dielectric layer 210 and a composite nanowire structure 500 arranged in sequence from bottom to top, and also includes a first electrode layer 310 located at the first end of the composite nanowire structure 500 and a second electrode layer 320 located at the second end of the composite nanowire structure 500.
[0056] Figure 6 Shown along Figure 4 Schematic diagram of the longitudinal cross-section structure of the CD line, as shown in Figure 6 As shown, the third oxidizing medium layer 230 wraps the second oxidizing medium layer 220 to form a composite nanowire structure 500 . The composite nanowire structure 500 and the first oxidizing medium layer 210 are disposed on the substrate 100 .
[0057] It should be noted that the main constituent material of the composite nanowires may be SiO2.
[0058] In the embodiment of the present application, the thickness of the resistive dielectric layer 200 is 1 nanometer to 100 nanometers.
[0059] It can be understood that the thickness of the resistive dielectric layer is set to 1 nm to 100 nm. Within this range, by adjusting parameters such as the time, temperature, and ventilation volume of thermal oxidation, the thickness of the resistive dielectric layer can be controlled within a thinner range, thereby reducing the longitudinal disordered growth of the conductive filaments, thereby suppressing the randomness of the conductive filaments in the prefabricated path through the width dimension and improving the uniformity of the resistive memory performance.
[0060] In the embodiment of the present application, the thickness of the second oxidizing medium layer 220 is greater than the thickness of the first oxidizing medium layer 210 and the thickness of the third oxidizing medium layer 230 .
[0061] It is understood that the second oxide dielectric layer is a wet oxide dielectric layer, which has a relatively fast oxidation rate and a high oxygen vacancy concentration, and the conductive filaments are primarily formed in the second oxide dielectric layer. The first and third oxide dielectric layers are dry oxide dielectric layers, which have a relatively slow oxidation rate and a low oxygen vacancy concentration. The thickness of the second oxide dielectric layer is greater than that of the first and third oxide dielectric layers. Because the oxygen vacancy concentration of the second oxide dielectric layer is higher than that of the first and third oxide dielectric layers, the conductive filaments are primarily formed in the second oxide dielectric layer, solidifying the movement path of the conductive filaments, thereby suppressing the randomness of the conductive filaments in the prefabricated path and improving the uniformity of the resistive random access memory performance.
[0062] In the embodiment of the present application, the length of the resistive dielectric layer 200 is 1 nanometer to 100 micrometers.
[0063] It can be understood that the length of the resistive dielectric layer is set to 1 nanometer to 100 microns. Within this range, the length of the conductive filament and the high / low resistance state switching time can be optimized by adjusting the length of the thermally oxidized nanowire between the electrodes, thereby suppressing the randomness of the conductive filament in the prefabricated path through the length dimension and improving the uniformity of the resistive memory performance.
[0064] The resistive random access memory provided by the present application is described below with reference to specific examples.
[0065] Example 1
[0066] like Figures 1 to 3 As shown, Figures 1 to 3 The resistive memory includes a substrate 100 , a resistive dielectric layer 200 , an electrode layer 300 , oxygen vacancies 400 , a first oxidized dielectric layer 210 , a second oxidized dielectric layer 220 , and a third oxidized dielectric layer 230 .
[0067] The resistive dielectric layer 200 is disposed on the substrate 100 and includes a first oxidizing dielectric layer 210, a second oxidizing dielectric layer 220, and a third oxidizing dielectric layer 230 disposed sequentially from bottom to top. The concentration of oxygen vacancies 400 in the second oxidizing dielectric layer 220 is higher than that in the first oxidizing dielectric layer 210 and the third oxidizing dielectric layer 230. The electrode layer 300 is disposed on the substrate 100 and connected to the resistive dielectric layer 200 to form a prefabricated path in the resistive dielectric layer 200. The electrode layer 300 includes a first electrode layer 310 and a second electrode layer 320. The first electrode layer 310 is located at the first end of the resistive dielectric layer 200, and the second electrode layer 320 is located at the second end of the resistive dielectric layer 200. Both the first electrode layer 310 and the second electrode layer 320 contact the second oxidizing dielectric layer 220. The width of the prefabricated path is narrow in the middle and wide at both ends in the direction from the first end to the second end to prevent the conductive filament from breaking at the narrowest point in the middle of the prefabricated path. The first electrode layer 310 and the second electrode layer 320 each have a pointed portion, and the pointed portions contact the second oxidizing dielectric layer 220. The first oxidizing dielectric layer 210, the second oxidizing dielectric layer 220, and the third oxidizing dielectric layer 230 are stacked in sequence to form a layered structure, with the second oxidizing dielectric layer 220 having an inverted trapezoidal shape. The thickness of the resistive dielectric layer 200 is 1 to 100 nanometers, and the thickness of the second oxidizing dielectric layer 220 is greater than the thickness of the first oxidizing dielectric layer 210 and the thickness of the third oxidizing dielectric layer 230. The length of the resistive dielectric layer 200 is 1 nanometer to 100 micrometers.
[0068] The substrate 100 is made of SiC, the resistive dielectric layer 200 is made of SiO2 and has a thickness of 30 nanometers. The length of the prefabricated conductive filament path is 1000 nanometers, with a width of 100 nanometers at its widest point and 30 nanometers at its narrowest point. The cross-section of the resistive dielectric layer 200 along the CD line is an inverted isosceles trapezoid or an inverted isosceles triangle, with the angle between its hypotenuse and the substrate 100 being 60° (i.e., θ). The first oxidizing dielectric layer 210 is 5 nanometers thick and has an oxidation temperature of 1000 degrees Celsius. The second oxidizing dielectric layer 220 is 15 nanometers thick and has an oxidation temperature of 1000 degrees Celsius. The third oxidizing dielectric layer 230 is 10 nanometers thick and has an oxidation temperature of 1000 degrees Celsius. The electrode layer 300 is made of Pt and has a thickness of 500 nanometers. The deposition method used is electron beam evaporation.
[0069] In the resistive random access memory provided in this example, since the oxygen vacancy concentration of the second oxide dielectric layer is higher than that of the first oxide dielectric layer and the third oxide dielectric layer, the conductive filaments are mainly formed in the second oxide dielectric layer and the movement path of the conductive filaments can be solidified, thereby suppressing the randomness of the conductive filaments in the prefabricated path and improving the performance uniformity of the resistive random access memory.
[0070] Example 2
[0071] like Figures 4 to 6 As shown, Figures 4 to 6 The resistive memory includes a substrate 100, a resistive dielectric layer 200, a first electrode layer 310 and a second electrode layer 320, oxygen vacancies 400, a first oxidizing dielectric layer 210, a second oxidizing dielectric layer 220, a third oxidizing dielectric layer 230, and a composite nanowire structure 500.
[0072] The resistive dielectric layer 200 is disposed on the substrate 100 and includes a first oxidizing dielectric layer 210, a second oxidizing dielectric layer 220, and a third oxidizing dielectric layer 230 disposed sequentially from bottom to top. The concentration of oxygen vacancies 400 in the second oxidizing dielectric layer 220 is higher than that in the first oxidizing dielectric layer 210 and the third oxidizing dielectric layer 230. The electrode layer 300 is disposed on the substrate 100 and connected to the resistive dielectric layer 200 to form a prefabricated path in the resistive dielectric layer 200. The electrode layer 300 includes a first electrode layer 310 and a second electrode layer 320. The first electrode layer 310 is located at the first end of the resistive dielectric layer 200, and the second electrode layer 320 is located at the second end of the resistive dielectric layer 200. The first electrode layer 310 and the second electrode layer 320 are both in contact with the second oxidizing dielectric layer 220. The first electrode layer 310 and the second electrode layer 320 each have a tip, and the tip contacts the second oxidizing dielectric layer 220. The third oxidizing dielectric layer 230 wraps around the second oxidizing dielectric layer 220 to form a composite nanowire structure 500. The thickness of the resistive dielectric layer 200 is 1 to 100 nanometers, and the thickness of the second oxidizing dielectric layer 220 is greater than the thickness of the first oxidizing dielectric layer 210 and the thickness of the third oxidizing dielectric layer 230. The length of the resistive dielectric layer 200 is 1 nanometer to 100 micrometers.
[0073] Among them, the material used for the substrate 100 is SiC, the thickness of the first oxidizing medium layer 210 is 20 nanometers, and its oxidation temperature is 1050 degrees Celsius; the material used for the first electrode layer 310 is Pt, its thickness is 500 nanometers, and the deposition method used is electron beam evaporation; the material used for the second electrode layer 320 is Ag, its thickness is 500 nanometers, and the deposition method used is electron beam evaporation; the material used for the composite nanowire structure 500 is SiO2, its diameter is 100 nanometers, and its length is 1000 nanometers; the material selected for the second oxidizing medium layer 220 is SiO2, the deposition method used is PECVD, and its diameter is 90 nanometers; the material used for the third oxidizing medium layer 230 is SiO2, its thickness is 10 nanometers, and its thermal oxidation temperature is 1050 degrees Celsius.
[0074] In the resistive random access memory provided in this example, a composite thermal oxidation technique is used to form nanowires as the resistive random access dielectric layer 200 on the substrate 100, thereby creating a prefabricated path for the conductive filaments. Since the oxygen vacancy concentration of the second oxide dielectric layer 220 is higher than that of the first oxide dielectric layer 210 and the third oxide dielectric layer 230, the conductive filaments are mainly formed in the second oxide dielectric layer 220, and the movement path of the conductive filaments can be solidified, thereby suppressing the randomness of the conductive filaments in the prefabricated path and improving the performance uniformity of the resistive random access memory.
[0075] The present application also provides a method for preparing a resistive random access memory, see Figure 7 , Figure 7 A flow chart of a method for preparing a resistive random access memory according to an embodiment of the present application is shown. Figure 7 As shown, the method includes but is not limited to steps S710 to S730:
[0076] Step S710: Spin-coat photoresist on the substrate to form a preparation area.
[0077] Step S720: Preparing a resistive dielectric layer in the preparation area. The resistive dielectric layer includes, from bottom to top, a first oxidizing dielectric layer, a second oxidizing dielectric layer, and a third oxidizing dielectric layer. The second oxidizing dielectric layer has a higher oxygen vacancy concentration than the first oxidizing dielectric layer and the third oxidizing dielectric layer.
[0078] Step S730: depositing an electrode layer on the resistive dielectric layer, where the electrode layer is used to form a prefabricated path in the resistive dielectric layer.
[0079] In the embodiment of the present application, a preparation area is formed by spin-coating a photoresist on a substrate, and a resistive dielectric layer is prepared in the preparation area, wherein the resistive dielectric layer includes, from bottom to top, a first oxide dielectric layer, a second oxide dielectric layer, and a third oxide dielectric layer. An electrode layer is deposited through the resistive dielectric layer, and the electrode layer is used to form a prefabricated path in the resistive dielectric layer. The oxygen vacancy concentration of the second oxide dielectric layer is higher than that of the first oxide dielectric layer and the third oxide dielectric layer. The conductive filament is mainly formed in the second oxide dielectric layer and can solidify the movement path of the conductive filament, thereby suppressing the randomness of the conductive filament in the prefabricated path and improving the uniformity of the performance of the resistive memory.
[0080] It should be noted that the deposition method of the electrode layer through the resistive dielectric layer includes but is not limited to thermal evaporation, electron beam evaporation, magnetron sputtering, ion beam sputtering, PECVD technology, etc.
[0081] In an embodiment of the present application, a resistive dielectric layer is prepared in a preparation area, including: post-baking a photoresist to form a mask layer having an inclined terrace, and converting the mask layer into a carbon film layer; forming a first oxidizing dielectric layer through the carbon film layer in a dry oxygen atmosphere; forming a second oxidizing dielectric layer on the first oxidizing dielectric layer in a wet oxygen atmosphere; and forming a third oxidizing dielectric layer on the second oxidizing dielectric layer in a dry oxygen atmosphere until the carbon film layer disappears.
[0082] It can be understood that after the preparation area is formed, the photoresist is post-baked to form a mask layer with an inclined terrace, and the photoresist reflow technology is used to form a mask layer with an inclined terrace. Part of the inclined terrace covers the preset resistive dielectric layer, and the two oblique sides of the terrace form an inverted trapezoid or an inverted triangle with the substrate. The angle θ of the inclined terrace is 1° to 90°. This shape will be transferred to the resistive dielectric layer through thermal oxidation. In a tube furnace and an atmosphere of protective gas such as argon, at a high temperature of 900 to 1600 degrees Celsius, the mask layer is converted into a carbon film layer. In a dry oxygen atmosphere, a first oxidizing dielectric layer is formed by the carbon film layer. In a wet oxygen atmosphere, a second oxidizing dielectric layer is formed on the first oxidizing dielectric layer. In a dry oxygen atmosphere, a third oxidizing dielectric layer is formed on the second oxidizing dielectric layer until the carbon film layer disappears.
[0083] In an embodiment of the present application, a resistive dielectric layer is prepared in a preparation area, including: converting the preparation area into a first oxide dielectric layer in a dry oxygen atmosphere; growing a second oxide dielectric layer in the shape of nanowires on the first oxide dielectric layer; spin-coating photoresist on the second oxide dielectric layer, and photolithographically exposing the nanowire area; and forming a third oxide dielectric layer in the nanowire area in a dry oxygen atmosphere.
[0084] It can be understood that in a dry oxygen atmosphere, the preparation area is converted into a first oxide dielectric layer. The first oxide dielectric layer is a dry oxide dielectric layer. Oxidation is continued until the carbon film layer completely disappears. SiO2 nanowires are grown on the first oxide dielectric layer using photolithography and PECVD techniques. Due to the rapid growth rate of PECVD, a large number of oxygen vacancies exist in the nanowires, forming a second oxide dielectric layer. Photoresist is again used as a mask layer to expose the nanowire area. In a dry oxygen atmosphere, a third oxide dielectric layer is formed in the nanowire area. Through photoresist reflow technology, the mask layer angle is transferred to the thermally oxidized nanowire, and its longitudinal cross-section presents an inverted trapezoidal or inverted triangle shape. The second oxide dielectric layer is thick in the middle with many oxygen vacancies and thin on both sides with few oxygen vacancies. This further confines the conductive filaments to the middle of the second oxide dielectric layer. The dimension of the oxygen vacancies suppresses the randomness of the conductive filaments, thereby improving the uniformity of the resistive random access memory performance.
[0085] In an embodiment of the present application, depositing an electrode layer on the resistive dielectric layer includes:
[0086] Electrode windows are opened at both ends of the second oxidizing medium layer, and a first electrode layer and a second electrode layer are deposited in the electrode windows.
[0087] It is understandable that the electrode window is opened by wet etching, and the oxide layer outside the active area is removed, and the first electrode layer and the second electrode layer are respectively deposited as electrodes in the electrode window by electron beam evaporation technology.
[0088] An embodiment of the present application further provides an electronic device, which includes the resistive random access memory provided in the above embodiment, or includes a resistive random access memory prepared by the method for preparing the resistive random access memory provided in the above embodiment.
[0089] It is understandable that the electronic device can be a computer, a smart phone, a smart TV, a smart set-top box, a smart router, an electronic digital camera and other devices, and the electronic device includes the resistive random access memory provided in the above embodiment. The resistive random access memory forms a storage unit through a packaging process. In addition, the storage unit also includes a storage controller, which is used to read and write data to the resistive random access memory. Specifically, the storage controller provides a write voltage or a read voltage to the resistive random access memory according to the received read and write instructions. The write voltage and the read voltage can cause the resistance of the resistive random access memory to change, thereby changing the storage state in the resistive random access memory, thereby writing data to the resistive random access memory or reading data from the resistive random access memory.
[0090] The electronic device provided in the embodiment of the present application may further include a processor, a display device, etc., wherein the processor writes data to the resistive memory or reads data from the resistive memory by sending read and write instructions, and the display device is used to visualize the data written to the resistive memory or read from the resistive memory, thereby realizing various functions of the electronic device.
[0091] It should be noted that the specific structure and technical effects of the resistive random access memory, and the specific steps and technical effects of the method for preparing the resistive random access memory can be found in the description of the above embodiments, and will not be repeated here.
[0092] The above is a detailed description of the preferred implementation of the present application, but the present application is not limited to the above implementation. Those skilled in the art can make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the present application.
Claims
1. A resistive random access memory, comprising: substrate; a resistive dielectric layer, disposed on the substrate, comprising a first oxidizing dielectric layer, a second oxidizing dielectric layer, and a third oxidizing dielectric layer disposed sequentially from bottom to top, wherein the second oxidizing dielectric layer has a higher oxygen vacancy concentration than the first oxidizing dielectric layer and the third oxidizing dielectric layer; The electrode layer is provided on the substrate and connected to the resistive dielectric layer, and is used to form a prefabricated path in the resistive dielectric layer.
2. The resistive random access memory according to claim 1, wherein: The electrode layer includes a first electrode layer and a second electrode layer. The first electrode layer is located at the first end of the resistive dielectric layer, the second electrode layer is located at the second end of the resistive dielectric layer, and both the first electrode layer and the second electrode layer are in contact with the second oxidizing dielectric layer.
3. The resistive random access memory according to claim 2, wherein: The width of the prefabricated path in the direction from the first end to the second end is narrow in the middle and wide at both ends, so as to limit the conductive thread from breaking at the narrowest point in the middle of the prefabricated path.
4. The resistive random access memory according to claim 2, wherein: The first electrode layer and the second electrode layer respectively have a tip portion, and the tip portion is in contact with the second oxidizing medium layer.
5. The resistive random access memory according to claim 1, wherein: The first oxidizing medium layer, the second oxidizing medium layer and the third oxidizing medium layer are stacked in sequence to form a layered structure.
6. The resistive random access memory according to claim 5, wherein: The second oxidizing medium layer is in an inverted trapezoidal shape.
7. The resistive random access memory according to claim 1, wherein: The third oxidizing medium layer wraps the second oxidizing medium layer to form a composite nanowire structure.
8. The resistive random access memory according to claim 1, wherein: The thickness of the resistive dielectric layer is 1 nanometer to 100 nanometers.
9. The resistive random access memory according to claim 8, wherein: The thickness of the second oxidizing medium layer is greater than the thickness of the first oxidizing medium layer and the thickness of the third oxidizing medium layer.
10. The resistive random access memory according to claim 1, wherein: The length of the resistive dielectric layer is 1 nanometer to 100 micrometers.
11. A method for preparing a resistive random access memory, the method comprising: Spin coating photoresist on the substrate to form a preparation area; Prepare a resistive dielectric layer in the preparation area, wherein the resistive dielectric layer includes, from bottom to top, a first oxidizing dielectric layer, a second oxidizing dielectric layer, and a third oxidizing dielectric layer, wherein the second oxidizing dielectric layer has an oxygen vacancy concentration higher than that of the first oxidizing dielectric layer and the third oxidizing dielectric layer; An electrode layer is deposited on the resistive dielectric layer, and the electrode layer is used to form a prefabricated path in the resistive dielectric layer.
12. The method according to claim 11, characterized in that The step of preparing the resistive dielectric layer in the preparation area includes: post-baking the photoresist to form a mask layer having an inclined terrace, and converting the mask layer into a carbon film layer; forming a first oxidizing medium layer through the carbon film layer in a dry oxygen atmosphere; forming a second oxidizing medium layer on the first oxidizing medium layer in a wet oxygen atmosphere; In a dry oxygen atmosphere, a third oxidizing medium layer is formed on the second oxidizing medium layer until the carbon film layer disappears.
13. The method according to claim 11, characterized in that The step of preparing the resistive dielectric layer in the preparation area includes: In a dry oxygen atmosphere, converting the prepared area into a first oxidizing medium layer; growing a second oxidizing medium layer in the shape of nanowires on the first oxidizing medium layer; Spin-coating a photoresist on the second oxide dielectric layer, and exposing the nanowire region by photolithography; A third oxide dielectric layer is formed in the nanowire region under a dry oxygen atmosphere.
14. The method according to claim 11, characterized in that Depositing an electrode layer on the resistive dielectric layer includes: Electrode windows are opened at both ends of the second oxidizing medium layer, and a first electrode layer and a second electrode layer are deposited in the electrode windows.
15. An electronic device, comprising the resistive random access memory according to any one of claims 1 to 10; or, comprising the resistive random access memory prepared by the method for preparing a resistive random access memory according to any one of claims 11 to 14.