Compression of translation lookaside buffer (TLB) tags using TLB metadata buffers in processor-based devices

Abstract

Compressing a translation lookaside buffer (TLB) tag using a TLB metadata buffer in a processor-based device is disclosed herein. In some aspects, a processor-based apparatus provides a memory management unit (MMU) that includes a TLB and a TLB metadata buffer that includes a plurality of TLB metadata buffer entries that store corresponding TLB metadata. The MMU is configured to select a TLB metadata buffer entry for accessing the TLB of the processor-based device. After selecting the TLB metadata buffer entry, the MMU stores a pointer to the TLB metadata buffer entry as an active TLB metadata pointer. When the MMU subsequently receives a memory access request including a virtual address (VA), the MMU generates a TLB entry for the VA in the TLB and stores the active TLB metadata pointer as part of a TLB tag of the TLB entry in place of the TLB metadata of the TLB metadata buffer entry.

Description

[0001] Priority application

[0002] This application claims priority to U.S. patent application serial number 18 / 168,871, filed on February 14, 2023, entitled “COMPRESSING TRANSLATIONLOOKASIDE BUFFER(TLB)TAGS USING A TLB METADATA BUFFERIN PROCESSOR-BASEDDEVICES,” which is incorporated herein by reference in its entirety. Background Art I. Technical Field

[0003] The technology of this disclosure generally relates to translation lookaside buffers (TLBs) in processor-based devices.

[0004] II. Background Technology

[0005] Microprocessors (also referred to herein as "processors") perform computing tasks for a wide variety of applications. Conventional processors utilize virtual memory, which refers to a memory management mechanism that maps memory addresses referenced by executing processes (i.e., virtual addresses or VAs) to physical addresses (PAs) within system memory. By using virtual memory, processor-based systems are able to provide access to a virtual memory space that is larger than the actual physical memory space and enhance inter-process security through memory isolation. The mapping of a VA to its corresponding PA is accomplished using a data structure called a page table. To further improve performance, page table entries retrieved from the page table during VA to PA translation are cached in a data structure called a translation lookaside buffer or TLB.

[0006] While using a TLB can effectively reduce memory access latency within a processor, the TLB may require a significant portion of the processor's physical area. This problem may be encountered more frequently as instruction set architectures (ISAs) increase the size of data such as VAs, application space identifiers (ASIDs), and virtual machine identifiers (VMIDs), which are conventionally stored as part of the tag of each TLB entry. Therefore, it may be desirable to reduce the area occupied by the TLB without adversely affecting the TLB lookup latency and while minimizing TLB misses. Summary of the Invention

[0007] Aspects disclosed in the detailed description include using a translation lookaside buffer (TLB) metadata buffer in a processor-based device to compress TLB tags. Related apparatus and methods are also disclosed. In this regard, in some exemplary aspects disclosed herein, a processor of a processor-based device provides a memory management unit (MMU) including a TLB and a TLB metadata buffer. The TLB metadata buffer includes a plurality of TLB metadata buffer entries, each TLB metadata buffer entry storing corresponding TLB metadata. The TLB metadata may include any data that is conventionally stored as part of a tag of a TLB entry and that may be replicated across multiple TLB entries during execution of a software process. Thus, as a non-limiting example, in some aspects, the TLB metadata may include an application space identifier (ASID) and a virtual machine identifier (VMID) of a processor context, while some aspects may provide that the TLB metadata includes multiple high bits of a virtual address (VA) of a memory region used by a processor pipeline of the processor.

[0008] In an exemplary operation, an MMU of a processor-based device selects a TLB metadata buffer entry for accessing a TLB of the processor-based device by, for example, selecting a TLB metadata buffer entry that stores an ASID and VMID of a new processor context as TLB metadata, or selecting a TLB metadata buffer entry that stores upper bits of a VA of a memory region used by a processor pipeline receiving a memory access request as TLB metadata. After selecting the TLB metadata buffer entry, the MMU stores a pointer to the TLB metadata buffer entry as an active TLB metadata pointer. When the MMU subsequently receives a memory access request that includes the VA, the MMU generates a TLB entry for the VA in the TLB and stores the active TLB metadata pointer as part of a tag of the TLB entry, replacing the TLB metadata of the TLB metadata buffer entry. Some aspects may also provide that when the MMU receives another memory request that includes the VA, the MMU accesses the TLB entry based on the active TLB metadata pointer (e.g., by matching the TLB tag of the TLB entry using the active TLB metadata pointer). In this way, aspects disclosed herein allow for smaller tag sizes per TLB entry without impacting TLB latency, and have the added benefit of simplifying TLB content addressable memory (CAM) logic.

[0009] In aspects where the TLB metadata stored in a TLB metadata buffer entry includes the ASID and VMID of a processor context, the MMU is configured to detect a processor context switch to a new context associated with the ASID and VMID. According to some aspects, if no TLB metadata buffer entry stores corresponding TLB metadata including the ASID and VMID of the new context, the MMU may allocate such a TLB metadata buffer entry. The MMU then selects a TLB metadata buffer entry storing corresponding TLB metadata including the ASID and VMID of the new context for accessing the TLB and stores a pointer to the TLB metadata buffer entry in an active pointer table entry of an active pointer table. Some such aspects provide that the TLB metadata buffer entry also includes a translation mechanism indicator, and the MMU stores a pointer to the TLB metadata buffer entry in an active pointer table entry corresponding to the translation mechanism indicated by the translation mechanism indicator of the TLB metadata buffer entry. Some aspects further provide that the TLB metadata buffer entry also includes a global indicator that, if set, indicates that any associated TLB entry can be used across multiple applications (i.e., only the VMID of the TLB entry needs to match). In these aspects, the MMU stores a pointer to the TLB metadata buffer entry as a global active TLB metadata pointer of the active pointer table entry.

[0010] In an aspect where TLB metadata stored in a TLB metadata buffer entry includes multiple upper bits of a VA of a memory region used by a processor pipeline of a processor, the MMU is configured to receive a memory access request that includes the VA and is associated with one of a plurality of processor pipelines of a processor-based device. According to some aspects, if no TLB metadata buffer entry stores corresponding TLB metadata that includes the upper bits of the VA, the MMU may allocate such a TLB metadata buffer entry. The MMU selects a TLB metadata buffer entry that stores corresponding TLB metadata that includes the multiple upper bits of the VA for accessing the TLB, and stores a pointer to the TLB metadata buffer entry in an active pointer table entry corresponding to the processor pipeline in an active pointer table entry.

[0011] In another aspect, a processor-based device is disclosed. The processor-based device includes a TLB, the TLB including multiple TLB entries, and the processor-based device also includes a TLB metadata buffer, the TLB metadata buffer including multiple TLB metadata buffer entries, each TLB metadata buffer entry being configured to store corresponding TLB metadata. The processor-based device also includes an MMU, the MMU being configured to select a TLB metadata buffer entry from the multiple TLB metadata buffer entries for accessing the TLB. The MMU is also configured to store a pointer to the TLB metadata buffer entry as an active TLB metadata pointer. The MMU is also configured to receive a first memory access request including a first VA. The MMU is further configured to generate a TLB entry for the first VA in the TLB in response to receiving the first memory access request, the TLB entry including a TLB tag, the TLB tag storing the active TLB metadata pointer in place of the TLB metadata of the TLB metadata buffer entry.

[0012] In another aspect, a processor-based device is disclosed. The processor-based device includes a component for selecting a TLB metadata buffer entry from a plurality of TLB metadata buffer entries of a TLB metadata buffer for accessing a TLB of the processor-based device, the plurality of TLB metadata buffer entries each being configured to store corresponding TLB metadata. The processor-based device also includes a component for storing a pointer to the TLB metadata buffer entry as an active TLB metadata pointer. The processor-based device also includes a component for receiving a first memory access request including a first VA. The processor-based device further includes a component for generating a TLB entry for the first VA in the TLB in response to receiving the first memory access request, the TLB entry including a TLB tag, the TLB tag storing the active TLB metadata pointer in place of the TLB metadata of the TLB metadata buffer entry.

[0013] In another aspect, a method for compressing TLB tags using a TLB metadata buffer in a processor-based device is disclosed. The method includes selecting, by an MMU of the processor-based device, one of a plurality of TLB metadata buffer entries in a TLB metadata buffer for accessing a TLB of the processor-based device, the plurality of TLB metadata buffer entries each being configured to store corresponding TLB metadata. The method also includes storing, by the MMU, a pointer to the TLB metadata buffer entry as an active TLB metadata pointer. The method also includes receiving, by the MMU, a first memory access request including a first VA. The method further includes generating, by the MMU, a TLB entry for the first VA in the TLB in response to receiving the first memory access request, the TLB entry including a TLB tag, the TLB tag storing the active TLB metadata pointer in place of the TLB metadata of the TLB metadata buffer entry.

[0014] In another aspect, a non-transitory computer-readable medium is disclosed. The non-transitory computer-readable medium stores computer-executable instructions that, when executed, cause a processor of a processor-based device to select one of a plurality of TLB metadata buffer entries in a TLB metadata buffer for accessing a TLB of the processor-based device, the plurality of TLB metadata buffer entries each being configured to store corresponding TLB metadata. The computer-executable instructions further cause the processor to store a pointer to the TLB metadata buffer entry as an active TLB metadata pointer. The computer-executable instructions further cause the processor to receive a first memory access request including a first VA. The computer-executable instructions further cause the processor to generate a TLB entry for the first VA in the TLB in response to receiving the first memory access request, the TLB entry including a TLB tag that stores the active TLB metadata pointer in place of the TLB metadata of the TLB metadata buffer entry. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a block diagram of an exemplary processor-based device including a memory management unit (MMU) and a translation lookaside buffer (TLB) configured to compress TLB tags using a TLB metadata buffer, according to some aspects;

[0016] Figure 2 Based on some aspects Figure 1 a block diagram of exemplary aspects of an MMU, wherein a TLB metadata buffer stores TLB metadata including application space identifiers (ASIDs) and virtual machine identifiers (VMIDs) for a plurality of translation mechanisms in response to a processor context switch;

[0017] Figure 3 Based on some aspects Figure 1 A block diagram of an exemplary aspect of an MMU, wherein a TLB metadata buffer stores TLB metadata including upper bits of virtual addresses (VAs) for multiple processor pipelines;

[0018] Figure 4 Provides examples according to some aspects Figures 1 to 3 Flowchart of exemplary operations of an MMU and a TLB for compressing TLB tags using a TLB metadata buffer;

[0019] Figures 5A to 5B Provides examples according to some aspects Figure 1 and Figure 2 Flowchart of exemplary operations of an MMU and a TLB for storing TLB metadata including ASIDs and VMIDs for multiple translation mechanisms in response to a processor context switch;

[0020] Figure 6 Provides examples according to some aspects Figure 1 and Figure 3 A flowchart of exemplary operation of an MMU and a TLB for storing TLB metadata including upper bits of VAs for multiple processor pipelines; and

[0021] Figure 7 Yes, it can include Figure 1 and Figure 2 A block diagram of an exemplary processor-based device of an MMU and TLB. DETAILED DESCRIPTION

[0022] With reference now to the accompanying drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0023] Aspects disclosed in the detailed description include using a translation lookaside buffer (TLB) metadata buffer in a processor-based device to compress TLB tags. Related apparatus and methods are also disclosed. In this regard, in some exemplary aspects disclosed herein, a processor of a processor-based device provides a memory management unit (MMU) including a TLB and a TLB metadata buffer. The TLB metadata buffer includes a plurality of TLB metadata buffer entries, each TLB metadata buffer entry storing corresponding TLB metadata. The TLB metadata may include any data that is conventionally stored as part of a tag of a TLB entry and that may be replicated across multiple TLB entries during execution of a software process. Thus, as a non-limiting example, in some aspects, the TLB metadata may include an application space identifier (ASID) and a virtual machine identifier (VMID) of a processor context, while some aspects may provide that the TLB metadata includes multiple high bits of a virtual address (VA) of a memory region used by a processor pipeline of the processor.

[0024] In an exemplary operation, an MMU of a processor-based device selects a TLB metadata buffer entry for accessing a TLB of the processor-based device by, for example, selecting a TLB metadata buffer entry that stores an ASID and VMID of a new processor context as TLB metadata, or selecting a TLB metadata buffer entry that stores upper bits of a VA of a memory region used by a processor pipeline receiving a memory access request as TLB metadata. After selecting the TLB metadata buffer entry, the MMU stores a pointer to the TLB metadata buffer entry as an active TLB metadata pointer. When the MMU subsequently receives a memory access request that includes the VA, the MMU generates a TLB entry for the VA in the TLB and stores the active TLB metadata pointer as part of a tag of the TLB entry, replacing the TLB metadata of the TLB metadata buffer entry. Some aspects may also provide that when the MMU receives another memory request that includes the VA, the MMU accesses the TLB entry based on the active TLB metadata pointer (e.g., by matching the TLB tag of the TLB entry using the active TLB metadata pointer). In this way, aspects disclosed herein allow for smaller tag sizes per TLB entry without impacting TLB latency, and have the added benefit of simplifying TLB content addressable memory (CAM) logic.

[0025] In aspects where the TLB metadata stored in a TLB metadata buffer entry includes the ASID and VMID of a processor context, the MMU is configured to detect a processor context switch to a new context associated with the ASID and VMID. According to some aspects, if no TLB metadata buffer entry stores corresponding TLB metadata including the ASID and VMID of the new context, the MMU may allocate such a TLB metadata buffer entry. The MMU then selects a TLB metadata buffer entry storing corresponding TLB metadata including the ASID and VMID of the new context for accessing the TLB and stores a pointer to the TLB metadata buffer entry in an active pointer table entry of an active pointer table. Some such aspects provide that the TLB metadata buffer entry also includes a translation mechanism indicator, and the MMU stores a pointer to the TLB metadata buffer entry in an active pointer table entry corresponding to the translation mechanism indicated by the translation mechanism indicator of the TLB metadata buffer entry. Some aspects further provide that the TLB metadata buffer entry also includes a global indicator that, if set, indicates that any associated TLB entry can be used across multiple applications (i.e., only the VMID of the TLB entry needs to match). In these aspects, the MMU stores a pointer to the TLB metadata buffer entry as a global active TLB metadata pointer of the active pointer table entry.

[0026] In an aspect where TLB metadata stored in a TLB metadata buffer entry includes multiple upper bits of a VA of a memory region used by a processor pipeline of a processor, the MMU is configured to receive a memory access request that includes the VA and is associated with one of a plurality of processor pipelines of a processor-based device. According to some aspects, if no TLB metadata buffer entry stores corresponding TLB metadata that includes the upper bits of the VA, the MMU may allocate such a TLB metadata buffer entry. The MMU selects a TLB metadata buffer entry that stores corresponding TLB metadata that includes the multiple upper bits of the VA for accessing the TLB, and stores a pointer to the TLB metadata buffer entry in an active pointer table entry corresponding to the processor pipeline in an active pointer table entry.

[0027] in this regard, Figure 1 is a diagram of an exemplary processor-based device 100 including a processor 102. Processor 102 (which may also be referred to as a "processor core" or a "central processing unit (CPU) core") may be an in-order or out-of-order processor (OoP) and / or may be one of a plurality of processors 102 provided by processor-based device 100. Figure 1In the example of FIG, the processor 102 includes an instruction processing circuit 104 including circuitry for processing instructions fetched from an instruction memory (in Figure 1 Instruction memory 110 may be provided in or as part of system memory in processor-based device 100. An instruction cache may also be provided in processor 102 (e.g., in the example embodiment of the present invention). Figure 1 An instruction memory 110 (labeled “INSTR cache” in FIG. 1 ) 114 is provided to cache instructions 108 fetched from the instruction memory 110 to reduce latency in the fetch circuit 112 .

[0028] Figure 1 The fetch circuitry 112 in the example of FIG is configured to provide the instruction 108 as a fetch instruction 108F to one or more processor pipelines 106(0)-106(P) in the instruction processing circuitry 104 for pre-processing before the fetch instruction 108F reaches the execution circuitry (in FIG). Figure 1 The processor pipeline 106(0)-106(P) across the different processing circuits or stages of the instruction processing circuitry 104 is provided to pre-process and process the fetched instruction 108F in a series of steps that may be performed concurrently to increase throughput before the fetched instruction 108F is executed by the execution circuitry 116.

[0029] Continue to refer Figure 1 , the instruction processing circuitry 104 includes a decode circuitry 120 configured to decode a fetch instruction 108F fetched by the fetch circuitry 112 into a decoded instruction 108D to determine an instruction type and a required action. The instruction type and required action encoded in the decoded instruction 108D may also be used to determine in which processor pipeline 106(0)-106(P) the decoded instruction 108D should be placed. In this example, the decoded instruction 108D is placed in one or more of the processor pipelines 106(0)-106(P) and is then provided to a rename circuitry 122 in the instruction processing circuitry 104. The rename circuitry 122 is configured to determine whether any register names in the decoded instruction 108D should be renamed to decouple any register dependencies that would prevent parallel or out-of-order processing.

[0030] Figure 1 The instruction processing circuit 104 in the processor 102 also includes a register access circuit (in Figure 1The register access circuitry 124 is configured to access physical registers in a physical register file (PRF) (not shown) based on mapping entries of logical registers in a register mapping table (RMT) (not shown) mapped to source register operands of the decoded instruction 108D to retrieve a produced value from the executed instruction 108E in the execution circuitry 116. The register access circuitry 124 is further configured to provide the produced value retrieved from the executed instruction 108E as a source register operand of the decoded instruction 108D to be executed.

[0031] In addition, in the instruction processing circuit 104, the scheduler circuit (in Figure 1 The scheduler circuit 126 (labeled "SCHED circuitry") 126 is provided in the processor pipeline 106(0)-106(P) and is configured to store the decoded instruction 108D in a reserved entry until all source register operands for the decoded instruction 108D are available. The scheduler circuit 126 issues the decoded instruction 108D to the execution circuit 116 to be executed. A write circuit 128 is also provided in the instruction processing circuit 104 to write or commit the resulting value from executing the instruction 108E back to a memory (such as a PRF), cache memory, or system memory.

[0032] like Figure 1 As seen in FIG, the processor-based device 100 also includes a memory system 130 that provides an MMU 132 configured to manage memory accesses. The MMU 132 provides a TLB 134, which is a cache of recently performed translations of virtual addresses to physical addresses (PAs) performed by the MMU 132 for memory pages containing instructions or data to be retrieved. Figure 1 The MMU 132 is also communicatively coupled to a memory controller 136, which is configured to perform memory read and write operations on a system memory 138. As a non-limiting example, in some aspects, the system memory 138 may include double data rate (DDR) synchronous dynamic random access memory (SDRAM).

[0033] Figure 1 The MMU 132 is responsible for performing VA to PA address translation operations to support virtual memory functions of the processor-based device 100. In this regard, according to some aspects, the MMU 132 may include a plurality of hierarchical page tables (not shown) containing page table entries, each of which represents a mapping of a subdivision of an addressable virtual memory space having a particular size (i.e., a memory page). The mappings stored by the page table entries of the hierarchical page tables of the MMU 132 may be cached in a plurality of TLB entries 140(0)-140(B) of the TLB 134, each of which includes a corresponding TLB tag (in Figure 1) 142(0)-142(B) and data elements (in Figure 1 Each of the TLB tags 142(0)-142(B) may include a virtual page address and may also include an ASID (not shown) to enable processor context switching without invalidating the TLB 134, and a VMID (not shown) to enable hypervisor virtual machine (VM) switching without invalidating the TLB 134. Each data element 144(0)-144(B) may include a corresponding PA for the TLB entry 140(0)-140(B). The TLB entries 140(0)-140(B) may also include Figure 1 Additional metadata not shown in , such as validity indicators, global indicators and / or memory properties, such as type and access permissions.

[0034] As described above, TLB 134 may require a significant portion of the physical area of ​​processor 102, a problem that may be exacerbated as the size of data (such as VA, ASID, and VMID) conventionally stored as part of TLB tags 142(0)-142(B) of TLB entries 140(0)-140(B) increases. In this regard, MMU 132 provides a plurality of TLB metadata buffer entries (in Figure 1 TLB metadata buffer 146 (labeled as "TMB entries" in FIG. 1 ). Each of the TLB metadata buffer entries 148 (0) - 148 (T) stores corresponding TLB metadata (in Figure 1 140(0)-140(B) and may be replicated among multiple TLB entries 140(0)-140(B) during execution of a software process by processor 102. Thus, for example, in the following description of Figure 2 In those aspects discussed, the TLB metadata 150(0)-150(T) may include the ASID and VMID of the processor context, as discussed below with respect to Figure 3 Some aspects of those discussed may provide that the TLB metadata 150 ( 0 )- 150 (T) include upper bits of a VA of a memory region used by the processor pipelines 106 ( 0 )- 106 (P) of the processor 102 .

[0035] In exemplary operation, the MMU 132 selects a TLB metadata buffer entry (such as TLB metadata buffer entry 148(0)) for use in accessing the TLB 134 of the processor-based device 100 (based on, for example, a processor context switch or a memory access request from a processor pipeline 106(0)-106(P)). The MMU 132 then stores a pointer to the TLB metadata buffer entry 148(0) (i.e., an index of the TLB metadata buffer entry 148(0) within the TLB metadata buffer 146) as the active TLB metadata pointer (in Figure 1 ACT TLB META PTR) 152. When MMU 132 receives a memory access request (in Figure 1 156) in the TLB 134 as part of an address translation operation. The MMU 132 stores the active TLB metadata pointer 152 as part of the TLB tag 142(0) in place of the TLB metadata 150(0) of the TLB metadata buffer entry 148(0), which would normally be stored as part of the TLB tag 142(0). When the MMU 132 receives another memory access request 158 ​​that includes the VA 156, the MMU 132 may access the TLB entry 140(0) based on the active TLB metadata pointer 152 (e.g., by matching the TLB tag 142(0) of the TLB entry 140(0) using the active TLB metadata pointer 152).

[0036] As discussed above, the processor 102 can concurrently fetch and process instructions in the processor pipelines 106(0)-106(P), which enables multiple processes (not shown) to be executed in parallel by the processor 102. Such processes are assigned an ASID by the operating system (OS) executed by the processor 102 and are also assigned their own set of translation tables for use by the MMU 132 when performing VM to PA translation operations. Upon a processor context switch (i.e., a transfer of execution from a first process to a second process), the processor 102 saves the execution state of the first process and restores the execution state of the second process. As part of the processor context switch, the processor 102 also switches the translation table entries to the translation table entries for the second process. To eliminate the need to flush the conventional TLB for each processor context switch, the conventional TLB stores the ASID of a particular process as part of the TLB tag of each TLB entry, thereby allowing multiple TLB entries for a given memory page used by different processes to exist in the TLB. In a similar manner, when a process is executing within a VM that is itself executing within a hypervisor, the conventional TLB also stores the VMID of the VM as part of the TLB tag of each TLB entry to eliminate the need to flush the TLB on VM switches.

[0037] To compress the size of TLB tags while providing ASIDs and VMIDs for different processes, Figure 1 Some aspects of the MMU 132 provide support for storing TLB metadata including ASID and VMID. In this regard, Figure 2 Shown Figure 1 Exemplary aspects of the MMU 132. Figure 2 As seen in FIG. 1 , MMU 132 includes functions corresponding to Figure 1 The TLB metadata buffer 200 of the TLB metadata buffer 146. The TLB metadata buffer 200 stores data that functionally corresponds to Figure 1 The plurality of TLB metadata buffer entries 202(0)-202(T) of the TLB metadata buffer entries 148(0)-148(T). Figure 2 In the example of , TLB metadata buffer entries 202(0)-202(T) include corresponding validity indicators ( Figure 2 ) 204(0)-204(T) and the corresponding least recently used (LRU) data (in Figure 2 (marked as "LRU") 206(0)-206(T). Figure 2 The TLB metadata buffer entries 202(0)-202(T) in the . Figure 2 ) 208(0)-208(T), these global indicators indicate Figure 1 The associated TLB entries 140(0)-140(B) of the TLB 134 of the processor are used for multiple processes. The TLB metadata buffer entries 202(0)-202(T) also include corresponding TLB metadata 210(0)-210(T), which include ASIDs 212(0)-212(T) and VMIDs 214(0)-214(T). Because different translation mechanisms (e.g., EL2, EL2&0, EL1&0, etc.) can be used during a given processor context, the TLB metadata 210(0)-210(T) also include corresponding translation mechanism indicators (in Figure 2 (marked as "TRANS REG") 216(0)-216(T).

[0038] The MMU 132 also provides an active pointer table 218 that stores a plurality of active pointer table entries 220(0)-220(A). Each of the active pointer table entries 220(0)-220(A) stores a respective active TLB metadata pointer 222(0)-222(A) that functionally corresponds to Figure 1 Active TLB metadata pointer 152 is stored in the active pointer table entries 220(0)-220(A) of the translation mechanism. Each active pointer table entry 220(0)-220(A) is associated with a translation mechanism and stores an active TLB metadata pointer 222(0)-222(A) to be included in the TLB tags 142(0)-142(B) of the TLB entries 140(0)-140(A) corresponding to the translation mechanism. Thus, for example, active pointer table entry 220(0) may be associated with translation mechanism EL1&0 such that active TLB metadata pointer 222(0) is stored as part of the TLB tags 142(0)-142(B) of the TLB entries 140(0)-140(B) corresponding to translation mechanism EL1&0. The active pointer table entries 220(0)-220(A) may also store corresponding global active TLB metadata pointers 224(0)-224(A), which may be used to point to TLB metadata buffer entries 202(0)-202(T) having corresponding global indicators 208(0)-208(T) set.

[0039] In an exemplary operation, Figure 2The MMU 132 detects a processor context switch to a new context 226 associated with an ASID 228 and a VMID 230. To ensure that there are TLB metadata buffer entries 202(0)-202(T) available for the new context 226, the MMU 132 may invalidate one or more least recently used TLB metadata buffer entries 202(0)-202(T) of the TLB metadata buffer 200. The MMU 132 may then determine whether there are one or more TLB metadata buffer entries 202(0)-202(T) that store TLB metadata 210(0)-210(T) that include the ASID 228 and VMID 230 of the new context 226 or store the VMID 230 of the new context 226 and have corresponding global indicators 208(0)-208(T) set. If not, the MMU 132 allocates a TLB metadata buffer entry, such as TLB metadata buffer entry 202(0), stores the ASID 228 and VMID 230 of the new context 226 as the ASID 212(0) and VMID 214(0) of the TLB metadata 210(0) of the TLB metadata buffer entry 202(0), and, in some aspects, sets the global indicator 208(0) appropriately.

[0040] After identifying a TLB metadata buffer entry (such as TLB metadata buffer entry 202(0)) that stores the corresponding TLB metadata 210(0) including the ASID 228 and VMID 230 of the new context 226 (or stores the corresponding TLB metadata 210(0) including the VMID 230 of the new context 226 and has the global indicator 208(0) set), the MMU 132 selects the TLB metadata buffer entry 202(0) for accessing the new context 226. Figure 1 The MMU 132 then stores a pointer to the TLB metadata buffer entry 202(0) in an active pointer table entry, such as active pointer table entry 220(0), that corresponds to the translation mechanism indicated by the translation mechanism indicator 216(0) of the TLB metadata buffer entry 202(0). Figure 2In the example of FIG, if translation mechanism indicator 216(0) indicates that TLB metadata buffer entry 202(0) corresponds to translation mechanism EL1&0 represented by active pointer table entry 220(0), MMU 132 stores a pointer to TLB metadata buffer entry 202(0) as active TLB metadata pointer 222(0) for active pointer table entry 220(0). When MMU 132 subsequently generates a TLB entry in TLB 134 for a memory access request issued during new context 226 under translation mechanism EL1&0, such as TLB entry 140(0), MMU 132 retrieves active TLB metadata pointer 222(0) from active pointer table entry 220(0) corresponding to translation mechanism EL1&0 and stores it as part of TLB tag 142(0) for TLB entry 140(0) in place of ASID 228 and VMID 230. In some aspects, if the global indicator 208(0) of the TLB metadata buffer entry 202(0) is set, the MMU 132 stores a pointer to the TLB metadata buffer entry 202(0) as the global active TLB metadata pointer 224(0) of the active pointer table entry 220(0).

[0041] In order to compress the size of TLB tags and Figure 1 The memory page accessed by the processor pipeline 106(0)-106(P) provides the high bit of VA, Figure 1 Some aspects of the MMU 132 provide support for storing TLB metadata including the upper bits of VA for implementation-specific quantities. In this regard, Figure 3 Illustrated Figure 1 Exemplary aspects of the MMU 132 provide functionality corresponding to Figure 1 The TLB metadata buffer 146 is the TLB metadata buffer 300 . Figure 3 The TLB metadata buffer 300 stores data that functionally corresponds to Figure 1 The plurality of TLB metadata buffer entries 302(0)-302(T) of the TLB metadata buffer entries 148(0)-148(T). Figure 3 The TLB metadata buffer entries 302(0)-302(T) in the example of FIG include corresponding validity indicators (in Figure 3 ) 304(0)-304(T) and the corresponding LRU data (in Figure 3 The TLB metadata buffer entries 302(0)-302(T) also include the corresponding TLB metadata (in Figure 3Each respective TLB metadata includes a plurality of upper VA bits 310 ( 0 )- 310 (T) of the VA of the memory page.

[0042] Figure 3 The MMU 132 also provides an active pointer table 312 that stores a plurality of active pointer table entries 314(0)-314(A), each active pointer table entry storing a pointer that functionally corresponds to Figure 1 The active TLB metadata pointers 152 of the active TLB table entries 316(0)-316(A). The active pointer table entries 314(0)-314(A) also store the corresponding pipeline identifiers (in Figure 3 Each corresponding pipeline identifier (labeled "Pipeline ID") 318(0)-318(A) identifies a processor pipeline among the processor pipelines 106(0)-106(P) associated with the corresponding activity pointer table entry 314(0)-314(A).

[0043] In an exemplary operation, Figure 3 The MMU 132 of the processor-based device 100 receives a memory access request 320 that includes a VA 322 having a plurality of upper VA bits 324 and is associated with one of the processor pipelines 106(0)-106(P), such as processor pipeline 106(0). The MMU 132 may determine whether there is a TLB metadata buffer entry 302(0)-302(T) storing corresponding TLB metadata 308(0)-308(T) including the plurality of upper bits 324 of the VA 322. If not, the MMU 132 may allocate a TLB metadata buffer entry, such as TLB metadata buffer entry 302(0), and store the plurality of upper bits 324 of the VA 322 as the TLB metadata 308(0) of the TLB metadata buffer entry 302(0).

[0044] After locating the TLB metadata buffer entry 302(0) storing the corresponding TLB metadata 308(0) including the upper plurality of bits 324 of the VA 322, the MMU 132 selects the TLB metadata buffer entry 302(0) for accessing Figure 1322 in processor pipeline 106(0) .

[0045] To illustrate some aspects Figure 1 Example operations of the MMU 132 and TLB 134 for compressing TLB tags using the TLB metadata buffer 146, Figure 4 A flow chart illustrating exemplary operation 400 is provided. Figure 4 Time reference Figure 1 Operation 400 begins with the MMU 132 of the processor-based device 100 selecting a TLB metadata buffer (e.g., Figure 1 TLB metadata buffer 146) of a plurality of TLB metadata buffer entries (such as Figure 1 One of the TLB metadata buffer entries 148(0)-148(T)) (e.g., Figure 1 TLB metadata buffer entry 148(0)) for accessing the TLB of the processor-based device 100 (such as Figure 1 134), a plurality of TLB metadata buffer entries 148(0)-148(T) are each configured to store corresponding TLB metadata (e.g., Figure 1 The MMU 132 stores a pointer to the TLB metadata buffer entry 148(0) as the active TLB metadata pointer (e.g., Figure 1 Active TLB metadata pointer 152) (block 404).

[0046] The MMU 132 then receives a message including a first VA such as Figure 1 VA 156) of the first memory access request (e.g., Figure 1In response to receiving the first memory access request 154, the MMU 132 generates a TLB entry for the first VA 156 in the TLB 134 (eg, Figure 1 TLB entry 140(0)), which includes a TLB tag (such as Figure 1 156 (block 408). In some aspects, the MMU 132 receives a second memory access request (e.g., Figure 1 In response to receiving the second memory access request 158, the MMU 132 accesses the TLB entry 140(0) based on the active TLB metadata pointer 152 (e.g., by matching the TLB tag 142(0) of the TLB entry 140(0) using the active TLB metadata pointer 152) (block 412).

[0047] Figures 5A to 5B Provides examples according to some aspects Figure 1 and Figure 2 Flowchart of exemplary operations 500 of the MMU 132 for storing TLB metadata including ASIDs and VMIDs for multiple translation mechanisms in response to a processor context switch. Figure 5A and Figure 5B When cited Figure 1 and Figure 2 It should be understood that Figure 5A and Figure 5B Some of the operations 500 illustrated in FIG. 5 correspond to those described above with respect to Figure 4 Describes the operation. Figure 5A Operations 500 begin when the MMU 132 detects a request to an ASID such as Figure 2 ASID 228) and VMID (e.g. Figure 2 230) associated with a new context (e.g., Figure 2 In some aspects, the MMU 132 may enable the TLB metadata buffer (such as Figure 2 TLB metadata buffer 200) of a plurality of TLB metadata buffer entries (eg, Figure 2In this way, the MMU 132 can ensure in advance that at least one or more least recently used TLB metadata buffer entries will be available for use within the new context 226.

[0048] Some aspects may provide that the MMU 132 determines that there is no corresponding TLB metadata (e.g., Figure 2 In response to determining that there is no TLB metadata buffer entry 202(0)-202(T) in the plurality of TLB metadata buffer entries 202(0)-202(T) that stores corresponding TLB metadata 210(0)-210(T) including the ASID 228 and VMID 230 of the new context 226, the MMU 132 performs a series of operations (block 508). The MMU 132 first allocates a TLB metadata buffer entry (e.g., Figure 2 The MMU 132 then stores the ASID 228 and VMID 230 of the new context 226 as the TLB metadata 210(0) of the TLB metadata buffer entry 202(0) (block 512). Operation 500 then Figure 5B Continue at block 514.

[0049] Now go to Figure 5B , the MMU 132 selects the TLB metadata buffer entry 202(0) storing the corresponding TLB metadata 210(0) including the ASID 228 and VMID 230 of the new context 226 for use in accessing the TLB 134 (block 514). Thus, in some aspects, the operations of block 502 for detecting a processor context switch to the new context 226 and the operations of block 514 for selecting the TLB metadata buffer entry 202(0) storing the corresponding TLB metadata 210(0) including the ASID 228 and VMID 230 of the new context 226 correspond to Figure 4 The MMU 132 then stores a pointer to the TLB metadata buffer entry 202(0) in the plurality of active pointer table entries 220(0)-220(A) of the active pointer table 218 corresponding to the translation mechanism indicator (e.g., Figure 2The active pointer table entry of the conversion mechanism indicated by the conversion mechanism indicator 216(0)) (such as Figure 2 Thus, in some aspects, the operation of block 516 for storing a pointer to the TLB metadata buffer entry 202(0) in the active pointer table entry 220(0) corresponding to the translation mechanism indicated by the translation mechanism indicator 216(0) of the TLB metadata buffer entry 202(0) corresponds to Figure 4 The operation of block 404 is performed.

[0050] In some aspects, the operations of block 516 for storing a pointer to the TLB metadata buffer entry 202(0) in the active pointer table entry 220(0) corresponding to the translation mechanism indicated by the translation mechanism indicator 216(0) of the TLB metadata buffer entry 202(0) may include the MMU 132 determining a global indicator (e.g., Figure 2 In response to determining that the global indicator 208(0) of the TLB metadata buffer entry 202(0) is set, the MMU 132 stores a pointer to the TLB metadata buffer entry 202(0) as the global active TLB metadata pointer (e.g., global active TLB metadata pointer) of the active pointer table entry 220(0). Figure 2 The global active TLB metadata pointer 224(0)) (block 520).

[0051] To illustrate some aspects Figure 1 and 3 Example operation of the MMU 132 for storing TLB metadata including upper bits of VAs for multiple processor pipelines, Figure 6 A flowchart illustrating exemplary operation 600 is provided. For clarity, Figure 6 When cited Figure 1 and Figure 3 It should be understood that Figure 6 Some of the operations 600 illustrated in FIG. 6 correspond to those described above with respect to Figure 4 Describes the operation. Figure 6 Operation 600 in which the MMU 132 receives a second VA (e.g., Figure 3 VA322) of the third memory access request (for example, Figure 3 320) and with multiple processor pipelines of the processor-based device 100 (such as Figure 1 of the processor pipelines 106(0)-106(P)) (e.g., Figure 1According to some aspects, the MMU 132 may determine that the TLB metadata buffer (e.g., Figure 3 There is no storage of the plurality of high bits (eg, Figure 3 The corresponding TLB metadata (such as the high bit 324 of Figure 3 TLB metadata buffer entries (such as TLB metadata 308(0)-308(T)) of Figure 3 In response to determining that there is no TLB metadata buffer entry 302(0)-302(T) in the plurality of TLB metadata buffer entries 302(0)-302(T) that stores corresponding TLB metadata 308(0)-308(T) including the plurality of upper bits 324 of the second VA 322, the MMU 132 performs a series of operations (block 606). The MMU 132 first allocates a TLB metadata buffer entry (e.g., Figure 3 The MMU 132 then stores the upper plurality of bits 324 of the second VA 322 as the TLB metadata 308(0) for the TLB metadata buffer entry 302(0) (block 608).

[0052] The MMU 132 selects the TLB metadata buffer entry 302(0) storing the corresponding TLB metadata 308(0) including the upper plurality of bits 324 of the second VA 322 for use in accessing the TLB (such as Figure 1 Thus, in some aspects, the operation of block 612 for selecting the TLB metadata buffer entry 302(0) storing the corresponding TLB metadata 308(0) including the upper plurality of bits 324 of the second VA 322 corresponds to Figure 4 The MMU 132 then stores a pointer to the TLB metadata buffer entry 302(0) in the active pointer table (e.g., Figure 3 312) of the active pointer table (such as Figure 3 The active pointer table entry corresponding to the processor pipeline 106(0) in the active pointer table entries 314(0)-314(A)) (e.g., Figure 3Thus, in some aspects, the operation of block 614 for storing a pointer to the TLB metadata buffer entry 302(0) in the active pointer table entry 314(0) corresponding to the processor pipeline 106(0) corresponds to Figure 4 The operation of block 404 is performed.

[0053] According to the disclosure herein and reference Figures 1 to 4 、 Figures 5A to 5B and Figure 6 The MMU and TLB of the discussed aspects may be provided in or integrated into any processor-based device. Non-limiting examples include: a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a Session Initiation Protocol (SIP) phone, a tablet computer, a phablet, a server, a computer, a portable computer, a mobile computing device, a laptop computer, a wearable computing device (e.g., a smartwatch, a health or fitness tracker, glasses, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, a motor vehicle, a vehicle component, an avionics system, an unmanned aerial vehicle, and a multirotor aircraft.

[0054] In this regard, Figure 7 An example of a processor-based device 700 is illustrated, which includes Figures 1 to 4 、 Figures 5A to 5B and Figure 6 The MMU and TLB illustrated and described. In this example, the functionality corresponds to Figure 1 The processor-based device 700 of the processor-based device 100 includes a processor 702 including one or more CPUs 704 coupled to a cache memory 706. The CPUs 704 are also coupled to a system bus 708 and can inter-couple devices included in the processor-based device 700. As is well known, the CPUs 704 communicate with these other devices by exchanging address, control, and data information on the system bus 708. For example, the CPUs 704 can communicate bus transaction requests to the memory controller 710. Although not illustrated in FIG. Figure 7 In the embodiment, multiple system buses 708 may be provided, wherein each system bus 708 constitutes a different fabric.

[0055] Other devices may be connected to the system bus 708. Figure 7As shown, as examples, these devices may include a memory system 712, one or more input devices 714, one or more output devices 716, one or more network interface devices 718, and one or more display controllers 720. The input device 714 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output device 716 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. The network interface device 718 may be any device configured to allow data exchange to and from the network 722. The network 722 may be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), Bluetooth TM Network and Internet. The network interface device 718 can be configured to support any type of communication protocol desired. The memory system 712 can include a memory controller 710 coupled to one or more memory arrays 724 and a TLB 728 (e.g., Figure 1 TLB 134) of the MMU 726 (e.g., Figures 1 to 3 MMU 132).

[0056] The CPU 704 may also be configured to access a display controller 720 via the system bus 708 to control information transmitted to one or more displays 730. The display controller 720 transmits information to be displayed to the display 730 via one or more video processors 732, which process the information to be displayed into a format suitable for the display 730. The display 730 may include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, and the like.

[0057] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the various aspects disclosed herein may be implemented as electronic hardware, instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device, or a combination of the two. As an example, the master and slave devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein may be a memory of any type and size and may be configured to store any type of information desired. In order to clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the entire system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be interpreted as resulting in a departure from the scope of this disclosure.

[0058] The various illustrative logical blocks, modules, and circuits described in conjunction with the various aspects disclosed herein may be implemented or executed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0059] The various aspects disclosed herein can be embodied in hardware and in instructions stored in hardware and can reside, for example, in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from and write information to the storage medium. In an alternative embodiment, the storage medium can be integral to the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. In an alternative embodiment, the processor and storage medium can reside as discrete components in a remote station, a base station, or a server.

[0060] It should also be noted that the operational steps described in any one of the exemplary aspects herein are described to provide examples and discussion. The described operations can be performed in a variety of different sequences in addition to the illustrated sequence. In addition, the operations described in a single operational step can actually be performed in many different steps. Additionally, one or more operational steps discussed in the exemplary aspects can be combined. It will be apparent to those skilled in the art that the operational steps illustrated in the flow charts may be subject to many different modifications. Those skilled in the art will also understand that any one of a variety of different technologies and methods can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0061] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Therefore, the disclosure is not intended to limit the disclosure to the examples and designs described herein, but is intended to accord the disclosure the widest scope consistent with the principles and novel features disclosed herein.

[0062] Specific implementation examples are described in the following numbered clauses:

[0063] 1. A processor-based device, comprising:

[0064] a translation lookaside buffer (TLB), the translation lookaside buffer (TLB) comprising a plurality of TLB entries;

[0065] A TLB metadata buffer, the TLB metadata buffer comprising a plurality of TLB metadata buffer entries, each TLB metadata buffer entry being configured to store corresponding TLB metadata; and

[0066] a memory management unit (MMU), the memory management unit (MMU) being configured to:

[0067] Selecting a TLB metadata buffer entry from the plurality of TLB metadata buffer entries for use in accessing the TLB;

[0068] storing a pointer to the TLB metadata buffer entry as an active TLB metadata pointer;

[0069] receiving a first memory access request including a first virtual address (VA); and

[0070] A TLB entry is generated in the TLB for the first VA in response to receiving the first memory access request, the TLB entry including a TLB tag that stores the active TLB metadata pointer in place of the TLB metadata of the TLB metadata buffer entry.

[0071] 2. The processor-based device of clause 1, wherein the MMU is further configured to:

[0072] receiving a second memory access request including the first VA; and

[0073] In response to receiving the second memory access request, the TLB entry is accessed based on the active TLB metadata pointer.

[0074] 3. A processor-based device according to any of clauses 1 to 2, wherein:

[0075] Each TLB metadata buffer entry of the plurality of TLB metadata buffer entries is configured to store the corresponding TLB metadata including an application space identifier (ASID) and a virtual machine identifier (VMID) of a processor context; and

[0076] The MMU is configured to select the TLB metadata buffer entry from among the plurality of TLB metadata buffer entries for accessing the TLB by being configured to:

[0077] detecting a processor context switch to a new context associated with the ASID and VMID; and

[0078] The TLB metadata buffer entry storing the corresponding TLB metadata including the A SID and the VMID of the new context is selected for accessing the TLB.

[0079] 4. The processor-based device of clause 3, wherein the MMU is further configured to: before selecting the TLB metadata buffer entry for storing the ASID and the VMID of the new context as the corresponding TLB metadata for accessing the TLB:

[0080] determining that there is no TLB metadata buffer entry storing corresponding TLB metadata including the ASID and the VMID of the new context among the plurality of TLB metadata buffer entries; and

[0081] In response to determining that there is no TLB metadata buffer entry storing corresponding TLB metadata including the ASID and the VMID of the new context among the plurality of TLB metadata buffer entries:

[0082] allocating the TLB metadata buffer entry; and

[0083] The ASID and the VMID of the new context are stored as the TLB metadata of the TLB metadata buffer entry.

[0084] 5. A processor-based device according to any of clauses 3 to 4, wherein:

[0085] The MMU further includes an active pointer table, the active pointer table including a plurality of active pointer table entries, each active pointer table entry associating an active TLB metadata pointer with a corresponding translation mechanism;

[0086] Each TLB metadata buffer entry of the plurality of TLB metadata buffer entries is configured to store the corresponding TLB metadata further including a translation mechanism indicator; and

[0087] The MMU is configured to store the pointer to the TLB metadata buffer entry as the active TLB metadata pointer by being configured to store the pointer to the TLB metadata buffer entry in an active pointer table entry corresponding to the translation mechanism indicated by the translation mechanism indicator of the TLB metadata buffer entry among the multiple active pointer table entries of the active pointer table.

[0088] 6. A processor-based device according to clause 5, wherein:

[0089] Each TLB metadata buffer entry of the plurality of TLB metadata buffer entries is configured to store the corresponding TLB metadata further including a global indicator;

[0090] Each active pointer table entry of the plurality of active pointer table entries further includes a global active TLB metadata pointer; and

[0091] The MMU is configured to store the pointer to the TLB metadata buffer entry in the active pointer table entry corresponding to the translation mechanism indicated by the translation mechanism indicator of the TLB metadata buffer entry by being configured to:

[0092] determining that the global indicator of the TLB metadata buffer entry is set; and

[0093] In response to determining that the global indicator for the TLB metadata buffer entry is set, storing the pointer to the TLB metadata buffer entry as the global active TLB metadata pointer of the active pointer table entry. 7. A processor-based device according to any of clauses 3 to 6, wherein the MMU is further configured to, upon detecting the processor context switch to the new context associated with the ASID and the VMID, invalidate one or more least recently used TLB metadata buffer entries of the plurality of TLB metadata buffer entries.

[0094] 8. A processor-based device according to any of clauses 1 to 2, wherein:

[0095] Each TLB metadata buffer entry of the plurality of TLB metadata buffer entries is configured to store the corresponding TLB metadata including a plurality of upper bits of a VA;

[0096] The MMU further includes an active pointer table including a plurality of active pointer table entries, each active pointer table entry associating an active TLB metadata pointer with a corresponding processor pipeline of the plurality of processor pipelines;

[0097] The MMU is configured to select the TLB metadata buffer entry from among the plurality of TLB metadata buffer entries for accessing the TLB by being configured to:

[0098] receiving a third memory access request including a second VA and associated with one of a plurality of processor pipelines of the processor-based device; and

[0099] selecting the TLB metadata buffer entry storing the corresponding TLB metadata including the upper plurality of bits of the second VA for use in accessing the TLB; and

[0100] The MMU is configured to store the pointer to the TLB metadata buffer entry as the active TLB metadata pointer by being configured to store the pointer to the TLB metadata buffer entry in an active pointer table entry corresponding to a processor pipeline among the plurality of active pointer table entries of the active pointer table.

[0101] 9. The processor-based device of clause 8, wherein the MMU is further configured to: before selecting the TLB metadata buffer entry storing the corresponding TLB metadata including the plurality of upper bits of the second VA for accessing the TLB:

[0102] determining that no TLB metadata buffer entry among the plurality of TLB metadata buffer entries stores corresponding TLB metadata including the plurality of upper bits of the second VA; and

[0103] In response to determining that there is no TLB metadata buffer entry storing corresponding TLB metadata including the plurality of upper bits of the second VA among the plurality of TLB metadata buffer entries:

[0104] allocating the TLB metadata buffer entry; and

[0105] The plurality of upper bits of the second VA are stored as the TLB metadata of the TLB metadata buffer entry.

[0106] 10. A processor-based device according to any one of clauses 1 to 9, wherein the processor-based device is integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet computer; a tablet phone; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; an unmanned aerial vehicle; and a multirotor aircraft.

[0107] 11. A processor-based device, comprising:

[0108] means for selecting one of a plurality of translation lookaside buffer (TLB) metadata buffer entries of a TLB metadata buffer for use in accessing the TLB of the processor-based device, the plurality of TLB metadata buffer entries each configured to store corresponding TLB metadata;

[0109] means for storing a pointer to said TLB metadata buffer entry as an active TLB metadata pointer;

[0110] means for receiving a first memory access request comprising a first virtual address (VA); and

[0111] means for generating a TLB entry in the TLB for the first VA in response to receiving the first memory access request, the TLB entry comprising a TLB tag storing the active TLB metadata pointer in place of the TLB metadata of the TLB metadata buffer entry.

[0112] 12. A method for compressing translation lookaside buffer (TLB) tags using a TLB metadata buffer, the method comprising:

[0113] selecting, by a memory management unit (MMU) of a processor-based device, one of a plurality of TLB metadata buffer entries in a TLB metadata buffer for use in accessing a TLB of the processor-based device, the plurality of TLB metadata buffer entries each configured to store corresponding TLB metadata;

[0114] storing, by the MMU, a pointer to the TLB metadata buffer entry as an active TLB metadata pointer;

[0115] receiving, by the MMU, a first memory access request including a first virtual address (VA); and

[0116] In response to receiving the first memory access request, the MMU generates a TLB entry in the TLB for the first VA, the TLB entry including a TLB tag that stores the active TLB metadata pointer in place of the TLB metadata of the TLB metadata buffer entry.

[0117] 13. The method according to clause 12, further comprising:

[0118] receiving, by the MMU, a second memory access request including the first VA; and

[0119] In response to receiving the second memory access request, the TLB entry is accessed by the MMU based on the active TLB metadata pointer.

[0120] 14. A method according to any one of clauses 12 to 13, wherein:

[0121] Each TLB metadata buffer entry of the plurality of TLB metadata buffer entries is configured to store the corresponding TLB metadata including an application space identifier (ASID) and a virtual machine identifier (VMID) of a processor context; and

[0122] Selecting the TLB metadata buffer entry among the plurality of TLB metadata buffer entries for accessing the TLB comprises:

[0123] detecting, by the MMU, a processor context switch to a new context associated with the ASID and VMID; and

[0124] The TLB metadata buffer entry storing the corresponding TLB metadata including the ASID and the VMID of the new context is selected by the MMU for accessing the TLB.

[0125] 15. The method of clause 14, further comprising, before selecting the TLB metadata buffer entry for storing the ASID and the VMID of the new context as the corresponding TLB metadata for accessing the TLB:

[0126] determining, by the MMU, that no TLB metadata buffer entry storing corresponding TLB metadata including the ASID and the VMID of the new context exists among the plurality of TLB metadata buffer entries; and

[0127] In response to determining that there is no TLB metadata buffer entry storing corresponding TLB metadata including the ASID and the VMID of the new context among the plurality of TLB metadata buffer entries:

[0128] allocating, by the MMU, the TLB metadata buffer entry; and

[0129] The ASID and the VMID of the new context are stored by the MMU as the TLB metadata of the TLB metadata buffer entry.

[0130] 16. A method according to any one of clauses 14 to 15, wherein:

[0131] The MMU further includes an active pointer table, the active pointer table including a plurality of active pointer table entries, each active pointer table entry associating an active TLB metadata pointer with a corresponding translation mechanism;

[0132] Each TLB metadata buffer entry of the plurality of TLB metadata buffer entries is configured to store the corresponding TLB metadata further including a translation mechanism indicator; and

[0133] Storing the pointer to the TLB metadata buffer entry as the active TLB metadata pointer includes storing, by the MMU, the pointer to the TLB metadata buffer entry in an active pointer table entry of the multiple active pointer table entries of the active pointer table corresponding to the translation mechanism indicated by the translation mechanism indicator of the TLB metadata buffer entry.

[0134] 17. The method according to clause 16, wherein:

[0135] Each TLB metadata buffer entry of the plurality of TLB metadata buffer entries is configured to store the corresponding TLB metadata further corresponding to a global indicator;

[0136] Each active pointer table entry of the plurality of active pointer table entries further includes a global active TLB metadata pointer; and

[0137] Storing the pointer to the TLB metadata buffer entry in the active pointer table entry corresponding to the translation mechanism indicated by the translation mechanism indicator of the TLB metadata buffer entry comprises:

[0138] determining, by the MMU, that the global indicator of the TLB metadata buffer entry is set; and

[0139] In response to determining that the global indicator of the TLB metadata buffer entry is set, the pointer to the TLB metadata buffer entry is stored by the MMU as the global active TLB metadata pointer of the active pointer table entry.

[0140] 18. A method according to any one of clauses 12 to 13, wherein:

[0141] Each TLB metadata buffer entry of the plurality of TLB metadata buffer entries is configured to store the corresponding TLB metadata including a plurality of upper bits of VA;

[0142] The MMU further includes an active pointer table including a plurality of active pointer table entries, each active pointer table entry associating an active TLB metadata pointer with a corresponding processor pipeline of the plurality of processor pipelines;

[0143] Selecting the TLB metadata buffer entry among the plurality of TLB metadata buffer entries for accessing the TLB comprises:

[0144] receiving, by the MMU, a third memory access request including a second VA and associated with one of a plurality of processor pipelines of the processor-based device; and

[0145] selecting, by the MMU, the TLB metadata buffer entry storing the corresponding TLB metadata including a plurality of upper bits of the second VA for use in accessing the TLB; and

[0146] Storing the pointer to the TLB metadata buffer entry as the active TLB metadata pointer includes storing, by the MMU, the pointer to the TLB metadata buffer entry in an active pointer table entry corresponding to the processor pipeline among the plurality of active pointer table entries of the active pointer table.

[0147] 19. The method of clause 18, further comprising, before selecting the TLB metadata buffer entry storing the corresponding TLB metadata including the plurality of upper bits of the second VA for accessing the TLB:

[0148] determining, by the MMU, that no TLB metadata buffer entry among the plurality of TLB metadata buffer entries stores corresponding TLB metadata including the plurality of upper bits of the second VA; and

[0149] In response to determining that there is no TLB metadata buffer entry storing corresponding TLB metadata including the plurality of upper bits of the second VA among the plurality of TLB metadata buffer entries:

[0150] allocating, by the MMU, the TLB metadata buffer entry; and

[0151] The plurality of upper bits of the second VA are stored by the MMU as the TLB metadata of the TLB metadata buffer entry.

[0152] 20. A non-transitory computer-readable medium having stored thereon computer-executable instructions that, when executed, cause a processor of a processor-based device to:

[0153] selecting a translation lookaside buffer (TLB) metadata buffer entry of a plurality of TLB metadata buffer entries for use in accessing the TLB of the processor-based device, the plurality of TLB metadata buffer entries each configured to store corresponding TLB metadata;

[0154] storing a pointer to the TLB metadata buffer entry as an active TLB metadata pointer;

[0155] Receiving a first memory access request including a first virtual address (VA); and generating a TLB entry for the first VA in the TLB in response to receiving the first memory access request, the TLB entry including a TLB tag, the TLB tag storing the active TLB metadata pointer in place of the TLB metadata of the TLB metadata buffer entry.

Claims

1. A processor-based device, comprising: a translation lookaside buffer (TLB), the translation lookaside buffer (TLB) comprising a plurality of TLB entries; A TLB metadata buffer, the TLB metadata buffer comprising a plurality of TLB metadata buffer entries, each TLB metadata buffer entry being configured to store corresponding TLB metadata; and a memory management unit (MMU), the memory management unit (MMU) being configured to: Selecting a TLB metadata buffer entry from the plurality of TLB metadata buffer entries for use in accessing the TLB; storing a pointer to the TLB metadata buffer entry as an active TLB metadata pointer; receiving a first memory access request including a first virtual address (VA); and A TLB entry is generated in the TLB for the first VA in response to receiving the first memory access request, the TLB entry including a TLB tag that stores the active TLB metadata pointer in place of the TLB metadata of the TLB metadata buffer entry.

2. The processor-based device of claim 1 , wherein the MMU is further configured to: receiving a second memory access request including the first VA; and In response to receiving the second memory access request, the TLB entry is accessed based on the active TLB metadata pointer.

3. The processor-based device of claim 1 , wherein: Each TLB metadata buffer entry of the plurality of TLB metadata buffer entries is configured to store the corresponding TLB metadata including an application space identifier (ASID) and a virtual machine identifier (VMID) of a processor context; and The MMU is configured to select the TLB metadata buffer entry from among the plurality of TLB metadata buffer entries for accessing the TLB by being configured to: Detecting a processor context switch to a new context associated with an ASID and VMID; as well as The TLB metadata buffer entry storing the corresponding TLB metadata including the ASID and the VMID of the new context is selected for accessing the TLB.

4. The processor-based device of claim 3 , wherein the MMU is further configured to: before selecting the TLB metadata buffer entry in which the ASID and the VMID of the new context are stored as the corresponding TLB metadata for accessing the TLB: determining that there is no TLB metadata buffer entry storing corresponding TLB metadata including the ASID and the VMID of the new context among the plurality of TLB metadata buffer entries; and In response to determining that there is no TLB metadata buffer entry storing corresponding TLB metadata including the ASID and the VMID of the new context among the plurality of TLB metadata buffer entries: allocating the TLB metadata buffer entry; and The ASID and the VMID of the new context are stored as the TLB metadata of the TLB metadata buffer entry.

5. The processor-based device of claim 3 , wherein: The MMU further includes an active pointer table, the active pointer table including a plurality of active pointer table entries, each active pointer table entry associating an active TLB metadata pointer with a corresponding translation mechanism; Each TLB metadata buffer entry of the plurality of TLB metadata buffer entries is configured to store the corresponding TLB metadata further including a translation mechanism indicator; and The MMU is configured to store the pointer to the TLB metadata buffer entry as the active TLB metadata pointer by being configured to store the pointer to the TLB metadata buffer entry in an active pointer table entry corresponding to the translation mechanism indicated by the translation mechanism indicator of the TLB metadata buffer entry among the multiple active pointer table entries of the active pointer table.

6. The processor-based device of claim 5, wherein: Each TLB metadata buffer entry of the plurality of TLB metadata buffer entries is configured to store the corresponding TLB metadata further including a global indicator; Each active pointer table entry of the plurality of active pointer table entries further includes a global active TLB metadata pointer; and The MMU is configured to store the pointer to the TLB metadata buffer entry in the active pointer table entry corresponding to the translation mechanism indicated by the translation mechanism indicator of the TLB metadata buffer entry by being configured to: determining that the global indicator of the TLB metadata buffer entry is set; and In response to determining that the global indicator of the TLB metadata buffer entry is set, the pointer to the TLB metadata buffer entry is stored as the global active TLB metadata pointer of the active pointer table entry.

7. The processor-based device of claim 3 , wherein the MMU is further configured to, upon detecting the processor context switch to the new context associated with the ASID and the VMID, invalidate one or more least recently used TLB metadata buffer entries of the plurality of TLB metadata buffer entries.

8. The processor-based device of claim 1 , wherein: Each TLB metadata buffer entry of the plurality of TLB metadata buffer entries is configured to store the corresponding TLB metadata including a plurality of upper bits of a VA; The MMU further includes an active pointer table comprising a plurality of active pointer table entries, each active pointer table entry associating an active TLB metadata pointer with a corresponding processor pipeline of the plurality of processor pipelines; The MMU is configured to select the TLB metadata buffer entry from among the plurality of TLB metadata buffer entries for accessing the TLB by being configured to: receiving a third memory access request including a second VA and associated with one of a plurality of processor pipelines of the processor-based device; as well as The TLB metadata buffer entry storing the corresponding TLB metadata including multiple high bits of the second VA is selected for accessing the TLB; and the MMU is configured to store the pointer to the TLB metadata buffer entry as the active TLB metadata pointer by being configured to store the pointer to the TLB metadata buffer entry in an active pointer table entry corresponding to a processor pipeline among the multiple active pointer table entries of the active pointer table.

9. The processor-based device of claim 8 , wherein the MMU is further configured to: before selecting the TLB metadata buffer entry storing the corresponding TLB metadata including the plurality of upper bits of the second VA for accessing the TLB: determining that no TLB metadata buffer entry among the plurality of TLB metadata buffer entries stores corresponding TLB metadata including the plurality of upper bits of the second VA; and In response to determining that there is no TLB metadata buffer entry storing corresponding TLB metadata including the plurality of upper bits of the second VA among the plurality of TLB metadata buffer entries: allocating the TLB metadata buffer entry; and The plurality of upper bits of the second VA are stored as the TLB metadata of the TLB metadata buffer entry.

10. The processor-based device of claim 1 , wherein the processor-based device is integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a Session Initiation Protocol (SIP) phone; a tablet computer; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; Satellite radio; Music player; Digital music player; Portable music player; Digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; drones; and multirotors.

11. A processor-based device, comprising: means for selecting one of a plurality of translation lookaside buffer (TLB) metadata buffer entries of a TLB metadata buffer for use in accessing the TLB of the processor-based device, the plurality of TLB metadata buffer entries each configured to store corresponding TLB metadata; means for storing a pointer to said TLB metadata buffer entry as an active TLB metadata pointer; means for receiving a first memory access request comprising a first virtual address (VA); and means for generating a TLB entry in the TLB for the first VA in response to receiving the first memory access request, the TLB entry comprising a TLB tag storing the active TLB metadata pointer in place of the TLB metadata of the TLB metadata buffer entry.

12. A method for compressing translation lookaside buffer (TLB) tags using a TLB metadata buffer, the method comprising: selecting, by a memory management unit (MMU) of a processor-based device, one of a plurality of TLB metadata buffer entries in a TLB metadata buffer for use in accessing a TLB of the processor-based device, the plurality of TLB metadata buffer entries each configured to store corresponding TLB metadata; storing, by the MMU, a pointer to the TLB metadata buffer entry as an active TLB metadata pointer; receiving, by the MMU, a first memory access request including a first virtual address (VA); and In response to receiving the first memory access request, the MMU generates a TLB entry in the TLB for the first VA, the TLB entry including a TLB tag that stores the active TLB metadata pointer in place of the TLB metadata of the TLB metadata buffer entry.

13. The method according to claim 12, further comprising: receiving, by the MMU, a second memory access request including the first VA; as well as In response to receiving the second memory access request, the TLB entry is accessed by the MMU based on the active TLB metadata pointer.

14. The method according to claim 12, wherein: Each TLB metadata buffer entry of the plurality of TLB metadata buffer entries is configured to store the corresponding TLB metadata including an application space identifier (ASID) and a virtual machine identifier (VMID) of a processor context; and Selecting the TLB metadata buffer entry among the plurality of TLB metadata buffer entries for accessing the TLB comprises: detecting, by the MMU, a processor context switch to a new context associated with the ASID and VMID; as well as The TLB metadata buffer entry storing the corresponding TLB metadata including the ASID and the VMID of the new context is selected by the MMU for accessing the TLB.

15. The method according to claim 14, further comprising: Prior to selecting the TLB metadata buffer entry storing the ASID and the VMID of the new context as the corresponding TLB metadata for accessing the TLB: Determining, by the MMU, that no TLB metadata buffer entry storing corresponding TLB metadata including the ASID and the VMID of the new context exists among the plurality of TLB metadata buffer entries; as well as In response to determining that there is no TLB metadata buffer entry storing corresponding TLB metadata including the ASID and the VMID of the new context among the plurality of TLB metadata buffer entries: Allocating the TLB metadata buffer entry by the MMU; as well as The ASID and the VMID of the new context are stored by the MMU as the TLB metadata of the TLB metadata buffer entry.

16. The method of claim 14, wherein: The MMU further includes an active pointer table, the active pointer table including a plurality of active pointer table entries, each active pointer table entry associating an active TLB metadata pointer with a corresponding translation mechanism; Each TLB metadata buffer entry of the plurality of TLB metadata buffer entries is configured to store the corresponding TLB metadata further including a translation mechanism indicator; and Storing the pointer to the TLB metadata buffer entry as the active TLB metadata pointer includes storing, by the MMU, the pointer to the TLB metadata buffer entry in an active pointer table entry of the multiple active pointer table entries of the active pointer table corresponding to the translation mechanism indicated by the translation mechanism indicator of the TLB metadata buffer entry.

17. The method according to claim 16, wherein: Each of the plurality of TLB metadata buffer entries is configured to store the corresponding TLB metadata further corresponding to a global indicator; each of the plurality of active pointer table entries further comprising a global active TLB metadata pointer; and Storing the pointer to the TLB metadata buffer entry in the active pointer table entry corresponding to the translation mechanism indicated by the translation mechanism indicator of the TLB metadata buffer entry comprises: determining, by the MMU, that the global indicator of the TLB metadata buffer entry is set; as well as In response to determining that the global indicator of the TLB metadata buffer entry is set, the pointer to the TLB metadata buffer entry is stored by the MMU as the global active TLB metadata pointer of the active pointer table entry.

18. The method of claim 12, wherein: Each TLB metadata buffer entry of the plurality of TLB metadata buffer entries is configured to store the corresponding TLB metadata including a plurality of upper bits of a VA; The MMU further includes an active pointer table comprising a plurality of active pointer table entries, each active pointer table entry associating an active TLB metadata pointer with a corresponding processor pipeline of the plurality of processor pipelines; Selecting the TLB metadata buffer entry among the plurality of TLB metadata buffer entries for accessing the TLB comprises: receiving, by the MMU, a third memory access request including a second VA and associated with one of a plurality of processor pipelines of the processor-based device; and selecting, by the MMU, the TLB metadata buffer entry storing the corresponding TLB metadata including a plurality of upper bits of the second VA for use in accessing the TLB; and Storing the pointer to the TLB metadata buffer entry as the active TLB metadata pointer includes storing, by the MMU, the pointer to the TLB metadata buffer entry in an active pointer table entry corresponding to the processor pipeline among the plurality of active pointer table entries of the active pointer table.

19. The method according to claim 18, further comprising: Before selecting the TLB metadata buffer entry storing the corresponding TLB metadata including the plurality of upper bits of the second VA for accessing the TLB: determining, by the MMU, that no TLB metadata buffer entry among the plurality of TLB metadata buffer entries stores corresponding TLB metadata including the plurality of upper bits of the second VA; and In response to determining that there is no TLB metadata buffer entry storing corresponding TLB metadata including the plurality of upper bits of the second VA among the plurality of TLB metadata buffer entries: allocating, by the MMU, the TLB metadata buffer entry; and The plurality of upper bits of the second VA are stored by the MMU as the TLB metadata of the TLB metadata buffer entry.

20. A non-transitory computer-readable medium having stored thereon computer-executable instructions that, when executed, cause a processor of a processor-based device to: selecting a translation lookaside buffer (TLB) metadata buffer entry of a plurality of TLB metadata buffer entries for use in accessing the TLB of the processor-based device, the plurality of TLB metadata buffer entries each configured to store corresponding TLB metadata; storing a pointer to the TLB metadata buffer entry as an active TLB metadata pointer; receiving a first memory access request including a first virtual address (VA); and A TLB entry is generated in the TLB for the first VA in response to receiving the first memory access request, the TLB entry including a TLB tag that stores the active TLB metadata pointer in place of the TLB metadata of the TLB metadata buffer entry.

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