Backside power delivery network

Abstract

An assembly may include a reconstitution element having a front surface and a back surface, the reconstitution element including: a semiconductor die having a front surface and a back surface, the semiconductor die including a circuit device closer to the front surface than to the back surface, and a via extending from the back surface of the semiconductor die to connect to the circuit device; an insulating material disposed along a side surface of the semiconductor die; a power rail extending from the front surface to the back surface of the reconstitution element and configured to deliver power to the semiconductor die; and an interconnect structure configured to electrically connect the power rail to the via and deliver power from the back side of the semiconductor die to the semiconductor die.

Description

[0001] Incorporation by reference into any priority application

[0002] Any and all applications claiming foreign or domestic priority identified in the Application Data Sheet filed with this application are incorporated herein by reference pursuant to 37 CFR 1.57.

[0003] This application claims the benefit of U.S. Provisional Application No. 63 / 385,754, filed December 1, 2022, the entire contents of which are incorporated herein by reference and for all purposes. Technical Field

[0004] The present disclosure relates to semiconductor device structures. Some embodiments relate to backside power delivery. Background Art

[0005] The approaches described in this section are approaches that could be pursued, but not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualifies as prior art merely by virtue of their inclusion in this section.

[0006] As features in semiconductor devices continue to shrink, power delivery becomes a growing concern because electrical isolation issues, feature size limitations, and losses caused by traversing numerous metal layers make it difficult to efficiently deliver power to semiconductor devices. Backside power delivery can provide relief by separating power delivery from signal routing. However, backside power delivery presents several challenges and can significantly complicate the manufacturing process. Summary of the Invention

[0007] The systems, methods, and devices described herein each have several aspects, no single one of which is solely responsible for its desirable attributes.Without limiting the scope of this disclosure, several non-limiting features will now be briefly described.

[0008] In some aspects, the technology described herein relates to an assembly comprising: a reconstruction element having a front surface and a back surface, the reconstruction element comprising: a semiconductor die having a front surface and a back surface, the semiconductor die including a circuit device closer to the front surface than to the back surface and a via extending from the back surface of the semiconductor die to connect to the circuit device; an insulating material disposed along a side surface of the semiconductor die; a power rail extending from the front surface to the back surface of the reconstruction element and configured to deliver power to the semiconductor die; and an interconnect structure configured to electrically connect the power rail to the via and deliver power from the back surface of the semiconductor die to the semiconductor die.

[0009] In some aspects, the technology described herein relates to a component in which the insulating material includes an inorganic dielectric.

[0010] In some aspects, the technology described herein relates to a component in which the insulating material includes silicon oxide.

[0011] In some aspects, the technology described herein relates to a component in which the insulating material includes an organic dielectric.

[0012] In some aspects, the technology described herein relates to an assembly in which an interconnect structure includes a redistribution layer disposed on a back surface of a reconstruction element.

[0013] In some aspects, the technology described herein relates to an assembly in which an interconnect structure includes an interconnect element hybrid-bonded to a backside of a semiconductor die.

[0014] In some aspects, the technology described herein relates to an assembly in which an interconnect structure includes one or more metallization layers.

[0015] In some aspects, the technology described herein relates to an assembly that also includes a power delivery die, where the power delivery die is hybrid bonded to a back surface of a reconstruction element.

[0016] In some aspects, the technology described herein relates to an assembly in which a power delivery die includes a redistribution layer.

[0017] In some aspects, the techniques described herein relate to an assembly in which the reconstruction element further includes an integrated voltage regulator.

[0018] In some aspects, the technology described herein relates to an assembly that also includes a dummy die, where the dummy die is directly bonded to a back surface of a reconstruction element.

[0019] In some aspects, the techniques described herein relate to an assembly that further includes a second reconstruction element comprising: an integrated voltage regulator; and an integrated power delivery circuitry, wherein the second reconstruction element is hybrid-joined to the reconstruction element.

[0020] In some aspects, the techniques described herein relate to an assembly that also includes a dummy die directly bonded to the second reconstruction element.

[0021] In some aspects, the technology described herein relates to an assembly that also includes a stack, where the stack includes a dummy die directly bonded to a second reconstruction element.

[0022] In some aspects, the techniques described herein relate to an assembly that also includes an integrated voltage regulator element hybrid-bonded to a reconstruction element.

[0023] In some aspects, the technology described herein relates to an assembly wherein the reconstruction element further comprises a dummy semiconductor element, wherein the power rail is provided in the dummy semiconductor element.

[0024] In some aspects, the techniques described herein relate to an assembly wherein the reconstruction element further includes an integrated voltage regulator, wherein the assembly further includes a power delivery die including one or more memory banks.

[0025] In some aspects, the technology described herein relates to an assembly that also includes an optical input / output system coupled to a front surface of a reconstruction element.

[0026] In some aspects, the techniques described herein relate to an assembly further comprising: a second reconfiguration element hybrid-joined to the reconfiguration element, wherein the second reconfiguration element comprises: an integrated power delivery circuit device; one or more memory banks; and one or more integrated voltage regulators.

[0027] In some aspects, the technology described herein relates to an assembly in which a circuit device includes one or more transistors.

[0028] In some aspects, the technology described herein relates to an assembly in which the semiconductor die has a thickness of less than 5 μm.

[0029] In some aspects, the technology described herein relates to an assembly in which the semiconductor die has a thickness of less than 1 μm.

[0030] In some aspects, the technology described herein relates to an assembly in which the semiconductor die is a logic die or a processor die.

[0031] In some aspects, the technology described herein relates to an assembly comprising: an insulating material; a power rail extending through the insulating material; an integrated device die at least partially embedded in the insulating material, the integrated device die having a front side and a back side, the integrated device die including a circuit arrangement closer to the front side than to the back side and a power delivery structure extending from the back side of the integrated device die to connect to the circuit arrangement; and an interconnect structure over the insulating material, the power rail, and the back side of the integrated device die, the interconnect structure configured to deliver power between the power rail and the power delivery structure at the back side of the integrated device die.

[0032] In some aspects, the technology described herein relates to a component in which the insulating material includes an inorganic dielectric material.

[0033] In some aspects, the technology described herein relates to an assembly that also includes a power delivery die hybrid-bonded to an interconnect structure.

[0034] In some aspects, the technology described herein relates to an assembly that also includes a dummy die, where the dummy die is directly bonded to the interconnect structure.

[0035] In some aspects, the technology described herein relates to a method for forming a bonding structure with backside power delivery, the method comprising: forming a bonding surface on a backside surface of a reconstruction element, the reconstruction element having a front surface and a backside surface, wherein the reconstruction element comprises: a semiconductor die having a front side and a backside, the die including a circuit device closer to the front side than to the backside and a via extending from the backside of the die to connect to the circuit device; an insulating material disposed along a side surface of the semiconductor die; a power rail extending from the front side to the backside of the reconstruction element and configured to deliver power to the semiconductor die; and an interconnect structure configured to electrically connect the power rail to the via and deliver power to the semiconductor die from the backside of the semiconductor die; and directly bonding a second element to the bonding surface of the reconstruction element.

[0036] In some aspects, the technology described herein relates to a method wherein the second component includes an integrated voltage regulator. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] These and other features, aspects and advantages of the present disclosure are described with reference to the accompanying drawings of certain embodiments, which are intended to illustrate rather than limit the present disclosure. It should be understood that the drawings, which are incorporated into and constitute a part of this specification, are for the purpose of illustrating the concepts disclosed herein and may not be drawn to scale.

[0038] Figure 1A Illustrated is a side view of an example device according to some embodiments.

[0039] Figure 1B A rear view of an example device is illustrated in accordance with some embodiments.

[0040] Figure 1C Illustrated is a side view of an example device including dummy silicon, in accordance with some embodiments.

[0041] Figure 2 An example device including a power delivery die is illustrated in accordance with some embodiments.

[0042] Figure 3 An example device including a dummy die is illustrated in accordance with some embodiments.

[0043] Figure 4 An example device including a reconstructed power delivery layer and a dummy die is illustrated in accordance with some embodiments.

[0044] Figure 5An example device including a power delivery layer and a dummy die is illustrated in accordance with some embodiments.

[0045] Figure 6 An example device including a memory layer is illustrated in accordance with some embodiments.

[0046] Figure 7 An example device including a reconstructed power delivery layer including memory banks and a dummy die is illustrated in accordance with some embodiments.

[0047] Figure 8 is a flow chart illustrating an example process for fabricating a component including back side power, according to some embodiments.

[0048] Figure 9A and Figure 9B A direct bonding process according to some embodiments is schematically illustrated. DETAILED DESCRIPTION

[0049] Although several embodiments, examples and descriptions are disclosed below, it will be understood by those skilled in the art that the invention described herein goes beyond the specifically disclosed embodiments, examples and descriptions and includes other uses of the invention and obvious modifications and equivalents thereof. Embodiments of the invention are described with reference to the accompanying drawings, in which like reference numerals refer to like elements throughout. The terminology used in the description given herein is not intended to be construed in any limited or restrictive manner, merely as it is used in conjunction with the detailed description of some specific embodiments of the invention. Furthermore, embodiments of the invention may include several novel features, and no single feature is solely responsible for its desired attributes or is necessary for practicing the invention described herein.

[0050] In conventional semiconductor devices, both signal transmission and power delivery occur through the front side of the device. As device features continue to shrink, it becomes increasingly difficult to deliver power and signals through the front side of the device without negatively impacting device performance. For example, as semiconductor device density and complexity increase, the number of metal layers comprising signal and power lines also tends to increase, effectively increasing the length of the wires and reducing the size (e.g., cross-sectional area) of the interconnects that deliver power to the transistors. This can result in significant power losses because the thin copper typically used for front-end power delivery has high resistance. For example, a typical device can be designed to accommodate a power delivery loss (e.g., voltage drop) of approximately 10%. However, at smaller manufacturing nodes and when there are many (e.g., about 10, about 15, about 20, or more) metal layers, larger voltage drops can be seen. In some processes, metal interconnects can include alternative materials such as cobalt or tungsten, such as in lower back-end-of-line (BEOL) levels, which can reduce losses, but the benefits of using other conductive materials are limited and may require a completely different approach. Furthermore, power lines occupy a significant area on the front side of the chip and device, effectively increasing device cell size and chip size.

[0051] Backside power delivery can alleviate some of the problems associated with scaling semiconductor devices to smaller process nodes, including reducing IR drop on the chip, scaling chip area, reducing back-end-of-line (BEOL) complexity, etc. For example, backside power delivery can alleviate congestion on the front side by eliminating or reducing the need to route power via the front side. Backside power delivery can enable shorter, wider, and thicker wires (which can have lower resistance than longer, thinner wires) to be used for power delivery, which can reduce power delivery losses. Backside power delivery can also significantly save space, facilitating increased density. In addition, backside power delivery can improve signal integrity because the power delivery is relatively far away from the signal transmission, thereby reducing the possibility of power delivery interfering with signal transmission.

[0052] While backside power delivery offers many potential benefits, manufacturing devices with backside power delivery can present significant challenges, such as extreme substrate thinning (e.g., less than 1 μm), backside-to-frontside alignment, and heat dissipation due to sandwiching the device silicon between dielectric layers for signal routing on the frontside and power routing on the backside. For example, backside power delivery implementations may use direct bonding, which can cause the structure to distort or warp and can complicate subsequent processing. Material selection for vias can be limited because backside power delivery components can be formed relatively early in the manufacturing process, possibly before front-end-of-line (FEOL) processing is complete. Therefore, using some materials, such as copper, may be impractical or impossible, and selecting materials that can withstand the high processing temperatures used in advanced manufacturing processes to produce high-quality semiconductor devices can be important.

[0053] Some embodiments herein may provide front package level access to power rails and ground rails as well as signal lines while providing back side power delivery to the device die. In some embodiments, relatively large power rails and / or ground rails may be provided outside the die footprint, enabling power to be delivered from the front side of the package to the back side of the die without a large voltage drop. In some embodiments, the back side power lines may be accessible to effectively thermally extract the heat generated during operation. In some embodiments, a reconfiguration approach may be used to provide power rails and / or ground rails outside the die area. In some embodiments, integrated voltage regulators, passive components, and the like may have a different size than the device die. This makes the use of reconfigured wafers or components particularly attractive. As used herein, unless the context clearly requires otherwise, the term "power" may be interpreted to include positive potential, negative potential, and / or zero potential (e.g., ground).

[0054] As described herein and in the accompanying figures, in some backside power delivery embodiments, as described in more detail herein, direct bonding and / or direct hybrid bonding can be used to form semiconductor device assemblies with backside power delivery and / or other features. Although the examples herein describe direct bonding or direct hybrid bonding at specific locations within the device stack, it should be understood that the specific locations of the direct bonding or direct hybrid bonding may vary depending on the specific implementation.

[0055] In addition to reduced losses due to resistance within metal layers and interfaces and reduced signal integrity issues, backside power delivery can also enable more efficient cooling because the power lines can be a major source of Joule heating and a cooling solution such as a heat sink, liquid cooling, etc. can be attached. For example, compared to some other integrated circuit device designs, the cooling solution can be attached to a side of the die that is relatively close to the power lines. For example, typically, a packaged device die has a front side facing downward (e.g., toward a printed circuit board or socket to which the device die is mounted). If power delivery circuitry is provided on the back side of the die, the power delivery circuitry can be closer to a heat sink, heat sink, liquid cooling, fan, or other cooling component that can be attached to the exposed side of the device. In various embodiments disclosed herein, the active circuitry (e.g., transistor(s)) of an element (e.g., a die) can be positioned closer to the front side of the element than the back side of the element.

[0056] As briefly discussed above, in some embodiments, power delivery can start at the front of the die or package and be routed to the back for backside power delivery. In some embodiments, the die may include signal pads but may not include power rails. Instead, the power rails may be formed in a surrounding dielectric (e.g., an inorganic dielectric such as silicon oxide) outside the die as part of a reconfiguration wafer or reconfiguration element. In some embodiments, the logic die may include signal routing. In some embodiments, the logic die may include buried power rails, power vias, or backside contacts (BSCs) to the source and / or drain (e.g., backside direct source contacts). In some embodiments, the logic die may include backside through-silicon vias (TSVs). In some embodiments, the logic die may form part of a reconfiguration element or reconfiguration wafer. For example, the logic die may be reconfigured onto a dummy or sacrificial carrier, and the power rails and / or ground rails may be formed in a reconfiguration wafer around the periphery of the logic die. In some embodiments, a direct bonding interface may be formed on the back surface of the reconfiguration element. In some embodiments, backside power delivery may be facilitated by directly bonding the power delivery circuitry to the backside of the reconfiguration element and / or depositing the power delivery circuitry on the backside of the reconfiguration element. In some embodiments, the direct-bonded power delivery circuitry may include silicon (e.g., a silicon wafer). In some embodiments, the direct-bonded power delivery circuitry may include a reconfiguration element and may include passive devices (e.g., resistors, inductors, capacitors, etc.), integrated voltage regulators, etc. The backside power delivery network may be configured to provide one or more voltages to the logic die.

[0057] Figure 1A A side view of a reconstruction element 100 including backside power delivery according to some embodiments is shown. Figure 1AIn the embodiment of the present invention, power (including supplied power and / or ground) can be routed from a front side 101 of the reconstruction element 100 (also referred to herein as the front surface 101 of the reconstruction element 100) to a back side 103 of the reconstruction element 100 (also referred to herein as the back surface 103 of the reconstruction element 100). The reconstruction element can include an integrated device die (e.g., a processor or logic die 102) having a front surface 104 (also referred to herein as the front side 104) and a back surface 106 (also referred to herein as the back side 106). Although only one die 102 is shown, it should be understood that the reconstruction element 100 can include multiple dies that are arranged adjacent to each other and separated by a dielectric 116. The die 102 can be a central processing unit (CPU), a graphics processing unit (GPU), a computer chip, a microprocessor, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a memory chip or memory stack (e.g., static random access memory (SRAM), dynamic random access memory (DRAM), NAND, etc.), or a combination thereof. The die 102 may include a back portion 108 (e.g., formed of a semiconductor material such as silicon) that includes power delivery structures 110. The power delivery structures 110 may include, for example, buried power rails, through silicon vias (TSVs), nano-TSVs, power vias, or back contacts to the source and / or drain. The die 102 may include a front portion 112 that may include active devices (e.g., transistors formed during front-end processing) and signaling structures (e.g., buildup layers including dielectrics and metallization formed during back-end processing). The front portion 112 may include routing lines connected to an active area 105 that may include active circuit devices (e.g., one or more transistors, active devices, and device cells and circuits, or electronic components for processing, storing, or transmitting signals) at or near the front surface 104 of the die 102. The transistors of active region 105 can be connected to routing circuitry and devices in front portion 112, and to power delivery structures 110 (e.g., buried power rails, nano-TSVs, backside contacts to the source and / or drain, etc.). As shown, power delivery structures 110 can extend from rear surface 106 of die 102 through back portion 108 to active region 105 including the transistors. In some embodiments, power delivery structures 110 only partially extend through the semiconductor material (e.g., silicon, gallium arsenide, indium phosphide, gallium nitride, silicon carbide, or any other suitable semiconductor material) of back portion 108 and can terminate within the semiconductor material to connect to the transistors of active region 105.In some embodiments, the power delivery structure 110 provides power to the transistor or device cell from the front side of the transistor or device (e.g., contacting the drain and source from the front side via a buried power rail), from the side of the transistor cell or device (e.g., electrically contacting the source and drain regions using a buried power rail, power vias, etc.), or by directly contacting the source / drain regions from the back side (e.g., BSC). In other embodiments, the power delivery structure 110 can extend completely through the semiconductor material of the back portion 108 to deliver power to the routing circuitry of the front portion 112, and the routing circuitry of the front portion 112 can deliver power to the transistors of the active area 105.

[0058] In some embodiments, power can be delivered from the back portion 108 to the active area 105 and the front portion 112 via a power delivery structure 110 (e.g., a power rail or nano-TSV). The reconstruction element can include an interconnect structure (e.g., a redistribution layer (RDL) or backside routing layer 118) including backside power delivery lines 120 embedded in the backside insulating material 107. In some embodiments, the reconstruction element can include a frontside routing layer 122 including power delivery lines 124 embedded in the frontside insulating material 109. In various embodiments, the backside routing layer 118 and the frontside routing layer 122 can include one or more dielectric and metallization layers. The power rail 114 disposed in the reconstruction dielectric 116 can be configured to deliver power to the backside layer 118. Advantageously, the power rail 114 can be relatively large, for example, with a width of about 0.5 μm to about 5 μm (e.g., a diameter if the cross-section is circular), which enables power to be transferred from the front side of the die 102 to the back side with minimal voltage loss (e.g., less than about 10%). In some embodiments, the power rails may be approximately 0.1 μm to 1 μm wide or 1 μm to 10 μm wide. The power rails 114 may include any suitable conductor, such as copper, aluminum, nickel, cobalt, etc. In some embodiments, the die 102 may be less than 20 μm, less than 10 μm, less than 1 μm, or less than 0.5 μm thick.

[0059] In some embodiments, the reconstructed dielectric 116 may include an inorganic dielectric material, such as a silicon-containing dielectric, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or the like. The reconstructed dielectric 116 may include one or more layers of insulating or dielectric material. For example, in one embodiment, the reconstructed dielectric 116 may include a single dielectric layer, such as a single silicon oxide layer. In other embodiments, the reconstructed dielectric 116 may include multiple layers of insulating or dielectric material. For example, the reconstructed dielectric 116 may include a first dielectric layer (e.g., silicon nitride) and a second dielectric layer (e.g., silicon oxide) disposed above the first dielectric layer. In some embodiments, the first dielectric layer may include a conformal layer that encapsulates the die 102, and the second dielectric layer may include a filler material disposed above the first layer and extending to the outer edges of the reconstructed element 100. In some embodiments, two or more second dielectric materials are used as the filler material. In other embodiments, the reconstructed dielectric 116 may include an organic dielectric, such as a molding compound, epoxy molding compound (EMC), a resin, or the like.

[0060] In some embodiments, the reconstruction element can be mounted or attached to another element 126. Element 126 can be, for example, a printed circuit board to which the reconstruction element is attached, for example, via a flip chip, a ball grid array (BGA), or the like, as described in more detail below. In some embodiments, the reconstruction element can be bonded (e.g., directly bonded or directly hybrid bonded) to element 126. For example, element 126 can include a dummy element configured to provide cooling, structural support, or the like. In some embodiments, element 126 can include a device die, wafer, or substrate that includes features such as active circuit devices (e.g., transistors), input / output, memory, cache, or the like. In some embodiments, element 126 can include an interposer die or wafer that can be an active interposer or a passive interposer without any active devices. In other embodiments, element 126 can include another reconstruction element in which one or more dies are embedded in a reconstruction dielectric (similar to reconstruction element 100). Additional components (eg, active components, power supply components, cooling components, dummy components, etc.) may be mounted to the backside routing layer 118 , such as by means of direct bonding, solder balls, or the like.

[0061] Figure 1B Pictured Figure 1A The bottom view of the reconstruction element 100 is shown. Figure 1BAs shown, the reconstruction element 100 may also include an integrated voltage regulator (IVR) 128. The IVR 128 may include an electrical device configured to control or regulate the voltage supplied to the die 102. The IVR 128 may be mounted to (e.g., directly bonded to, soldered to, or wire-bonded to) the element 126. In some embodiments, power may be supplied through the element 126 and may be routed from the front side 101 of the reconstruction element 100 to the back side 103 of the reconstruction element 100 via power rails 114 (e.g., through-dielectric vias) extending through the reconstruction dielectric 116. The backside routing layer 118 may transfer electrical power from the power rails 114 to the power delivery structure 110, which may deliver power through the back side 108 of the die 102. As explained above, in some embodiments, the vias of the power delivery structure 110 may extend partially through the back side 108 to deliver power to the transistors of the active area 105 without routing power along the routing circuitry of the front side 112. In other embodiments, the vias of power delivery structure 110 may extend through the die to routing circuitry in front portion 112, which may route power to transistors in active area 105. In some embodiments, power delivery lines 124 within front side routing layer 122 may also provide some power from front side 101 to die 102.

[0062] Advantageously, routing power from the back surface 106 of the die 102 to the active area 105 can allow the number of signal lines at the front surface 104 of the die 102 to be increased, because the space on the front surface 104 that would otherwise be occupied by power lines can be used instead for signal lines and signals. In some embodiments, only signal pads are provided on the front surface 104 of the die 102, so that only signals are passed from the front surface 104 to the active area 105. In some embodiments, at least 90% of the pads (e.g., at least 95% of the pads) on the front surface 104 are configured to pass signals to the die 102 (as opposed to power pads). In some embodiments, at least 30% of the pads (e.g., at least 50% of the pads) on the front surface 104 are configured to pass signals to the die 102 (as opposed to power pads or dummy pads). In some embodiments, at least 70% of the active pads or non-dummy pads on the front surface 104 are configured to pass signals to the die 102. In some embodiments, more than 50% of the active pads or non-dummy pads at the front surface 104 are configured to pass signals to the die 102 .

[0063] To form the reconstruction element 100, the die 102 may be mounted (e.g., adhered or directly bonded) to a temporary carrier or handle. The die 102 may be embedded in a reconstruction dielectric 116, and the power rails 114 may be disposed in the dielectric 116. The dielectric 116, the power rails 114, and the die 102 may be thinned from the back side to create a substantially flush back side of the reconstruction element. The power delivery structure 110 may be exposed after the back side thinning, or formed (e.g., drilled and filled) after the back side thinning to contact the transistors and devices on the front side. A backside routing layer 118 may be deposited and patterned to extend over the back surface 106 of the die 102, the back side of the reconstruction dielectric 116, and the rear end of the power rails 114. A frontside routing layer 122 may be disposed over the front surface 104 of the die, the front side of the reconstruction dielectric 116, and the front end of the power rails 114. One or both of the front routing layer 122 and the back routing layer 118 may include a redistribution layer (RDL) to route signals laterally (e.g., laterally inward or outward) along the component 100. As described above, one or both of the front routing layer 122 and the back routing layer 118 may be prepared for direct bonding (e.g., hybrid bonding). As used herein, delivering power to the die 102 may include delivering current to power devices on the die 102 and may also include connecting the devices to electrical ground.

[0064] Figure 1C The diagram is similar to Figure 1A However, in Figure 1C In , the power rail 114 is not disposed in the reconstructed dielectric 116 but is surrounded on one or more sides by an element 130 (e.g., a semiconductor element or dummy silicon, glass, ceramic, etc.) or another material different from the reconstructed dielectric 116. Figure 1C In the embodiment of the present invention, the power rail 114 may include a through-substrate via (TSV) disposed through the component 130 or the dummy semiconductor component 130. In some embodiments, the die 102 and the component 130 may be embedded in the reconfiguration dielectric 116. In some embodiments, the component 130 may include a passive component (e.g., a capacitor, an inductor, etc.) or other active component. Advantageously, the use of the component 130 may be used to reduce stress and provide structural support and a heat dissipation path for the reconfiguration component 100.

[0065] Figure 2 An example embodiment of a device including a power delivery die 132 according to some embodiments is illustrated. Unless otherwise stated, Figure 2 The structure shown is generally similar to Figure 1A-1C The structure shown. Figure 2The device in FIG. 1 includes an integrated voltage regulator 128 disposed in a reconfiguration dielectric 116. As shown, some IVRs 128 may be connected to a redistribution layer 136 by means of vias or tracks 114 extending from the IVR to the back side of the reconfiguration element 100. Figure 2 The IVR 128 is shown connected to the front routing 122, but the IVR 128 can also be connected to the back routing 118 or redistribution layer (RDL) 136 shown in Figure 1 from the top surface of the IVR. Figure 2 , the component 126 may be a printed circuit board, and the reconstruction element is attached and electrically connected to the component 126 via BGA balls 134. In other embodiments, the component 126 may include any other type of component, such as an integrated device die, another reconstruction element, an interposer (e.g., organic, inorganic or semiconductor, glass, etc.), a wafer, a substrate, a panel, etc. As described above, the component 126 may alternatively be directly bonded (e.g., hybrid bonded) to the component 126. The power delivery die 132 may be bonded (e.g., directly bonded) to the reconstruction element 100. The power delivery die 132 may include a redistribution layer (RDL) 136. The power delivery die 132 may include pads 138, which may be electrically connected to corresponding pads (not shown) of the reconstruction element 100. In some embodiments, as Figure 2 As shown, the power delivery die 132 can be directly bonded (e.g., hybrid bonded) to the reconstruction element 100 at a direct bonding interface 140. Thus, in the illustrated embodiment, a backside routing layer may not be deposited on the backside 103 of the reconstruction element 100. Instead, an RDL 136 can be deposited on the power delivery die 132 and directly bonded to the reconstruction element 100 (e.g., directly bonded to the reconstruction dielectric 116, the back surface 106 of the die 102 (which may include a bonding layer thereon), and the power rails 114). Figure 2 In some embodiments, the RDL 136 may include interconnect elements that are hybrid bonded to the reconstruction element 100. In some embodiments, the power delivery die 132 may be directly bonded (eg, hybrid bonded) to a hybrid bonding layer formed on or above the reconstruction element 100.

[0066] Although Figure 2The power delivery die 132 is shown to include a redistribution layer 136 and pads 138 and is directly bonded (e.g., directly hybrid bonded) to the reconstruction element 100, but other configurations are possible. For example, in some embodiments, the redistribution layer 136 can be deposited onto the back surface 106 of the die 102 using semiconductor processing techniques such as photolithography, etching, deposition, and polishing. In some embodiments, instead of the power delivery die 132 being bonded to the reconstruction element 100, the power delivery functionality can be deposited directly on the back surface of the reconstruction element 100 and can form part of the reconstruction element 100. Advantageously, directly bonding the power die 132 to the reconstruction element 100 can enable a more efficient process that utilizes a greater number of pins for power (including ground). As explained above, as used herein, delivering power to the die 102 can include delivering current to power devices on the die 102 and can also include connecting the devices to electrical ground.

[0067] Figure 3 An example assembly is shown that includes at least one of a dummy die 142, a structural support die, a carrier die, a passive die, or a heat dissipation element. The dummy die 142 can be bonded (e.g., directly bonded) to the reconstruction element 100. In some embodiments, the dummy die 142 can be bonded (e.g., directly bonded) to the reconstruction element 100. In some embodiments, the dummy die 142 can include an electrically inert element, for example, the dummy die 142 can lack active circuitry (e.g., no transistors). In some embodiments, the dummy die 142 can include passive circuitry (e.g., capacitors, resistors, inductors, transformers, etc.); in other embodiments, the dummy die 142 can lack passive components. In some embodiments, the dummy die 142 can include a structural support element (e.g., a semiconductor material such as silicon) that provides mechanical support and / or reduces stress applied to the die 102. In some embodiments, the dummy die 142 can be used, for example, to facilitate heat dissipation to transfer heat away from the die 102. For example, in some embodiments, dummy die 142 may include a heat sink or heat sink. In some embodiments, dummy die 142 may be used to provide cavity cooling. For example, dummy die 142 may include one or more cooling cavities therein, and a cooling fluid may be provided through the cooling cavities to transfer heat from die 102. Figure 3 In the embodiment of FIG. 1 , the bonding interface 136 may be provided between the dummy die 142 and the corresponding bonding layer of the reconstruction element 100 . Figure 3100 , and the dummy die 142 is bonded to the routing layer 111. In some embodiments, the routing layer 111 can be disposed on the back side 103 of the reconstruction element 100, and the routing layer 113 can be disposed on the front side of the dummy die 142. The respective bonding surfaces of the routing layers 111, 113 can be directly bonded along the bonding interface 136. However, in other embodiments, the bonding interface 136 can be disposed between the routing layer of the dummy die 142 and the back side 103 of the reconstruction element 100 (e.g., the back side of the dielectric 116, the die 102, and the rails 114). In some embodiments, the routing layer 111 can be disposed on the back side 103 of the reconstruction element 100, and the dummy die 142 can be directly bonded to the routing layer 111 without any separate routing layer 113 on the front side of the dummy die 142.

[0068] In some embodiments, multiple components can be bonded together (e.g., directly bonded or directly hybrid bonded) to form an assembly. For example, a second component including a power delivery circuit device can be bonded (e.g., directly hybrid bonded) to the reconstruction element 100, and a third component, such as a dummy die, a heat sink, a passive component, or a liquid cooling element can be attached to the second component, for example, by direct bonding. In some embodiments, the second component and / or the third component can be a reconstruction element.

[0069] Figure 4 An exemplary embodiment is illustrated in which a second reconstruction element 144 is bonded (eg, directly hybrid bonded) to the reconstruction element 100 along a bonding interface 136a, and a third element 146 (which may be similar to Figure 3 The first component 142 (e.g., a dummy die, heat sink, liquid cooling, etc.) is bonded (e.g., directly bonded) to the second reconstruction component 144 along the bonding interface 136b to form a stack. The second reconstruction component 144 may include an integrated voltage regulator (IVR) 128, a spacer 148, and any other suitable active, passive, or dummy components. In some embodiments, the second reconstruction component 144 may include passive components, integrated power delivery, etc. Figure 4 As shown, in some embodiments, the second reconstruction element 144 may include a redistribution layer (RDL) 150, although in other embodiments, the redistribution layer 150 may not be included in the second reconstruction element 144, but may be formed (e.g., deposited) on the reconstruction element 100. In some embodiments, the spacer(s) 148 and the IVR 128 may be reconstructed in the dielectric 116a, and the redistribution layer 150 may be deposited on the dielectric 116a, the spacer(s) 148, and the IVR 128. The bonding surface of the RDL 150 may be hybrid bonded to the reconstruction element 100. Although not shown, through-dielectric vias (e.g., similar to the conductive vias of the power rail 114) may be provided through the dielectric 116a.

[0070] Figure 5 The diagram shows a typical Figure 4 1 . However, instead of the second reconstruction element 144, the second element 152 may not be reconstructed. For example, the second element 152 may be a wafer or a monolithic component thereof. The second element 152 may include the same or similar functional parts as the second reconstruction element 144. In some embodiments, for example, the second element 152 may include an IVR and / or passive components patterned or formed therein. The second element 152 may be directly bonded to the reconstruction element 100 along the bonding interface 136a, and the third element 146 may be directly bonded to the second element 152 along the bonding interface 136b. It should be understood that, depending on the location of the corresponding bonding layers, the bonding interfaces 136a, 136b may be at other locations, for example, along the back surface 103 of the reconstruction element 100, etc.

[0071] Figure 4 and Figure 5 The second component is depicted as being formed from a single piece (e.g., from a silicon wafer) or as an assembly of a reconstruction element. However, other embodiments are possible. For example, an integrated voltage regulator, passive components, integrated power delivery components, spacers, etc. may be bonded (e.g., directly bonded or directly hybrid bonded) to the reconstruction element 100. In some embodiments, a filler material (e.g., a dielectric) may be deposited after the various components are bonded to the reconstruction element 100.

[0072] Figure 6 and Figure 7 An embodiment is illustrated in which additional or alternative circuitry is included in a second element 152 that is bonded (eg, directly bonded) to the reconstruction element 100. Figure 6 In the embodiment, the second element 152 includes a semiconductor element (e.g., a single semiconductor chip in some embodiments) in which a memory body 154 is formed. In some embodiments, the second element 152 may have a memory device (e.g., NAND, DRAM, SRAM, etc.). Figure 6 As shown, in some embodiments, the fourth element 156 can be bonded (e.g., directly bonded) to the front surface 104 of the reconstruction element 100. The fourth element 156 can include, for example, electrical signal input / output, optical signal input / output, cache, etc. As described above, the element 146 can include a dummy element that can provide at least one of structural support and heat transfer to the assembly.

[0073] Figure 7 Similar to Figure 6, except that the second element 152 is not a single element with a memory bank formed therein, but rather a reconstructed element having an integrated voltage regulator, spacers, memory banks (or memory devices), and / or other devices embedded in the dielectric 116a. Figure 6-Figure 7 The use of direct bonding technology may enable high-speed connections between memory bank 154 and logic die 102 with a high pin count due to the fine pitch achieved by the direct bonding process.

[0074] Figure 8 8 is a flow chart illustrating an example process 800 for manufacturing a component including backside power delivery according to some embodiments. At block 802, a reconstituted wafer may be formed. For example, in a die-to-wafer bonding process, a known good logic die may be bonded (e.g., directly bonded) to a carrier wafer. The front side of the logic die (e.g., the side closest to the logic circuitry) may be bonded to the carrier wafer. Integrated voltage regulators, passive components, etc. may also be bonded directly to the carrier wafer, although in some embodiments, they may be formed or mounted by other means (such as deposition or soldering), or such components may not be present. The gaps between the dies may be filled with a dielectric material (e.g., by a deposition process, such as one or more layers of silicon nitride, silicon oxide, etc.). One or more power rails and / or ground rails may be formed within the dielectric and may extend from the front surface of the dielectric to the back surface of the dielectric. The power rails and / or ground rails may be formed after the dielectric, for example, by selectively etching areas of the dielectric material to provide gaps that can be filled by deposition, plating, etc. Alternatively, the power rails and / or ground rails can be formed before the dielectric, such as by electroplating the power rails (e.g., copper pillars) followed by dielectric deposition. Each logic die and its associated dielectric material, power rails / ground rails, and other associated circuitry can include a reconfiguration element. The reconfiguration wafer can include one or more reconfiguration elements. In some embodiments, the reconfiguration element can include one or more dies, including one or more logic and / or memory dies.

[0075] At block 804, the back side of the reconstructed element can be thinned, for example, by chemical mechanical polishing (CMP), etching, or back grinding, to expose power delivery contacts. The power delivery contacts can be, for example, contact pads (e.g., backside direct source contacts) that are in electrical contact with buried power rails, nano-TSVs, power vias, or backside contacts (BSCs) to the source and / or drain, or are part of buried power rails, nano-TSVs, power vias, or backside contacts. After thinning, at block 806, a hybrid bonding interface layer can optionally be formed on the exposed back side of the reconstructed element to facilitate subsequent bonding of additional dies, dummy silicon, etc.

[0076] At block 808, a second element can be bonded to the back surface of the reconstructed element. As discussed above, the second element can be, for example, a power delivery die, dummy silicon, a reconstructed die, or the like.

[0077] At block 810, the carrier may be removed from the reconstruction element, thereby exposing the front surface of the reconstruction element. The front surface may then be further processed, such as by polishing. At block 812, the front surface of the reconstruction element may be metallized.

[0078] Direct bonding

[0079] Various embodiments disclosed herein relate to directly bonded structures in which two or more elements can be directly bonded to each other without an intermediate adhesive. Such processes and structures are referred to herein as "direct bonding" processes or "directly bonded" structures. Direct bonding can involve bonding one material to one element and bonding one material to another element (also referred to herein as "uniform" direct bonding), wherein the materials on different elements do not need to be the same, without the need for traditional adhesive materials. Direct bonding can also include bonding multiple materials on one element to multiple materials on another element (e.g., hybrid bonding).

[0080] In some implementations (not shown), each bonding layer has one material. In these uniform direct bonding processes, only one material is directly bonded to each component. Example uniform direct bonding processes include those commercially available from Adeia of San Jose, CA. Technology. The materials of the relative bonding layers on different elements may be the same or different and may include element or compound materials. For example, in some embodiments, the non-conductive bonding layer may be blanket deposited on a substrate portion without being patterned with conductive features (e.g., without pads). In other embodiments, the bonding layers may be patterned on one or two elements and may be the same or different from each other, but a material from each element is directly bonded without an adhesive across the surface of the element (or across the surface of the smaller element if the elements are of different sizes). In another implementation of uniform direct bonding, one or two non-conductive bonding layers may include one or more conductive features, but the conductive features are not involved in bonding. For example, in some implementations, relative non-conductive bonding layers may be uniformly bonded directly to each other, and after bonding, a through-substrate via (TSV) may then be formed through one element to provide electrical communication to another element.

[0081] In various embodiments, the bonding layer 908a and / or 908b may include a non-conductive material, such as a dielectric material or an undoped semiconductor material, such as undoped silicon, which may include a native oxide. Suitable dielectric bonding surfaces or materials for direct bonding include, but are not limited to, inorganic dielectrics, such as silicon oxide, silicon nitride, or silicon oxynitride, or may include carbon, such as silicon carbide, silicon carbonitride, low-K dielectric materials, SiCOH dielectrics, silicon carbonitride, or diamond-like carbon, or materials including diamond surfaces. Although containing carbon, such carbon-containing ceramic materials may be considered inorganic. In some embodiments, the dielectric material at the bonding surface does not include a polymer material, such as an epoxy resin (e.g., an epoxy adhesive, a cured epoxy resin, or an epoxy composite material, such as an FR-4 material), a resin, or a molding material.

[0082] In other embodiments, the bonding layer may include a conductive material, such as a deposited conductive oxide material, such as indium tin oxide (ITO), as disclosed in U.S. Provisional Patent Application No. 63 / 524,564, filed on June 30, 2023, the entire contents of which are incorporated herein by reference to provide examples of conductive bonding layers that do not short-circuit contacts through the interface.

[0083] In direct bonding, the first element and the second element can be directly bonded to each other without an adhesive, which is different from a deposition process and, compared to the interface produced by deposition, can result in an interface with different structures. In one application, the width of the first element in the bonding structure is similar to the width of the second element. In some other embodiments, the width of the first element in the bonding structure is different from the width of the second element. The width or area of ​​the larger element in the bonding structure can be at least 10% larger than the width or area of ​​the smaller element. In addition, different from the interface below the deposited layer, the interface between the structures directly bonded can include a defective region in which there is a nanometer-scale void (nanovoid). Nanovoids can be formed due to the activation (e.g., exposure to plasma, as described below) of one or both bonding surfaces.

[0084] Compared to the main body of the bonding layer, the bonding interface between the non-conductive bonding surfaces may include a higher concentration of material from the activation and / or final chemical treatment process. For example, in an embodiment in which nitrogen plasma is utilized for activation, a nitrogen concentration peak may be formed at the bonding interface. In some embodiments, a secondary ion mass spectrometry (SIMS) technique may be used to detect the nitrogen concentration peak. In various embodiments, for example, a nitrogen termination process (e.g., exposing the bonding surface to a nitrogen-containing plasma) may replace the OH groups of the hydrolysis (OH termination) surface with NH2 molecules to produce a nitrogen-terminated surface. In an embodiment in which oxygen plasma is utilized for activation, an oxygen concentration peak may be formed at the bonding interface between the non-conductive bonding surfaces. In some embodiments, the bonding interface may include silicon oxynitride, silicon carbonitride or silicon carbonitride. A direct bond may include a covalent bond that is stronger than a van der Waals bond. The bonding layer may also include a polished surface that is planarized to a high degree of smoothness.

[0085] In direct bonding processes, such as uniform direct bonding and hybrid bonding, two elements are bonded together without an intermediate adhesive. In indirect bonding processes utilizing adhesives, an intermediate material is typically applied to one or both elements to achieve a physical connection between the elements. For example, in some adhesive-based processes, a flowable adhesive (e.g., an organic adhesive, such as an epoxy resin) that may include a conductive filler material may be applied to one or both elements and cured to form a physical (rather than chemical or covalent) connection between the elements. Typical organic adhesives lack strong chemical or covalent bonds to either element. In such processes, the connection between the elements is weak and / or easily reversed, such as by reheating or desoldering.

[0086] In contrast, direct bonding processes bond two elements by forming a strong chemical bond (e.g., a covalent bond) between the opposing non-conductive materials. For example, in a direct bonding process between non-conductive materials, one or both non-conductive surfaces of the two elements are planarized and chemically prepared (e.g., activated and / or terminated) so that when the elements come into contact, a strong chemical bond (e.g., a covalent bond) is formed that is stronger than van der Waals forces or hydrogen bonds. In some implementations (e.g., between opposing dielectric surfaces, such as opposing silicon oxide surfaces), chemical bonds can occur spontaneously when in contact at room temperature. In some implementations, the chemical bonds between the opposing non-conductive materials can be strengthened after the elements are annealed.

[0087] As described above, hybrid bonding is a direct bonding in which non-conductive features are directly bonded to non-conductive features, and conductive features are directly bonded to conductive features of the bonded elements. The non-conductive bonding materials and interfaces can be as described above, and the conductive bond can be formed as, for example, a direct metal-to-metal connector. In conventional metal bonding processes, a fusible metal alloy (e.g., solder) can be provided between the conductors of the two elements, heated to melt the alloy, and cooled to form a connector between the two elements. The resulting bond often exhibits a sharp interface with the conductors of the two elements and is easily reversed by reheating. In contrast, the direct metal bonding employed in hybrid bonding does not require melting or an intermediate fusible metal alloy, and can produce powerful mechanical and electrical connectors, often exhibiting interdiffusion of grain growth on the bonding interface between the conductive features of the bonding and the elements, even without the much higher temperatures and pressures of thermocompression bonding.

[0088] Figure 9A and Figure 9B Schematically illustrates cross-sectional side views of a first element 902 and a second element 904 before and after a process of forming a directly bonded structure, and more specifically a hybrid bonded structure, respectively, according to some embodiments. Figure 9B , a joined structure 900 includes a first component 902 and a second component 904 that are directly joined to one another without an intervening adhesive at a joining interface 918. A conductive feature 906a of the first component 902 can be electrically connected to a corresponding conductive feature 906b of the second component 904. In the illustrated hybrid joined structure 900, the conductive feature 906a is directly joined to the corresponding conductive feature 906b without an intervening solder or conductive adhesive.

[0089] The conductive features 906a and 906b of the illustrated embodiment are respectively embedded in the first bonding layer 908a of the first element 902 and the second bonding layer 908b of the second element 904 and can be regarded as parts thereof. The field region of the bonding layers 908a, 908b extends between the conductive features 906a, 906b and partially or completely surrounds the conductive features 906a, 906b. As described above, the bonding layers 908a, 908b may include a non-conductive material layer suitable for direct bonding, and the field regions are directly bonded to each other without an adhesive. The non-conductive bonding layers 908a, 908b may be disposed on the respective front sides 914a, 914b of the substrate portions 910a, 910b.

[0090] The first element 902 and the second element 904 may include microelectronic elements, such as semiconductor elements, including, for example, integrated device dies, wafers, passive devices, discrete active devices, such as power switches, MEMS, etc. In some embodiments, the base substrate portion may include device portions, such as bulk semiconductor (e.g., silicon) portions of the elements 902, 904, and back-end-of-line (BEOL) interconnect layers above such semiconductor portions. The bonding layers 908a, 908b may be provided as part of such BEOL layers during device fabrication, as part of a redistribution layer (RDL), or as a specific bonding layer added to an existing device, with bonding pads extending from underlying contacts. Active devices and / or circuitry may be patterned and / or otherwise disposed in or on the substrate portions 910a, 910b and may be electrically connected to at least some of the conductive features 906a, 906b. Active devices and / or circuitry may be disposed at or near the front side 914a, 914b of the substrate portions 910a, 910b and / or at or near the opposite back side 916a, 916b of the substrate portions 910a, 910b. In other embodiments, the base substrate portions 910a, 910b may not include active circuitry but may include a dummy substrate, a passive interposer, a passive optical element (e.g., a glass substrate, a grating, a lens), etc. The bonding layer 908a, 908b is shown as being disposed on the front side of the element, but a similar bonding layer may additionally or alternatively be disposed on the back side of the element.

[0091] In certain embodiments, the base substrate portions 910a and 910b may have significantly different coefficients of thermal expansion (CTE), and the bonding element including such different base substrate portions may form a heterojunction structure. The CTE difference between the base substrate portions 910a and 910b, particularly between the bulk semiconductor (typically single crystal) portions of the base substrate portions 910a and 910b, may be greater than 5 ppm / °C, or greater than 10 ppm / °C. For example, the CTE difference between the base substrate portions 910a and 910b may be in the range of 5 ppm / °C to 100 ppm / °C, 5 ppm / °C to 40 ppm / °C, 10 ppm / °C to 100 ppm / °C, or 10 ppm / °C to 40 ppm / °C.

[0092] In some embodiments, one of the base substrate portions 910a, 910b may include an optoelectronic single crystal material, including a perovskite material that can be used for optical, piezoelectric, or thermoelectric applications, while the other of the base substrate portions 910a, 910b may include a more conventional substrate material. For example, one of the base substrate portions 910a, 910b may include lithium tantalate (LiTaO3) or lithium niobate (LiNbO3), and the other of the base substrate portions 910a, 910b may include silicon (Si), quartz, fused silica glass, sapphire, or glass. In other embodiments, one of the base substrate portions 910a, 910b may include a single III-V semiconductor material, such as gallium arsenide (GaAs) or gallium nitride (GaN), and the other of the base substrate portions 910a, 910b may include a non-III-V semiconductor material, such as silicon (Si), or may include other materials with similar CTEs, such as quartz, fused silica glass, sapphire, or glass. In other embodiments, one of the base substrate portions 910a, 910b includes a semiconductor material and the other of the base substrate portions 910a, 910b includes an encapsulation material, such as a glass, organic, or ceramic substrate.

[0093] In some arrangements, the first element 902 may include a singulated element, such as a singulated integrated device die. In other arrangements, the first element 902 may include a carrier or substrate (e.g., a semiconductor wafer) comprising a plurality of (e.g., tens, hundreds, or more) device regions that form a plurality of integrated device dies when singulated, although in other embodiments, such carriers may be package substrates or passive or active interposers. Similarly, the second element 904 may include a singulated element, such as a singulated integrated device die. In other arrangements, the second element 904 may include a carrier or substrate (e.g., a semiconductor wafer). Therefore, the embodiments disclosed herein may be applied to wafer-to-wafer (W2W), die-to-die (D2D), or die-to-wafer (D2W) bonding processes. In a W2W process, two or more wafers may be directly bonded to each other (e.g., direct hybrid bonding) and singulated using a suitable singulation process. After singulation, side edges of the singulated structure (e.g., side edges of two bonded elements) can be substantially flush (substantially aligned xy dimensions), and / or edges of the bonding interface of both the bonded elements and the singulated element can extend together and can include markings indicating a common singulation process of the bonded structure (e.g., saw marks if a saw singulation process is used).

[0094] Although only two elements 902 and 904 are shown, any suitable number of elements can be stacked in the bonding structure 900. For example, a third element (not shown) can be stacked on the second element 904, a fourth element (not shown) can be stacked on the third element, and so on. In such embodiments, substrate vias (TSVs) can be formed to provide vertical electrical communication between and / or among the vertically stacked elements. Additionally or alternatively, one or more additional elements (not shown) can be stacked laterally adjacent to each other along the first element 902. In some embodiments, the laterally stacked additional elements can be smaller than the second element. In some embodiments, the bonding structure can be encapsulated with an insulating material, such as an inorganic dielectric (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.). One or more insulating layers can be disposed on the bonding structure. For example, in some embodiments, a first insulating layer can be conformally deposited on the bonding structure, and a second insulating layer (which can include the same material as the first insulating layer, or a different material) can be disposed on the first insulating layer.

[0095] To achieve direct bonding between the bonding layers 908a, 908b, the bonding layers 908a, 908b may be prepared for direct bonding. The non-conductive bonding surfaces 912a, 912b at the upper or outer surfaces of the bonding layers 908a, 908b may be prepared for direct bonding by polishing (e.g., by chemical mechanical polishing (CMP)). The roughness of the polished bonding surfaces 912a, 912b may be less than For example, the roughness of the bonding surfaces 912a and 912b can be about to to or to Polishing can also be adjusted to leave the conductive layers 906a, 906b recessed relative to the field regions of the bonding layers 908a, 908b.

[0096] Preparation for direct bonding may also include cleaning one or both of the bonding surfaces 912a, 912b and exposing them to a plasma and / or etchant to activate at least one of the surfaces 912a, 912b. In some embodiments, one or both of the surfaces 912a, 912b may be terminated with a substance after or during activation (e.g., during the plasma and / or etching process). Without being limited by theory, in some embodiments, an activation process may be performed to break chemical bonds at the bonding surface(s) 912a, 912b, and a termination process may provide additional chemicals at the bonding surface(s) 912a, 912b that alter the chemical bonds and / or increase the bonding energy during direct bonding. In some embodiments, activation and termination are performed in the same step, e.g., plasma activation and termination of the surface(s) 912a, 912b. In other embodiments, one or both of the bonding surfaces 912a, 912b may be terminated in a separate process to provide additional substances for direct bonding. In various embodiments, the termination substance may include nitrogen. For example, in some embodiments, the bonding surface(s) 912a, 912b may be exposed to a nitrogen-containing plasma. Depending on the material of the bonding surfaces 912a, 912b, other termination substances may be suitable for increasing the bonding energy. Additionally, in some embodiments, the bonding surface(s) 912a, 912b may be exposed to fluorine. For example, there may be one or more fluorine concentration peaks at or near the bonding interface 918 between the first element 902 and the second element 904. Typically, the fluorine concentration peak occurs at the interface between the material layers. Other examples of activation and / or termination treatments may be found in U.S. Patent No. 9,391,143 at col. 5, line 55 to col. 7, line 3; col. 8, line 52 to col. 9, line 45; col. 10, lines 24-36; col. 11, lines 24-32, lines 42-47, lines 52-55, and lines 60-64; col. 12, lines 3-14, lines 31-33, and lines 5 5-67; ​​column 14, lines 38-40 and 44-50; and No. 10,434,749, column 4, lines 41-50; column 5, lines 7-22, line 39, 55-61; column 8, lines 25-31, lines 35-40 and 49-56; and column 12, lines 46-61, the activation and termination teachings of which are incorporated herein by reference.

[0097] Thus, in the direct bond structure 900, the bonding interface 918 between the two non-conductive materials (e.g., bonding layers 908a, 908b) may include a very smooth interface with a high nitrogen (or other termination species) content and / or fluorine concentration peak at the bonding interface 918. In some embodiments, various types of inspection techniques, such as SIMS techniques, may be used to detect the nitrogen and / or fluorine concentration peaks. After the activation process, the polished bonding surfaces 912a and 912b may be slightly rougher (e.g., about 100 nm). to to Or possibly rougher). In some embodiments, activation and / or termination may result in a slightly smoother surface prior to bonding, such as plasma treatment preferentially etching high points on the bonding surface.

[0098] Non-conductive bonding layers 908a and 908b can be directly bonded together without adhesive. In some embodiments, elements 902, 904 are put together at room temperature without applying voltage, and no external pressure or force is required except for starting the contact between the two elements 902, 904. Independent contacts can cause direct bonding (e.g., covalent dielectric bonding) between the non-conductive surfaces of bonding layers 908a, 908b. Subsequent annealing of the bonding structure 900 can directly bond the conductive features 906a, 906b.

[0099] In some embodiments, prior to direct bonding, the conductive features 906a, 906b are recessed relative to the surrounding field region such that the total gap between opposing contacts after dielectric bonding and before annealing is less than 15 nm, or less than 10 nm. Due to process variations, the depth of the recesses of the conductive features 906a and 906b may vary on each element, so the gaps noted may represent the maximum or average gap (before annealing) between corresponding conductive features 906a, 906b of the two bonded elements. Upon annealing, the conductive features 906a and 906b may expand and contact each other to form a metal-to-metal direct bond.

[0100] During annealing, the conductive features 906a, 906b (e.g., metal material) can expand, while the direct bond between the surrounding non-conductive material of the bonding layer 908a, 908b resists separation of the components, such that thermal expansion increases the internal contact pressure between the opposing conductive features. Annealing can also cause metal grains to grow at the bonding interface, such that grains from one component migrate at least partially across the bonding interface into the other component, and vice versa. Thus, in some hybrid bonding embodiments, the opposing conductive materials are bonded without heating above the melting temperature of the conductive materials, such that the bond can be formed at a lower annealing temperature than soldering or thermocompression bonding.

[0101] In various embodiments, the conductive features 906a, 906b may include discrete pads, contacts, electrodes, or traces at least partially embedded in the non-conductive field region of the bonding layer 908a, 908b. In some embodiments, the conductive features 906a, 906b may include exposed contact surfaces of TSVs (e.g., through-silicon vias).

[0102] As noted above, in some embodiments, prior to direct bonding, Figure 1A In the elements 902, 904, portions of the corresponding conductive features 906a and 906b can be recessed below the non-conductive bonding surfaces 912a and 912b, for example, by less than 30nm, less than 20nm, less than 15nm, or less than 10nm, for example, in the range of 2nm to 20nm, or in the range of 4nm to 10nm. Due to process variations, both the dielectric thickness and the conductor recess depth can vary across the element. Therefore, the above recess depth ranges can be applied to individual conductive features 906a, 906b or the average depth of the recess relative to the local non-conductive field region. Even for a single conductive feature 906a, 906b, the vertical recess can vary across the feature and can therefore be measured at or near the lateral middle or center of the cavity in which a given conductive feature 906a, 906b is formed, or can be measured at the side of the cavity.

[0103] It is beneficial to use hybrid bonding techniques such as direct bonding interconnects or Technology commercially available from Adeia of San Jose, California) can enable high density connections (eg, small pitch or fine pitch in a regular array) between conductive features 906a, 906b on a direct bonding interface 918.

[0104] In some embodiments, the pitch p of the conductive features 906a, 906b, such as conductive traces embedded in the bonding surface of one of the bonding elements, can be less than 40 μm, less than 20 μm, less than 10 μm, less than 5 μm, less than 2 μm, or even less than 1 μm. For some applications, the ratio of the pitch of the conductive features 906a and 906b to one of the lateral dimensions (e.g., diameter) is less than 20, or less than 10, or less than 5, or less than 3, and sometimes desirably less than 2. In various embodiments, the conductive features 906a and 906b and / or traces can include copper or a copper alloy, although other metals may also be suitable, such as nickel, aluminum, or alloys thereof. The conductive features disclosed herein, such as the conductive features 906a and 906b, can include fine-grained metal (e.g., fine-grained copper). Furthermore, the major lateral dimension (eg, pad diameter) may also be small, such as in the range of approximately 0.25 μm to 30 μm, in the range of approximately 0.25 μm to 5 μm, or in the range of approximately 0.5 μm to 5 μm.

[0105] For hybrid junction elements 902, 904, as shown, the orientation of one or more conductive features 906a, 906b of the opposing elements can be opposite to each other. As is known in the art, conductive features with nearly vertical sidewalls can generally be formed, particularly when the conductor sidewalls are defined by directional reactive ion etching (RIE) directly by etching the conductive material or indirectly by etching the surrounding insulator in a damascene process. However, there may be some slight taper in the conductor sidewalls, where the conductor becomes narrower as it moves away from the surface initially exposed to the etching. The taper is more pronounced when the conductive sidewalls are defined directly or indirectly by isotropic wet or dry etching. In the illustrated embodiment, at least one conductive feature 906b (and / or at least one internal conductive feature, such as a BEOL feature) in the junction layer 908b of the upper element 904 can taper or narrow upward away from the junction surface 912b. In contrast, at least one conductive feature 906a (and / or at least one internal conductive feature, such as a BEOL feature) in the bonding layer 908a of the lower component 902 can taper or narrow downwardly away from the bonding surface 912a. Similarly, any bonding layer (not shown) on the backside 916a, 916b of the components 902, 904 can taper or narrow away from the backside, with an opposite tapered orientation relative to the frontside conductive features 906a, 906b of the same component.

[0106] As described above, during the annealing phase of the hybrid bond, the conductive features 906a, 906b can expand and contact each other to form a direct metal-to-metal bond. In some embodiments, the materials of the conductive features 906a, 906b of the relative elements 902, 904 can diffuse into each other during the annealing process. In some embodiments, metal grains grow on each other across the bonding interface 918. In some embodiments, the metal is or includes copper, which can have grains oriented along 111 crystal planes to improve copper diffusion across the bonding interface 918. In some embodiments, the conductive features 906a and 906b can include a nano-twinned copper grain structure, which helps to merge the conductive features during annealing. At or near the bonded conductive features 906a and 906b, there is substantially no gap between the non-conductive bonding layers 908a and 908b. In some embodiments, a barrier layer can be provided below the conductive features 906a and 906b and / or laterally around the conductive features 906a and 906b (e.g., it can include copper). However, in other embodiments, there may be no barrier layer beneath the conductive features 906a and 906b.

[0107] Additional Examples

[0108] In the foregoing description, the systems and processes have been described with reference to specific embodiments. However, it will be apparent that various modifications and changes may be made thereto without departing from the broader spirit and scope of the embodiments disclosed herein. Accordingly, the description and drawings are to be regarded as illustrative rather than restrictive.

[0109] In fact, although the systems and processes have been disclosed in the context of specific embodiments and examples, it will be understood by those skilled in the art that the various embodiments of the systems and processes may extend beyond the specifically disclosed embodiments to other alternative embodiments and / or uses of the systems and processes and their obvious modifications and equivalents. In addition, although several variations of the embodiments of the systems and processes have been shown and described in detail, other modifications within the scope of the present disclosure will be apparent to those skilled in the art based on the present disclosure. It is also conceivable that various combinations or sub-combinations of the specific features and embodiments of the embodiments may be made and still fall within the scope of the present disclosure. It should be understood that the various features and embodiments of the disclosed embodiments may be combined or replaced with each other to form different modes of embodiments of the disclosed systems and processes. None of the methods disclosed herein need to be performed in the order described. Therefore, the scope of the systems and processes disclosed herein should not be limited by the specific embodiments described above.

[0110] It should be understood that the systems and methods of the present disclosure each have several innovative embodiments, no single one of which is solely responsible for or requires the desired properties disclosed herein. The various features and processes described above can be used independently of one another or can be combined in various ways. All possible combinations and subcombinations are intended to fall within the scope of the present disclosure.

[0111] Certain features described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable subcombination. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed as such, one or more features from a claimed combination may in some cases be deleted from that combination, and a claimed combination may be directed to subcombinations or variations of subcombinations. No single feature or set of features is essential or indispensable for every embodiment.

[0112] It should also be understood that, unless otherwise specifically stated or understood otherwise in the context of use, conditional language used herein, such as "can," "could," "might," "may," "for example," and the like, is generally intended to convey that certain embodiments include certain features, elements, and / or steps, while other embodiments do not. Thus, such conditional language is generally not intended to express that one or more embodiments require features, elements, and / or steps in any way, or that one or more embodiments must include logic for determining, with or without author input or prompting, whether such features, elements, and / or steps are included or will be performed in any particular embodiment. The terms "comprising," "including," "having," and the like are synonymous and are used in an open and inclusive manner and do not exclude additional elements, features, actions, operations, and the like. Furthermore, the term "or" is used in its inclusive sense (and not in its exclusive sense), so that when used, for example, to connect a list of elements, the term "or" means one, some, or all of the elements in the list. In addition, unless otherwise indicated, the articles "a," "an," and "the" as used in this application and the appended claims should be interpreted to mean "one or more" or "at least one." Similarly, although operations are depicted in the accompanying drawings in a particular order, it should be recognized that the operations need not be performed in the particular order or sequence shown, or that all of the illustrated operations need not be performed to achieve the desired results. In addition, the accompanying drawings may schematically depict one or more example processes in the form of flow charts. However, other operations not shown may be incorporated into the schematically illustrated example methods and processes. For example, one or more additional operations may be performed before, after, simultaneously with, or between any of the illustrated operations. In addition, in other embodiments, the operations may be rearranged or reordered. In addition, other embodiments are also within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve the desired results.

[0113] Furthermore, while the methods and devices described herein are susceptible to various modifications and alternative forms, specific examples thereof have been shown in the accompanying drawings and described in detail herein. However, it should be understood that the embodiments are not limited to the specific forms or methods disclosed; rather, the embodiments are intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the various embodiments described and the appended claims. Furthermore, any specific feature, aspect, method, property, characteristic, quality, attribute, element, etc. disclosed herein in connection with an embodiment or example can be used in all other embodiments or examples described herein. None of the methods disclosed herein need be performed in the order recited. The methods disclosed herein may include certain actions taken by the practitioner; however, these methods may also include any third-party indication of these actions, whether express or implied. The ranges disclosed herein also include any and all overlaps, sub-ranges, and combinations thereof. Language such as "up to," "at least," "greater than," "less than," "between," etc., includes the recited numbers. Numbers beginning with a term such as "about" or "approximately" are inclusive of the recited phrase and should be interpreted based on the circumstances (e.g., as accurate as reasonably possible under the circumstances, e.g., ±5%, ±10%, ±15%, etc.). For example, "about 3.5 mm" includes "3.5 mm." Phrases beginning with a term such as "substantially" are inclusive of the recited phrase and should be interpreted based on the circumstances (e.g., as accurate as reasonably possible under the circumstances). For example, "substantially constant" includes "constant." Unless otherwise noted, all measurements are made under standard conditions, including temperature and pressure.

[0114] As used herein, a phrase referring to "at least one of" a series of items refers to any combination of these items, including individual members. As an example, "at least one of A, B, or C" is intended to cover A, B, C, A and B, A and C, B and C, and A, B, and C. Unless specifically stated otherwise, joint language such as the phrase "at least one of X, Y, and Z" should be understood together with the context and is generally used to convey that an item, term, etc. can be at least one of X, Y, or Z. Therefore, such joint language is generally not intended to express that certain embodiments require that at least one of X, at least one of Y, and at least one of Z be present individually. The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the devices and methods disclosed herein.

[0115] Thus, the claims are not intended to be limited to the embodiments shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles and the novel features disclosed herein.

Claims

1. A component comprising: A reconstruction element having a front surface and a back surface, the reconstruction element comprising: a semiconductor die having a front side and a back side, the semiconductor die including a circuit device closer to the front side than to the back side and a via extending from the back side of the semiconductor die to connect to the circuit device; an insulating material disposed along a side surface of the semiconductor die; a power rail extending from the front surface to the back surface of the reconstruction element and configured to deliver power to the semiconductor die; and An interconnect structure is configured to electrically connect the power rail to the via and deliver power from the back side of the semiconductor die to the semiconductor die.

2. The assembly of claim 1, wherein the insulating material comprises an inorganic dielectric. The assembly of claim 2 , wherein the insulating material comprises silicon oxide. The assembly of claim 1 , wherein the insulating material comprises an organic dielectric. 5 . The assembly of claim 1 , wherein the interconnect structure comprises a redistribution layer disposed on the back surface of the reconstruction element.

6. The assembly of claim 1 wherein the interconnect structure comprises an interconnect element hybrid-bonded to the backside of the semiconductor die.

7. The assembly of claim 1, wherein the interconnect structure comprises one or more metallization layers.

8. The assembly of claim 1 , further comprising a power delivery die, wherein the power delivery die is hybrid bonded to the back surface of the reconstruction element.

9. The assembly of claim 8, wherein the power delivery die comprises a redistribution layer.

10. The assembly of claim 1, wherein the reconfiguration element further comprises an integrated voltage regulator.

11. The assembly of claim 1 , further comprising a dummy die, wherein the dummy die is directly bonded to the back surface of the reconstruction element.

12. The assembly of claim 1 , further comprising a second reconfiguration element, the second reconfiguration element comprising: Integrated voltage regulator; as well as integrated power delivery circuit device, wherein the second reconstruction element is hybrid-bonded to the reconstruction element.

13. The assembly of claim 12, further comprising a dummy die directly bonded to the second reconfiguration element.

14. The assembly of claim 12, further comprising a stack, wherein the stack includes a dummy die directly bonded to the second reconstruction element.

15. The assembly of claim 1 , further comprising: An integrated voltage regulator element is hybrid-bonded to the reconstruction element. 16 . The assembly of claim 1 , wherein the reconstruction element further comprises a dummy semiconductor element, wherein the power rail is provided in the dummy semiconductor element.

17. The assembly of claim 1 , wherein the reconfiguration element further comprises an integrated voltage regulator, The assembly further includes a power delivery die including one or more memory banks.

18. The assembly of claim 17, further comprising an optical input / output system coupled to the front surface of the reconstruction element.

19. The assembly of claim 1 , further comprising: a second reconfiguration element, hybrid-joined to said reconfiguration element, The second reconstruction element comprises: integrated power delivery circuit devices; one or more memory banks; and One or more integrated voltage regulators.

20. The assembly of claim 1, wherein the circuit device comprises one or more transistors.

21. The assembly of claim 1, wherein the semiconductor die has a thickness of less than 5 μm.

22. The assembly of claim 1, wherein the semiconductor die has a thickness of less than 1 μm.

23. The assembly of claim 1, wherein the semiconductor die is a logic die or a processor die.

24. An assembly comprising: Insulation materials; a power rail extending through the insulating material; an integrated device die at least partially embedded in the insulating material, the integrated device die having a front side and a back side, the integrated device die including a circuit arrangement closer to the front side than to the back side, and a power delivery structure extending from the back side of the integrated device die to connect to the circuit arrangement; as well as An interconnect structure is over the insulating material, the power rail, and the backside of the integrated device die, the interconnect structure configured to deliver power between the power rail and the power delivery structure at the backside of the integrated device die.

25. The assembly of claim 24, wherein the insulating material comprises an inorganic dielectric material.

26. The assembly of claim 24, further comprising a power delivery die hybrid bonded to the interconnect structure.

27. The assembly of claim 24, further comprising a dummy die, wherein the dummy die is directly bonded to the interconnect structure.

28. A method for forming a bonded structure with backside power delivery, the method comprising: forming an engagement surface on a rear surface of a reconstruction element, the reconstruction element having a front surface and a rear surface, The reconstruction element comprises: a semiconductor die having a front side and a back side, the semiconductor die including a circuit device closer to the front side than to the back side and a via extending from the back side of the semiconductor die to connect to the circuit device; an insulating material disposed along a side surface of the semiconductor die; a power rail extending from the front surface to the back surface of the reconstruction element and configured to deliver power to the semiconductor die; and an interconnect structure configured to electrically connect the power rail to the via and deliver power from the back side of the semiconductor die to the semiconductor die; and A second element is bonded directly to the bonding surface of the reconstruction element.

29. The method of claim 28, wherein the second component comprises an integrated voltage regulator.

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