Semiconductor laser chip

Abstract

Provided is a semiconductor laser chip which is not susceptible to malfunction even when the driving time is long. A wide-region semiconductor laser chip (chip 10) is provided with: a substrate (11); an active layer (13); and a current injection strip that injects a current into the active layer (13). Each of a pair of side surfaces of the chip is composed of a rough surface (1142, 1162) serving as a cleaving starting point and a cleaving surface (1141, 1161), grooves (G1, G2) penetrating through the active layer (13) are formed in a region between the rough surface (1142, 1162) and the current injection strip, and the distance between the grooves (G1, G2) and the side surfaces is 25 [mu] m or more.

Description

Technical Field

[0001] The present invention relates to a wide-area semiconductor laser chip. Background Art

[0002] High-output semiconductor laser chips exceeding 10W are known (see, for example, Figure 9 of Patent Document 1). Hereinafter, semiconductor laser chips will be referred to simply as chips. Such chips achieve high output by increasing the width of the current injection stripe, the electrode used to inject current into the active layer. Such chips are referred to as wide-area chips.

[0003] In mass production, these chips are manufactured in large quantities using a single wafer. The chips are arranged in a matrix on the main surface of the wafer during the manufacturing process. The wafer is then cleaved along the boundaries between adjacent chips, separating each chip from the others.

[0004] The typical dimensions of a chip are several mm in length along the long side and several hundred μm in length along the short side.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Laid-Open No. 9-36493

[0008] Patent Document 2: Japanese Patent Application Publication No. 2019-057671 Summary of the Invention

[0009] (1) Technical issues to be resolved

[0010] In paragraphs 0002 to 0006 of Patent Document 2, it is described that a scratch is formed on the wafer to form a starting point for cleaving the wafer; when the scratch is formed, a crack may be generated in the crystal from the starting point of cleaving. Based on this, the abstract and paragraph 0007 of Patent Document 2 describe that by providing a groove 44 (see Patent Document 2), Figure 1 ), even if cracks occur in the rough surface region 58, their propagation is prevented in the groove 44 which is deeper than the active layer 32, thereby preventing the active layer 32 from being affected.

[0011] However, when the inventors of the present application attempted to apply the technology of Patent Document 2 to a wide-area chip, they discovered that the chip might fail if driven for a long time (eg, several thousand to tens of thousands of hours).

[0012] One embodiment of the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a chip that is less likely to malfunction than conventional chips even when driven for a long time.

[0013] (2) Technical solution

[0014] To address the aforementioned issues, one embodiment of the present invention is a wide-area chip comprising: a substrate, an active layer laminated on the substrate, and current injection bars for injecting current into the active layer. This chip employs the following structure: the chip comprises a pair of principal surfaces, a reflective end facet, an emitting end facet, and a pair of side surfaces. Each of the pair of side surfaces comprises a roughened surface that serves as a starting point for cleavage and a cleaved surface. When the principal surface of the active layer is viewed from a direction normal to the principal surface, a groove is formed along the side surface in the region between the roughened surface and the current injection bar. The groove penetrates the active layer, and the spacing between the groove and each side surface is 25 μm or greater.

[0015] To address the aforementioned issues, one embodiment of the present invention is a wide-area chip comprising: a substrate; an active layer laminated on the substrate; a high-reflection film and a low-reflection film that together with the active layer form a resonator; and a current injection bar for injecting current into the active layer. This chip employs the following structure: the chip has a pair of principal surfaces, a reflective end facet, an emitting end facet, and a pair of side surfaces. Each of the pair of side surfaces is composed of a roughened surface and a cleaved surface that serve as cleavage starting points. When the principal surface of the active layer is viewed from a direction normal to the principal surface, a step region is formed along the side surface between the roughened surface and the current injection bar. The active layer is formed to different depths in the step region and in areas outside the step region. The distance between the step region and each of the side surfaces is 25 μm or greater.

[0016] (3) Beneficial effects

[0017] The chip according to one embodiment of the present invention can be less likely to malfunction than conventional chips even when driven for a long time. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a perspective view of a chip according to one embodiment of the present invention.

[0019] Figure 2 (a) is Figure 1 The top view of the chip shown, (b) is Figure 1 A cross-sectional view of the chip is shown.

[0020] Figure 3 yes Figure 1 A cross-sectional view of a modified example of the chip shown.

[0021] Figure 4 (a) to (f) represent Figure 1 A cross-sectional view of a chip manufacturing method is shown.

[0022] Figure 5 Yes means through Figure 4 A top view of multiple chips manufactured by the manufacturing method shown.

[0023] Figure 6 (a) to (c) represent Figure 3 A cross-sectional view of a chip manufacturing method is shown. DETAILED DESCRIPTION

[0024] [Chip Overview]

[0025] The semiconductor laser chip (corresponding to the "semiconductor laser chip" in the claims) of one embodiment of the present invention is what is called a wide-area chip. Examples of wide-area chips include excitation of YAG solid crystals and excitation of ytterbium-doped optical fibers. When exciting YAG solid crystals, the chip is designed so that the central wavelength of the laser is, for example, 808 nm. Furthermore, when exciting ytterbium-doped optical fibers, the chip is designed so that the central wavelength of the laser is, for example, 976 nm. However, the central wavelength of the laser of the chip of one embodiment of the present invention is not limited to these and can be appropriately designed according to the application, etc.

[0026] Chip Structure

[0027] Reference Figure 1 as well as Figure 2 A chip 10 according to one embodiment of the present invention will be described. Figure 1 is a perspective view of the chip 10 . Figure 2 (a) is a top view of the chip 10, Figure 2 (b) is a cross-sectional view of the chip 10 . Figure 2 The top view (a) is a top view of the chip 10, viewed from the direction normal to the principal surface of the active layer 13 (the principal surface of the pair of principal surfaces facing away from the substrate 11). In the following, unless otherwise specified, the term "top view" refers to a view from the direction normal to the principal surface of the active layer 13. Figure 2 (b) is along Figure 2 The cross section is taken along the line AA′ shown in FIG. 1 (a), and is a cross-sectional view obtained on a cross section parallel to the normal line to the main surface of the active layer 13 .

[0028] exist Figure 1 as well as Figure 2 In the chip 10 shown, the structures of the n-type layer 12 and the p-type layer 14 are simplified. For more detailed structures of the n-type layer 12 and the p-type layer 14 in the chip 10, refer to Figure 4 This will be described later. Figure 2 In the figure, the strain suppression layer 20 is omitted.

[0029] like Figure 1 As shown, the chip 10 includes a substrate 11, an n-type layer 12, an active layer 13, a p-type layer 14, a dielectric layer 15, an electrode layer 16, and an electrode layer 17. In addition, the chip 10 further includes a strain suppression layer 20 formed on the upper layer of the electrode layer 16. Figure 2 As shown in (a) of FIG, the chip 10 further includes a low-reflection film 18 and a high-reflection film 19. However, the strain suppression layer 20 may be omitted.

[0030] The chip 10 uses 4 mm as the total length of the current injection bar 161 described later, that is, the length L (see Figure 2 (a)). That is, the resonator length in the chip 10 is 4 mm. In addition, the chip 10 is the width W1 of the current injection strip 161 described later (see Figure 2 (b)) A wide-area chip with a width of 75 μm or greater throughout the entire region. The wide-area chip 10 can emit laser light with an output of 10 W or greater. Furthermore, the minimum value of the width W1 of the current injection bar 161 is not limited to 75 μm, and similarly, the output of the chip 10 is not limited to 10 W. In this embodiment, reference to the laser output of the chip 10 refers to the maximum output of the chip 10. In this embodiment, the chip resonator length and width W1 are 4 mm and 220 μm, respectively, resulting in an output exceeding 20 W. In one embodiment of the chip 10, if the heat generated in the chip 10 during operation is sufficiently dissipated, a laser beam of 13 W can be stably emitted per 100 μm width W1. That is, when the width W1 is 220 μm, by selecting the length L within the range of approximately 4 mm to 6 mm, a laser beam with an output of approximately 25 W to 28 W can be stably emitted.

[0031] <Substrate>

[0032] The substrate 11 is a plate-shaped member made of a single crystal semiconductor. The substrate 11 includes flat main surfaces 111 and 112 (see Figure 2 (b)). In addition, the substrate 11 includes a pair of end faces, namely, end faces 113 and 115 (see Figure 1 as well as Figure 2 (a)) and a pair of side surfaces, namely side surfaces 114 and 116 (refer to Figure 1 as well as Figure 2 (a)).

[0033] In this embodiment, the end face 113, the side face 114, the end face 115, and the side face 116 are each obtained by cleaving a wafer made of a semiconductor single crystal. Here, the side face 114 includes a cleavage face 1141 formed by cleavage and a rough surface 1142 caused by a scratch that serves as a starting point for cleavage (see Figure 1 as well as Figure 2 ). Similarly, the side surface 116 includes a cleavage surface 1161 formed by cleavage and a rough surface 1162 caused by the scratch that serves as the starting point of cleavage (see Figure 2 ). In addition, Figure 1 In FIG, the rough surface 1142 is shown as a region. However, in Figure 2 In (a) and (b), the rough surface 1142 is shown as a thick line segment. Figure 1 、 Figure 2 (a) and Figure 2 In (b), the rough surface 1162 is illustrated as a thick line segment.

[0034] In this embodiment, GaAs is used as the semiconductor constituting the substrate 11. However, the semiconductor constituting the substrate 11 can be selected as appropriate.

[0035] On one main surface of the substrate 11, Figure 1 as well as Figure 2 In (b), electrode layer 17 is formed on the lower main surface 111. Electrode layer 17 is a metal thin film formed to cover main surface 111. In this embodiment, a three-layer film of Ni / Ge / Au is used as electrode layer 17. However, electrode layer 17 is not limited to this.

[0036] On the other main surface of the substrate 11, Figure 1 as well as Figure 2 In (b), the main surface 112 located on the upper side has the n-type layer 12 , the active layer 13 , the p-type layer 14 , the dielectric layer 15 , and the electrode layer 16 stacked in this order.

[0037] <n-type layer>

[0038] The n-type layer 12 is composed of an n-type semiconductor. Examples of n-type semiconductors constituting the n-type layer 12 include GaAs-based semiconductors (e.g., AlGaAs). The n-type layer 12 may also have a multilayer structure, with each layer composed of a different type of n-type semiconductor. In this case, each layer of the n-type layer 12 may have different functions, such as a layer functioning as a buffer layer, a layer functioning as a cladding layer, and a layer functioning as a guide layer.

[0039] Active layer

[0040] The active layer 13 is made of a semiconductor. Examples of the semiconductor that makes up the active layer 13 include GaAs-based semiconductors (eg, InGaAs).

[0041] <p-type layer>

[0042] The p-type layer 14 is composed of a p-type semiconductor. Examples of p-type semiconductors constituting the p-type layer 14 include GaAs-based semiconductors (e.g., AlGaAs). The p-type layer 14 may also have a multilayer structure, with each layer composed of a different type of p-type semiconductor. In this case, each layer of the p-type layer 14 may have different functions, such as a layer functioning as a guide layer, a layer functioning as a cladding layer, and a layer functioning as a contact layer.

[0043] <Dielectric layer>

[0044] like Figure 1 as well as Figure 2 As shown in (b), the dielectric layer 15 is formed on the main surface opposite to the active layer 13 of the pair of main surfaces of the p-type layer 14 (in Figure 2 A dielectric thin film is provided (the main surface is located on the upper side in (b)). Dielectric layer 15 is interposed between electrode layer 16 and active layer 13 to separate them. Dielectric layer 15 is provided to define a region where current can be injected from electrode layer 16 into active layer 13.

[0045] The dielectric layer 15 is made of a dielectric. Examples of dielectrics that constitute the dielectric layer 15 include SiO2, SiN, and Al2O3. The dielectric layer 15 has an opening 151 formed therein to limit the area through which the current injected from the electrode layer 16 flows (see FIG. 1 ). Figure 2 In this embodiment, when the main surface of the dielectric layer 15 (the main surface of the pair of main surfaces on the side away from the substrate 11) is viewed from above, the shape of the opening 151 is a rectangle (see Figure 2 (a)). However, the shape of the opening 151 is not limited to a rectangle as long as it is a strip extending in one direction.

[0046] <Electrode layer>

[0047] Electrode layer 16 is a metal thin film formed to cover the principal surface of the pair of principal surfaces of p-type layer 14, the principal surface opposite to active layer 13. In this embodiment, a two-layer film of Ti / Au is used as electrode layer 16. However, electrode layer 16 is not limited to this.

[0048] Electrode layer 16 and electrode layer 17 function as an electrode pair that allows current to flow through active layer 13. In the following text, when looking down at the principal surface of electrode layer 16 (the principal surface of the pair of principal surfaces opposite to dielectric layer 15), the region where current is injected into active layer 13 is referred to as current injection stripe 161. Specifically, when looking down at the principal surface of electrode layer 16, the region that overlaps with opening 151 and where current is injected into active layer 13 is referred to as current injection stripe 161. Therefore, current injection stripe 161 also includes the region of p-type layer 14 between electrode layer 16 and active layer 13 that overlaps with opening 151.

[0049] <Reflective film>

[0050] like Figure 2 As shown in (a) of FIG. 1 , in the chip 10 , a pair of reflective films corresponding to each of the pair of end faces constituting the resonator are formed. Figure 2 As shown in (a), one of the pair of end faces of the chip 10 that constitute the resonator (in Figure 2 A low reflection film 18 is formed on the lower end face in (a) and a low reflection film 18 is formed on the other end face ( Figure 2 A high-reflection film 19 is formed on the upper end face of (a). That is, the interval between the low-reflection film 18 and the high-reflection film 19 corresponds to the resonator length of the chip 10. The end face formed with the low-reflection film 18 is the emission end face, and the end face formed with the high-reflection film 19 is the reflection end face. In addition, the reflectivity of the low-reflection film 18 to the light of the oscillation wavelength is lower than the reflectivity of the high-reflection film to the same light. In addition, Figure 1 In the figure, the low reflection film 18 and the high reflection film 19 are omitted.

[0051] The reflectivity of each of the high-reflection film 19 and the low-reflection film 18 can be appropriately set according to the design of the chip 10. The structures of each of the high-reflection film 19 and the low-reflection film 18 can be appropriately selected from existing structures. For example, as the low-reflection film 18 having a relatively low reflectivity, a single layer of Al2O3, AlN, Si, SiO2, TiO2, or the like, or a multilayer film composed of these materials can be used. Alternatively, as the high-reflectivity film 19 having a relatively high reflectivity, a multilayer film obtained by repeatedly laminating two layers of these materials can be used.

[0052] Thus, of the pair of end faces of the chip 10 , the end face formed with the high reflection film 19 functions as a reflection end face for reflecting light propagating in the resonator, and the end face formed with the low reflection film 18 functions as an emission end face for emitting laser light.

[0053] <Strain suppression layer>

[0054] The strain suppression layer 20 is formed on the main surface of the electrode layer 16 on the side opposite to the active layer 13 (in the pair of main surfaces). Figure 1 The strain suppression layer 20 covers the current injection strip 161 in the electrode layer 16 and the area surrounding the current injection strip 161. Figure 2 In the figure, the strain suppression layer 20 is omitted.

[0055] In this embodiment, the strain suppression layer 20 is formed using a plating method. However, the method for forming the strain suppression layer 20 is not limited to plating. The method for forming the strain suppression layer 20 can be appropriately selected from methods that can form a film of a desired thickness (e.g., 2 μm, 3 μm, etc.). Examples of methods for forming the strain suppression layer 20 other than plating include sputtering.

[0056] The strain suppression layer 20 is interposed between the electrode layer 16 and the solder layer to suppress strain that may be generated in the chip when the chip 10 is mounted on a base using solder, for example.

[0057] <Main surface, end surface, and side surface of the chip>

[0058] As described above, chip 10 includes: substrate 11; active layer 13 laminated on main surface 112 of substrate 11 via n-type layer 12; high-reflection film 19 and low-reflection film 18, which together with active layer 13 form a resonator; and current injection bar 161 for injecting current into active layer 13. Chip 10 has a pair of main surfaces 101 and 102.

[0059] In addition, the chip 10 has a pair of side surfaces along the propagation direction of light in the resonator. The main part of the pair of side surfaces is composed of a pair of side surfaces 114 and 116 of the substrate 11. However, the pair of side surfaces of the n-type layer 12, the active layer 13, the p-type layer 14, the dielectric layer 15, and the electrode layer 16 are also included in the pair of side surfaces of the chip 10. In addition, in the pair of side surfaces, the region where the rough surface 1142 and 1162 is formed extends from the main surface 102 not only to the side surfaces of the electrode layer 16, the dielectric layer 15, the p-type layer 14, the active layer 13, and the n-type layer 12, but also to the pair of side surfaces 114 and 116 (see Figure 2 (b)).

[0060] Furthermore, the chip 10 has an end facet for reflecting propagating light (i.e., a reflection end facet) and an end facet for emitting a portion of the propagating light (i.e., an emission end facet) within the resonator. The emission end facet and the reflection end facet primarily consist of a pair of end faces 113 and 115 of the substrate 11. However, the end faces of the n-type layer 12, active layer 13, p-type layer 14, dielectric layer 15, and a pair of electrode layers 16 are also included in the emission end facet and the reflection end facet.

[0061] <Slot>

[0062] The chip 10 has grooves G1 and G2 (see Figure 2 (b)).

[0063] In a plan view, a groove G1 is formed along the side surface 114 in the region between the rough surface 1142 of the side surface 114 and the current injection bar 161. Similarly, in a plan view, a groove G2 is formed along the side surface 116 in the region between the rough surface 1162 of the side surface 116 and the current injection bar 161.

[0064] The groove G1 and the groove G2 have a shape extending from the main surface 102 of the pair of main surfaces 101 and 102 of the chip 10 toward the inside of the semiconductor layer constituting the chip 10. Figure 2 As shown in (b), the grooves G1 and G2 penetrate the p-type layer 14 and the active layer 13. In the chip 10, the main surface 101 is the main surface on the main surface 111 side, and the main surface 102 is the main surface on the main surface 112 side.

[0065] like Figure 2 As shown in (a) and (b), chip 10 is linearly symmetrical about an axis that passes through the center axis of current injection bar 161 and is perpendicular to the main surface of active layer 13. Therefore, slots G1 and G2 are linearly symmetrical. The following description uses slot G1 as an example to illustrate the slot structure. However, the same structures as those for slot G1 also apply to slot G2.

[0066] like Figure 2 As shown in (b), the width of groove G1 is referred to as width W2, the distance between groove G1 and current injection bar 161 is referred to as width W3, and the distance between groove G1 and side surface 114 is referred to as width W4. In chip 10, width W4 is 25 μm or greater. Furthermore, in chip 10, width W3 is preferably 30 μm or greater.

[0067] In this embodiment, 12 μm is used as the width W2 , 35 μm is used as the width W3 , and 43 μm is used as the width W4 .

[0068] like Figure 2 As shown in (a), when looking down at the main surface 102 of the chip 10, the groove G1 is formed in the region between the emitting end face of the chip 10 and the reflecting end face of the chip 10. Both ends of the groove G1, namely, ends G11 and G12, are located between the emitting end face of the chip 10 and the reflecting end face of the chip 10. Ends G11 and G21 are separated from the reflecting end face 115 by a width of W5. Furthermore, ends G12 and G22 are separated from the emitting end face 113 by a width of W5. In other words, each of ends G11 and G12 does not reach either the emitting end face of the chip 10 or the reflecting end face of the chip 10.

[0069] <Chip Variation Example>

[0070] Reference Figure 3 A chip 30, which is a modified example of the chip 10, is described. The chip 10 has grooves G1 and G2 ( Figure 2 (b)). In contrast, the chip 30 has the step region S1 and the step region S2. In this modification, the differences between the chip 10 and the chip 30 will be described.

[0071] In chip 10, reference numerals starting with 1 are used to designate the components of chip 10. In contrast, in chip 30, components corresponding to components of chip 10 are designated with reference numerals starting with 3. For example, substrate 31, n-type layer 32, active layer 33, and p-type layer 34 of chip 30 correspond to substrate 11, n-type layer 12, active layer 13, and p-type layer 14 of chip 10, respectively. Furthermore, side surfaces 314 and 316 of chip 30 correspond to side surfaces 114 and 116 of chip 10, respectively. Furthermore, cleavage surface 3141 and rough surface 3142 of chip 30 correspond to cleavage surface 1141 and rough surface 1142 of chip 10, respectively.

[0072] When viewed from above, two grooves are formed on one main surface of the substrate 31 of the chip 30, corresponding to the areas where the grooves G1 and G2 of the chip 10 are formed. An n-type layer 32, an active layer 33, a p-type layer 34, and an electrode layer 36 are stacked on the main surface of the substrate 31 where the grooves are formed. Furthermore, a barrier layer 35 is embedded in the p-type layer 34. The barrier layer 35 corresponds to the dielectric layer 15 in the chip 10 and is provided to limit the area where current can be injected from the electrode layer 36 into the active layer 33. Like the dielectric layer 15, the barrier layer 35 is made of a semiconductor or dielectric having a lower conductivity than the p-type semiconductor constituting the p-type layer 34. An example of a material constituting the barrier layer 35 is n-type GaAs.

[0073] The barrier layer 35 has an opening 351 (see FIG. 1 ) formed therein to limit the region through which the current injected from the electrode layer 36 flows. Figure 3 ). Opening 351 and Figure 2 The opening 151 shown in the figure. When looking down at the principal surface of the electrode layer 36 (the principal surface of the pair of principal surfaces opposite to the barrier layer 35), the region where current is injected into the active layer 33 is referred to as a current injection stripe 361. Specifically, when looking down at the principal surface of the electrode layer 36, the region that overlaps with the opening 351 and where current is injected into the active layer 33 is referred to as the current injection stripe 361. Therefore, the current injection stripe 361 also includes the region of the p-type layer 34 between the electrode layer 16 and the active layer 13 that overlaps with the opening 351.

[0074] Thus, in the chip 30, the semiconductor layers of the n-type layer 32, the active layer 33, and the p-type layer 34 are stacked on the main surface 312 of the substrate 31 having the grooves formed therein, and thus step regions S1 and S2 are formed in each semiconductor layer (see FIG. Figure 3 The active layer 33 is formed to different depths in each of the step region S1 and the step region S2, and in regions other than the step region S1 and the step region S2.

[0075] Furthermore, when viewed from above, the areas where step regions S1 and S2 are formed in chip 30 are identical to the areas where grooves G1 and G2 are formed in chip 10. Specifically, taking step region S1 as an example, when viewed from above, step region S1 is formed between the rough surface 3142 of side surface 314 and current injection bar 361, and the distance W4 between step region S1 and side surface 314 is greater than 25 μm. Furthermore, when viewed from above, step region S1 is formed between the reflective end facet and the emitting end facet, with both ends of step region S1 not reaching either reflective end facet or emitting end facet. Furthermore, the distance between step region S1 and current injection bar 361, or width W3, is greater than 30 μm.

[0076] In addition, although the step region S1 is described as an example here, the same applies to the step region S2 .

[0077] Chip Manufacturing Method

[0078] Reference Figure 4 as well as Figure 5 The manufacturing method of the chip 10 is described. In the description of this manufacturing method, Figure 1 as well as Figure 2 A specific example of the chip 10 is shown. Figure 4 (a) to (f) are cross-sectional views showing a specific example of a method for manufacturing the chip 10. This method includes a stacking step, a first etching step, a second etching step, a barrier layer forming step, a first electrode layer stacking step, a second electrode layer stacking step, and a cleaving step. Figure 5 1 is a plan view showing a plurality of chips 10 manufactured on a wafer W by the present manufacturing method.

[0079] Figure 4 (a) shows substrate 11 after the lamination step. The lamination step involves laminating buffer layer 121, n-type cladding layer 122, n-type guide layer 123, active layer 13, p-type guide layer 141, p-type cladding layer 142, and p-type contact layer 143 on primary surface 112 of substrate 11. In this manufacturing method, these layers are laminated using MOCVD.

[0080] The buffer layer 121, the n-type cladding layer 122, and the n-type guide layer 123 correspond to Figure 1 as well as Figure 2 The n-type layer 12 shown. In addition, the p-type guide layer 141 and the p-type cladding layer 142 correspond to the p-type contact layer 143 described later. Figure 1 as well as Figure 2 The p-type layer 14 is shown.

[0081] In this manufacturing method, a GaAs plate-shaped member is used as the substrate 11. In addition, GaAs is used as the material constituting the buffer layer 121, and Al is used as the material constituting the buffer layer 121. x1 Ga 1-x1 As is the material constituting the n-type cladding layer 122, Al x2 Ga 1-x2 As is used as the material constituting the n-type guide layer 123, undoped InGaAs is used as the material constituting the active layer 13, and Al is used as the material constituting the n-type guide layer 123. x3 Ga 1-x3 As is the material constituting the p-type guide layer 141, Al x4 Ga 1-x4 As is used as the material constituting the p-type cladding layer 142, and GaAs is used as the material constituting the p-type contact layer 143. Here, x1>x2, x4>x3. The composition and film thickness of the active layer 13 can be appropriately adjusted to obtain a desired oscillation wavelength.

[0082] Figure 4 (b) shows the state of the substrate 11 after the first etching process is performed. In the first etching process, first, a photoresist is applied on the p-type contact layer 143, and a photomask 401 corresponding to the current injection bar 161 is formed using a photolithography method. Then, etching is performed until the thickness of the p-type contact layer 143 is reduced to about half. By performing the first etching process, a ridge structure in which the area corresponding to the current injection bar 161 is raised is obtained. In the first etching process, etching can be performed using a tartaric acid / hydrogen peroxide mixture, a sulfuric acid / hydrogen peroxide mixture, or a chlorine-based dry etching method. In addition, an etching stop layer can be provided in the epitaxial layer in advance to specify the amount of wet etching.

[0083] Figure 4(c) shows the substrate 11 after the second etching step. After removing photomask 401 using an organic solvent, photoresist is applied to the p-type contact layer 143, and photolithography is used to form a photomask 402 with openings corresponding to grooves G1 and G2. Etching is then performed until grooves G1 and G2 are formed, penetrating the p-type layer 14, which is composed of the p-type guide layer 141, the p-type cladding layer 142, and the p-type contact layer 143. Grooves G1 and G2 only need to penetrate the active layer 13 and the p-type layer 14. The depth of etching the n-type layer 12, which is composed of the buffer layer 121, the n-type cladding layer 122, and the n-type guide layer 123, can be determined as appropriate. The second etching step forms grooves G1 and G2.

[0084] Figure 4 (d) shows the state of the substrate 11 after the barrier layer forming process is performed. After removing the photomask 402 using an organic solvent, a dielectric layer 15 composed of SiN is formed on the p-type contact layer 143 by the PCVD method. Then, in the same manner as the first etching process and the second etching process, an opening 151 is formed on the dielectric layer 15 using photolithography and etching. Then, the photomask formed on the dielectric layer 15 is removed using an organic solvent. By performing the barrier layer forming process, all areas other than the opening 151 are covered by the dielectric layer 15. In addition, the etching or removal of the dielectric film constituting the dielectric layer 15 can be performed using dry etching such as HF and F series, stripping based on a photoresist, etc., depending on the etching characteristics of the dielectric constituting the dielectric film. For example, in the case where the dielectric is SiO2 or SiN, dry etching can be used. On the other hand, when using a dielectric that cannot be removed by the aforementioned dry etching, it is possible to form an opening 151 by placing a mask made of a photoresist or a soluble material at the desired position before forming the dielectric layer 15. Then, the dielectric layer 15 is formed and the mask is dissolved. Alternatively, after forming the opening 151 in the barrier layer formation step, the p-type contact layer 143 exposed from the opening 151 may be subjected to a surface treatment. An example of such a surface treatment is shallow etching using an inorganic acid.

[0085] Figure 4 (e) shows the substrate 11 after the first electrode layer lamination step. In the first electrode layer lamination step, an electrode layer 16 composed of Ti / Pt / Au is formed on the dielectric layer 15 having the opening 151 formed therein. Alternatively, a strain suppression layer 20 composed of Au may be formed on the electrode layer 16 during the first electrode layer lamination step. The strain suppression layer 20 can be formed using plating or photolithography.

[0086] Figure 4(f) shows the substrate 11 after the second electrode layer stacking process. In the second electrode layer stacking process, after grinding and polishing the main surface 111 of the substrate 11 to adjust the thickness, an electrode layer 17 composed of Ni / Ge / Au is formed, and heat treatment is performed. The method of forming the electrode layer 17 can be selected from existing film forming methods such as electron beam evaporation method, sputtering method, etc. In addition, the temperature of the heat treatment can also be appropriately selected, and 400 °C can be cited as an example. In addition, after forming the electrode layer 17, a metallization layer (Japanese: メタライズ層) (for example, Ti / Pt / Au) with the surface being Au can also be provided. By providing the metallization layer, the wire bonding property when mounted on a pedestal, an external electrode, etc. can be improved.

[0087] Figure 5 is a top view of a plurality of chips 10 manufactured on the wafer W. Figure 5 The double-dashed line shown indicates the boundary between adjacent chips 10. Figure 5 Each chip 10 shown corresponds to the chip 10 shown in Figure 2 (a). In Figure 5 , the grooves G1, the groove G2, and the strain suppression layer 20 are shown by solid lines, and the current injection bars 161 located below the strain suppression layer 20 are shown by dashed lines. In addition, in Figure 5 , a total of 18 chips 10 constituting three laser bars are shown. In addition, in Figure 5 , a part of the substrate S (the region including three laser bars) is shown in an enlarged view. More laser bars are provided on the main surface of the substrate S.

[0088] The chip 10 is divided and diced at the position of the double-dashed line shown in Figure 5 . In the dicing process, first, the wafer W is diced at the position of the double-dashed line corresponding to the boundary between the emission end surface and the reflection end surface of adjacent chips 10 (the double-dashed line extending in the left-right direction in Figure 5 ) to obtain the emission end surface and the laser bar with 115 exposed. At this time, as long as the scratch mark that is the starting point of the dicing is located outside the region of the chips 10 arranged in the column direction. By this dicing, a pair of end surfaces of the chip 10 are formed.

[0089] Next, a low-reflection film 18 is formed on the cleavage surface constituting the emission end face of the chip 10, and a high-reflection film 19 is formed on the cleavage surface constituting the reflection end face of the chip 10. The reflectivity of each of the low-reflection film 18 and the high-reflection film 19 can be freely selected according to the design of the chip 10. Specifically, by combining a single-layer film or a multilayer film of about two layers of Al2O3, AlN, Si, SiO2, TiO2, etc., a low-reflection film 18 with a desired reflectivity can be achieved. The reflectivity of the low-reflection film 18 can be appropriately designed, and as a typical example, a reflectivity of not less than 0.5% and not more than 5% can be cited. In addition, by repeatedly stacking a double-layer film selected from Al2O3, AlN, Si, SiO2, TiO2, etc., a high-reflection film 19 with a high reflectivity close to 100% can be achieved.

[0090] Next, each chip 10 is cleaved from the laser bar on which the low reflection film 18 and the high reflection film 19 are formed, and the chips are formed into chips. Figure 5 A very short scratch is made in the middle of the emitting end face and the reflecting end face (shown as a two-dot chain line extending vertically in the figure), thereby cleaving each chip 10 from the laser bar. The scratched portion corresponds to the rough surface 1142 and the rough surface 1162 of the chip 10 after chipping. This cleavage forms a pair of side faces of the chip 10.

[0091] Cleaving is possible even if the length of the scribe line is approximately the same as the resonator length of the chip 10. However, since the number of chips 10 to be cleaved is orders of magnitude greater than the number of rows of laser bars, increasing the length of the scribe line increases costs in terms of both production cycle time and scribe point life, and is therefore not preferred.

[0092] On the rough surface 1142 and the rough surface 1162, damage remains due to the disorder of the crystal structure, the stress at the beginning of cleavage, etc. This damage is likely to become a major cause of slip when the driving time is long. Therefore, when looking down at the main surface 102 of the chip 10, it is preferred that the grooves G1 and G2 are longer than the rough surface 1142 and the rough surface 1162 in the length direction of the resonator, and the two ends of the rough surface 1142 and the rough surface 1162 are respectively located at a position closer to the inside than the two ends of the groove G1 and the groove G2, that is, the end G11, G12 and the end G21, G22 (see FIG. Figure 2 (a)). This is also the case with the chip 30. That is, when looking down at the main surface 302 of the chip 30 (see Figure 3), it is preferred that the step region S1 and the step region S2 are longer than the rough surface 3142 and the rough surface 3162 in the length direction of the resonator, and the respective ends of the rough surface 3142 and the rough surface 3162 are located at positions closer to the inside than the ends of the step region S1 and the step region S2. In addition, the damage caused by the scratches can reach the deep part (near the main surface 112) of the semiconductor layers (n-type layer 12, active layer 13 and p-type layer 14) constituting the chip 10. Therefore, when the driving time is long, the slip may also spread from a deeper position of the semiconductor layer toward the active layer. In order to prevent such slip from spreading from a deeper position, the width W4 (see Figure 2 (b)) is 25 μm or more.

[0093] [Second specific example of chip]

[0094] Reference Figure 6 A second specific example of the chip 10 will be described. Figure 6 (a) to (c) are cross-sectional views showing a method of manufacturing a second specific example of the chip 10. This specific example is Figure 3 A specific example of the chip 30 is shown.

[0095] In this manufacturing method, before the lamination step is performed, a groove G31 and a groove G32 are formed on the main surface 312 of the substrate 31. The groove G31 is formed in a region corresponding to the step region S1, and the groove G32 is formed in a region corresponding to the step region S2 (see FIG. Figure 6 (a)). The grooves G31 and G32 are formed by combining photolithography and etching.

[0096] Figure 6 (b) shows the substrate 31 after the lamination step. The lamination step involves laminating a buffer layer 321, an n-type cladding layer 322, an n-type guide layer 323, an active layer 33, a p-type guide layer 341, a p-type cladding layer 342, a p-type contact layer 343, and a barrier layer 350 on the main surface 312 of the substrate 31. The buffer layer 321, n-type cladding layer 322, n-type guide layer 323, active layer 33, p-type guide layer 341, p-type cladding layer 342, p-type contact layer 343, and barrier layer 350 correspond to the buffer layer 121, n-type cladding layer 122, n-type guide layer 123, active layer 13, p-type guide layer 141, p-type cladding layer 142, p-type contact layer 143, and dielectric layer 15 of the chip 10, respectively. Therefore, the film formation methods thereof are omitted.

[0097] like Figure 6 As shown in (b), by performing the lamination process, the step region S1 and the step region S2 are formed.

[0098] Then, the barrier layer 35 is formed by forming an opening 351 in the barrier layer 350, and the electrode layer 36 is formed thereon to obtain the chip 30 (see FIG. Figure 6 (c)). The barrier layer 35 corresponds to the dielectric layer 15 of the chip 10 , the opening 351 corresponds to the opening 151 of the chip 10 , and the electrode layer 36 corresponds to the electrode layer 16 of the chip 10 .

[0099] 〔Summarize〕

[0100] A semiconductor laser chip (chip) according to a first embodiment of the present invention is a wide-area semiconductor laser chip comprising: a substrate, an active layer laminated on the substrate, and a current injection bar for injecting current into the active layer. This semiconductor laser chip employs the following structure: the semiconductor laser chip comprises a pair of principal surfaces, a reflection end facet, an emission end facet, and a pair of side surfaces. Each of the pair of side surfaces comprises a roughened surface serving as a starting point for cleavage and a cleaved surface. When the principal surface of the active layer is viewed from a direction normal to the principal surface, a groove is formed along the side surface in a region between the roughened surface and the current injection bar. The groove penetrates the active layer, and the spacing between the groove and each side surface is 25 μm or greater.

[0101] The reason why semiconductor laser chips are prone to failure when the drive time is long is not limited to the cracks described in Patent Document 2. As a factor of this failure, slip extending from the starting point of cleavage (i.e., the rough surface mentioned above) can also be considered. The slip that causes the failure can be regarded as a dislocation loop extending linearly on the slip plane parallel to the cleavage plane. The slip is believed to be slowly moving toward the light-emitting portion (the area in the active layer that overlaps with the current injection bar). Therefore, when the drive time is long, the failure occurs due to the slip reaching the light-emitting portion.

[0102] After analyzing a semiconductor laser chip driven for a long time, the inventors of the present application obtained the following findings regarding slip.

[0103] (1) There are also semiconductor laser chips that do not slip even when driven for a long time. In these semiconductor laser chips, malfunctions caused by long driving times rarely occur.

[0104] (2) Slip occurs at various depths in the rough surface formed on each side surface of the semiconductor laser chip. Furthermore, the rough surface extends from the surface layer of the semiconductor laser chip to the substrate.

[0105] (3) Slip tends to propagate toward the free surface, i.e., the surface layer of the semiconductor laser chip. However, due to the strong strain in the active layer, slip that reaches the active layer is easily captured directly by the active layer.

[0106] (4) Since slip has the characteristics of (3) above, slip generated on the substrate side of the active layer spreads toward the surface of the semiconductor laser chip, but crosses the active layer along the way. There is a high possibility that such slip will directly spread within the active layer where it is trapped, and even reach the light-emitting portion.

[0107] The inventors of this application have found that even slip starting from a deep layer close to the substrate will mostly be captured by the active layer during the expansion of 25μm and observed as a dark slip line. According to the above structure, since grooves are provided at positions with an interval of more than 25μm from each side surface, the slip captured by the active layer can be released from the free surface, i.e., the side surface of the groove. Therefore, according to the above structure, even in the case of slip generated as the driving time is long, further expansion of the slip can be prevented at the groove, thereby suppressing the slip from passing through the groove and the substrate and reaching the light-emitting portion. Therefore, in the present semiconductor laser chip, even in the case of a long driving time, failure is less likely to occur than in the past.

[0108] In addition, in the semiconductor laser chip of the second embodiment of the present invention, in addition to the structure of the semiconductor laser chip of the first embodiment described above, the following structure is adopted: in the resonator, the end face for reflecting the light and the end face for emitting the light are respectively used as the reflection end face and the emission end face, and when the main surface of the active layer is viewed from the normal direction of the main surface of the active layer, the groove is formed in the area between the reflection end face and the emission end face, and both ends of the groove do not reach either the reflection end face or the emission end face.

[0109] In a semiconductor laser chip, the reflection end face and the emission end face are obtained by cleaving a wafer or substrate, respectively. In the process of cleaving a wafer or substrate, it is preferred that there are no discontinuous structures at the positions corresponding to the reflection end face and the emission end face, respectively. In the case where there are discontinuous structures at the positions corresponding to the reflection end face and the emission end face, respectively, steps are likely to be generated on the reflection end face and the emission end face, respectively, due to the offset generated in the crystal plane when the cleavage progresses. Such steps are unlikely to cause problems if they are generated in a manner that does not appear in the emission area for laser emission in the emission end face, but if they are generated in a manner that appears in the emission area, they are likely to cause COD failure (Catastrophic Optical Damage) of the semiconductor laser chip. This is also true for the reflection end face.

[0110] According to the above structure, during the process of cleaving a wafer or substrate, since discontinuous structures are not provided at the positions corresponding to the reflective end facet and the emitting end facet, respectively, the possibility of steps being generated on the reflective end facet and the emitting end facet can be reduced. Therefore, the yield rate when manufacturing semiconductor laser chips can be improved.

[0111] Furthermore, wide-area semiconductor laser chips have wide current injection stripes, which results in wide emission and reflection regions. Therefore, when steps occur, the likelihood of a step occurring in either the emission or reflection region is higher than in non-wide-area semiconductor laser chips. Therefore, the above-described structure is suitable for wide-area semiconductor laser chips.

[0112] A semiconductor laser chip according to a third aspect of the present invention adopts a structure in which, in addition to the structure of the semiconductor laser chip according to the first or second aspect, the interval between the groove and the current injection bar is 30 μm or greater.

[0113] In order to miniaturize semiconductor laser chips, it is urgently desired to narrow the width of the semiconductor laser chip (the distance between a pair of side surfaces). To this end, it is preferable to make the distance between the groove and the current injection bar close. On the other hand, the inventors found that if the distance between the groove and the current injection bar is too close, the refractive index distribution in the area where the laser propagates in the semiconductor laser chip will be affected by the groove. In this case, the shape of the beam spot of the emitted laser is deformed from the desired shape. In order to suppress the possible deformation of the beam spot, it is preferable that the distance between the groove and the current injection bar is 30μm or more.

[0114] A fourth aspect of the present invention is a wide-area semiconductor laser chip comprising a substrate, an active layer laminated on the substrate, a high-reflection film and a low-reflection film that together with the active layer form a resonator, and a current injection bar for injecting current into the active layer. This semiconductor laser chip has a structure in which the semiconductor laser chip has a pair of principal surfaces, a reflection end facet, an emission end facet, and a pair of side surfaces. Each of the pair of side surfaces comprises a roughened surface that serves as a starting point for cleavage and a cleaved surface. When the principal surface of the active layer is viewed from a direction normal to the principal surface, a step region is formed along the side surface between the roughened surface and the current injection bar. The active layer is formed to different depths in the step region and in areas other than the step region. The distance between the step region and each of the side surfaces is 25 μm or greater.

[0115] In the semiconductor laser chip of the first embodiment described above, a groove is formed through the active layer, and the spacing between the groove and each side surface is set to 25μm or more, thereby suppressing the intrusion of slip into the inner region of the resonator (i.e., the region where laser light propagates). In this semiconductor laser chip, a stepped region where the layers forming the active layer differ from each other is used instead of a groove to suppress the intrusion of slip into the inner region of the resonator (i.e., the region where laser light propagates). Therefore, this structure achieves the same effect as the semiconductor laser chip of the first embodiment.

[0116] Furthermore, the present semiconductor laser chip can be manufactured more easily than the semiconductor laser chip of the first embodiment.

[0117] In addition, in the semiconductor laser chip of the fifth embodiment of the present invention, in addition to the structure of the semiconductor laser chip of the fourth embodiment described above, the following structure is adopted: in the resonator, the end face for reflecting the light and the end face for emitting the light are respectively used as the reflection end face and the emission end face, and when the main surface of the active layer is viewed from the normal direction of the main surface of the active layer, the step region is formed in the region between the reflection end face and the emission end face, and both end portions of the step region do not reach either the reflection end face or the emission end face.

[0118] According to the above-described structure, the same effects as those of the semiconductor laser chip according to the second aspect are achieved.

[0119] Furthermore, a semiconductor laser chip according to a sixth aspect of the present invention has, in addition to the structure of the semiconductor laser chip according to either the fourth or fifth aspect, a structure in which the distance between the step region and the current injection bar is 30 μm or greater.

[0120] According to the above-mentioned structure, the same effects as those of the semiconductor laser chip of the third embodiment are achieved.

[0121] Furthermore, a semiconductor laser chip according to a seventh aspect of the present invention adopts a configuration in which, in addition to the configuration of the semiconductor laser chip according to any one of the first to sixth aspects, the width of the current injection bar is 75 μm or greater throughout the entire area.

[0122] The above-described configuration can provide a semiconductor laser chip having an output exceeding 10 W. Therefore, the present semiconductor laser chip can be suitably used for excitation of YAG solid crystals, excitation of ytterbium-doped optical fibers, and the like.

[0123] 〔Remarks〕

[0124] The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims. Embodiments obtained by appropriately combining technical means disclosed in different embodiments are also included in the technical scope of the present invention.

[0125] Description of reference numerals:

[0126] 10, 30: chip (semiconductor laser chip); 11, 31: substrate; 12, 32: n-type layer; 121, 321: buffer layer; 122, 322: n-type cladding layer; 123, 323: n-type guide layer; 13, 33: active layer; 14, 34: p-type layer; 141, 341: p-type guide layer; 142, 342: p-type cladding layer; 143, 343: p-type contact layer; 15, 35: barrier layer; 16, 17, 36, 7: electrode layer; 161, 361: current injection bar; 18: low-reflection film; 19: high-reflection film; 20: strain suppression layer; G1, G2: groove; S1, S2: step region.

Claims

1. A semiconductor laser chip, characterized in that: A wide-area semiconductor laser chip comprising: a substrate, an active layer stacked on the substrate, and a current injection bar for injecting current into the active layer. The semiconductor laser chip has a pair of main surfaces, a reflection end surface, an emission end surface, and a pair of side surfaces. The pair of side surfaces are each composed of a rough surface that becomes a starting point for cleavage and a cleavage surface. When the main surface of the active layer is viewed from a normal direction thereof, a groove is formed along the side surface in a region between the rough surface and the current injection strip. The groove passes through the active layer, The distance between the groove and each of the side surfaces is 25 μm or more.

2. The semiconductor laser chip according to claim 1, wherein When the main surface of the active layer is viewed from its normal direction, the groove is formed in a region between the reflective end facet and the emitting end facet, and both ends of the groove do not reach either the reflective end facet or the emitting end facet.

3. The semiconductor laser chip according to claim 1 or 2, characterized in that: The distance between the groove and the current injection bar is greater than 30 μm.

4. A semiconductor laser chip, characterized in that: A wide-area semiconductor laser chip comprises: a substrate, an active layer stacked on the substrate, a high-reflection film and a low-reflection film that together with the active layer form a resonator, and a current injection bar for injecting current into the active layer. The chip has a pair of main surfaces, a reflection end surface, an emission end surface and a pair of side surfaces. The pair of side surfaces are each composed of a rough surface that becomes a starting point for cleavage and a cleavage surface. When the main surface of the active layer is viewed from the normal direction thereof, a step region along the side surface is formed in a region between the rough surface of the side surface and the current injection strip. The active layer is formed to different depths in the step region and in a region other than the step region. The distance between the step region and each of the side surfaces is 25 μm or more.

5. The semiconductor laser chip according to claim 4, characterized in that When the main surface of the active layer is viewed from its normal direction, the step region is formed in a region between the reflective end facet and the emitting end facet, and both ends of the step region do not reach either the reflective end facet or the emitting end facet.

6. The semiconductor laser chip according to claim 4 or 5, characterized in that The distance between the step region and the current injection strip is greater than 30 μm.

7. The semiconductor laser chip according to any one of claims 1 to 6, characterized in that The width of the current injection strip is greater than 75 μm in the entire region.

Images