Semiconductor light-emitting element and method for manufacturing semiconductor light-emitting element

Abstract

Provided are: a semiconductor light-emitting element which has a better light-emitting output power per injection power than conventional light-emitting elements, and which is capable of forming a protective film without generating voids; and a method for manufacturing the semiconductor light-emitting element. This semiconductor light-emitting element has a first conductivity-type cladding, a light-emitting layer, and a second conductivity-type cladding in this order, with the second conductivity-type cladding as a light extraction side, and is characterized in that the light-emitting layer is a group III-V compound semiconductor containing one or more elements selected from among Al, Ga, and In as group III, and one or more elements selected from among As, Sb, and P as group V, and the light-emitting layer is a group III-V compound semiconductor containing one or more elements selected from among Al, Ga, and In as group V, and the light-emitting layer is a group III-V compound semiconductor containing one or more elements selected from among Al, Ga, and In as group V. The first conductivity-type cladding layer has a light emission center wavelength of 1000 nm to 1900 nm, the second conductivity-type cladding layer has a composition of InxGayAlzAs (0.49 < = x < = 0.55, 0.10 < = z < 0.35, and x + y + z = 1), and the expansion area ratio (Sdr) of the light extraction surface of the second conductivity-type cladding layer is 4.0 or more.

Description

Technical Field

[0001] The present invention relates to a semiconductor light emitting element and a method for manufacturing the semiconductor light emitting element. Background Art

[0002] As the semiconductor material for the semiconductor layer in the semiconductor light-emitting element, a III-V compound semiconductor, such as InGaAsP, InGaAlAs, or InAsSbP, is used, as disclosed in Patent Document 1. By adjusting the composition ratio of the light-emitting layer formed of the III-V compound semiconductor material, the emission wavelength of the semiconductor light-emitting element can be adjusted over a wide range from green to infrared. For example, an infrared-emitting semiconductor light-emitting element that emits in the infrared region of 1000 nm or longer is widely used in applications such as sensors, gas analysis, surveillance cameras, and communications.

[0003] In addition, Patent Document 2 records an attempt to alleviate the multi-peaks in the luminescence spectrum by forming a concave-convex pattern in a semiconductor stack composed of multiple layers of InGaAsP-based III-V compound semiconductor layers containing In and P, which includes an n-type cladding layer, an active layer and a p-type cladding layer in sequence, and forming a concave-convex pattern in the n-type cladding layer serving as the light extraction side.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2021-077885

[0007] Patent Document 2: Japanese Patent Application Publication No. 2018-101675 Summary of the Invention

[0008] Problems to be solved by the invention

[0009] In recent years, there has been a need to further improve the luminous efficiency of light-emitting elements. The present inventors have conducted research to increase the luminous output power per unit of injected power in light-emitting elements. Furthermore, attempts have been made to increase the luminous output power by controlling the surface roughness of the light extraction surface. The surface roughness of Patent Document 2, which has an extended area ratio (Sdr) value of less than 1, is insufficient to increase the luminous output power, and further improvement of the luminous output power is desired.

[0010] The present inventors have conducted research to obtain a concave-convex light extraction surface suitable for improving the luminous output power, and found that gouging sometimes occurs. In the present invention, gouging refers to the situation where, in a state where a film or the like that prevents etching is formed on a portion of the surface of a III-V compound semiconductor layer, when the surface is roughened by etching, etching is performed not only in the vertical direction of the thickness of the III-V semiconductor layer near the periphery of the film or the like, but also in the horizontal direction, resulting in a state where the bottom of the film or the like near the periphery of the film or the like is also etched. The present inventors have newly recognized the following technical problem: if gouging occurs, when a protective film is formed on the light extraction surface by a plasma CVD method, a sputtering method, or the like, it will cause the generation of an area (void portion) where the protective film is not fully formed, which will cause problems in practical applications.

[0011] Therefore, an object of the present invention is to provide a semiconductor light emitting element and a method for manufacturing the same, which has a better light emitting output per unit of injected power than conventional light emitting elements and can form a protective film without generating voids.

[0012] Solutions for solving problems

[0013] To achieve the above-mentioned technical problems, the present inventors conducted intensive research and discovered that, in infrared-emitting semiconductor light-emitting devices emitting light in the infrared region of 1000 nm or longer, the composition of the cladding layer, which serves as the light extraction side, is more easily achieved with an InGaAlAs system containing no P than with a cladding layer containing P. Furthermore, it was found that a high Al content in the InGaAlAs system is more likely to achieve surface roughness suitable for improving light output. However, it was discovered that excessively high Al content leads to significant gouging, leading to the completion of the present invention described below.

[0014] That is, the gist of the present invention is as follows.

[0015] (1) A semiconductor light emitting element comprising, in order, a first conductivity type cladding layer, a light emitting layer, and a second conductivity type cladding layer, with the second conductivity type cladding layer being a light extraction side, wherein:

[0016] The light-emitting layer is a III-V compound semiconductor, wherein the III-V compound semiconductor includes one or more of Al, Ga, and In as the III group, and one or more of As, Sb, and P as the V group, and the emission center wavelength is 1000 nm to 1900 nm.

[0017] The composition of the second conductive type cladding layer is In x Ga y Al zAs(0.49≤x≤0.55, 0.10≤z<0.35, x+y+z=1),

[0018] The spread area ratio (Sdr) of the light extraction surface of the second conductivity type cladding layer is 4.0 or greater.

[0019] (2) The semiconductor light emitting element according to (1), wherein the Al composition ratio z of the second conductivity type cladding layer is 0.15≤z≤0.30.

[0020] (3) The semiconductor light emitting element according to (1) or (2), wherein the arithmetic mean height (Sa) of the second conductivity type cladding layer in the light extraction surface is 0.60 μm or less, and the skewness (Ssk) is 0.30 or more.

[0021] (4) The semiconductor light emitting element according to any one of (1) to (3), wherein the band gap of the second conductivity type cladding layer is larger than the band gap of the light emitting layer.

[0022] (5) The semiconductor light emitting element according to any one of (1) to (4), wherein the thickness of the second conductivity type cladding layer is 2 μm or more and 10 μm or less.

[0023] (6) The semiconductor light emitting element according to any one of (1) to (5), wherein the light emitting layer has a quantum well structure in which InGaAlAs-based well layers and InGaAlAs-based barrier layers are alternately stacked.

[0024] (7) The semiconductor light-emitting element according to any one of (1) to (6), further comprising an undoped spacer layer between the first conductivity type cladding layer and the light-emitting layer and between the light-emitting layer and the second conductivity type cladding layer.

[0025] (8) The semiconductor light emitting element according to any one of (1) to (7), comprising, in order, a supporting substrate, a first conductivity type cladding layer, a light emitting layer, and a second conductivity type cladding layer, and a metal reflective layer between the supporting substrate and the first conductivity type cladding layer.

[0026] The semiconductor light emitting element further includes a dielectric layer and a contact portion provided in parallel between the metal reflective layer and the first conductivity type cladding layer.

[0027] (9) A method for manufacturing a semiconductor light-emitting element, wherein the semiconductor light-emitting element has a second conductivity type cladding layer as a light extraction side, the method comprising:

[0028] a semiconductor stack forming step of sequentially forming a first conductivity type cladding layer, a light emitting layer, and the second conductivity type cladding layer; and

[0029] a surface roughening step of immersing the second conductivity type cladding layer in concentrated nitric acid to roughen the surface, thereby making the spread area ratio (Sdr) of the light extraction surface of the second conductivity type cladding layer 4.0 or more;

[0030] The light-emitting layer is a III-V compound semiconductor, wherein the III-V compound semiconductor includes one or more of Al, Ga, and In as the III group, and one or more of As, Sb, and P as the V group, and the emission center wavelength is 1000 nm to 1900 nm.

[0031] The composition of the second conductive type cladding layer is In x Ga y Al z As(0.49≤x≤0.55, 0.10≤z<0.35, x+y+z=1).

[0032] (10) The method for manufacturing a semiconductor light-emitting element according to (9) above, wherein, in the surface roughening treatment step, the temperature of the concentrated nitric acid is lower than 10°C.

[0033] (11) The method for manufacturing a semiconductor light-emitting element according to (9) or (10) above, wherein, in the surface roughening treatment step, the concentration of the concentrated nitric acid is 60 wt % or more.

[0034] (12) The method for manufacturing a semiconductor light emitting device according to any one of (9) to (11) above, wherein the Al composition ratio z of the second conductivity type cladding layer is set to 0.15≤z≤0.30.

[0035] (13) A method for manufacturing a semiconductor light-emitting element according to any one of (9) to (12) above, wherein, in the surface roughening process, the surface roughening is performed in such a manner that the arithmetic mean height (Sa) of the light extraction surface of the second conductive type cladding becomes less than 0.6 μm and the skewness (Ssk) becomes greater than 0.3.

[0036] (14) The method for manufacturing a semiconductor light-emitting element according to any one of (9) to (13) above, further comprising, after the surface roughening step, a step of forming a mesa structure; and a step of cutting the portion removed by mesa formation into individual pieces.

[0037] (15) A method for manufacturing a semiconductor light emitting element, comprising:

[0038] a semiconductor stack formation step of sequentially forming an etching stop layer, a second conductivity type cladding layer, a light emitting layer, and a first conductivity type cladding layer on a growth substrate;

[0039] forming a dielectric layer and a contact portion arranged in parallel on the first conductive type cladding layer;

[0040] a metal reflective layer forming step of forming a metal reflective layer on the dielectric layer and the contact portion;

[0041] a bonding step of bonding a support substrate different from the growth substrate with the metal reflective layer interposed therebetween;

[0042] a growth substrate removal step of removing the growth substrate to expose the etching stop layer;

[0043] a second-conductivity-type cladding layer exposing step of removing the etching stop layer to expose a top surface of the second-conductivity-type cladding layer on a light extraction side; and

[0044] a surface roughening treatment step, after the second conductivity type cladding layer exposing step, immersing the second conductivity type cladding layer in concentrated nitric acid to roughen the surface, thereby making the spread area ratio (Sdr) of the light extraction surface of the second conductivity type cladding layer be 4.0 or more;

[0045] The light-emitting layer is a III-V compound semiconductor, wherein the III-V compound semiconductor includes one or more of Al, Ga, and In as the III group, and one or more of As, Sb, and P as the V group, and the emission center wavelength is 1000 nm to 1900 nm.

[0046] The composition of the second conductive type cladding layer is In x Ga y Al z As(0.49≤x≤0.55, 0.10≤z<0.35, x+y+z=1).

[0047] Effects of the Invention

[0048] According to the present invention, a semiconductor light emitting element having better light output per unit of injected power than conventional light emitting elements and capable of forming a protective film without generating voids and a method for manufacturing the same can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 This is a schematic cross-sectional view illustrating a semiconductor light emitting element according to one embodiment of the present invention.

[0050] Figure 2 This is a schematic cross-sectional view during the manufacturing process of a semiconductor light emitting element according to one embodiment of the present invention.

[0051] Figure 3 Then Figure 2A schematic cross-sectional view of a manufacturing process of a semiconductor light-emitting element according to one embodiment of the present invention.

[0052] Figure 4 This is a schematic cross-sectional view illustrating a preferred embodiment of a dielectric layer and the periphery of a contact portion of a semiconductor light emitting element according to one embodiment of the present invention.

[0053] Figure 5 Then Figure 3 A schematic cross-sectional view of a manufacturing process of a semiconductor light-emitting element according to one embodiment of the present invention.

[0054] Figure 6 Then Figure 4 A schematic cross-sectional view of a manufacturing process of a semiconductor light-emitting element according to one embodiment of the present invention.

[0055] Figure 7 This is a schematic cross-sectional view illustrating a semiconductor light emitting element according to one embodiment of the present invention.

[0056] Figure 8 This is a schematic plan view showing the pattern of the top surface electrode of Example 1.

[0057] Figure 9 This is a graph comparing Al composition ratio and Sa in Examples of the present invention and Comparative Examples.

[0058] Figure 10 This is a graph comparing Al composition ratio and Sdr in Examples of the present invention and Comparative Examples.

[0059] Figure 11 This is a graph comparing the Al composition ratio and Ssk in Examples of the present invention and Comparative Examples.

[0060] Figure 12 This is an electron microscope observation image of the vicinity of the light extraction surface of the second conductivity type cladding layer in Comparative Example 1.

[0061] Figure 13 This is an electron microscope observation image of the vicinity of the light extraction surface of the second conductivity type cladding layer in Example 1.

[0062] Figure 14 This is an electron microscope observation image of the vicinity of the light extraction surface of the second conductivity type cladding layer in Comparative Example 4. DETAILED DESCRIPTION

[0063] Before describing the embodiments of the present invention, the following points will be described.

[0064] <Composition>

[0065] First, when referred to as "III-V compound semiconductor" in this specification, its composition is represented by the general formula: (In a Ga b Al c )(P x As y Sb z Here, regarding the composition ratio of each element, the following relationship holds.

[0066] For Group III elements, c = 1-ab, 0≤a≤1, 0≤b≤1, 0≤c≤1;

[0067] For Group V elements, z = 1-xy, 0≤x≤1, 0≤y≤1, 0≤z≤1;

[0068] The Group III-V compound semiconductor layer of the present invention is composed of one or more Group III elements selected from the group consisting of Al, Ga, and In, and one or more Group V elements selected from the group consisting of As, Sb, and P.

[0069] In addition, when the composition ratio is not explicitly stated and it is simply expressed as "InGaAsP", it refers to an arbitrary compound in which the chemical composition ratio of the group III element (the sum of In and Ga) and the group V element (As, P) is 1:1, and the ratio of In and Ga as group III elements and the ratio of As and P as group V elements are respectively unspecified. In this case, it includes the case where neither In nor Ga is contained in the group III elements, and it also includes the case where neither As nor P is contained in the group V elements. Among them, in the case of InGaAsP that is clearly stated as "containing at least In and P", the group III elements contain In at a rate of greater than 0% and less than 100%, and the group V elements contain P at a rate of greater than 0% and less than 100%. In addition, when it is expressed as "InGaAs", it means that P is not contained in the above-mentioned "InGaAsP" except for unavoidable mixing during production. Similarly, when expressed as "InGaAlAs", it refers to any compound in which the chemical composition ratio of group III elements (the sum of In, Ga, and Al) to group V elements (As) is 1:1, and the ratios of In, Ga, and Al as group III elements and the ratio of As as group V element are respectively uncertain. Furthermore, when expressed as "InP", it means that Ga and As are not included in the above-mentioned "InGaAsP" except for those inevitably mixed in during manufacturing. It should be noted that the composition ratios of each component such as InGaAsP and InGaAs can be measured by photoluminescence measurement and X-ray diffraction measurement. In addition, the "inevitable mixing during manufacturing" mentioned here refers not only to the inevitable mixing in the manufacturing equipment using raw material gases, but also to the diffusion phenomenon of atoms at the interfaces of each layer during crystal growth and subsequent heat treatment.

[0070] <Conductive type>

[0071] In this specification, a layer that functions electrically as a p-type semiconductor layer is referred to as a p-type semiconductor layer (sometimes simply referred to as a "p-type layer"), and a layer that functions electrically as an n-type semiconductor layer is referred to as an n-type semiconductor layer (sometimes simply referred to as an "n-type layer"). On the other hand, when no specific impurities such as Si, Zn, S, Sn, Mg, and Te are intentionally added, it is referred to as "undoped". Undoped III-V compound semiconductor layers may contain impurities that are unavoidable during the manufacturing process. Specifically, the dopant concentration is low (for example, less than 5×10 16 atoms / cm 3 ), it is considered as “undoped” in this specification. Moreover, even if no impurities are intentionally added to the III-V compound semiconductor layer but 5×10 16 atoms / cm 3Impurities (O, C, H, etc.) that are unavoidable during the manufacturing process such as the decomposition of the raw material gas are also considered undoped. It should be noted that, since InAs functions electrically as an n-type even when undoped, all undoped or n-type InAs layers are InAs layers that function as an n-type. In addition, the values ​​of the impurity concentrations of Si, Zn, S, Sn, Mg, Te, etc. are based on SIMS analysis. It should be noted that the value of the dopant concentration varies significantly near the boundary of each semiconductor layer. Therefore, the value of the dopant concentration at the center of the film thickness direction of each layer is used as the value of the dopant concentration.

[0072] <Thickness and composition of each layer>

[0073] The thickness of each layer can be calculated based on the cross-sectional observation of the growth layer based on a transmission electron microscope (TEM). Regarding the composition ratio (solid phase ratio) of each layer in this specification, the value obtained by SIMS analysis is used. Regarding the composition ratio (solid phase ratio) of each layer of the light-emitting layer and the composition ratio of the spacer layer in this specification, the value obtained by performing SIMS analysis (quadrupole) in the thickness direction of the light-emitting layer after the uppermost layer of the light-emitting layer is exposed by etching (from the n-layer side) is used. It should be noted that for the SIMS analysis results, the value of the average element concentration of half the thickness range of each layer in the central part of the thickness direction of each layer is used. During manufacturing, for the layer grown in the form of a single film, the solid phase ratio is calculated by using the value obtained by converting the lattice constant measured based on XRD and the luminescence center wavelength measured based on photoluminescence (PL) into Eg (i.e., band gap), thereby determining the growth conditions for achieving the target composition ratio, and using the growth conditions to stack layers with the target composition ratio.

[0074] <Surface roughness parameters>

[0075] The expansion area ratio Sdr used in this specification indicates how much the expanded area (surface area) of the defined area has increased relative to the area of ​​the defined area. The Sdr of a completely flat surface is zero. In addition, the skewness Ssk is a value that indicates the symmetry of the peaks and valleys with the average line as the center. If Ssk is zero, it is symmetrical up and down relative to the average line (normal distribution). If it is positive, it means that it is biased to the lower side (valley side) relative to the average line. If it is negative, it means that it is biased to the upper side (peak side) relative to the average line. In addition, the arithmetic mean height Sa used in this specification is a value indicating the surface roughness (μm). These indicators are all in accordance with ISO25178.

[0076] Surface roughness parameters such as spread area ratio (Sdr), skewness (Ssk), and arithmetic mean height (Sa) can be measured using a non-stylus shape analysis laser microscope (Keyence VK-X1000 / 1100). Surface roughness parameters are measured in accordance with ISO 25178-2:2012.

[0077] In this specification, the surface roughness parameters are measured as follows. That is, the surface roughness is measured at any 9 positions of the rough surface after the surface roughening process using a shape analysis laser microscope (VK-X1000 / 1100 manufactured by KEYENCE) to obtain the average value. The measurement conditions are set as follows:

[0078] Lens magnification 50x

[0079] Pixel count: 2048×1536

[0080] Use Gaussian filter (S filter: 0.5μm)

[0081] The specific input parameters of the surface roughness measuring device are as follows.

[0082] Sxp: p = 2.5%

[0083] Vvv: p=80.0%

[0084] ·Vvc: p=10.0%, q=80.0%

[0085] Vmp: p = 10.0%

[0086] ·Vmc: p=10.0%, q=80.0%

[0087] Then, according to ISO25178-2:2012, the surface roughness parameters Sa (arithmetic mean height), Sz (maximum height), Sq (root mean square height), Sdr (interface expansion area ratio), Spc (arithmetic mean curvature of the peak apex), Sdr (composite parameter), Ssk (skewness: degree of deviation), and Sku (peakedness: sharpness) are automatically calculated.

[0088] The following describes embodiments of the present invention in detail with reference to the accompanying drawings. It should be noted that, in principle, identical components are denoted by the same reference numerals, and repeated descriptions are omitted. In the figures, for ease of explanation, the vertical and horizontal ratios of the substrate and each layer are exaggerated compared to the actual ratios.

[0089] (Semiconductor light-emitting element)

[0090] Reference Figure 1, an example of an embodiment of the semiconductor light-emitting element 100 of the present invention is described. The semiconductor light-emitting element 100 is a semiconductor light-emitting element having a first conductive type cladding layer 37, a light-emitting layer 35, and a second conductive type cladding layer 31 in sequence, with the second conductive type cladding layer 31 being the light extraction side. The light-emitting layer 35 is a III-V compound semiconductor, wherein the III-V compound semiconductor contains one or more of Al, Ga, and In as the III group, and contains one or more of As, Sb, and P as the V group, and the emission center wavelength is 1000nm to 1900nm. The composition of the second conductive type cladding layer 31 is In x Ga y Al z As (0.49≤x≤0.55, 0.10≤z<0.35, x+y+z=1), the spread area ratio (Sdr) of the light extraction surface 31A of the second conductive type cladding layer 31 is 4.0 or more.

[0091] Each structure is described below, and the details are further described when describing the embodiment of the manufacturing method described later. It should be noted that in this embodiment, the case where the bonding type technology is used is described as an example. When the bonding type technology described later is used in the manufacturing method, the substrate provided by the light-emitting element 100 is a supporting substrate 80. When the bonding method is not used, the substrate provided by the light-emitting element 100 can be set as a growth substrate 10 (in Figure 2 etc.).

[0092] <First Conductivity Type Cladding Layer>

[0093] The composition of the first-conductivity-type cladding layer 37 is not particularly limited and can be a known composition. The first-conductivity-type cladding layer 37 can be an InGaAlAs-based or InGaAsP-based III-V compound semiconductor containing at least In and P, as long as it has a small lattice mismatch with the light-emitting layer described later and is transparent to the emission center wavelength. Of these, an InGaAsP-based III-V compound semiconductor containing at least In and P, such as InP, is preferred.

[0094] <Luminescent layer>

[0095] The light-emitting layer preferably has a quantum well structure in which InGaAlAs well layers 35W and InGaAlAs barrier layers 35B are alternately stacked. This structure is called a multi-quantum well (MQW) structure. By having a multi-quantum well structure, the light-emitting output power can be improved by suppressing crystal defects. By changing the composition of the light-emitting layer, the center wavelength of light emission of the semiconductor light-emitting element 100 can be made 1000nm to 1900nm. It should be noted that in the case of a quantum well structure, in addition to changing the composition, it is also preferred to adjust the composition difference between the well layer 35W and the barrier layer 35B to apply strain to the well layer 35W.

[0096] <Al Composition Ratio of Second Conductivity Type Cladding Layer>

[0097] According to the experiments of the inventors, it was confirmed that gouging occurred when the Al composition ratio of the second conductive type cladding 31 was high. As shown in the comparative example described later, for example, when the Al composition ratio was 0.35 or more, gouging occurred when the surface of the second conductive type cladding 31 was roughened. On the other hand, when the Al composition ratio of the second conductive type cladding 31 was low, the composition was close to the light absorbing composition of the desired luminous center wavelength of 1100nm to 1900nm, which is the range of the present invention. Therefore, the luminous output power of the semiconductor light emitting element became smaller due to this situation. From this perspective, the composition of the second conductive type cladding 31 needs to satisfy In x Ga y Al z As (0.49≤x≤0.55, 0.10≤z<0.35, x+y+z=1). In particular, the Al composition ratio z preferably satisfies 0.15≤z≤0.30, and more preferably satisfies 0.20≤z≤0.30.

[0098] It should be noted that the above-mentioned gouging refers to a state in which, when a film or the like is formed on a portion of the surface of a III-V compound semiconductor layer and the surface is roughened by etching, etching occurs not only in the direction perpendicular to the thickness of the III-V semiconductor layer, but also in the horizontal direction near the periphery of the film or the like, resulting in etching below the film or the like near the periphery of the film or the like. For example, when observing a cross-section of the surface unevenness, horizontal erosion or holes in the thickness are observed, exceeding the boundary between the area to be surface-roughened and the area not surface-roughened due to the film or the like, and reaching directly below the area not surface-roughened. Such gouging occurs during etching in the surface roughening process as described above. In the subsequent step of forming a protective film such as SiO2 after the surface roughening process, which will be described later, it causes the formation of an incomplete protective film having a portion (also referred to as a void) where the protective film does not contact the surface (light extraction surface) of the second conductive type cladding layer 31. This may result in the failure to achieve power-on life characteristics when the semiconductor light-emitting element is finally formed into a device-mountable semiconductor light-emitting element. In addition, this may cause insufficient resist application and removal.

[0099] <Surface Asperities of the Light Extraction Surface of the Second Conductivity Type Cladding Layer>

[0100] Here, Figure 1 The light emitted from the light-emitting layer 35 in the semiconductor light-emitting element 100 is released to the outside through the surface of the portion of the second conductive type cladding layer 31 where no electrodes or the like are formed. It should be noted that in this specification, the "light extraction side" refers to the side of the semiconductor light-emitting element 100 where the light emitted from the light-emitting layer 35 is released to the outside. In this embodiment, the second conductive type cladding layer 31 is set as the "light extraction side". In addition, the "light extraction surface" refers to the surface of the top surface of the second conductive type cladding layer 31 as the "light extraction side" where no electrodes or the like are formed. The semiconductor light-emitting element 100 is subjected to a surface roughening treatment, and the extended area ratio (Sdr) of the light extraction surface 31A of the second conductive type cladding layer 31 is greater than 4.0. If the Sdr of the light extraction surface 31A of the second conductive type cladding layer 31 is less than 4.0, the semiconductor light-emitting element cannot obtain sufficient light-emitting output power. The extended area ratio (Sdr) is preferably greater than 4.4. Sdr is preferably 7.0 or less, and in order to reliably avoid the above-mentioned gouging on the surface roughened, it is further preferably 5.8 or less. In addition, it is preferred that the arithmetic mean height (Sa) of the light extraction surface 31A of the second conductive type cladding layer 31 is 0.60 μm or less and the skewness (Ssk) is 0.30 or more, and more preferably Sa is 0.55 μm or less and Ssk is 0.40 or more. A small arithmetic mean height (Sa), such as 0.60 μm or less, can improve the adhesion with the protective film. It should be noted that the side surface of the second conductive type cladding layer 31 may or may not be surface roughened.

[0101] <Band Gap of Second Conductivity-Type Cladding Layer>

[0102] For similar reasons, the second-conductivity-type cladding layer 31 preferably does not absorb light from the light-emitting layer. Therefore, more directly, the band gap of the second-conductivity-type cladding layer 31 is preferably larger than the band gap of the light-emitting layer 35. The band gap of the second-conductivity-type cladding layer 31 can be estimated based on its composition, while the band gap of the light-emitting layer 35 can be measured by PL measurement.

[0103] <Thickness of the Second Conductivity Type Cladding Layer>

[0104] Furthermore, considering the surface roughening, the thickness of the second conductive type cladding layer 31 is preferably greater than a certain value. On the other hand, if it is too thick, the production cost increases. Therefore, the thickness of the second conductive type cladding layer 31 is preferably greater than 2 μm and less than 10 μm.

[0105] When the first conductivity type cladding layer 37 is n-type, the second conductivity type cladding layer 31 is p-type. Conversely, when the first conductivity type cladding layer 37 is p-type, the second conductivity type cladding layer 31 is n-type.

[0106] <Spacer layer, metal reflective layer, dielectric layer, and contact portion (contact layer and ohmic metal portion)>

[0107] Furthermore, undoped spacer layers may be provided between the first-conductivity-type cladding layer 37 and the light-emitting layer 35 and between the light-emitting layer 35 and the second-conductivity-type cladding layer 31, respectively; a metal reflective layer 60 may be provided between the support substrate 80 and the first-conductivity-type cladding layer 37; and a dielectric layer 50 and a contact portion 40 may be provided in parallel between the metal reflective layer 60 and the first-conductivity-type cladding layer 37. Furthermore, the contact portion 40 includes a contact region 41A formed from a portion of the contact layer 41 and an ohmic metal portion 43. The ohmic metal portion 43 may be provided on the surface of the contact region 41A.

[0108] <Top surface electrode and back surface electrode>

[0109] The semiconductor light emitting element 100 may form a top surface electrode 93 including a wiring portion 93A and a pad portion 93B on the second conductivity type cladding layer 31 , and may further form a back surface electrode 91 on the back surface of the support substrate 80 .

[0110] (Method for Manufacturing Semiconductor Light-Emitting Element)

[0111] The manufacturing method of the semiconductor light-emitting element of the present invention uses the second conductive type cladding as the light extraction side. The manufacturing method includes: a semiconductor stack formation step, in which the first conductive type cladding, the light-emitting layer, and the second conductive type cladding are formed in sequence; a surface roughening treatment step, in which the second conductive type cladding is immersed in concentrated nitric acid for surface roughening, thereby making the extended area ratio (Sdr) of the light extraction surface of the second conductive type cladding 4.0 or more. The light-emitting layer is a III-V compound semiconductor, and the III-V compound semiconductor contains one or more of Al, Ga, and In as the III group, and contains one or more of As, Sb, and P as the V group, and the emission center wavelength is 1000nm to 1900nm. The composition of the second conductive type cladding is In x Ga y Al z As(0.49≤x≤0.55, 0.10≤z<0.35, x+y+z=1).

[0112] Next, refer to Figures 2 to 7 An example of a method for manufacturing a semiconductor light-emitting element according to one embodiment of the present invention is described. This embodiment uses a bonding technique as an example. The method for manufacturing a semiconductor light-emitting element may include: a semiconductor stack formation step, a metal reflective layer formation step, a bonding step, a growth substrate removal step, a second conductivity-type cladding layer exposure step, and a surface roughening step. Each step is described in detail below.

[0113] <Semiconductor stack formation step>

[0114] like Figure 2 As shown, in the semiconductor stack formation step, an etching stop layer 20, a second conductivity type cladding layer 31, a light emitting layer 35, and a first conductivity type cladding layer 37 are sequentially formed on a growth substrate 10, thereby forming a semiconductor stack 30. The light emitting layer is a III-V compound semiconductor, wherein the III-V compound semiconductor contains one or more of Al, Ga, and In as group III elements and one or more of As, Sb, and P as group V elements, and has a light emission center wavelength of 1000 nm to 1900 nm. The second conductivity type cladding layer 31 is composed of In. x Ga y Al z As (0.49≤x≤0.55, 0.10≤z<0.35, x+y+z=1), preferably, the Al composition ratio z is set to 0.15≤z≤0.30. The details of this step will be described below.

[0115] First, if Figure 2As shown in step 10 of the method, in the semiconductor stack formation process, a growth substrate 10 is prepared. In this embodiment, since a p-type cladding layer is formed as the first conductive type cladding layer 37 and an n-type cladding layer is formed as the second conductive type cladding layer 31, an InP substrate is preferably used as the growth substrate 10. It should be noted that as the InP substrate, a commonly available n-type InP substrate or a high-resistance (also called semi-insulating) InP substrate (e.g., Fe-doped, with a resistivity of 1×10 6 Ω·cm or more), or a p-type InP substrate. For ease of explanation, the following description uses an n-type InP substrate as the growth substrate 10. Therefore, in the following embodiments, the first conductive type cladding layer 37 is sometimes referred to as the p-type cladding layer 37, and the second conductive type cladding layer 31 is sometimes referred to as the n-type cladding layer 31.

[0116] Then, if Figure 2 As shown in step 20, an etching stop layer 20 is formed on the growth substrate 10. The etching stop layer 20 only needs to have etching selectivity with respect to the growth substrate 10. In the present invention, InGaAs is used for the etching stop layer 20. This etching stop layer 20 can be used when removing the growth substrate 10 by etching during the growth substrate removal step. In order to achieve lattice matching between the n-type InP substrate and the InGaAs, the etching stop layer 20 preferably has an In composition ratio of 0.3 to 0.7 among the group III elements, and more preferably uses InGaAs having an In composition ratio of 0.5 to 0.6.

[0117] Next, a semiconductor stack 30 is formed by sequentially forming an n-type cladding layer 31, a light-emitting layer 35, and a p-type cladding layer 37 on the etching stop layer 20. The semiconductor stack 30 can be configured as a double heterogeneous (DH) structure or a multi-quantum well (MQW) structure in which the light-emitting layer 35 is sandwiched between the p-type cladding layer 37 and the n-type cladding layer 31. In order to improve the light output power by suppressing crystal defects, the light-emitting layer 35 is more preferably configured as a multi-quantum well structure. The multi-quantum well structure can be formed by alternating well layers 35W and barrier layers 35B. The well layers 35W and the barrier layers 35B contain one or more of Al, Ga, and In as group III elements, and contain one or more of As, Sb, and P as group V elements. It is more preferable to set the group V element to one, for example, the well layer 35W can be set to InGaAlAs, and the barrier layer 35B can be set to InGaAlAs having a band gap larger than that of the well layer 35W. By changing the composition of the well layer 35W, the emission center wavelength can be set to 800nm~1650nm. In the case of the MQW structure, in addition to changing the composition, the emission center wavelength can be set to 1100nm~1900nm by adjusting the composition difference between the well layer and the barrier layer and applying strain to the well layer. That is, the emission center wavelength of the light-emitting layer 35 can be designed within the range of 800nm~1900nm, and the emission center wavelength is preferably set to 1000nm~1900nm. In addition, the component composition of the well layer 35W is expressed as In xw Ga yw Al zw In the case of As, it can be appropriately selected from the range of 0.50≤xw≤0.70, 0.00≤yw≤0.50, and 0.00≤zw≤0.50. Similarly, in the barrier layer 35B, the component composition is represented by In. xb Ga yb Al zb In the case of As, it may be appropriately selected from the ranges of 0.40≤xb≤0.60, 0.00≤yb≤0.60, and 0.00≤zb≤0.60.

[0118] The overall thickness of the semiconductor stack 30 is not limited and can be, for example, 2.4 μm to 15 μm. Furthermore, the thickness of the p-type cladding layer 37 is also not limited and can be, for example, 0.4 μm to 5 μm. The thickness of the n-type cladding layer 31 can be set to 2 μm to 10 μm due to surface roughening of the second conductive type cladding layer 31 on the light extraction side. When the light-emitting layer 35 has a quantum well structure, the thickness of the well layer 35W can be set to 3 nm to 15 nm, and the thickness of the barrier layer 35B can be set to 5 nm to 15 nm. The number of groups of the well layer and the barrier layer can be set to 1 to 50.

[0119] In addition, the semiconductor stack 30 preferably has a p-type cap layer 39 composed of InGaAsP containing at least In and P on the p-type cladding layer 37. By providing the p-type cap layer 39, lattice mismatch can be alleviated. The thickness of the p-type cap layer 39 is not limited and can be set to 50nm to 200nm, for example. In the following embodiments, for ease of description, the outermost layer of the semiconductor stack 30 is described as the p-type cap layer 39. However, since the p-type cap layer 39 can be of any configuration, the outermost layer of the semiconductor stack 30 can also be set to the p-type cladding layer 37, for example.

[0120] It should be noted that, although not shown in the figure, the semiconductor stack 30 also preferably has an i-type InGaAlAs spacer layer and an i-type InP spacer layer between the n-type cladding layer 31 and the light-emitting layer 35 and between the light-emitting layer 35 and the p-type cladding layer 37, respectively. By providing a spacer layer, the diffusion of dopants can be prevented. It should be noted that there is no limit to the thickness of the spacer layer, for example, it can be set to 50nm to 400nm. In addition, the semiconductor stack 30 can also have a window layer between each n-type and p-type cladding layer and the spacer layer. The window layer can be set to the same composition as the cladding layer, or it can be set to a composition with a changed dopant concentration to efficiently inject carriers into the active layer.

[0121] Here, each layer of the semiconductor stack 30 can be formed by epitaxial growth, for example, by a well-known thin film growth method such as metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), sputtering, etc. For example, by using trimethyl indium (TMIn) as an In source, trimethyl gallium (TMGa) as a Ga source, arsine (AsH3) as an As source, and phosphine (PH3) as a P source in a predetermined mixing ratio, and by causing these raw material gases to grow in the gas phase while using a carrier gas, each semiconductor stack can be formed with a desired thickness according to the growth time. It should be noted that when each layer is doped to p-type or n-type, it is sufficient to further use a dopant source gas as desired.

[0122] In addition, the example of the embodiment of the present manufacturing method preferably includes a contact portion forming step and a dielectric layer forming step after the semiconductor stack forming step, and these steps will be described below.

[0123] <<Contact portion forming process>>

[0124] In the contact portion forming step, a contact layer 41 composed of a III-V compound semiconductor is first formed on the semiconductor stack 30. For example, Figure 2As shown in step 30, a p-type contact layer 41 can be formed on the p-type cap layer 39. The p-type contact layer 41 is a layer that contacts the ohmic metal portion 43 and is sandwiched between the ohmic metal portion 43 and the semiconductor stack 30. Any composition can be used as long as the contact resistance between the p-type contact layer 41 and the ohmic metal portion 43 is lower than that of the semiconductor stack 30. For example, a p-type InGaAs layer can be used. The thickness of the contact layer 41 is not limited and can be, for example, 50 nm to 200 nm.

[0125] Then, if Figure 3 As shown in step 40, an ohmic metal portion 43 is formed on a portion of the contact layer 41, and an exposed area is left on the surface of the contact layer 41. The ohmic metal portion 43 can be formed by dispersing it into an island shape in a prescribed pattern. In the case of using a p-type InGaAs layer as the p-type contact layer 41, for example, Au, AuZn, AuBe, AuTi, etc. can be used as the ohmic metal portion 43, and their stacked structure is preferably used. For example, Au / AuZn / Au can be set as the ohmic metal portion 43. There is no limit to the thickness (or total thickness) of the ohmic metal portion 43, for example, it can be set to 300nm to 1300nm, and more preferably to 350nm to 800nm.

[0126] Here, for example, the ohmic metal portion 43 can be formed by forming a resist pattern on the surface of the contact layer 41, vapor-depositing the ohmic metal portion 43, and then peeling off the resist pattern, thereby leaving an exposed area on the surface of the contact layer 41. Alternatively, the ohmic metal portion 43 can be formed by forming a predetermined metal layer on the entire surface of the contact layer 41, forming a mask on the metal layer, and performing etching. In either case, Figure 3 As shown in step 40 , the ohmic metal portion 43 may be formed on a portion of the contact layer 41 , and a surface, ie, an exposed area, of the contact layer 41 is formed without contact with the ohmic metal portion 43 .

[0127] It should be noted that the shape of the ohmic metal portion 43 is as follows: Figure 3 As shown in step 40, the ohmic metal portion 43 may be trapezoidal in cross-section, but this is merely a schematic illustration. The ohmic metal portion 43 may be rectangular or have rounded corners in cross-section.

[0128] In addition, if Figure 3As shown in step 50, in the contact portion forming process, the contact layer 41 in the exposed area is removed until the surface of the semiconductor stack 30 is exposed, forming the contact portion 40 consisting of the ohmic metal portion 43 and the contact region 41A. That is, the contact layer 41 at a location other than the previously formed ohmic metal portion 43 is etched until the surface of the p-type cap layer 39, which is the outermost layer of the semiconductor stack 30, is exposed, forming the contact region 41A. For example, a resist mask can be formed on the ohmic metal portion 43 and its vicinity (approximately 2 to 5 μm), and the exposed area of ​​the contact layer 41 can be wet-etched using a tartaric acid-hydrogen peroxide system or the like. Alternatively, wet etching can be performed using an inorganic acid-hydrogen peroxide system or an organic acid-hydrogen peroxide system etchant. In addition, when forming the exposed area, when a mask is formed on the above-mentioned predetermined metal layer and the ohmic metal portion 43 is formed by etching, etching can be performed continuously.

[0129] It should be noted that the thickness of the contact portion 40 corresponds to the total thickness of the contact layer 41 (contact region 41A) and the ohmic metal portion 43 , and can be set to 350 nm to 1500 nm, more preferably 400 nm to 1000 nm.

[0130] <<Dielectric layer formation process>>

[0131] In the dielectric layer forming process, Figure 3 As shown in step 60, a dielectric layer 50 is formed on at least a portion of the cap layer 39 of the semiconductor stack 30. The dielectric layer 50 can be formed, for example, as follows.

[0132] First, a dielectric layer is formed on the entire surface of the semiconductor stack 30 so as to cover the semiconductor stack 30 and the contact portion 40. As a film formation method, known methods such as plasma CVD and sputtering can be applied. Furthermore, if the dielectric layer 50 on the surface of the formed dielectric layer, above the contact portion 40, has a dielectric layer on the contact portion 40 formed thereon, a mask can be formed as desired, and the dielectric layer on the contact portion 40 can be removed by etching or the like. For example, the dielectric layer on the contact portion 40 can be wet-etched using buffered hydrofluoric acid (BHF) or the like.

[0133] It should be noted that if Figure 4As shown, it is also preferred to form a dielectric layer 50 on a portion of the cap layer 39 of the semiconductor stack 30, and to make the area around the contact portion 40 an exposed portion. Such a dielectric layer 50 and the exposed portion can be formed, for example, as follows. First, a dielectric layer is formed on the entire surface of the semiconductor stack 30, and a window pattern is formed on the surface of the formed dielectric layer above the contact portion 40 using a resist to completely surround the contact portion 40. In this case, the window pattern preferably has an extension of approximately 1 μm to 5 μm relative to the length of the contact portion 40 in both the width direction and the length direction. By using the resist pattern thus formed and removing the dielectric around the contact portion 40 by etching, the dielectric layer 50 is formed, and the area around the contact portion 40 becomes an exposed portion.

[0134] In order to reliably obtain this shape, the width W of the exposed portion is preferably set to 0.5 μm or more and 5 μm or less, and more preferably set to 1 μm or more and 3.5 μm or less.

[0135] Here, the contact area ratio between the dielectric layer 50 and the semiconductor stack 30 is preferably set to 80% or more and 95% or less. This is because by reducing the area of ​​the contact portion 40 and increasing the area of ​​the dielectric layer 50, light absorption by the contact portion 40 can be suppressed. It should be noted that the contact area ratio can be measured in the wafer state or after singulation.

[0136] It should be noted that there is no particular limitation on the relationship between the thickness H1 of the dielectric layer 50 formed by the dielectric layer forming step and the thickness H2 of the contact portion 40. Figure 4 As shown, when the thickness of the dielectric layer 50 is represented by H1 and the thickness of the contact portion 40 is represented by H2, H1 ≥ H2 can be set, and preferably H1 > H2. Under this condition, the thickness of the dielectric layer 50 can be set, for example, to 360 nm to 1600 nm, and more preferably to 410 nm to 1100 nm. Furthermore, the difference H1 - H2 between the thickness H1 of the dielectric layer 50 and the thickness H2 of the contact portion 40 is preferably set to be greater than 10 nm and less than 100 nm.

[0137] Furthermore, SiO 2 , SiN, ITO, AlN, and the like can be used as the dielectric layer 50 . In particular, the dielectric layer 50 is preferably made of SiO 2 because SiO 2 can be easily etched using BHF or the like.

[0138] <Metal Reflective Layer Formation Step>

[0139] In the metal reflective layer forming process, Figure 5As shown in step 70, a metal reflective layer 60 that reflects light emitted from the light-emitting layer 35 is formed on the parallel dielectric layer 50 and the contact portion 40. It should be noted that when an exposed portion is formed in the dielectric layer formation step, the metal reflective layer 60 is also formed on the exposed portion. The metal reflective layer 60 can be made of Au, Al, Pt, Ti, Ag, etc., and Au is particularly preferably used as the main component. In this case, Au preferably accounts for more than 50% by mass of the composition of the metal reflective layer 60, and more preferably, Au accounts for more than 80% by mass. The metal reflective layer 60 can include multiple metal layers. When including a metal layer composed of Au (hereinafter referred to as "Au metal layer"), the thickness of the Au metal layer is preferably set to be greater than 50% of the total thickness of the metal reflective layer 60. For example, the metal reflective layer can be a single layer composed solely of Au, or the metal reflective layer can include two or more Au metal layers. In order to ensure reliable bonding in the subsequent bonding step, the outermost layer of the metal reflective layer (the surface opposite to the semiconductor stack 30) is preferably an Au metal layer. For example, metal layers can be formed in the order of Al, Au, Pt, and Au on the dielectric layer 50, the exposed portion, and the contact portion 40 to serve as the metal reflective layer. The thickness of the Au metal layer in the metal reflective layer can be, for example, 400 nm to 2000 nm, and the thickness of the metal layer composed of a metal other than Au can be, for example, 5 nm to 200 nm. The metal reflective layer 60 can be formed on the dielectric layer 50, the exposed portion, and the contact portion 40 by conventional methods such as vapor deposition.

[0140] <Joining process>

[0141] In the joining process, Figure 5 As shown in step 80, a support substrate 80 different from the growth substrate 10 is bonded to the metal reflective layer 60 via a metal bonding layer 60. A metal bonding layer 70 may be formed on the surface of the support substrate 80 in advance by sputtering, vapor deposition, or the like. The metal bonding layer 70 and the metal reflective layer 60 are bonded together by placing them opposite each other and then performing heat compression bonding at a temperature of approximately 250°C to 500°C.

[0142] The metal bonding layer 70 bonded to the metal reflective layer 60 can be made of metals such as Ti, Pt, Au, or metals that form a eutectic alloy with gold (such as Sn), and is preferably a layer formed by stacking these. For example, the metal bonding layer 70 can be a layer formed by stacking Ti with a thickness of 400 nm to 800 nm, Pt with a thickness of 5 nm to 20 nm, and Au with a thickness of 700 nm to 1200 nm in this order from the surface of the support substrate 80. It should be noted that to facilitate the bonding of the metal reflective layer 60 and the metal bonding layer 70, it is preferred that the outermost layer on the metal bonding layer 70 side be an Au metal layer, and the metal layer on the metal reflective layer 60 and the metal bonding layer 70 side also be Au, with the Au layers bonding each other by Au-Au diffusion.

[0143] It should be noted that the support substrate 80 can be, for example, a conductive Si substrate, a conductive GaAs substrate, or a Ge substrate. Furthermore, in addition to the aforementioned semiconductor substrates, a metal substrate can be used, or a base substrate using a heat-dissipating insulating substrate such as sintered AlN can be used.

[0144] Growth substrate removal process

[0145] Furthermore, in the growth substrate removal step, as Figure 6 As shown in step 90, the growth substrate 10 is removed to expose the etching stop layer 20. The growth substrate 10 can be removed by wet etching using, for example, a hydrochloric acid dilution solution, and the etching stop layer 20 can be used as the end point of the wet etching.

[0146] <Second Conductivity Type Cladding Layer Exposure Step>

[0147] In the second conductive type cladding layer exposure step, Figure 6 As shown in steps 100 and 110, an n-side electrode 93 serving as a top surface electrode is formed on the exposed n-side electrode forming region 20A of the etch-stop layer 20, and a portion of the etch-stop layer 20 is removed, allowing the light extraction surface 31A to be provided on the semiconductor stack 30. The n-side electrode 93 may be provided on the n-side electrode forming region 20A before the portion of the etch-stop layer 20 is removed. Alternatively, the etch-stop layer 20 other than the n-side electrode forming region 20A may be removed before forming the n-side electrode 93. The etch-stop layer 20 may be removed by wet etching using a sulfuric acid-hydrogen peroxide-based or tartaric acid-hydrogen peroxide-based etchant.

[0148] It should be noted that the etching stop layer 20 on the second-conductivity-type cladding layer 31 in the light extraction surface 31A can also be etched during the surface roughening process described later, and can also be removed simultaneously with the surface roughening process. Therefore, the etching stop layer 20 removal process described above can be omitted. It is also preferable to use the etching stop layer 20 as a mask to delay the start of etching the second-conductivity-type cladding layer 31, thereby controlling the surface irregularities of the second-conductivity-type cladding layer 31 in the light extraction surface 31A.

[0149] Surface roughening process

[0150] Then, in the surface roughening process, as Figure 7 As shown, the exposed second-conductivity-type cladding layer 31, excluding the n-side electrode 93, is surface roughened by immersing it in concentrated nitric acid. This allows the light extraction surface 31A of the second-conductivity-type cladding layer 31 to have an extended area ratio (Sdr) of 4.0 or greater. Concentrated nitric acid used for surface roughening can be used, for example, a 61 wt% etchant or a commercially available etchant such as nitric acid for electronics (manufactured by Kanto Chemical Co., Ltd., Nitric Acid 1.38). The Sdr is preferably set to 4.4 or greater. Furthermore, the Sdr is preferably set to 7.0 or less, and more preferably 5.8 or less. The temperature of the concentrated nitric acid is preferably below 10°C, more preferably below 9°C, and even more preferably below 8°C. Since the etching rate increases at higher temperatures, the cladding layer may be etched through or disappear. The concentration of the concentrated nitric acid is preferably 60 wt% or greater, more preferably 61 wt% or greater, and even more preferably 62 wt% or greater. If the concentration of the concentrated nitric acid is less than 60 wt%, the formation of the roughened surface may be insufficient. Furthermore, it is preferred to perform surface roughening treatment so that the arithmetic mean height (Sa) of the light extraction surface 31A of the second conductive type cladding 31 is less than 0.60 μm and the skewness (Ssk) is greater than 0.30. It is more preferred to perform surface roughening treatment so that Sa is less than 0.55 μm and Ssk is greater than 0.40. In addition, after the surface roughening treatment process, there may be a process of further forming a mesa structure and a process of cutting off the portion removed by the mesa to perform singulation. In addition, in the surface roughening treatment process, in addition to the case where the top surface electrode is exposed, the process may also include masking the top surface electrode area and the portion that is not subjected to surface roughening using a resist or the like before immersing in the etching solution. In this way, it is possible to produce Figure 7 The semiconductor light emitting element 200 is shown.

[0151] <<Protective film formation process>>

[0152] In addition, although not shown in the figure, after the surface roughening treatment process, a protective film can be provided on the surface of the light extraction surface 31A including the second conductive type cladding 31 to obtain a semiconductor light emitting element. The protective film can be applied by well-known methods such as the plasma CVD method and the sputtering method. The protective film can use SiO2, SiN, ITO and AlN, etc. The protective film has the effect of suppressing the refractive index difference between the n-type cladding 31 and the air to improve the light extraction effect and the effect of improving the power-on life characteristics of the semiconductor light emitting element. However, in the second conductive type cladding 31 that has undergone the surface roughening treatment process of the present invention, the boundary between the surface roughening area and the surface roughening area is not cut, so the protective film can be formed without generating a portion (gap portion) where the protective film does not contact the second conductive type cladding 31. It should be noted that a protective film can also be provided to protect the side of the semiconductor stack 30.

[0153] For ease of explanation, this embodiment is set as an embodiment using an n-type InP substrate as the growth substrate 10. Therefore, although the n-type and p-type of each layer formed on the growth substrate 10 are as described above, it can of course be understood that the n-type / p-type conductivity type of each layer can be reversed.

[0154] The present embodiment is described above, but the embodiment is not limited thereto. Various modifications can be made using known techniques within the scope of the present invention. For example, when the bonding method is not used, for example, when an n-type substrate is used as the growth substrate 10, the first conductive type cladding layer is changed to n-type, and the second conductive type cladding layer 31 is changed to p-type. The first conductive type cladding layer 37, the light emitting layer 35, and the second conductive type cladding layer 31 are sequentially formed on the growth substrate 10 to produce the semiconductor stack 30. After forming the contact layer 41 on the second conductive type cladding layer 31, as shown in FIG. Figure 3 The ohmic metal portion 43 is formed on the surface of the contact layer 41 as in steps 40 and 50, and then the second conductive type cladding layer ( Figure 3 The top surface of the first conductive type cladding layer 37 and the cap layer 39 in the substrate 10 is the light extraction surface 31A, and a surface roughening treatment process is performed, and a back electrode 91 is formed on the back side of the growth substrate 10. In this case, the ohmic metal part 43 plays the role of the top surface electrode. When the bonding method is not used, the etching stop layer 20 is optional. In addition, although the side surface of the semiconductor stack 30 shown in the figure is depicted vertically, the side surface of the semiconductor stack 30 can be inclined by mesa etching in the process of forming the mesa structure. The present invention is described in more detail below using examples, but the present invention is not limited to the following examples.

[0155] Example

[0156] The target emission center wavelength was set to 1000 nm to 1900 nm, and semiconductor light emitting devices according to Examples 1 to 5 and Comparative Examples 1 to 6 were produced by bonding. The present invention will be described in more detail below using Examples, but the present invention is not limited to the following Examples.

[0157] (Example 1)

[0158] Table 1 shows the thickness and dopant concentration of each configuration of the semiconductor light emitting element according to Example 1 in a state grown on a growth substrate before being bonded to a support substrate.

[0159] [Table 1]

[0160]

[0161] according to Figures 2 to 4 The semiconductor light emitting element of Example 1 is manufactured by using a flow chart of a method for manufacturing a junction type semiconductor light emitting element. The details are as follows. First, an n-type InP initial growth layer (100nm), an n-type InP primary growth layer (100nm), an n-type InP secondary growth layer (100nm), and an n-type InP secondary growth layer (100nm) are sequentially formed on the (100) surface of an n-type InP substrate using an MOCVD device. 0.57 Ga 0.43 As etching stop layer (20nm), n-type In 0.52 Ga 0.18 Al 0.30 As (i.e. Al composition ratio 30%) cladding (thickness: 4800nm, dopant concentration: 5.0×10 17 atoms / cm 3 ), i-type In 0.52 Ga 0.18 Al 0.30 As spacer layer (thickness: 100 nm), quantum well structured light-emitting layer with a light emission wavelength of 1490 nm (total 188 nm), i-type InP spacer layer (thickness: 320 nm), p-type InP cladding layer (2400 nm, dopant concentration: 7.0 × 10 17 atoms / cm 3 ), p-type In 0.8 Ga 0.20 As 0.5 P 0.5 Cap layer (thickness: 50 nm, dopant concentration: 5.0 × 10 18 atoms / cm 3 ), p-type In 0.57 Ga 0.43 As contact layer (thickness: 100 nm, dopant concentration: 1.5×10 19 atoms / cm 3). It should be noted that when forming the light-emitting layer of the quantum well structure, 0.526 Ga 0.398 Al 0.076 After the As barrier layer (thickness: 8 nm), 10 sets of In 0.567 Ga 0.352 Al 0.081 As well layer (thickness: 10 nm) and In 0.526 Ga 0.398 Al 0.076 As barrier layer (thickness: 8 nm).

[0162] In p-type In 0.57 Ga 0.43 A p-type ohmic electrode (Au / AuZn / Au, total thickness: 530nm) dispersed in an island pattern was formed on the As contact layer to form the contact portion. During this patterning, a resist pattern was formed, followed by vapor deposition of the ohmic electrode, and the resist pattern was peeled off to form the contact portion. When the semiconductor stack of the wafer was observed from above using an optical microscope in this state, the contact area ratio between the p-type ohmic electrode portion and the semiconductor stack was 0.95%. A heat treatment was performed at 300°C for 1 minute to establish the ohmic contact.

[0163] Next, a resist mask was formed on the ohmic electrode portion, and the p-type In layer except for the portion where the ohmic electrode portion was formed was removed by tartaric acid-hydrogen peroxide based wet etching. 0.57 Ga 0.43 As contact layer. After removing the resist, p-type In 0.80 Ga 0.20 As 0.50 P 0.50 A dielectric layer (thickness: 700nm) made of SiO2 is formed on the entire surface of the cap layer. In addition, a window pattern with an additional width of 10μm is formed in the area above the p-type ohmic electrode using a resist. The p-type ohmic electrode and the dielectric layer around it are removed by wet etching with BHF, leaving the p-type In 0.80 Ga 0.20 As 0.50 P 0.50 The cap layer is exposed. At this time, the p-type In 0.80 Ga 0.20 As 0.50 P 0.50 The height H1 of the dielectric layer on the cap layer (700 nm) is 30 nm higher than the height H2 (670 nm) of the contact layer consisting of the p-type contact layer (120 nm thick) and the p-type ohmic electrode portion (530 nm thick). It should be noted that when the semiconductor stack of the wafer is viewed from above using an optical microscope in this state, the contact area ratio of the dielectric layer (SiO2) is 93%.

[0164] Then, by evaporation on the p-type In 0.80 Ga 0.20 As 0.50 P 0.50 A metal reflective layer (Ti / Au / Pt / Au) is formed on the entire surface of the cap layer and the dielectric layer. The thickness of each metal layer of the metal reflective layer is 2 nm for Ti, 650 nm for Au, 10 nm for Pt, and 900 nm for Au.

[0165] On the other hand, a metal bonding layer (Ti / Pt / Au) was formed on a conductive Si substrate (thickness: 300 μm) serving as a support substrate. The thickness of each metal layer in the metal bonding layer was 650 nm for Ti, 10 nm for Pt, and 900 nm for Au.

[0166] The metal reflective layer and the metal bonding layer were arranged to face each other and were heat-compressed and bonded at 315° C. The InP substrate was then wet-etched with a hydrochloric acid dilute solution to remove the InP substrate.

[0167] Next, the top ohmic electrode is formed. A resist pattern is formed except for the position where the top electrode is formed, and an n-type electrode (Au (thickness: 10nm) / Ge (thickness: 33nm) / Au (thickness: 57nm) / Ni (thickness: 34nm) / Au (thickness: 800nm) / Ti (thickness: 100nm) / Au (thickness: 1000nm)) is evaporated. By peeling off the resist pattern, a pattern of the top electrode is formed. In addition, a pad portion (Ti (thickness: 150nm) / Pt (thickness: 100nm) / Au (thickness: 2500nm)) is formed on the circular portion in the center of the n-type electrode to make a Figure 8 The pattern of the top surface electrodes is shown.

[0168] The etching stop layer is removed by etching using a tartaric acid-hydrogen peroxide-based etching solution.

[0169] Next, the light extraction surface of the n-type cladding is subjected to surface roughening treatment. First, a resist pattern is formed for the area where the surface roughening is not performed (the predetermined position of the mesa etching described later on the top surface of the n-type cladding and the upper part and periphery of the top surface electrode). The resist is a film that prevents etching. The area where the resist pattern is not formed is the area where the surface roughening is performed. Then, it is immersed in concentrated nitric acid (61wt%) for semiconductors cooled to 8°C and allowed to stand for 5 seconds. It is then immediately taken out and washed with flowing water in overflowing pure water for 60 seconds, washed with alkali in ammonia water for 80 seconds, washed with flowing water in overflowing pure water for another 60 seconds, and blown dry. Then, the resist pattern is removed.

[0170] Next, a cutting line is formed by mesa etching. A resist pattern is formed for the area other than the cutting line, and the semiconductor stack on the cutting line is removed by dry etching. Furthermore, SiN (thickness 190 nm) is formed as a protective film on the entire surface by a plasma CVD method in a manner covering the inclined side (mesa side) and the above-mentioned light extraction surface of the semiconductor stack formed by dry etching. In order to expose a portion of the surface of the pad electrode required for wire bonding, the protective film (SiN) on the pad electrode is partially removed. After protecting the light-emitting layer side with a resist, a grinding device is used to grind until the thickness of the supporting substrate (Si substrate) reaches 150 μm. Furthermore, a back electrode (Ti (thickness: 10 nm) / Pt (thickness: 50 nm) / Au (thickness 200 nm)) is formed on the ground surface of the Si substrate, i.e., the back side, and chip singulation based on cutting is performed to produce the semiconductor light-emitting element involved in Example 1. It should be noted that the chip size is 250 μm × 250 μm.

[0171] (Examples 2 to 4, Comparative Examples 1 to 6)

[0172] In the following examples and comparative examples, semiconductor light emitting devices were produced in which the Al composition ratio of the n-type cladding layer composed of InGaAlAs was appropriately changed from 48% to 0%, and in which the composition of the n-type cladding layer was changed to InP or GaAs.

[0173] (Example 2)

[0174] In addition to changing the composition of the n-type cladding from In 0.52 Ga 0.18 Al 0.30 As changed to In 0.52 Ga 0.23 Al 0.25 A semiconductor light emitting device according to Example 2 was obtained in the same manner as in Example 1 except for As (ie, Al composition ratio of 25%).

[0175] (Example 3)

[0176] In addition to changing the composition of the n-type cladding from In 0.52 Ga 0.18 Al 0.30 As changed to In 0.52 Ga 0.28 Al 0.20 A semiconductor light emitting device according to Example 3 was obtained in the same manner as in Example 1 except for As (ie, Al composition ratio of 20%).

[0177] (Example 4)

[0178] In addition to changing the composition of the n-type cladding from In 0.52 Ga0.18 Al 0.30 As changed to In 0.52 Ga 0.33 Al 0.15 A semiconductor light emitting device according to Example 4 was obtained in the same manner as in Example 1 except for As (ie, Al composition ratio of 15%).

[0179] (Example 5)

[0180] In addition to changing the composition of the n-type cladding from In 0.52 Ga 0.18 Al 0.30 As changed to In 0.52 Ga 0.38 Al 0.10 A semiconductor light emitting device according to Example 5 was obtained in the same manner as in Example 1 except for As (ie, Al composition ratio of 10%).

[0181] (Comparative Example 1)

[0182] In addition to changing the composition of the n-type cladding from In 0.52 Ga 0.18 Al 0.30 As changed to In 0.52 Al 0.48 A semiconductor light emitting device according to Comparative Example 1 was obtained in the same manner as in Example 1 except for As (ie, Al composition ratio of 48%).

[0183] (Comparative Example 2)

[0184] In addition to changing the composition of the n-type cladding from In 0.52 Ga 0.18 Al 0.30 As changed to In 0.52 Ga 0.13 Al 0.35 A semiconductor light emitting device according to Comparative Example 2 was obtained in the same manner as in Example 1 except for As (ie, Al composition ratio of 35%).

[0185] (Comparative Example 3)

[0186] In addition to changing the composition of the n-type cladding from In 0.52 Ga 0.18 Al 0.30 As changed to In 0.52 Ga 0.43 Al 0.05 A semiconductor light emitting device according to Comparative Example 3 was obtained in the same manner as in Example 1 except for As (ie, Al composition ratio of 5%).

[0187] (Comparative Example 4)

[0188] In addition to changing the composition of the n-type cladding from In0.52 Ga 0.18 Al 0.30 As changed to In 0.52 Ga 0.43 A semiconductor light emitting device according to Comparative Example 4 was obtained in the same manner as in Example 1 except for the addition of As (ie, the Al composition ratio was 0%).

[0189] (Comparative Example 5)

[0190] In addition to changing the composition of the n-type cladding from In 0.52 Ga 0.18 Al 0.30 A semiconductor light emitting element according to Comparative Example 5 was obtained in the same manner as in Example 1 except that As was changed to InP.

[0191] (Comparative Example 6)

[0192] In addition to changing the composition of the n-type cladding from In 0.52 Ga 0.18 Al 0.30 A semiconductor light emitting element according to Comparative Example 6 was obtained in the same manner as in Example 1 except that As was changed to GaAs.

[0193] (Evaluation of Luminescence Characteristics)

[0194] For the semiconductor light-emitting elements involved in Examples 1 to 4 and Comparative Examples 1 to 6, the forward voltage Vf (V) and the luminous output power Po (mW) based on the integrating sphere were measured when a forward current If (mA) of 30 mA and 36 mA was passed through a constant current voltage power supply. In addition, the luminous center wavelength λp (nm) and the half-value width (FWHM, unit: nm) were also measured based on a spectrum analyzer (AQ6374 manufactured by Yokogawa Instruments Co., Ltd.). It should be noted that the average value of the measurement results of the three samples was calculated during the measurement. Then, the luminous output power was divided by the injected power at that time to calculate Po / (Vf·If), and this value was used as an indicator of the luminous output power per unit injected power. In addition, in each Example and Comparative Example, the rate of increase of the luminous output power was evaluated relative to a comparative product produced by all the same processes except that the surface roughening of the second conductive type cladding was not implemented. The respective measurement results and calculation results are shown in Table 2. Here, a Po increase rate of 120% or more was evaluated as A, a Po increase rate of 110% or more was evaluated as B, and a Po increase rate of less than 110% was evaluated as C. Although not shown in Table 2, the emission center wavelengths of the respective samples were within the range of 1490 nm ± 10 nm.

[0195] [Table 2]

[0196]

[0197] ※Po rise rate A: 120% or more, B: 110% or more, C: less than 110%

[0198] (Measurement of the roughness of the light extraction surface)

[0199] As described above, the rough surface shape of the n-type cladding layer (second conductivity type cladding layer) in the surface-roughened chips (after dicing) was measured using a shape analysis laser microscope (VK-X1000 / 1100 manufactured by KEYENCE). The lens magnification was set to 50x, and the pixel count was set to 2048 × 1536.

[0200] During data measurement, the surface roughness parameters (Sa, Sz, Spc, Sdr, Ssk, etc.) according to ISO 25178 are automatically calculated. Among these values, Sa, Sdr, and Ssk are shown in Table 2 above, and their relationship with the Al composition ratio is shown in Table 2. Figures 9-11 The graph shows this in the table. The graph also shows that as the Al composition ratio increases, the effect of etching on surface roughening increases, with a particularly clear linear correlation observed with Sdr. It should be noted that since InP is not etched, the surface roughness parameter for Comparative Example 5 is indicated as "-" in Table 2.

[0201] In addition, as a representative example, electron microscope observation images of the vicinity of the surface of the n-type cladding layer after surface roughening treatment in cross sections cut across the n-side electrode formation region of the light-emitting elements of Comparative Example 1, Example 1, and Comparative Example 4 are shown in FIG. Figures 12-14 It was observed that the surface of the second conductive type cladding layer of Example 1, which meets the scope of the present invention, is formed with Figure 13 On the other hand, it was confirmed that in Comparative Example 1 where the Al composition ratio exceeded and was higher than the range of the present invention, Figure 12 As shown in FIG. 1 , the boundary between the area where the surface roughening was not performed and the area where the surface roughening was performed using the resist pattern was produced (the frame line and the dotted line are added by the applicant). In Example 1 and Comparative Example 4, no such Figure 12 Excavation shown.

[0202] Industrial applicability

[0203] According to the present invention, a semiconductor light emitting element having better light output per unit of injected power than conventional light emitting elements and capable of forming a protective film without generating voids and a method for manufacturing the same can be provided.

[0204] Description of Reference Numerals

[0205] 10 Growth substrate

[0206] 20 Etch stop layer

[0207] 30 Semiconductor stack

[0208] 31 Second conductivity type cladding layer

[0209] 31A Light extraction surface

[0210] 35 Luminous Layer

[0211] 35W well layer

[0212] 35B barrier layer

[0213] 37 1st conductivity type cladding layer

[0214] 39 cap layer

[0215] 40 Contact Department

[0216] 41 contact layer

[0217] 41A contact area

[0218] 43 Ohm Metal Division

[0219] 50 dielectric layer

[0220] 60 Metal reflective layer

[0221] 70 Metal bonding layer

[0222] 80 Support base plate

[0223] 100 semiconductor light-emitting elements

[0224] 91 back electrode

[0225] 93 Top electrode

Claims

1. A semiconductor light emitting element comprising, in order, a first conductivity type cladding layer, a light emitting layer, and a second conductivity type cladding layer, wherein the second conductivity type cladding layer is a light extraction side, The light-emitting layer is a III-V compound semiconductor, wherein the III-V compound semiconductor includes one or more of Al, Ga, and In as the III group, and one or more of As, Sb, and P as the V group, and the light-emitting center wavelength is 1000 nm to 1900 nm. The composition of the second conductive type cladding layer is In x Ga y Al z As, where 0.49≤x≤0.55, 0.10≤z<0.35, x+y+z=1, The light extraction surface of the second conductive type cladding layer has an extended area ratio Sdr of 4.0 or more.

2. The semiconductor light emitting element according to claim 1, wherein The Al composition ratio z of the second conductivity type cladding layer is 0.15≤z≤0.

30.

3. The semiconductor light emitting element according to claim 1, wherein The second conductive type cladding layer has an arithmetic mean height Sa on a light extraction surface of 0.60 μm or less, and a skewness Ssk of 0.30 or more. The semiconductor light emitting element according to claim 1 , wherein: The band gap of the second conductivity type cladding layer is larger than the band gap of the light emitting layer. The semiconductor light emitting element according to claim 1 , wherein The second conductive type cladding layer has a thickness of 2 μm or more and 10 μm or less. The semiconductor light emitting element according to claim 1 , wherein: The light emitting layer has a quantum well structure in which InGaAlAs-based well layers and InGaAlAs-based barrier layers are alternately stacked.

7. The semiconductor light emitting element according to claim 1, wherein An undoped spacer layer is provided between the first conductivity type cladding layer and the light emitting layer and between the light emitting layer and the second conductivity type cladding layer.

8. The semiconductor light emitting element according to claim 1, comprising a supporting substrate, a first conductivity type cladding layer, a light emitting layer, and a second conductivity type cladding layer in this order, and a metal reflective layer between the supporting substrate and the first conductivity type cladding layer. The semiconductor light emitting element further includes a dielectric layer and a contact portion provided in parallel between the metal reflective layer and the first conductivity type cladding layer.

9. A method for manufacturing a semiconductor light-emitting element, wherein the semiconductor light-emitting element has a second conductivity type cladding layer as a light extraction side, the manufacturing method comprising: a semiconductor stack forming step of sequentially forming a first conductivity type cladding layer, a light emitting layer, and the second conductivity type cladding layer; as well as a surface roughening step of immersing the second conductivity type cladding layer in concentrated nitric acid to roughen the surface, thereby making the spread area ratio Sdr of the light extraction surface of the second conductivity type cladding layer be 4.0 or more; The light-emitting layer is a III-V compound semiconductor, wherein the III-V compound semiconductor includes one or more of Al, Ga, and In as the III group, and one or more of As, Sb, and P as the V group, and the light-emitting center wavelength is 1000 nm to 1900 nm. The composition of the second conductive type cladding layer is In x Ga y Al z As, where 0.49≤x≤0.55, 0.10≤z<0.35, x+y+z=1.

10. The method for manufacturing a semiconductor light emitting element according to claim 9, wherein: In the surface roughening treatment step, the temperature of the concentrated nitric acid is lower than 10°C.

11. The method for manufacturing a semiconductor light emitting element according to claim 9, wherein: In the surface roughening treatment step, the concentration of the concentrated nitric acid is greater than 60 wt %.

12. The method for manufacturing a semiconductor light emitting element according to claim 9, wherein: The Al composition ratio z of the second conductivity type cladding layer is set to 0.15≤z≤0.

30.

13. The method for manufacturing a semiconductor light emitting element according to claim 9, wherein: In the surface roughening step, the surface roughening is performed so that the arithmetic mean height Sa of the light extraction surface of the second conductivity type cladding layer becomes 0.6 μm or less and the skewness Ssk becomes 0.3 or more. 14 . The method for manufacturing a semiconductor light emitting element according to claim 9 , further comprising, after the surface roughening step, a step of forming a mesa structure; and a step of cutting the portion removed by the mesa structure into individual pieces.

15. A method for manufacturing a semiconductor light-emitting element, comprising: a semiconductor stack formation step of sequentially forming an etching stop layer, a second conductivity type cladding layer, a light emitting layer, and a first conductivity type cladding layer on a growth substrate; forming a dielectric layer and a contact portion in parallel on the first conductive type cladding layer; a metal reflective layer forming step of forming a metal reflective layer on the dielectric layer and the contact portion; a bonding step of bonding a support substrate different from the growth substrate with the metal reflective layer interposed therebetween; a growth substrate removal step of removing the growth substrate to expose the etching stop layer; a second-conductivity-type cladding layer exposing step of removing the etching stop layer to expose the top surface of the second-conductivity-type cladding layer on the light extraction side; as well as a surface roughening treatment step, after the second conductivity type cladding layer exposing step, immersing the second conductivity type cladding layer in concentrated nitric acid to roughen the surface, thereby making the spread area ratio Sdr of the light extraction surface of the second conductivity type cladding layer be 4.0 or more; The light-emitting layer is a III-V compound semiconductor, wherein the III-V compound semiconductor includes one or more of Al, Ga, and In as the III group, and one or more of As, Sb, and P as the V group, and the light-emitting center wavelength is 1000 nm to 1900 nm. The composition of the second conductive type cladding layer is In x Ga y Al z As, where 0.49≤x≤0.55, 0.10≤z<0.35, x+y+z=1.

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