Capacitive sensor interface circuit and detection method

Abstract

The invention provides a capacitive sensor interface circuit and a detection method. The circuit comprises a capacitive sensor, a passive common-mode control circuit, an active common-mode control circuit, a voltage-capacitance conversion circuit and a sampling hold circuit. The capacitance matching between the capacitance sensor and the reference capacitor is realized based on negative feedback by adopting the active common-mode control circuit, and the two-stage voltage-capacitance conversion circuit is adopted, so that compared with a traditional amplifier, the finite gain error of the capacitance detection circuit is reduced, the error caused by the load effect of the feedback capacitor is reduced, and the reliability of the amplifier is improved. And the signal-to-noise ratio and the capacitance detection resolution are effectively improved.

Description

Technical Field

[0001] The present disclosure relates to the field of sensor technology, and in particular to a capacitance sensor interface circuit and a detection method. Background Art

[0002] Capacitive sensors offer high precision and can withstand significant temperature fluctuations. Capacitive interface circuits convert the changing capacitance signals collected by the capacitive sensor into voltage signals. The performance of this interface circuit directly impacts the overall performance of the capacitive microelectromechanical system (MEMS). Therefore, the research and design of capacitive sensor interface circuits is of great significance. Traditional capacitive interface circuits suffer from a range of issues, including low capacitance detection resolution and poor linearity, due to problems such as mismatch between the sensor and the internal reference capacitor, large parasitic capacitance between the MEMS sensor and the chip, and limited gain and noise within the circuit. Summary of the Invention

[0003] The purpose of the embodiments of the present disclosure is to provide a capacitance sensor interface circuit and detection method to solve the problems in the prior art of mismatch between the capacitance sensor and the reference capacitance, limited internal gain of the circuit, and excessive noise.

[0004] The embodiment of the present disclosure adopts the following technical solution: a capacitance sensor interface circuit, the capacitance sensor includes at least a first fixed electrode plate, a second fixed electrode plate and an intermediate electrode plate arranged between the first fixed electrode plate and the second fixed electrode plate, the intermediate electrode plate is connected to the positive power supply through a first switch, and the intermediate electrode plate is connected to the negative power supply through a second switch, the interface circuit at least includes: a passive common-mode control circuit, including at least a first reference capacitor and a second reference capacitor, the first end of the first reference capacitor and the first end of the second reference unit are connected to the negative power supply through a third switch and to the positive power supply through a fourth switch, the second end of the first reference capacitor is connected to the first fixed electrode plate and a first node, and the second end of the second reference capacitor is connected to the second fixed electrode plate and a second node; an active common-mode control circuit, including at least a first amplifier, the non-inverting input terminal of the first amplifier is connected to the reference voltage, the inverting input terminal of the first amplifier is connected to the first node and the The first amplifier is connected to the second node, the output end of the first amplifier is connected to the first node in series with the first negative feedback capacitor, and the output end of the first amplifier is connected to the second node in series with the second negative feedback capacitor; the voltage-capacitance conversion circuit includes at least a first-stage conversion circuit and a second-stage conversion circuit, the first-stage conversion circuit is connected to the first node and the second node, and is used to collect and amplify the first capacitance signal between the first fixed electrode and the intermediate electrode for the first time, and output a first amplified signal, and to collect and amplify the second capacitance signal between the second fixed electrode and the intermediate electrode for the first time, and output a second amplified signal; the second-stage conversion circuit is connected to the first-stage conversion circuit and the reference voltage, and is used to amplify the first amplified signal and the second amplified signal for the second time, and output a third amplified signal and a fourth amplified signal; the sampling and holding circuit is connected to the second-stage conversion circuit, and is used to control the output of the third amplified signal and the fourth amplified signal.

[0005] The present disclosure also provides a detection method for a capacitance sensor, which uses the capacitance sensor interface circuit as described above. The detection method includes: in an initialization phase, controlling the first switch and the third switch to be closed, and the second switch and the fourth switch to be opened, so that the middle plate of the capacitance sensor is connected to a positive power supply, the passive common mode control circuit is connected to a negative power supply, the active common mode control circuit achieves adaptive common mode level stability through negative feedback, and controls the reference voltage to be connected to the voltage capacitance conversion circuit, the first node and the second node for initialization; in a sampling phase, controlling the first switch and the third switch to be opened, and the second switch and the fourth switch to be closed, so that the middle plate is connected to a negative power supply. power supply, the passive common-mode control circuit is connected to a positive power supply, and controls the first-stage conversion circuit to collect a first capacitance signal between the first fixed electrode plate and the intermediate electrode plate, and a second capacitance signal between the second fixed electrode plate and the intermediate electrode plate; in the amplification stage, controls the first-stage conversion circuit to amplify the first capacitance signal and the second capacitance signal for a first time, outputs a first amplified signal and a second amplified signal, controls the second-stage conversion circuit to amplify the first amplified signal and the second amplified signal for a second time, outputs a third amplified signal and a fourth amplified signal, and controls the sampling and holding circuit to output the third amplified signal and the fourth amplified signal.

[0006] The beneficial effects of the embodiments of the present disclosure are: an active common-mode control circuit is adopted to achieve capacitance matching between the capacitance sensor and the reference capacitor based on negative feedback, and a two-stage voltage-capacitance conversion circuit is adopted. Compared with traditional amplifiers, the limited gain error of the capacitance detection circuit is reduced, the error caused by the load effect of the feedback capacitor is reduced, and the signal-to-noise ratio and capacitance detection resolution are effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate one or more embodiments of this specification or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0008] Figure 1 This is a schematic structural diagram of a capacitance sensor interface circuit in the first embodiment of the present disclosure;

[0009] Figure 2 is the physical model of the capacitive sensor in the first embodiment of the present disclosure;

[0010] Figure 3 Schematic diagram of the circuit structure of the voltage-capacitance conversion circuit in the first embodiment of the present disclosure;

[0011] Figure 4 for Figure 3 Schematic diagram of the timing of on-off control of all switches in the system;

[0012] Figure 5 This is an overall framework diagram of the sigma-delta modulator in the first embodiment of the present disclosure;

[0013] Figure 6 2 is a schematic structural diagram of a first-stage integrator in the first embodiment of the present disclosure;

[0014] Figure 7 Flowchart of the detection method in the second embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below in conjunction with the drawings in one or more embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this document.

[0016] Capacitive sensors offer high precision and can withstand significant temperature fluctuations. Capacitive interface circuits convert the changing capacitance signals collected by the capacitive sensor into voltage signals. The performance of this interface circuit directly impacts the overall performance of the capacitive microelectromechanical system (MEMS). Therefore, the research and design of capacitive sensor interface circuits is of great significance. Traditional capacitive interface circuits suffer from a range of issues, including low capacitance detection resolution and poor linearity, due to problems such as mismatch between the sensor and the internal reference capacitor, large parasitic capacitance between the MEMS sensor and the chip, and limited gain and noise within the circuit.

[0017] In order to solve the above problems, a first embodiment of the present disclosure provides a capacitance sensor interface circuit for accurately collecting capacitance changes of a capacitance sensor. Figure 1 FIG. 1 is a schematic diagram of the structure of the interface circuit in this embodiment. Figure 1As shown, the capacitance sensor 10 serves as the capacitance to be detected, which includes at least a first fixed electrode 11, a second fixed electrode 12 and an intermediate electrode 13 located between the above two fixed electrodes. The intermediate electrode 13 is connected to the positive power supply VDD through the first switch S1 and is connected to the negative power supply VSS through the second switch S2. The interface circuit includes a passive common-mode control circuit 20, which includes at least a first reference capacitor CM1 and a second reference capacitor CM2, wherein the first end of the first reference capacitor CM1 and the first end of the second reference unit CM2 are connected to the negative power supply VSS through a third switch S3 and to the positive power supply VDD through a fourth switch S4, the second end of the first reference capacitor CM1 is connected to the first fixed plate 11 and the first node A, and the second end of the second reference unit CM2 is connected to the second fixed plate 12 and the second node B; an active common-mode control circuit 30 includes at least a first amplifier 31, whose non-inverting input terminal is connected to the reference voltage VREF, and whose inverting input terminal is connected to the first node A and the second node B, the output terminal of the first amplifier 31 is connected in series with the first negative feedback capacitor Cfb1 and then connected to the first node A, and the output terminal of the first amplifier 31 is also connected in series with the second negative feedback capacitor Cfb2 and then connected to the second node B; the voltage-capacitance conversion circuit 40 includes at least a first-stage conversion circuit and a second-stage conversion circuit ( Figure 1 (not shown in the figure), wherein the first-stage conversion circuit is connected to the first node and the second node, and is used to collect and amplify the first capacitance signal between the first fixed electrode plate and the middle electrode plate for the first time, and output the first amplified signal, and collect and amplify the second capacitance signal between the second fixed electrode plate and the middle electrode plate for the first time, and output the second amplified signal; the second-stage conversion circuit is connected to the first-stage conversion circuit and the reference voltage, and is used to amplify the first amplified signal and the second amplified signal for the second time, and output the third amplified signal and the fourth amplified signal; the sampling and holding circuit 50 is connected to the second-stage conversion circuit, and is used to control the output of the third amplified signal and the fourth amplified signal.

[0018] In this embodiment, using Figure 1Each cycle of the capacitance sensor capacitance detection performed by the interface circuit shown includes three stages. The first stage is an initialization stage. During the initialization stage, the first switch S1 and the third switch S3 are controlled to be closed, and the second switch S2 and the fourth switch S4 are controlled to be disconnected, so that the intermediate plate 13 is connected to VDD, the passive common-mode control circuit 20 is connected to VSS, and the active common-mode control circuit 30 achieves adaptive common-mode level stabilization through negative feedback, and controls the reference voltage to be connected to the voltage-capacitance conversion circuit 40, the first node A and the second node B for initialization. The second stage is a sampling stage. At this time, the first switch S1 and the third switch S3 are controlled to be disconnected, and the second switch S2 and the fourth switch S4 are closed, so that the intermediate plate 13 is connected to VSS, the passive common-mode control circuit 20 is connected to VDD, and the switch state within the first-stage conversion circuit is controlled so that the first-stage conversion circuit collects the first capacitance signal CS between the first fixed plate and the intermediate plate. + , and the second capacitance signal CS between the second fixed plate and the middle plate - ; The third stage is the amplification stage. At this time, the switching states of S1 to S4 remain unchanged. By controlling the switching states inside the first-stage conversion circuit and the second-stage conversion circuit, the first-stage conversion circuit amplifies the first capacitor signal and the second capacitor signal for the first time, and outputs the first amplified signal and the second amplified signal. The second-stage conversion circuit amplifies the first amplified signal and the second amplified signal for the second time, and outputs the third amplified signal and the fourth amplified signal, and controls the sampling and holding circuit to output the third amplified signal and the fourth amplified signal.

[0019] The capacitive sensor used in this embodiment can be, but is not limited to, a variable distance capacitive sensor or a variable area capacitive sensor. Figure 2 Figure 2 shows a physical model of a capacitive sensor. Figure 2 As shown, the upper and lower plates 11 and 12 are fixed, and the middle plate 13 changes according to the acceleration α. ​​According to the physical principle of capacitance, when the middle plate changes, the change in the distance Δx between the upper and lower plates will become a change in capacitance value. That is, when the middle plate 13 moves toward the first fixed plate 11 or the second fixed plate 12, the first capacitance signal between the first fixed plate 12 and the middle plate 13, and the second capacitance signal between the second fixed plate 12 and the middle plate 13 will change. If the first capacitance signal is CS + , the second capacitance signal is CS - , when the capacitance sensor is in equilibrium, the distance between the middle plate and the fixed plates on both sides is d, then CS + =CS _ = C0, when the middle plate 13 moves, the distance between it and the upper and lower plates changes in the same way, both are Δx, then the first capacitance signal and the second capacitance signal will change by the same capacitance value ΔC, then the first capacitance signal CS+ =C0+ΔC, the second capacitance signal CS - =C0-ΔC.

[0020] Specifically, the positive power supply VDD may be, but is not limited to, a power supply capable of providing a positive voltage, and may be an alternating current power supply. The negative power supply VSS may be, but is not limited to, a power supply capable of providing a negative voltage. In an exemplary embodiment, the negative power supply VSS may be a ground terminal. In a typical implementation, the reference voltage VREF = 1 / 2 VDD.

[0021] The passive common-mode control circuit 20 corresponds to the design of the reference capacitor. Under normal circumstances, the capacitance of the first reference capacitor CM1 and the second reference capacitor CM2 is equal to the capacitance value C0 when the capacitance sensor is in a balanced state to ensure the accuracy of the capacitance sensor signal detection. Therefore, the first reference capacitor CM1 and the second reference capacitor CM2 can be changed according to different capacitance sensors, making it applicable to the detection requirements of any capacitance sensor, thereby improving the universality and flexibility of the capacitance sensor interface circuit. In some embodiments, the first reference capacitor CM1 and the second reference capacitor CM2 can be implemented using multiple capacitors connected in parallel, each with a different capacitance value. By connecting capacitors of different capacitance values ​​during use, the equivalent capacitance value can be changed, thereby achieving the variability of the capacitance values ​​of the first reference capacitor CM1 and the second reference capacitor CM2.

[0022] Furthermore, although the passive common mode control circuit partially realizes the adjustment of the reference capacitance, its adjustable range is large, but the adjustment accuracy cannot be guaranteed. Therefore, this embodiment further provides an active common mode control circuit 30 to realize the adaptive common mode level stabilization function through negative feedback. Figure 1 As shown, the active common mode control circuit 30 mainly includes a first amplifier 31 and two negative feedback capacitors Cfb1 and Cfb2. + , CS - When the balancing capacitors C0 and CM are the same, the common-mode voltage at the first node A and the second node B will always remain constant at 1 / 2 VDD in each cycle. At this time, the non-inverting input terminal of the active common-mode control section, first amplifier 31, is set to 1 / 2 VDD. The output of the first amplifier 31 remains unchanged, and the voltages at the first node A and the second node B will not be affected by the two negative feedback capacitors. If CM and C0 are different, after entering the sampling phase, the voltages at the first node A and the second node B will no longer be 1 / 2 VDD, but will have a certain deviation. The following describes the principle of eliminating this deviation in the active common-mode control circuit, combining the principle of charge conservation. To avoid affecting the analysis, this embodiment does not consider differential-mode signals, but only common-mode conditions.

[0023] According to the principle of conservation of charge:

[0024] (V0-VDD)CM+V0*C0=1 / 2VDD*CM+(1 / 2VDD-VDD)*C0;

[0025] get:

[0026]

[0027] Where V0 represents the voltage difference between the first node A and the second node B, 1 / 2VDD is the reference voltage, C0 is the capacitance of the reference capacitor in the equilibrium state, and CM is the capacitance of the reference capacitor. Based on formula (1), it can be seen that the greater the difference between CM and C0, the greater the deviation between V0 and 1 / 2VDD. When CM = C0, V0 = 1 / 2VDD.

[0028] After adding the active common-mode control circuit, the first amplifier uses the principle of charge conservation to obtain the following equation:

[0029] (V0′-Vt)Cfb+(V0′-VDD)CM+V0′*C0=(V0-VDD)CM+V0*C0;

[0030] And we have: Vt=(V0'-1 / 2VDD)*A+1 / 2VDD, we get:

[0031]

[0032] Where A is the gain of the first amplifier, Vt is the output voltage of the first amplifier, and V0′ is the voltage difference between the first node A and the second node B. Compared with formula (1), the error term V0′ has an additional (1-A)Cfb in the denominator. Therefore, as long as the gain A is large enough, V0′ can be infinitely close to 1 / 2VDD. In this way, the common-mode level can be well controlled near 1 / 2VDD without significantly changing the differential signal.

[0033] Figure 3 FIG. 1 shows a schematic diagram of the circuit structure of the voltage-capacitance conversion circuit of this embodiment. Figure 3 The circuit structure shown in FIG. 4 shows that the entire C / V conversion (i.e., capacitance-voltage conversion) is divided into two stages, namely, the first stage conversion circuit 41 and the second stage conversion circuit 42. Figure 3 The two-stage conversion circuit structure shown is coordinated with the timing control of each switch so that the outputs of the two conversion circuits are separated.

[0034] Specifically, if Figure 3As shown, the first stage conversion circuit 41 mainly includes a second amplifier 410, a first conversion capacitor C1, a second conversion capacitor C2, a first load capacitor Ccls1, a second load capacitor Ccls2, a first sampling capacitor Ccds1 and a second sampling capacitor Ccds2. The non-inverting input terminal of the second amplifier 410 is connected in series with the first sampling capacitor Ccds1 and then connected to the first node A. The inverting input terminal of the second amplifier 410 is connected in series with the second sampling capacitor Ccds2 and then connected to the second node B. The first output terminal of the second amplifier 410 is connected in series with the fifth switch S5 and then connected to the non-inverting input terminal of the second amplifier 410. The second output terminal of the second amplifier 410 is connected in series with the sixth switch S6 and then connected to the inverting input terminal of the second amplifier 410. The first end of the first conversion capacitor C1 is connected to the first node A. The second end of the first conversion capacitor C1 is connected in series with the seventh switch S7 and then connected to the third node C. The third node C is connected in series with the ninth switch S9 and then connected to the first output terminal of the second amplifier 410. The first end of the second conversion capacitor C2 is connected to the second node B. The second end of the second conversion capacitor C2 is connected in series with the eighth switch S8 and then connected to the fourth node D. The fourth node D is connected to the second output terminal of the second amplifier 410 through the tenth switch S10. A first end of a load capacitor Ccls1 is connected to the first output end through an eleventh switch S11, a second end of the first load capacitor Ccls1 is connected to the third node C, a first end of a second load capacitor Ccls2 is connected to the second output end through a twelfth switch S12, and a second end of the second load capacitor Ccls2 is connected to the fourth node D; a first end of the first conversion capacitor C1 is also connected to the reference voltage VREF through a thirteenth switch S13, a second end of the first conversion capacitor C1 is also connected to the reference voltage VREF through a fifteenth switch S15, a first end of the second conversion capacitor C2 is also connected to the reference voltage VREF through a fourteenth switch S14, a second end of the second conversion capacitor C2 is also connected to the reference voltage VREF through a sixteenth switch S16, a second end of the first load capacitor Ccls1 is also connected to the reference voltage VREF through a seventeenth switch S17, and a second end of the second load capacitor Ccls2 is also connected to the reference voltage VREF through an eighteenth switch S18.

[0035] Since the common mode capacitance interference has been offset by the passive and active common mode control circuits, the common mode level change is ignored when analyzing the differential mode gain. That is, it is assumed that CM = C0 at this time, and the reference capacitance is exactly equal to the capacitance sensor balance capacitance. When the capacitance sensor generates a capacitance signal, CS + =C0+ΔC; CS - = C0 - ΔC. C1 and C2 are the first-stage conversion capacitors, used to convert the aforementioned capacitance signal into a voltage signal. The following deduces the charge conservation relationship for the first, second, third, and fourth nodes, as well as the two output terminals of the second amplifier, according to different stages within the detection cycle.

[0036] For the charge of the first node A:

[0037] In the initialization phase, the control switches S1, S3, S5, S6, S9, S10, S13, S14, S15, and S16 are closed, and the remaining switches are open. At this time, the charge QA at the first node A is + for:

[0038] QA + =CM*(VREF-0)+CS + *(VREF-VDD)+Ccds1*(VREF-V C );

[0039] Among them, V C represents the voltage value of the third node C at this time, CM is the capacitance of the current reference capacitor, and CS + Indicates the capacitance between the first fixed plate and the middle plate.

[0040] In the sampling phase, the control switches S2, S4, S7, S8, S9, S10, S17, and S18 are closed, and the remaining switches are open. At this time, the charge of the first node A for:

[0041]

[0042] Among them, V A is the voltage value of the first node A at this time, Vin + The voltage value input to the non-inverting input terminal of the second amplifier.

[0043] Similarly, for the second node B, its charge conditions in the initialization phase and the sampling phase are respectively:

[0044] QB - =CM*(VREF-0)+CS - *(VREF-VDD)+Ccds2*(VREF-V D );

[0045]

[0046] Among them, QB - is the charge of the second node B in the initialization stage, is the charge of the second node B during the sampling phase, V B is the voltage of the second node B, V D is the voltage of the fourth node D, CS - is the capacitance between the second fixed plate and the middle plate, Vin - The voltage value input to the negative input terminal of the second amplifier.

[0047] Based on the principle of charge conservation, And there are:

[0048] A*((Vin + -Vin - )=V D -V C ;

[0049] Between the initial stage and the sampling stage, the charge conservation at the third and fourth nodes is expressed as follows:

[0050]

[0051]

[0052] Due to the common-mode input feedback, we have: V A +V B =VDD;

[0053] In the sampling phase, since S9, S10, S17 and S18 are closed and S11 and S12 are open, Ccls1 and Ccls2 act as the load of the amplifier, and the voltages on them are Vo1 and Vo2, that is, the voltages output by the two output terminals of the amplifier. At this time, Vo1 = V C , Vo2=V D , corresponding to the first capacitance signal and the second capacitance signal obtained by sampling respectively:

[0054]

[0055] where K represents the error attenuation factor at the end of the sampling phase:

[0056]

[0057] In the amplification stage, the control switches S2, S4, S7, S8, S11, and S12 are closed, and the other switches are open. Ccls1 is connected between the first output terminal of the amplifier and the third node, and Ccls2 is connected between the second output terminal of the amplifier and the fourth node. At this time, V C The first amplified signal V is obtained after the first capacitor signal is amplified for the first time. D This corresponds to the second amplified signal obtained after the first amplification of the second capacitor signal:

[0058]

[0059] where Keq represents the error attenuation factor at the end of the amplification phase:

[0060] Keq=K(K+2)≈K 2; (6)

[0061] Based on the above formula, we can see that the output voltages of Vout2 and Vout3 both have an error term. This is because the amplifier's gain is limited, and the amplifier is not an ideal virtual short at the input. Therefore, when using charge conservation calculations, there is a deviation from the ideal situation. Therefore, during the sampling phase, the charge signal cannot be completely transferred to C1 and C2. At this time, the actual voltage difference between the positive and negative input terminals of the amplifier is Vd2:

[0062] Vd2=Vout2 / A;

[0063] However, as can be seen from equations (3) and (5), the error term for Vout3 is even smaller at the end of the amplification phase. This is because during the amplification phase, the second terminal of Ccls, originally connected to the reference voltage, is connected across the amplifier's output, reducing the actual voltage difference at the amplifier's output. Originally, at the end of the sampling phase, the amplifier output voltage was Vout2 = Vo1 - Vo2. After entering the amplification phase, the amplifier output voltage becomes Vout3 - Vout2, significantly reducing the actual voltage difference Vd3 between the amplifier's positive and negative input terminals:

[0064] Vd3≈(Vout3-Vout2) / A;

[0065] Vd3 is much smaller than Vd2, significantly reducing the finite gain error of the second amplifier. The charge signal can be more perfectly transferred to the conversion capacitors C1 and C2, and the output voltage Vout3 can accurately reflect the magnitude of the differential capacitance signal.

[0066] In some embodiments, the second amplifier is implemented using a folded cascode amplifier with gain bootstrapping, which has a higher gain and can significantly improve detection accuracy.

[0067] Furthermore, in order to detect capacitance signals below the femtofarad level and achieve high-resolution function, C1 usually needs to be made very small, but at this time the denominator A*C1 in the K expression may be very small. At this time, it is not enough to use the amplification stage phase to reduce the finite gain error to the square term of K, because K itself is very small. Therefore, this embodiment uses a two-stage conversion circuit for amplification, so that the capacitance of the conversion capacitor in the first-stage conversion circuit does not need to be set too low, and part of the gain is achieved by the second-stage amplification, which ensures both high precision and high resolution.

[0068] Specifically, if Figure 3As shown, the second-stage conversion circuit 42 at least includes: a third amplifier 420, a first feedback capacitor C3, a second feedback capacitor C4, a first gain capacitor CE1, and a second gain capacitor CE2; wherein, the non-inverting input terminal of the third amplifier 420 is connected in series with the first gain capacitor CE1 and the nineteenth switch S19 and then connected to the third node B, and the inverting input terminal of the third amplifier 420 is connected in series with the second gain capacitor CE2 and the twentieth switch S20 and then connected to the fourth node D; the first end of the first feedback capacitor C3 is connected to the non-inverting input terminal of the third amplifier 420, the second end of the first feedback capacitor C3 is connected to the first output terminal of the third amplifier 420, and the first end of the second feedback capacitor C4 is connected to the inverting input terminal of the third amplifier 420. The second end of the second feedback capacitor C4 is connected to the second output end of the third amplifier 420; the first end of the first gain capacitor CE1 is also connected to the reference voltage VREF through the twenty-first switch S21, the first end of the second gain capacitor CE2 is also connected to the reference voltage VREF through the twenty-second switch S22, the first end of the first feedback capacitor C3 is also connected to the reference voltage VREF through the twenty-third switch S23, the first end of the second feedback capacitor C4 is also connected to the reference voltage VREF through the twenty-fourth switch S24, the second end of the first feedback capacitor C3 is also connected to the reference voltage VREF through the twenty-fifth switch S25, and the second end of the second feedback capacitor C4 is also connected to the reference voltage VREF through the twenty-sixth switch S26.

[0069] In the initialization phase and sampling phase, control S21 and S22 are closed, and the other switches are disconnected; in the amplification phase, control S19, S20, S23, S24, S25, and S26 are closed, and S21 and S22 are disconnected, and the first amplified signal and the second amplified signal output by the first-stage conversion circuit are sampled onto CE1 and CE2 respectively. At this time, the first ends of CE1 and CE2 have been set to the reference voltage, and the second ends of CE1 and CE2 are the first amplified signal and the second amplified signal respectively, and the feedback capacitors C3 and C4 are reset to the reference voltage; when the amplification phase is about to end but before entering the initialization phase of the next cycle Before the initialization stage, S19, S20, S23, S24, S25, and S26 are disconnected in advance to eliminate the undesirable charge distribution effect caused by the disconnection at the same time as the amplification stage. At this time, S21 and S22 are not closed yet; in the initialization stage of the next cycle, S21 and S22 are controlled to be closed, and the other switches are disconnected. The second end of CE is set to the reference voltage, and the input end of the third amplifier is virtually shorted, so its input end is also the reference voltage, so that the charge signal is transferred to the feedback capacitors C3 and C4, realizing the second amplification after being disconnected from the first-stage conversion circuit. The ratio between the gain capacitor and the feedback capacitor is the amplification gain of the second-stage conversion circuit.

[0070] The principle of the second amplification is explained by analyzing the charge conservation of the fifth node E and the sixth node F:

[0071]

[0072]

[0073] Since the positive and negative input terminals of the third amplifier are virtually shorted, V E =V F , and CE1=CE2, C3=C4, then:

[0074]

[0075] Among them, V E is the voltage of the fifth node E, V F is the voltage of the sixth node F, V G is the voltage of the seventh node G, that is, the voltage value obtained after the first amplified signal is amplified twice, V H is the voltage of the eighth node H, ie, the voltage value obtained after the second amplified signal is amplified twice.

[0076] Finally, the output of the second-stage conversion circuit is:

[0077]

[0078] It should be noted that Figure 3 All switches in the system are implemented using a pair of complementary transistors (NMOS and PMOS in parallel). This reduces the on-resistance of the switches, improves the speed of capacitor sampling, and reduces the nonlinearity caused by charge injection, which has a significant impact when a single MOS is used as a switch. The on and off control of the corresponding switches is achieved based on opposite control signals applied to the gates of the complementary transistors. Figure 4 Shown Figure 3 The timing diagram of the on-off control of all switches in the system. For convenience, the high and low levels represent the gate signals of the nmos tube (the opposite is true for pmos). Figure 4 All high levels correspond to control signals for closing corresponding switches, and all low levels correspond to control signals for opening corresponding switches. Figure 4 There are 5 control signals in total, among which the first control signal K1 is used to control S1, S3, S5, S6, S13, S14, S15, and S16; the second control signal K2 is used to control S2, S4, S7, and S8; the third control signal K3 is used to control S11 and S12; the fourth control signal K4 is used to control S9, S10, S17, S18, S21, and S22; the fifth control signal K5 is used to control S19, S20, S23, S24, S25, and S26, and Figure 4 The different stages within a cycle are marked in the figure, where T1 represents the initialization stage, T2 represents the sampling stage, and T3 represents the amplification stage. The figure also shows the differences in timing control of different control signals within the same stage.

[0079] Further integration Figure 1 The interface circuit further includes a sigma-delta modulator 60 connected to the output terminal of the sample-and-hold circuit 50, and configured to modulate the voltage difference between the third amplified signal and the fourth amplified signal into a digital signal for output. Specifically, in some embodiments, the sigma-delta modulator is a fourth-order single-bit discrete modulator, and its overall framework is shown in FIG. Figure 5 As shown, and since the contribution of the operational amplifier of the first-stage integrator of the modulator to the noise is basically dominant, the first-stage integrator of the fourth-order single-bit discrete modulator of this embodiment is an integrator with chopping modulation, and its structure is as follows: Figure 6 As shown in the figure, by adding chopping switches Ch1 and Ch2 to the input and output of the op amp, chopping modulation can be used to modulate low-frequency flicker noise and offset voltage to a high frequency. This noise is then removed through subsequent processing, and the signal is restored to its input frequency through modulation and demodulation. The higher the chopping frequency, the higher the frequency band can be pushed to. The voltage signal is finally converted to a 1-bit digital output by the modulator. It should be noted that Figure 6 The switches shown in the Figure 4 The control signal shown is used to control the Figure 6 The switches are not numbered, and only the on-off control conditions of the corresponding control signals are described.

[0080] In some embodiments, the interface circuit should also include a clock circuit 70 and a low-dropout linear voltage regulator circuit 80 (LDO circuit). The clock circuit 70 is used to provide a suitable clock to the switches of other circuit parts. Since the design of the switch not only involves sampling accuracy and speed, different compensation schemes are designed for switches at different positions in the circuit to minimize the impact of clock feedthrough and charge injection. The LDO circuit 80 is used to provide corresponding power supply and reference voltage, such as VDD and VREF. Since the accuracy of the corresponding voltage will affect the final detected output voltage value, the LDO circuit is designed inside the chip to provide precise voltage, which further ensures the detection accuracy.

[0081] This embodiment uses an active common-mode control circuit to achieve capacitance matching between the capacitance sensor and the reference capacitor based on negative feedback, and adopts a two-stage voltage-capacitance conversion circuit. Compared with traditional amplifiers, this reduces the finite gain error of the capacitance detection circuit and the error caused by the load effect of the feedback capacitor, effectively improving the signal-to-noise ratio and capacitance detection resolution.

[0082] Based on the same inventive concept, the second embodiment of the present disclosure provides a detection method for a capacitance sensor, which is mainly applied to the capacitance sensor interface circuit provided in the first embodiment of the present disclosure. The flow chart of the method is shown in FIG. Figure 7 As shown, it mainly includes steps S10 to S30:

[0083] S10, in the initialization phase, controlling the first switch and the third switch to be closed, and the second switch and the fourth switch to be open, so that the middle plate of the capacitive sensor is connected to a positive power supply, the passive common-mode control circuit is connected to a negative power supply, the active common-mode control circuit achieves adaptive common-mode level stabilization through negative feedback, and controls the reference voltage to be connected to the voltage-capacitance conversion circuit, the first node, and the second node for initialization;

[0084] S20, in a sampling phase, controlling the first switch and the third switch to be open and the second switch and the fourth switch to be closed, so that the inter-plate is connected to a negative power supply, the passive common-mode control circuit is connected to a positive power supply, and the first-stage conversion circuit is controlled to collect a first capacitance signal between the first fixed plate and the middle plate, and a second capacitance signal between the second fixed plate and the middle plate;

[0085] S30, in the amplification stage, controls the first-stage conversion circuit to amplify the first capacitor signal and the second capacitor signal for the first time, outputs the first amplified signal and the second amplified signal, controls the second-stage conversion circuit to amplify the first amplified signal and the second amplified signal for the second time, outputs the third amplified signal and the fourth amplified signal, and controls the sampling and holding circuit to output the third amplified signal and the fourth amplified signal.

[0086] In some embodiments, in combination with the specific circuit structure of the voltage-capacitance conversion circuit, in the initialization stage, the reference voltage is controlled to be connected to the voltage-capacitance conversion circuit, the first node and the second node for initialization, including: controlling the fifth switch, the sixth switch, the thirteenth switch, the fourteenth switch, the fifteenth switch and the sixteenth switch to be closed, and the other switches in the first-stage conversion circuit to be disconnected, so as to initialize the first conversion capacitor, the second conversion capacitor, the first sampling capacitor, the second sampling capacitor, the first node and the second node.

[0087] In some embodiments, in combination with the specific circuit structure of the voltage-capacitance conversion circuit, in the sampling stage, the first-stage conversion circuit is controlled to collect the first capacitance signal between the first fixed electrode plate and the intermediate electrode plate, and to collect the second capacitance signal between the second fixed electrode plate and the intermediate electrode plate, including: controlling the seventh switch, the eighth switch, the ninth switch, the tenth switch, the seventeenth switch and the eighteenth switch to be closed, and the other switches in the first-stage conversion circuit to be disconnected, so that the third node collects the first capacitance signal between the first fixed electrode plate and the intermediate electrode plate, and the fourth node collects the second capacitance signal between the second fixed electrode plate and the intermediate electrode plate.

[0088] In some embodiments, in combination with the specific circuit structure of the voltage-capacitance conversion circuit, in the amplification stage, controlling the first-stage conversion circuit to perform a first amplification on the first capacitance signal and the second capacitance signal to output the first amplified signal and the second amplified signal, and controlling the second-stage conversion circuit to perform a second amplification on the first amplified signal and the second amplified signal to output the third amplified signal and the fourth amplified signal, includes: controlling the seventh switch, the eighth switch, the eleventh switch, the twelfth switch, the nineteenth switch, the twentieth switch, the twenty-third switch, the twenty-fourth switch, the twenty-fifth switch, and the twenty-sixth switch to be closed, and other switches in the first-stage conversion circuit and the second-stage conversion circuit to be opened, so that the first-stage conversion circuit performs a first amplification on the first capacitance signal and the second capacitance signal, the third node outputs the first amplified signal, and the fourth node outputs the second amplified signal; controlling the nineteenth switch, the twentieth switch, the twenty-third switch, the twenty-fourth switch, the twenty-fifth switch, and the twenty-sixth switch to be opened, so that the second-stage conversion circuit performs a second amplification on the first amplified signal and the second amplified signal, the first output terminal of the third amplifier outputs the third amplified signal, and the second output terminal of the third amplifier outputs the fourth amplified signal.

[0089] Because the capacitive sensor detection method provided in this embodiment is implemented using the capacitive sensor interface circuit provided in the first embodiment, the capacitive sensor detection method possesses the technical features of the capacitive sensor interface circuit provided in the first embodiment and can achieve the beneficial effects of the capacitive sensor interface circuit provided in the first embodiment. Similarities can be found in the description of the capacitive sensor interface circuit provided in the first embodiment, and will not be repeated here.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A capacitance sensor interface circuit, characterized in that: The capacitive sensor includes at least a first fixed plate, a second fixed plate, and an intermediate plate disposed between the first fixed plate and the second fixed plate, wherein the intermediate plate is connected to a positive power supply via a first switch, and the intermediate plate is connected to a negative power supply via a second switch, and the interface circuit includes at least: A passive common-mode control circuit includes at least a first reference capacitor and a second reference capacitor, wherein a first end of the first reference capacitor and a first end of the second reference unit are connected to a negative power supply via a third switch and to a positive power supply via a fourth switch, a second end of the first reference capacitor is connected to the first fixed plate and a first node, and a second end of the second reference capacitor is connected to the second fixed plate and a second node; An active common-mode control circuit includes at least a first amplifier, wherein a non-inverting input terminal of the first amplifier is connected to a reference voltage, an inverting input terminal of the first amplifier is connected to the first node and the second node, an output terminal of the first amplifier is connected in series with a first negative feedback capacitor and then connected to the first node, and an output terminal of the first amplifier is connected in series with a second negative feedback capacitor and then connected to the second node; A voltage-capacitance conversion circuit includes at least a first-stage conversion circuit and a second-stage conversion circuit, wherein the first-stage conversion circuit is connected to the first node and the second node, and is configured to collect and amplify a first capacitance signal between the first fixed plate and the intermediate plate, outputting a first amplified signal, and collect and amplify a second capacitance signal between the second fixed plate and the intermediate plate, outputting a second amplified signal; and the second-stage conversion circuit is connected to the first-stage conversion circuit and the reference voltage, and is configured to amplify the first amplified signal and the second amplified signal for a second time, outputting a third amplified signal and a fourth amplified signal. The sampling and holding circuit is connected to the second-stage conversion circuit and is used to control the output of the third amplified signal and the fourth amplified signal.

2. The capacitance sensor interface circuit according to claim 1, wherein: The first-stage conversion circuit at least includes: a second amplifier, a first conversion capacitor, a second conversion capacitor, a first load capacitor, a second load capacitor, a first sampling capacitor and a second sampling capacitor; wherein, A non-inverting input terminal of the second amplifier is connected in series with the first sampling capacitor and then connected to the first node; an inverting input terminal of the second amplifier is connected in series with the second sampling capacitor and then connected to the second node; a first output terminal of the second amplifier is connected in series with a fifth switch and then connected to the non-inverting input terminal of the second amplifier; a second output terminal of the second amplifier is connected in series with a sixth switch and then connected to the inverting input terminal of the second amplifier; A first end of the first conversion capacitor is connected to the first node, a second end of the first conversion capacitor is connected in series with a seventh switch and then connected to a third node, the third node is connected in series with a ninth switch and then connected to the first output terminal, a first end of the second conversion capacitor is connected to the second node, a second end of the second conversion capacitor is connected in series with an eighth switch and then connected to a fourth node, and the fourth node is connected to the second output terminal via a tenth switch; The first end of the first load capacitor is connected to the first output end via an eleventh switch, the second end of the first load capacitor is connected to the third node, the first end of the second load capacitor is connected to the second output end via a twelfth switch, and the second end of the second load capacitor is connected to the fourth node; The first end of the first conversion capacitor is also connected to the reference voltage through the thirteenth switch, the second end of the first conversion capacitor is also connected to the reference voltage through the fifteenth switch, the first end of the second conversion capacitor is also connected to the reference voltage through the fourteenth switch, the second end of the second conversion capacitor is also connected to the reference voltage through the sixteenth switch, the second end of the first load capacitor is also connected to the reference voltage through the seventeenth switch, and the second end of the second load capacitor is also connected to the reference voltage through the eighteenth switch.

3. The capacitive sensor interface circuit according to claim 2, characterized in that: The second-stage conversion circuit at least includes: a third amplifier, a first feedback capacitor, a second feedback capacitor, a first gain capacitor and a second gain capacitor; wherein, The non-inverting input terminal of the third amplifier is connected in series with the first gain capacitor and the nineteenth switch and then connected to the third node; the inverting input terminal of the third amplifier is connected in series with the second gain capacitor and the twentieth switch and then connected to the fourth node; A first end of the first feedback capacitor is connected to a non-inverting input terminal of the third amplifier, a second end of the first feedback capacitor is connected to a first output terminal of the third amplifier, a first end of the second feedback capacitor is connected to an inverting input terminal of the third amplifier, and a second end of the second feedback capacitor is connected to a second output terminal of the third amplifier; The first end of the first gain capacitor is further connected to the reference voltage through a twenty-first switch, the first end of the second gain capacitor is further connected to the reference voltage through a twenty-second switch, the first end of the first feedback capacitor is further connected to the reference voltage through a twenty-third switch, the first end of the second feedback capacitor is further connected to the reference voltage through a twenty-fourth switch, the second end of the first feedback capacitor is further connected to the reference voltage through a twenty-fifth switch, and the second end of the second feedback capacitor is further connected to the reference voltage through a twenty-sixth switch.

4. The capacitive sensor interface circuit according to claim 1, wherein: Also includes: sigma-delta modulator; The sigma-delta modulator is connected to the output end of the sample and hold circuit, and is used to modulate the voltage difference between the third amplified signal and the fourth amplified signal into a digital signal and then output it.

5. The capacitance sensor interface circuit according to claim 4, characterized in that: The sigma-delta modulator is a fourth-order single-bit discrete modulator, and the first-stage integrator of the fourth-order single-bit discrete modulator is an integrator with chopping modulation.

6. The capacitive sensor interface circuit according to any one of claims 1 to 5, characterized in that: Also includes: Clock circuit and low voltage difference linear voltage regulator circuit.

7. A detection method for a capacitance sensor, characterized in that: Using the capacitive sensor interface circuit according to any one of claims 1 to 6, the detection method includes: During the initialization phase, the first and third switches are controlled to be closed, and the second and fourth switches are opened, so that the middle plate of the capacitive sensor is connected to a positive power supply, the passive common-mode control circuit is connected to a negative power supply, the active common-mode control circuit achieves adaptive common-mode level stabilization through negative feedback, and controls the reference voltage to be connected to the voltage-capacitance conversion circuit, the first node, and the second node for initialization; During a sampling phase, the first switch and the third switch are controlled to be disconnected, and the second switch and the fourth switch are controlled to be closed, so that the inter-plate is connected to a negative power supply, the passive common-mode control circuit is connected to a positive power supply, and the first-stage conversion circuit is controlled to collect a first capacitance signal between the first fixed plate and the intermediate plate, and a second capacitance signal between the second fixed plate and the intermediate plate; In the amplification stage, the first-stage conversion circuit is controlled to amplify the first capacitor signal and the second capacitor signal for the first time, and output a first amplified signal and a second amplified signal; the second-stage conversion circuit is controlled to amplify the first amplified signal and the second amplified signal for the second time, and output a third amplified signal and a fourth amplified signal; and the sampling and holding circuit is controlled to output the third amplified signal and the fourth amplified signal.

8. The detection method according to claim 7, characterized in that In the initialization phase, the reference voltage is controlled to be connected to the voltage-capacitance conversion circuit, the first node, and the second node for initialization, including: The fifth switch, the sixth switch, the thirteenth switch, the fourteenth switch, the fifteenth switch, and the sixteenth switch are controlled to be closed, and the other switches in the first-stage conversion circuit are opened to initialize the first conversion capacitor, the second conversion capacitor, the first sampling capacitor, the second sampling capacitor, the first node, and the second node.

9. The detection method according to claim 8, characterized in that In the sampling phase, controlling the first-stage conversion circuit to collect a first capacitance signal between the first fixed electrode plate and the intermediate electrode plate, and collecting a second capacitance signal between the second fixed electrode plate and the intermediate electrode plate, includes: The seventh switch, the eighth switch, the ninth switch, the tenth switch, the seventeenth switch, and the eighteenth switch are controlled to be closed, and the other switches in the first-stage conversion circuit are opened, so that the third node collects the first capacitance signal between the first fixed electrode plate and the intermediate electrode plate, and the fourth node collects the second capacitance signal between the second fixed electrode plate and the intermediate electrode plate.

10. The detection method according to claim 9, characterized in that: In the amplification stage, controlling the first-stage conversion circuit to amplify the first capacitance signal and the second capacitance signal for the first time, outputting a first amplified signal and a second amplified signal, and controlling the second-stage conversion circuit to amplify the first amplified signal and the second amplified signal for the second time, outputting a third amplified signal and a fourth amplified signal, including: controlling the seventh switch, the eighth switch, the eleventh switch, the twelfth switch, the nineteenth switch, the twentieth switch, the twenty-third switch, the twenty-fourth switch, the twenty-fifth switch, and the twenty-sixth switch to be closed, and the other switches in the first-stage conversion circuit and the second-stage conversion circuit to be open, so that the first-stage conversion circuit performs a first amplification on the first capacitor signal and the second capacitor signal, and the third node outputs the first amplified signal, and the fourth node outputs the second amplified signal; The nineteenth switch, the twentieth switch, the twenty-third switch, the twenty-fourth switch, the twenty-fifth switch, and the twenty-sixth switch are controlled to be open, so that the second-stage conversion circuit amplifies the first amplified signal and the second amplified signal for a second time, the first output end of the third amplifier outputs the third amplified signal, and the second output end of the third amplifier outputs the fourth amplified signal.

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