Optimized variable sampling rate implementation method based on FPGA (Field Programmable Gate Array)

Abstract

The invention provides an optimization variable sampling rate implementation method based on an FPGA. The method comprises the steps that S101, a broadband intermediate frequency real signal s (t) is converted into an intermediate frequency real sequence s (n) after being sampled; s102, performing down-conversion on the s (n) to obtain a baseband complex signal x (n); s103, sampling rate conversion is decomposed into M-level processing, M is larger than or equal to 1, first-level sampling rate conversion is carried out on x (n), and a sequence y '(n) is obtained; d1-time interpolation, filtering and L-time extraction are completed in one step in the first-stage sampling rate conversion; the method comprises the following steps of S104, carrying out sampling rate conversion processing of the rest (M-1) levels in the mode of the step S103 to obtain a sequence y ''(n), and S105, carrying out up-conversion on the sequence y'' (n) to obtain an intermediate frequency complex signal y (m), namely, a sampling-changed sequence with a sampling clock T2. According to the method, hardware resources can be saved, and the working efficiency of an embedded system is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of software radio signal processing, and in particular to an optimized variable sampling rate implementation method based on FPGA (Field Programmable Gate Array). Background Art

[0002] In software-defined radio systems, particularly receiver / transmitter systems developed with embedded FPGAs, designers often want the signal processing portion to maintain a consistent clock rate for various analog-to-digital (AD) and digital-to-analog (DA) converter inputs to accommodate multiple sampling rates. This reduces development workload and increases the adaptability of the signal processing software. Therefore, FPGA-based fast sample rate conversion (SRC) technology is a key technology in software-defined radio systems.

[0003] There are currently relevant literatures that discuss SRC technology in software radio. The typical architecture for achieving arbitrary sampling rate conversion is the sampling rate fractional conversion structure in software radio. The implementation block diagram based on real signals is as follows: Figure 1 The formula is derived as follows:

[0004] According to the sampling theorem, the analog signal x(t) is sampled according to the clock period T, and the resulting sequence X(n) can be expressed as:

[0005]

[0006] Its spectrum is:

[0007]

[0008] After passing through an N-order FIR (Finite Impulse Response) filter, its output sequence y(n) can be expressed as:

[0009]

[0010] After passing through the filter and decimating by L times, the new sequence becomes:

[0011]

[0012] Similarly, after D-fold interpolation, the new sequence can also be expressed as:

[0013]

[0014] Therefore, after the system is FIR filtered, extracted and interpolated, the new sequence can be expressed as:

[0015]

[0016] At this time, the alias-free bandwidth becomes B=B0*D / L.

[0017] The sampling rate of the filter after interpolation is the same as that of the filter before decimation, so it can be replaced by a low-pass filter whose frequency characteristics should meet the following requirements:

[0018]

[0019] In summary, if Figure 1 The fractional sampling rate conversion architecture shown can achieve arbitrary sampling rate conversion, and has a simple structure and is relatively easy to implement in engineering. However, it also has obvious shortcomings:

[0020] (1) The filter is placed after interpolation and before decimation. At this time, the sampling rate is high and the order of the low-pass filter will also be high, which greatly increases the signal processing resources;

[0021] (2) Figure 1 Although the fractional sampling rate conversion architecture uses a filter to connect interpolation and decimation, a large number of filtered data components will be discarded after decimation. For FPGA signal processing, the decimated components still pass through the filter, occupying a large amount of multiplier resources and increasing the processing burden of the embedded system. Summary of the Invention

[0022] In response to the above-mentioned problems, the present invention provides an optimized variable sampling rate implementation method based on FPGA to improve the existing variable sampling rate architecture. While ensuring the system bandwidth, this method uses a simple method to save FPGA processing resources as much as possible and improve the working efficiency of the embedded system.

[0023] In one embodiment, the present invention provides an optimized variable sampling rate implementation method based on FPGA, comprising the following steps:

[0024] S101, a broadband intermediate frequency real signal s(t) is sampled by an analog-to-digital converter AD at time T1 and converted into an intermediate frequency real sequence s(n);

[0025] S102, down-converting the intermediate frequency real sequence s(n) to obtain a baseband complex signal x(n);

[0026] S103, decomposing the sampling rate conversion into M-level processing, where M≥1, first performing a first-level sampling rate conversion on the baseband complex signal x(n) to obtain a sequence y'(n); the first-level sampling rate conversion is completed in one step by D1-fold interpolation, filtering, and L-fold decimation;

[0027] S104, performing sampling rate conversion processing on the remaining M-1 levels in the same manner as in step S103, and finally obtaining a sequence y" (n);

[0028] S105 , up-convert the sequence y”(n) to obtain an intermediate frequency complex signal y(m), which is a sampled sequence with a sampling clock of T2.

[0029] Furthermore, in step S102, the baseband complex signal x(n) is expressed as:

[0030]

[0031] Where f0 is the center frequency of the broadband intermediate frequency real signal s(t).

[0032] Furthermore, the filtering in step S103 is as follows: splitting the filter into D1 phase, delaying the interpolated sequence by LT to also obtain D1 phase, and performing multi-phase filtering.

[0033] Furthermore, in step S105, the intermediate frequency complex signal y(m) is expressed as:

[0034]

[0035] Where f0 is the center frequency of the broadband intermediate frequency real signal s(t).

[0036] In another embodiment, the present invention provides a method for optimizing variable sampling rate based on FPGA, comprising the following steps:

[0037] S201, the broadband intermediate frequency real signal s(t) is sampled by the analog-to-digital converter AD according to time T1 and converted into an intermediate frequency real sequence s(n);

[0038] S202, down-converting the intermediate frequency real sequence s(n) to obtain a baseband complex signal x(n);

[0039] S203, designing a polyphase filter based on the bandwidth B of the baseband complex signal x(n) to filter out out-of-band clutter components in the baseband complex signal x(n);

[0040] S204, decomposing the sampling rate conversion into M-level processing, where M≥1, firstly performs a first-level sampling rate conversion on the sequence obtained by passing the baseband complex signal x(n) through a polyphase filter to obtain a sequence y'(n); the first-level sampling rate conversion is performed in a single step by D1-fold interpolation, filtering, and L-fold decimation;

[0041] S205, performing sampling rate conversion processing on the remaining M-1 levels in the same manner as in step S204, and finally obtaining a sequence y" (n);

[0042] S206 , up-convert the sequence y”(n) to obtain an intermediate frequency complex signal y(m), that is, a sampled sequence with a sampling clock of T2.

[0043] Furthermore, in step S202, the baseband complex signal x(n) is expressed as:

[0044]

[0045] Where f0 is the center frequency of the broadband intermediate frequency real signal s(t).

[0046] Furthermore, in step S203, the frequency response of the polyphase filter is:

[0047]

[0048] Where ω represents the digital angular frequency.

[0049] Furthermore, the filtering in step S204 is as follows: splitting the filter into D1 phase, delaying the interpolated sequence by LT to also obtain D1 phase, and performing multi-phase filtering.

[0050] Furthermore, in step S206, the intermediate frequency complex signal y(m) is expressed as:

[0051]

[0052] Where f0 is the center frequency of the broadband intermediate frequency real signal s(t).

[0053] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0054] 1. The hardware resources required by the present invention are lower than those of the traditional method. The present invention completes the architecture of interpolation-filtering-decimation in one step. Compared with the traditional method, the multiplier can be reduced. The higher the filter order, the more phases the system processes in parallel, and the more hardware resources are saved by using this method.

[0055] 2. The present invention can adapt to the conversion of any sampling rate and has universal applicability.

[0056] 3. The present invention has the capability of real-time processing and is very suitable for implementation by FPGA-based embedded software.

[0057] 4. The present invention does not sacrifice the original signal quality and guarantees In this case, there is no loss of signal bandwidth. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 This is a block diagram for implementing fractional sampling rate conversion.

[0059] Figure 2This is a block diagram of an implementation method for optimizing variable sampling rate based on FPGA provided by the present invention.

[0060] Figure 3 This is a block diagram for implementing the interpolation-filtering-decimation step in an embodiment of the present invention.

[0061] Figure 4a This is a diagram showing the first-stage filter setting of a specific example in an embodiment of the present invention.

[0062] Figure 4b This is a diagram showing the configuration of a second-stage filter according to a specific example in an embodiment of the present invention.

[0063] Figure 5 The following is a diagram of the ModelSim simulation results for a specific example of an embodiment of the present invention. These include: (1) IF signal at 1GHz sampling rate; (2) DDC; (3) interpolation-filtering-decimation; (4) second-order interpolation; (5) results after filtering and DUC; and (6) comparison with MATLAB theoretical simulation. DETAILED DESCRIPTION

[0064] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0065] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are intended to fall within the scope of protection of the present invention.

[0066] Example

[0067] The embodiment of the present invention provides a method for optimizing variable sampling rate based on FPGA. Figure 1 Two changes were made to the variable sampling rate architecture:

[0068] First, the three steps of interpolation, filtering, and extraction are combined into one step, and the signal components that should be discarded in the extraction step are discarded before filtering, which greatly reduces the cost of filter implementation.

[0069] The second is to split the interpolation into multiple stages to reduce the filter order of each stage and further save multiplier resources.

[0070] Assume that the T1 sampling sequence needs to be converted to T2 through sampling rate conversion, and there is no integer multiple relationship between T1 and T2. Then there must be a pair of integers L and D such that That is, interpolation D↑ and extraction L↓. Since interpolation will increase the sampling rate, the subsequent filter order will increase accordingly. Therefore, it is considered to decompose the sampling rate conversion into M-level processing, M≥1, that is, to hierarchically process the interpolation D↑ and split it into multiple levels of interpolation (in this embodiment, the example of splitting into two levels of interpolation is: interpolation D1↑ and D2↑, D=D1·D2) to reduce the sampling rate. In addition, assuming that the signal bandwidth is B, in order to ensure that the spectrum is not aliased, the extraction step should be placed after the interpolation D1↑, and ensure that

[0071] Therefore, if Figure 2 As shown, an embodiment of the present invention provides an optimized variable sampling rate implementation method based on FPGA, comprising the following steps:

[0072] Step 1: The broadband intermediate frequency real signal s(t) is sampled by the analog-to-digital converter AD at time T1 and converted into an intermediate frequency real sequence s(n);

[0073] Step 2: Down-convert the intermediate frequency real sequence s(n) to obtain the baseband complex signal x(n), which is expressed as Where f0 is the center frequency of the broadband intermediate frequency real signal s(t);

[0074] Step 3: design a polyphase filter according to the bandwidth B of the baseband complex signal x(n) to filter out out-of-band clutter components in the baseband complex signal x(n);

[0075] The frequency response of the polyphase filter designed in this embodiment is: Where ω represents the angular frequency. If full probability interception of the signal is required, then step 3 can be omitted; if step 3 is omitted, the sequence x initially processed in step 4 below is h (n) is the baseband complex signal x(n). If step 3 is not omitted, the sequence x initially processed in step 4 is h (n) is the sequence obtained after the baseband complex signal x(n) passes through the polyphase filter;

[0076] Step 4, this step includes interpolation, filtering and extraction, which are completed in the same step. The implementation method of this step is deduced in detail below. Suppose the sequence x obtained after passing through the polyphase filter is h (n)=[s0,s1,...,s N-1 ], the sequence x after interpolation D1↑ h '(n) can be expressed as The number of rows in the matrix is ​​D1. Assume that the M-order low-pass filter h(n) = [h0,h1,…,h M-1], then the signal component after the M-order low-pass filter can be expressed as the sequence y(n)=x h '(n)*h(n), where:

[0077]

[0078] Then, the sequence y(n) is extracted by L↓ to obtain the sequence y'(n), which can be expressed as:

[0079]

[0080] From the above derivation, it can be seen that after the first stage D1 times interpolation, filtering and L times decimation, the sampling rate becomes And should be in D1f s The filtering completed at the sampling rate can actually be reduced by L times to reduce the filtering sampling rate to This is the core reason why the present invention can reduce FPGA resources. Assuming that the system in the FPGA is processed in p-phase parallel, the traditional method will consume pM filters, while the method of the present invention only requires At the same time, the interpolation-filtering-decimation process that originally required three steps can actually be completed in one step. The specific implementation method is: split the filter into D1 phase, delay the interpolated sequence by LT to obtain the D1 phase, and perform multi-phase filtering. The implementation block diagram is as follows Figure 3 shown.

[0081] Step 5, repeat step 4, perform second-level interpolation D2↑ and filtering to obtain the sequence y”(n);

[0082] Step 6: Up-convert the sequence y(n) to obtain the intermediate frequency complex signal y(m). f0 is the center frequency of the broadband intermediate frequency real signal s(t). At this point, a variable sampling sequence with a sampling clock of T2 is obtained, and the complete signal bandwidth is maintained.

[0083] A specific example:

[0084] Convert 1G sampling rate to 2.4G sampling rate. The parameters are as follows: center frequency f c =750M, bandwidth B = 400M, AD data width 16bit. Analog point frequency continuous wave frequency f0 = 760M, signal-to-noise ratio 20dB. LP filter uses Kaiser window function filter, and the corresponding filter order theoretical calculation formula is:

[0085]

[0086] Among them, N is the filter order, δ is the stop band attenuation, Δf is the transition band bandwidth, here we take 50M, f s is the sampling rate.

[0087] The two-stage filter is set up as Figure 4a 、 4b As shown in the figure, the first-order LP filter has a passband of 200M, a stopband of 250M, a stopband attenuation of 40dB, and a Kaiser window. The calculated theoretical order is 135. The second-order LP filter has a passband of 250M, a stopband of 300M, and a theoretical order of 96.

[0088] like Figure 5 The figure shows the RTL simulation results of the FPGA. The output results of each level in the example are given. The simulation results are imported into the CPU for step-by-step analysis, and the final results are compared with the results obtained by theoretical calculation. It is found that the results are consistent with the theoretical simulation.

[0089] The FPGA resource consumption corresponding to the signal processing in the example is shown in Table 1.

[0090] Table 1 shows the FPGA resource consumption corresponding to the signal processing in the example.

[0091]

[0092] As can be seen from Table 1, compared to the traditional arbitrary variable sampling rate architecture implementation, the present invention reduces the DSP resources occupied by 41%, which is very beneficial for engineering implementation. DSP resource consumption mainly comes from the two filter banks and DDC, where resource optimization is reflected in the first filter bank. The 1G sampling is first interpolated three times to become parallel data with a 10-phase 300MHz sampling clock. It is filtered according to a 135-order half-band filter. The traditional method requires ceil(135 / 2)×10=680 multipliers. Using the interpolation-filtering-decimation method to complete the process simultaneously, decimation is performed by 5 times before filtering. This can reduce the number of filters in this step to 136, proving the correctness and usefulness of the present invention.

[0093] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A method for optimizing variable sampling rate based on FPGA, characterized in that: The steps include: S101, a broadband intermediate frequency real signal s(t) is sampled by an analog-to-digital converter AD at time T1 and converted into an intermediate frequency real sequence s(n); S102, down-converting the intermediate frequency real sequence s(n) to obtain a baseband complex signal x(n); S103, decomposing the sampling rate conversion into M-level processing, where M≥1, first performing a first-level sampling rate conversion on the baseband complex signal x(n) to obtain a sequence y'(n); the first-level sampling rate conversion is completed in one step by D1-fold interpolation, filtering, and L-fold decimation; S104, performing sampling rate conversion processing on the remaining M-1 levels in the same manner as in step S103, and finally obtaining a sequence y" (n); S105 , up-convert the sequence y”(n) to obtain an intermediate frequency complex signal y(m), which is a sampled sequence with a sampling clock of T2.

2. The method for realizing optimized variable sampling rate based on FPGA according to claim 1, characterized in that: In step S102, the baseband complex signal x(n) is expressed as: Where f0 is the center frequency of the broadband intermediate frequency real signal s(t).

3. The method for realizing optimized variable sampling rate based on FPGA according to claim 1, characterized in that: The filtering in step S103 is as follows: splitting the filter into D1 phase, delaying the interpolated sequence by LT to also obtain D1 phase, and performing multi-phase filtering.

4. The method for realizing optimized variable sampling rate based on FPGA according to claim 1, characterized in that: In step S105, the intermediate frequency complex signal y(m) is expressed as: Where f0 is the center frequency of the broadband intermediate frequency real signal s(t).

5. A method for optimizing variable sampling rate based on FPGA, characterized in that: The steps include: S201, the broadband intermediate frequency real signal s(t) is sampled by the analog-to-digital converter AD according to time T1 and converted into an intermediate frequency real sequence s(n); S202, down-converting the intermediate frequency real sequence s(n) to obtain a baseband complex signal x(n); S203, designing a polyphase filter based on the bandwidth B of the baseband complex signal x(n) to filter out out-of-band clutter components in the baseband complex signal x(n); S204, decomposing the sampling rate conversion into M-level processing, where M≥1, firstly performs a first-level sampling rate conversion on the sequence obtained by passing the baseband complex signal x(n) through a polyphase filter to obtain a sequence y'(n); the first-level sampling rate conversion is performed in a single step by D1-fold interpolation, filtering, and L-fold decimation; S205, performing sampling rate conversion processing on the remaining M-1 levels in the same manner as in step S204, and finally obtaining a sequence y" (n); S206 , up-convert the sequence y”(n) to obtain an intermediate frequency complex signal y(m), that is, a sampled sequence with a sampling clock of T2.

6. The method for realizing optimized variable sampling rate based on FPGA according to claim 5, characterized in that: In step S202, the baseband complex signal x(n) is expressed as: Where f0 is the center frequency of the broadband intermediate frequency real signal s(t).

7. The method for realizing optimized variable sampling rate based on FPGA according to claim 5, characterized in that: In step S203, the frequency response of the polyphase filter is: Where ω represents the digital angular frequency.

8. The method for realizing optimized variable sampling rate based on FPGA according to claim 1, characterized in that: The filtering in step S204 is as follows: splitting the filter into D1 phase, delaying the interpolated sequence by LT to also obtain D1 phase, and performing multi-phase filtering.

9. The method for realizing optimized variable sampling rate based on FPGA according to claim 1, characterized in that: In step S206, the intermediate frequency complex signal y(m) is expressed as: Where f0 is the center frequency of the broadband intermediate frequency real signal s(t).

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