Test method, test device and test equipment

Abstract

The invention discloses a test method, a test device and test equipment, which are used for improving the efficiency of testing the equipment. The test method comprises the following steps: a test device obtains a first memory space of a to-be-tested device; a second memory space is determined, the second memory space comprises a first area and a second area, and the first area is a simulation memory space for the first memory space; and running a target process on the second area, wherein the target process is used for testing the first area.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a testing method, a testing device, and a testing equipment. Background Art

[0002] Embedded devices have a wide range of applications in fields such as industrial automation, automotive electronics, consumer electronics, medical equipment, and communications infrastructure. Embedded devices typically refer to computer systems that contain microprocessors (MPUs) or microcontrollers (MCUs) and are specifically designed to perform specific functions. Embedded device testing is a systematic verification process designed to ensure that the hardware, firmware, and software within an embedded system work together correctly and meet design specifications, performance standards, safety requirements, and reliability metrics.

[0003] During the testing process of embedded devices, current mainstream embedded devices are limited by their small memory space. Therefore, it is difficult for mainstream embedded devices to run test suites (such as automated testing frameworks, coverage testing tools, or address disinfection tools), resulting in insufficient testing results. Summary of the Invention

[0004] The present application provides a testing method, a testing apparatus and a testing device for improving the efficiency of testing a device.

[0005] In a first aspect, the present application provides a testing method. In an embodiment of the present application, the testing method is performed by a testing device, and the testing method includes:

[0006] Acquire a first memory space of the device to be tested; determine a second memory space, the second memory space including a first area and a second area, the first area being a simulated memory space for the first memory space; run a target process on the second area, the target process being used to test the first area.

[0007] In an embodiment of the present application, the first memory space of the device to be tested is simulated into the first area of ​​the second memory space of the test device through memory simulation technology, and then the target process is run in the second area of ​​the second memory space, so as to test the first area through the target process. Since the first area is a simulated memory space for the first memory space, the test behavior on the first area can be equivalent to the test behavior on the first memory space. In an embodiment of the present application, the test process of the target process does not need to rely on the actual storage of the first memory space, which reduces the demand for the memory space capacity of the device to be tested, so that the device to be tested with a smaller memory space capacity can still be tested through the test suite, thereby improving the efficiency and flexibility of the test. On the other hand, it can be seen from the above that the test device runs the target process in the second area, and the target process is used to test the first area. Therefore, the resource overhead of the target process when it is running is avoided from affecting the test results of the first area, thereby improving the accuracy of the test.

[0008] Based on the first aspect, in an optional embodiment, the device to be tested is a hardware entity configured with a storage unit, and the memory space corresponding to the storage unit is the first memory space exemplified in the embodiment of the present application. In practical applications, the device to be tested may be an embedded device, and the embedded device includes but is not limited to a microprocessor (Micro Processing Unit, MPU), a microcontroller (Microcontroller Unit, MCU) or a system-on-a-chip (SoC, System-on-a-Chip), which is not specifically limited here. Exemplary, the storage unit includes but is not limited to a random access memory (Random Access Memory, RAM), a read-only memory (Read-Only Memory, ROM) or a flash memory in the above-mentioned test device.

[0009] Based on the first aspect, in an optional implementation, the testing device configures metadata in the second memory space, and the metadata is used to monitor and record the usage of the first area. This enables timely recording of operations and behaviors in the first area, thereby assisting in analyzing test results in the first area and improving testing efficiency.

[0010] Based on the first aspect, in an optional implementation, the test device may configure metadata in the second area of ​​the second memory space, thereby preventing resource overhead occupied by the metadata from affecting the test results of the first area and improving the accuracy of the test.

[0011] Based on the first aspect, in one optional implementation, the test device can obtain risky access instructions for the first area based on metadata. Specifically, because the test device monitors and records the usage of the first area in real time through metadata, any risky access instructions targeting the first area will also be recorded in the metadata. Therefore, by querying the metadata, risky access instructions targeting the first area can be promptly detected, improving data security during the test process.

[0012] Based on the first aspect, in an optional implementation, if a risky access instruction is sensed, the test device can generate a risk warning for the risky access instruction, which is convenient for testers to discover and handle in time, thereby ensuring data security during the test process.

[0013] Based on the first aspect, in an optional implementation, the testing device directly intercepts the risky access instruction, thereby ensuring the data security of the first area in a timely manner.

[0014] Based on the first aspect, in an optional implementation, a test result of the target process for the first area is generated according to the usage of the first area recorded in the metadata, so that the test result is more comprehensive and the test efficiency is higher.

[0015] Based on the first aspect, in an optional implementation, the access permission configuration of the first region is the same as the access permission configuration of the first memory space, that is, the first region also simulates the access permission of the first memory space. This makes the test results for the first memory space more accurate and more in line with actual scenarios.

[0016] Based on the first aspect, in an optional implementation, a simulator may be used to perform memory simulation on the first memory space, thereby obtaining the first area in the second memory space.

[0017] Based on the first aspect, in an optional implementation, multiple storage units (including RAM and flash memory) of a device under test are tested. A first memory space of the device under test includes a memory space corresponding to the RAM and a memory space of the flash memory. The testing device can perform memory simulation on both the RAM and the flash memory of the device under test to obtain a first area in the second memory space, where the first area includes a simulated memory space for the RAM and a simulated memory space for the flash memory.

[0018] Based on the first aspect, in an optional implementation, metadata is only used to record the usage of the simulated memory space of the RAM in the first area, so that the test device does not need to record metadata for the entire first area, thereby reducing the resource overhead required for recording metadata.

[0019] In a second aspect, the present application provides a testing device, the testing device comprising:

[0020] An acquiring unit, configured to acquire a first memory space of the device to be tested;

[0021] a processing unit, configured to determine a second memory space, the second memory space including a first area and a second area, the first area being a simulated memory space for the first memory space;

[0022] The processing unit is further configured to run a target process on the second area, where the target process is used to test the first area.

[0023] Based on the second aspect, in an optional implementation, the second memory space includes metadata, and the metadata is used to record usage of the first area.

[0024] Based on the second aspect, in an optional implementation, the second area of ​​the second memory space includes metadata.

[0025] Based on the second aspect, in an optional implementation manner, the processing unit is further configured to:

[0026] A risk access instruction for the first area is obtained according to the metadata.

[0027] Based on the second aspect, in an optional implementation manner, the processing unit is further configured to:

[0028] Generate risk warnings for risky access instructions.

[0029] Based on the second aspect, in an optional implementation manner, the processing unit is further configured to:

[0030] Block risky access instructions.

[0031] Based on the second aspect, in an optional implementation manner, the processing unit is further configured to:

[0032] Generate a test result of the target process for the first region based on the metadata.

[0033] Based on the second aspect, in an optional implementation, the access permission configuration of the first area is the same as the access permission configuration of the first memory space.

[0034] Based on the second aspect, in an optional implementation, the first area is obtained by processing the first memory space through an emulator.

[0035] Based on the second aspect, in an optional implementation, the first memory space includes a memory space of a random access memory RAM and a memory space of a flash memory, and the first area includes an emulation memory space for the RAM and an emulation memory space for the flash memory.

[0036] Based on the second aspect, in an optional implementation, the metadata is used to record usage of the simulated memory space of the RAM in the first area.

[0037] The information interaction and execution process and other contents of the embodiment shown in this aspect are based on the same concept as the embodiment shown in the first aspect. Therefore, for the description of the beneficial effects shown in this aspect, please refer to the above-mentioned first aspect, and the details will not be repeated here.

[0038] In a third aspect, the present application provides a testing device, comprising: a processor, the processor being coupled to a memory, the memory being used to store instructions, and when the instructions are executed by the processor, the computing device implements the method of the above-mentioned first aspect, or any possible implementation of the first aspect.

[0039] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having instructions stored thereon, which, when executed, enables a computer to execute the method in the above-mentioned first aspect or any possible implementation of the first aspect.

[0040] In a fifth aspect, an embodiment of the present application provides a computer program product, which stores computer-readable instructions. When the computer-readable instructions are executed by a processor, the method in the first aspect or any possible implementation of the first aspect is implemented.

[0041] In a sixth aspect, an embodiment of the present application provides a chip, comprising: a processor, the processor being coupled to a memory, the memory being used to store instructions, and when the instructions are executed by the processor, the chip implements the method in the above-mentioned first aspect, or any possible implementation of the first aspect.

[0042] Among them, the technical effects brought about by any implementation method of the third to sixth aspects can refer to the technical effects brought about by the implementation method of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0044] Figure 1 A possible, non-limiting system architecture diagram of the testing method in the embodiments of the present application;

[0045] Figure 2Schematic diagram of the test method in the embodiment of the present application;

[0046] Figure 3 A schematic diagram of a scenario of a second memory space determined by a test device in an embodiment of the present application;

[0047] Figure 4 This is a schematic diagram of a scenario in which a test device runs a target process in an embodiment of the present application;

[0048] Figure 5 A schematic diagram of the structure of a testing device provided in an embodiment of the present application;

[0049] Figure 6 A schematic diagram of the logical structure of the test equipment provided in an embodiment of the present application. DETAILED DESCRIPTION

[0050] The embodiments of the present application provide a testing method, a testing apparatus, and a testing device for improving the efficiency of testing a device.

[0051] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application. The terms used in the implementation methods of the present application are only used to explain the specific embodiments of the present application and are not intended to limit the embodiments of the present application. It is known to those skilled in the art that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0052] In the embodiments of the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0053] The terms "first," "second," "third," "fourth," etc. (if any) in the specification and claims of the present application and in the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential sequence. It should be understood that the numbers used in this way are interchangeable where appropriate, so that the embodiments of the present application described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions, for example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or apparatus.

[0054] The following is an explanation of some nouns or terms used in the embodiments of the present application, which are also considered part of the content of the invention.

[0055] Emulators: During embedded development, emulators can create memory simulation models to emulate the memory system of target hardware (such as a microcontroller or processor). These models accurately reflect the behavior and characteristics of actual physical memory, including different types of memory cells such as RAM, ROM, and Flash, as well as their access speeds, size limitations, and address mapping.

[0056] Random Access Memory (RAM): RAM is also known as main memory or internal memory. RAM is an internal memory in computers and digital systems that is used to temporarily store programs, data, and intermediate results. The main feature of RAM is that it can be read and written at any time (except when refreshed), and the reading and writing speed is very fast. It is usually used as a temporary data storage medium for operating systems or other running programs. The characteristics of RAM include random access and volatility. Random access means that when data in the memory is read or written, the time required is independent of the location of the information, and information can be written or read from any specified address. Volatility means that once the power is cut off, the data stored in RAM will be lost.

[0057] Next, possible application scenarios involved in the embodiments of the present application are introduced.

[0058] Embedded devices have a wide range of applications in fields such as industrial automation, automotive electronics, consumer electronics, medical equipment, and communications infrastructure. Embedded devices typically refer to computer systems that contain microprocessors (MPUs) or microcontrollers (MCUs) and are specifically designed to perform specific functions. Embedded device testing is a systematic verification process designed to ensure that the hardware, firmware, and software within an embedded system work together correctly and meet design specifications, performance standards, safety requirements, and reliability metrics.

[0059] During the testing process of embedded devices, current mainstream embedded devices are limited by their small memory space. Therefore, it is difficult for mainstream embedded devices to run test suites (such as automated testing frameworks, coverage testing tools, or address disinfection tools), resulting in insufficient testing results.

[0060] Currently, to meet testing requirements, embedded devices can have their physical memory expanded to run test suites. Physical memory expansion of embedded devices refers to increasing the device's memory space by increasing memory capacity or optimizing memory management. This can improve the performance and reliability of embedded devices, enabling them to better cope with various testing scenarios and requirements. Specific implementation methods include adding memory chips, upgrading firmware, using external storage, or optimizing programs.

[0061] However, because embedded devices are often designed with strict size, power consumption, and cost constraints, their physical memory size is typically fixed and carefully selected based on the intended application scenario. Therefore, expanding the physical memory capacity of an embedded device requires redesigning the physical board, which is costly and inconsistent with actual production scenarios.

[0062] On the other hand, virtual memory expansion technology allows Flash memory to be used as embedded device memory, effectively extending the memory footprint to run test suites. Although Flash memory virtualization technology can expand the memory capacity of embedded devices, the slower read and write speeds of Flash memory significantly lag behind the read and write speeds of physical memory, thus degrading the performance of embedded devices.

[0063] In view of this, the embodiments of the present application provide a test method, a test apparatus and a test device for improving the efficiency of testing a device. For ease of understanding, first, a possible, non-restrictive system architecture of the test method in the embodiments of the present application is introduced. Figure 1 , Figure 1 This is a possible, non-limiting system architecture diagram of the test method in the embodiment of this application. Figure 1 As shown, the memory space in the device to be tested is the first memory space exemplified in this application, and the test device includes a second memory space, and the second memory space includes a first area and a second area. Among them, the first area is a simulated memory space for the first memory space. In other words, the first area in the second memory space is a memory simulation model for the first memory space, and the first area in the second memory space can accurately reflect the behavior and characteristics of the actual physical memory of the first memory space, including but not limited to the access speed, size limit, access permission or address mapping method of the first memory space. In the embodiment of the present application, by Figure 1 The test equipment shown performs the test method to Figure 1 The first memory space of the device to be tested is tested in the example.

[0064] Next, the test method in the embodiment of the present application is introduced with reference to the accompanying drawings. Figure 2 , Figure 2 The flowchart of the test method in the embodiment of the present application is shown in FIG. The test method in the embodiment of the present application is illustrated by taking the test device as the execution subject, but the present application does not limit the execution subject of the interactive illustration, nor does it limit the specific hardware form or software form of the test device. For example, Figure 2 The test device in the embodiment may be a chip, chip system, processor, server or computer device used to support the test device to implement the test method. Figure 2 As shown, the testing method in the embodiment of the present application includes but is not limited to steps 101 to 103.

[0065] 101. Obtain a first memory space of the device to be tested.

[0066] In an embodiment of the present application, a test method is executed by a test device to test the first memory space of the device to be tested. First, the test device first obtains the first memory space of the device to be tested in order to determine the object to be tested. Wherein, the device to be tested is a hardware entity configured with a storage unit, and the memory space corresponding to the storage unit is the first memory space exemplified in the embodiment of the present application. In practical applications, the device to be tested may be an embedded device, and the embedded device includes but is not limited to a microprocessor (Micro Processing Unit, MPU), a microcontroller (Microcontroller Unit, MCU) or a system-on-a-chip (SoC, System-on-a-Chip), which is not specifically limited here. Exemplarily, the storage unit includes but is not limited to a random access memory (Random Access Memory, RAM), a read-only memory (Read-Only Memory, ROM) or a flash memory in the above-mentioned test device.

[0067] 102. The testing device determines the second memory space.

[0068] The test device determines a second memory space, wherein the second memory space can be a partial memory space or a complete memory space in the storage unit of the test device. Specifically, the test device performs memory simulation processing based on the first memory space of the device to be tested, thereby obtaining a simulated memory space for the first memory space, and the physical address mapped by the simulated memory space in the storage unit is the first area of ​​the second memory space in the embodiment of the present application. Therefore, the simulated memory space (the first area in the second memory space) can accurately simulate the access speed, size limit and address mapping method corresponding to the first memory space.

[0069] In one possible implementation, the access permission configuration of the first region is the same as the access permission configuration of the first memory space, that is, the first region also simulates the access permission of the first memory space. This makes the test results for the first memory space more accurate and more in line with actual scenarios.

[0070] In a possible implementation, an emulator (such as QEMU (Quick EMUlator)) may be used to perform memory emulation on the first memory space, thereby obtaining the first area in the second memory space.

[0071] On the other hand, the test device determines another physical address in the storage unit as the second area in the second memory space. In the storage unit of the test device, the physical addresses between the first area and the second area can be continuous or discontinuous. In actual applications, the test device can dynamically update the size and physical address of the second area based on actual scenario requirements (such as the memory usage of the target process to be run).

[0072] In one possible implementation, multiple storage units (including RAM and flash memory) of a device under test are tested. A first memory space of the device under test includes memory space corresponding to the RAM and memory space of the flash memory. The testing device can then perform memory simulation on both the RAM and the flash memory of the device under test to obtain a first area in a second memory space, where the first area includes simulated memory space for the RAM and simulated memory space for the flash memory.

[0073] For example, see Figure 3 , Figure 3 This is a schematic diagram of the second memory space determined by the test device in the embodiment of the present application. Figure 3 In the illustrated scenario, the storage units of the device under test include memory-mapped I / O (MMIO), dynamic random access memory (DRAM), and flash memory. The test device performs memory simulation on the MMIO, DRAM, and flash memory in a first memory space to obtain a first region in a second memory space. Furthermore, the test device determines another physical address as the second region in the second memory space.

[0074] 103. Run a target process on the second area, where the target process is used to test the first area.

[0075] The test device runs a target process in the second area, and the target process is used to test the first area. Specifically, the test device first installs the test suite on the local disk. In the embodiment of the present application, after the test suite is installed, when the operating system of the test device loads and executes the test suite, the operating system creates the target process in the embodiment of the present application for the test suite and loads the target process's code, data, stack, and other components into the first area of ​​the second memory space. The target process runs in the second area to test the first area.

[0076] See also Figure 4 , Figure 4 Schematic diagram of the scenario in which the test device runs the target process in the embodiment of the present application. Figure 4As shown, the test device can run the target process in the second area of ​​the second memory space. For example, the target process includes but is not limited to Figure 4 The automated testing framework (Test Harness), coverage testing tool (Coverage Test) and address disinfection tool (Address Sanitizer) shown.

[0077] In an embodiment of the present application, the first memory space of the device to be tested is simulated into the first area of ​​the second memory space of the test device through memory simulation technology, and then the target process is run in the second area of ​​the second memory space, so as to test the first area through the target process. Since the first area is a simulated memory space for the first memory space, the test behavior on the first area can be equivalent to the test behavior on the first memory space. In an embodiment of the present application, the test process of the target process does not need to rely on the actual storage of the first memory space, which reduces the demand for the memory space capacity of the device to be tested, so that the device to be tested with a smaller memory space capacity can still be tested through the test suite, thereby improving the efficiency and flexibility of the test. On the other hand, since the target process is running in the second area when testing the first area, the resource overhead of the target process when running is avoided from affecting the test results of the first area, thereby improving the accuracy of the test.

[0078] 104. The test device records usage of the first area through metadata.

[0079] The test device configures metadata in the second memory space. The metadata is used to monitor and record the usage of the first area (including but not limited to memory allocation operations, memory deallocation operations, memory access operations, or storage operations performed on the first area). This enables timely recording of operations and behaviors in the first area to assist in analyzing the test results of the first area and improve test efficiency.

[0080] In a possible implementation, the test device may configure metadata in the second area of ​​the second memory space, thereby preventing resource overhead occupied by the metadata from affecting the test results of the first area and improving the accuracy of the test.

[0081] In one possible implementation, the test device monitors and records the usage of the first area in real time through metadata. Therefore, if there are risky access instructions to the first area, they will also be recorded by the metadata. Therefore, by querying the metadata, risky access instructions to the first area can be perceived in a timely manner, thereby improving data security during the test process. Furthermore, if a risky access instruction is perceived, the test device can generate a risk warning for the risky access instruction, which is convenient for testers to discover and handle in a timely manner. Optionally, the test device can also directly intercept the risky access instruction to ensure the data security of the first area in a timely manner.

[0082] In one possible implementation, the test device can perform memory simulation on both the RAM and the flash memory of the device to be tested to obtain a first area in the second memory space, where the first area includes a simulated memory space for the RAM and a simulated memory space for the flash memory. The metadata can be used only to record the usage of the simulated memory space for the RAM in the first area, or the metadata can be used only to record the usage of the simulated memory space for the flash memory in the first area, thereby reducing the resource overhead required to record the metadata.

[0083] 105. Generate test results of the target process for the first area.

[0084] Based on the usage of the first area recorded in the metadata, a test result of the target process for the first area is generated. Thus, the usage of the first area recorded in the metadata and the test result of the target process are combined to generate the test result for the first area, making the test result more comprehensive and the test efficiency higher.

[0085] Accordingly, the present application also provides a device for implementing the above solution. Figure 5 , Figure 5 A schematic diagram of the structure of the test device provided in the embodiment of the present application. Figure 5 As shown, the test device includes:

[0086] An acquiring unit 201 is configured to acquire a first memory space of a device to be tested;

[0087] The processing unit 202 is configured to determine a second memory space, where the second memory space includes a first area and a second area, and the first area is a simulated memory space for the first memory space;

[0088] The processing unit 202 is further configured to run a target process on the second area, where the target process is used to test the first area.

[0089] Based on the second aspect, in an optional implementation, the second memory space includes metadata, and the metadata is used to record usage of the first area.

[0090] Based on the second aspect, in an optional implementation, the second area of ​​the second memory space includes metadata.

[0091] Based on the second aspect, in an optional implementation, the processing unit 202 is further configured to:

[0092] A risk access instruction for the first area is obtained according to the metadata.

[0093] Based on the second aspect, in an optional implementation, the processing unit 202 is further configured to:

[0094] Generate risk warnings for risky access instructions.

[0095] Based on the second aspect, in an optional implementation, the processing unit 202 is further configured to:

[0096] Block risky access instructions.

[0097] Based on the second aspect, in an optional implementation, the processing unit 202 is further configured to:

[0098] Generate a test result of the target process for the first region based on the metadata.

[0099] Based on the second aspect, in an optional implementation, the access permission configuration of the first area is the same as the access permission configuration of the first memory space.

[0100] Based on the second aspect, in an optional implementation, the first area is obtained by processing the first memory space through an emulator.

[0101] Based on the second aspect, in an optional implementation, the first memory space includes a memory space of a random access memory RAM and a memory space of a flash memory, and the first area includes an emulation memory space for the RAM and an emulation memory space for the flash memory.

[0102] Based on the second aspect, in an optional implementation, the metadata is used to record usage of the simulated memory space of the RAM in the first area.

[0103] It should be noted that the information interaction and execution process between the modules / units in the test device are the same as those in this application. Figure 2 The corresponding method embodiments are based on the same concept. For specific contents, please refer to the description in the method embodiments shown above in this application, which will not be repeated here.

[0104] See also Figure 6 , Figure 6 A logical structure diagram of the test device 30 provided in the embodiment of the present application. The test device 30 may be deployed with Figure 5 The test device described in the corresponding embodiment is used to implement Figure 2 The test device 30 includes a memory 301 , a processor 302 , a communication interface 303 and a bus 304 . The memory 301 , the processor 302 and the communication interface 303 are connected to each other via the bus 304 .

[0105] The memory 301 may be a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 301 may store programs. When the program stored in the memory 301 is executed by the processor 302, the processor 302 and the communication interface 303 are used to perform steps 101-105 of the above-described test method embodiment.

[0106] The processor 302 can be a central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), a graphics processing unit (GPU), a digital signal processor (DSP), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component or any combination thereof, used to execute relevant programs to implement one or more steps 101-105 of the test method embodiment in this application. The steps of the data processing method disclosed in the embodiment of the present application can be executed by a compiler and an executor, wherein the compiler and executor can be executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium mature in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers, etc. The storage medium is located in the memory 301, and the processor 302 reads the information in the memory 301 and executes one or more steps 101-105 of the test method embodiment in this application in combination with its hardware.

[0107] The communication interface 303 uses a transceiver device such as, but not limited to, a transceiver to implement communication between the test device 30 and other devices or a communication network.

[0108] The bus 304 can realize the path for transmitting information between the various components of the test device 30 (for example, the memory 301, the processor 302 and the communication interface 303). The bus 304 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For convenience of representation, Figure 6 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0109] The present application also provides a computer program product including instructions. The computer program product may be a software or program product including instructions that can be run on a computing device or stored in any available medium. When the computer program product is run on at least one computing device, the at least one computing device executes the aforementioned Figure 2 The illustrated embodiment describes the method.

[0110] The embodiment of the present application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that can be stored by a computing device or a data storage device such as a data center that contains one or more available media. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid-state hard disk). The computer-readable storage medium includes instructions that instruct the computing device to execute the above application to execute the above application. Figure 2 The illustrated embodiment describes the method.

[0111] The communication device provided in the embodiment of the present application may be a chip, which includes: a processing unit and a communication unit. The processing unit may be, for example, a processor, and the communication unit may be, for example, an input / output interface, a pin, or a circuit. The processing unit may execute the computer-executable instructions stored in the storage unit to enable the chip to execute the above-mentioned Figure 2The method described in the embodiment shown. Optionally, the storage unit is a storage unit within the chip, such as a register, a cache, etc. The storage unit may also be a storage unit located outside the chip within the wireless access device, such as a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM), etc.

[0112] It should be noted that the device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed across multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, in the drawings of the device embodiments provided in the embodiments of the present application, the connection relationship between the modules indicates that there is a communication connection between them, which can be specifically implemented as one or more communication buses or signal lines.

[0113] Through the description of the above embodiments, it is clear to those skilled in the art that the embodiments of the present application can be implemented by means of software plus necessary general hardware, and of course can also be implemented by dedicated hardware including application-specific integrated circuits, dedicated CPUs, dedicated memories, dedicated components, etc. In general, all functions performed by computer programs can be easily implemented with corresponding hardware, and the specific hardware structures used to implement the same function can also be various, such as analog circuits, digital circuits, or application-specific circuits, etc. However, for the embodiments of the present application, software program implementation is a better implementation method in most cases. Based on such an understanding, the technical solutions of the embodiments of the present application are essentially or partly contributed to the prior art can be embodied in the form of a software product, which is stored in a readable storage medium, such as a computer's floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., including a number of instructions to enable a computer device (which can be a personal computer, training equipment, or network equipment, etc.) to execute the methods described in each embodiment of the present application.

[0114] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

[0115] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, a computer, a training device or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website, a computer, a training device or a data center. The computer-readable storage medium can be any available medium that a computer can store or a data storage device such as a training device, a data center, etc. that includes one or more available media integrations. The available medium can be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

Claims

1. A testing method, characterized in that: The method is applied to a test device, and the method comprises: Obtain the first memory space of the device to be tested; Determine a second memory space, where the second memory space includes a first area and a second area, and the first area is a simulated memory space for the first memory space; A target process is run in the second area, where the target process is used to test the first area.

2. The method according to claim 1, characterized in that The second memory space includes metadata, and the metadata is used to record usage of the first area.

3. The method according to claim 2, characterized in that The second area of ​​the second memory space includes the metadata.

4. The method according to claim 2 or 3, characterized in that The method further comprises: A risk access instruction for the first area is obtained according to the metadata.

5. The method according to claim 4, characterized in that The method further comprises: A risk prompt is generated for the risky access instruction.

6. The method according to claim 4 or 5, characterized in that The method further comprises: The risky access instruction is intercepted.

7. The method according to any one of claims 2 to 6, characterized in that The method further comprises: A test result of the target process for the first area is generated according to the metadata.

8. The method according to any one of claims 1 to 7, characterized in that The access permission configuration of the first area is the same as the access permission configuration of the first memory space.

9. The method according to any one of claims 1 to 8, characterized in that The first area is obtained by processing the first memory space through an emulator.

10. The method according to any one of claims 1 to 9, characterized in that The first memory space includes a memory space of a random access memory RAM and a memory space of a flash memory, and the first area includes a simulation memory space for the RAM and a simulation memory space for the flash memory.

11. The method according to claim 10, characterized in that The metadata is used to record usage of the emulated memory space of the RAM in the first area.

12. A testing device, characterized in that: The testing device comprises: An acquiring unit, configured to acquire a first memory space of the device to be tested; a processing unit, configured to determine a second memory space, where the second memory space includes a first area and a second area, where the first area is a simulated memory space for the first memory space; The processing unit is further configured to run a target process on the second area, where the target process is used to test the first area.

13. The testing device according to claim 12, characterized in that: The second memory space includes metadata, and the metadata is used to record usage of the first area.

14. The testing device according to claim 13, characterized in that: The second area of ​​the second memory space includes the metadata.

15. The testing device according to claim 13 or 14, characterized in that: The processing unit is further configured to: A risk access instruction for the first area is obtained according to the metadata.

16. The testing device according to claim 15, characterized in that The processing unit is further configured to: A risk prompt is generated for the risky access instruction.

17. The testing device according to claim 15 or 16, characterized in that: The processing unit is further configured to: The risky access instruction is intercepted.

18. The testing device according to any one of claims 13 to 17, characterized in that The processing unit is further configured to: A test result of the target process for the first area is generated according to the metadata.

19. The testing device according to any one of claims 12 to 18, characterized in that The access permission configuration of the first area is the same as the access permission configuration of the first memory space.

20. The testing device according to any one of claims 12 to 19, characterized in that The first area is obtained by processing the first memory space through an emulator.

21. The testing device according to any one of claims 12 to 20, characterized in that The first memory space includes a memory space of a random access memory RAM and a memory space of a flash memory, and the first area includes a simulation memory space for the RAM and a simulation memory space for the flash memory.

22. The testing device according to claim 21, characterized in that The metadata is used to record usage of the emulated memory space of the RAM in the first area.

23. A testing device, characterized in that: comprising a processor coupled to a memory, The memory is used to store instructions; The processor is configured to execute instructions in the memory, so that the testing device performs the method according to any one of claims 1 to 11.

24. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 11 is implemented.

25. A computer program product, characterized in that The computer program product stores computer-readable instructions, and when the computer-readable instructions are executed by a processor, the method according to any one of claims 1 to 11 is implemented.

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