Auxiliary bus main circuit, electronic equipment and control method of auxiliary bus main circuit

Abstract

The invention provides an auxiliary bus main circuit, an electronic device and a control method of the auxiliary bus main circuit. The auxiliary bus main circuit is connected or can be connected to a bus of a system in which a high-priority main circuit having a high-priority bus access right and a low-priority main circuit having a low-priority bus access right are connected to one bus. The low-priority main circuit has a bus access right having a priority lower than that of the high-priority main circuit, and the auxiliary bus main circuit is provided with a control circuit that controls the low-priority main circuit on the basis of the timing at which at least one of high-priority main signals, which are signals exchanged through the bus, is output from the high-priority main circuit. And outputting an access request signal for requesting the access right to the bus.

Description

Technical Field

[0001] The invention relates to an auxiliary bus main circuit, electronic equipment and a control method for the auxiliary bus main circuit. Background Art

[0002] Burst transfers are sometimes used when large amounts of data need to be transferred at high speed. In normal transfers, each time a piece of data is transferred, if both the address and data values ​​are specified, the data is transferred, and the transfer is complete. In contrast, in burst transfers, a starting address and a specified number of data values ​​are specified, and then the specified number of data are transferred starting from the starting address. In other words, burst transfers are pipelined, enabling high-speed transmission of data at consecutive addresses.

[0003] Furthermore, when there are multiple bus masters performing data transmission, it is necessary to give priority to granting data transmission permission to bus masters with strict time limits, for example. Therefore, there is a system that sets a priority for each bus master and gives priority to granting data transmission permission to bus masters with higher priorities. For example, Japanese Patent Application Laid-Open No. 2021-82103 discloses a data transmission system that dynamically changes priorities based on weight data corresponding to the period from the theoretical time when data transmission is completed to the time when the next transmission request is issued, thereby improving the transmission efficiency of the entire system. Summary of the Invention

[0004] Problems to be solved by the invention

[0005] The purpose of the data transmission system disclosed in Japanese Patent Application Laid-Open No. 2021-82103 is to dynamically change the priority of data transmission based on transmission requests issued by multiple master controllers, thereby improving the transmission efficiency of the entire system. However, in this system, even when a specific bus master controller (herein referred to as a high-priority master circuit) needs to complete multiple consecutive data transmissions in a short period of time in a discrete address space, transmission requests from other master controllers are sometimes inserted between the transmission requests (single transmission or burst transmission) continuously issued by the high-priority master circuit. Therefore, even if the priority of the high-priority master circuit is set to the highest, continuous transmission cannot be performed with the highest priority, and there is a problem of consuming time before all continuous transmissions issued by the high-priority master circuit are completed.

[0006] The present invention is completed in view of the above actual situation, and its advantage is to provide an auxiliary bus main circuit, electronic equipment and control method of the auxiliary bus main circuit that can complete the data transmission in a short time when a high priority main circuit performs multiple consecutive data transmissions.

[0007] Means for solving problems

[0008] In order to achieve the above-mentioned purpose, one mode of the auxiliary bus master circuit of the present invention is that the auxiliary bus master circuit is connected to or can be connected to the bus of a system, and the system is a system in which a high-priority main circuit and a low-priority main circuit are connected to one of the buses, the high-priority main circuit has a high-priority bus access right, and the low-priority main circuit has a bus access right with a priority lower than that of the high-priority main circuit, and the auxiliary bus master circuit has a control circuit, and the control circuit outputs an access request signal requesting access rights to the bus based on the timing of at least one signal among the high-priority main signals output from the high-priority main circuit and exchanged through the bus.

[0009] Effects of the Invention

[0010] According to the present invention, when a high-priority master circuit performs multiple consecutive data transmissions, the data transmission can be completed in a short time. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a diagram showing a configuration example of a system according to an embodiment.

[0012] Figure 2 It is a diagram showing a configuration example of an auxiliary bus master circuit according to an embodiment.

[0013] Figure 3 This is a diagram showing a structural example of a D flip-flop with a load function.

[0014] Figure 4 This diagram shows a configuration example of a D flip-flop with a load function corresponding to 2-bit input and output.

[0015] Figure 5 This is a diagram showing an example of a timing chart when performing a burst transfer for writing.

[0016] Figure 6 This is a diagram showing a configuration example of a system including three low-priority main circuits.

[0017] Figure 7A It means in Figure 6 The diagram shows an example of bus access when the auxiliary bus master circuit operates in the system shown. Figure 7B It means in Figure 6 The diagram shows an example of bus access when the auxiliary bus master circuit is not operating in the system shown.

[0018] Figure 8 This is a diagram showing an example of a timing chart when burst transfer for read is performed.

[0019] Figure 9This is a diagram showing an example of a timing chart when the operation of the auxiliary bus master circuit is stopped in the middle of a burst transfer for writing.

[0020] Figure 10 It means in Figure 6 The diagram shows an example of bus access in a system where the auxiliary bus master circuit is not operating and not all low-priority master circuits are performing data transmission.

[0021] Figure 11 This is a diagram showing an example of a portion of a code describing a control program for a control circuit according to an embodiment.

[0022] Figure 12 It is a diagram showing a configuration example of a sound source system according to an embodiment. DETAILED DESCRIPTION

[0023] The auxiliary bus master circuit and the like according to the embodiment will be described with reference to the accompanying drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals.

[0024] like Figure 1 As shown, an auxiliary bus master circuit 100 of the embodiment is connected to a bus 400 of a system 500. The system 500 is a system in which a high-priority master circuit 200 and a low-priority master circuit 300 are connected to a single bus 400. The high-priority master circuit 200 has a high-priority bus access right, and the low-priority master circuit 300 has a lower-priority bus access right than the high-priority master circuit 200. The low-priority master circuit 300 can be a single master controller or a plurality of master controllers.

[0025] The bus 400 of the system 500 is an Advanced High-Performance Bus (AHB)-Lite bus based on the Advanced Microcontroller Bus Architecture (AMBA) standard. The specific specifications of the bus 400 are described in the ARM specification documents published by ARM. The ARM specification documents can be downloaded from, for example, https: / / developer.arm.com / documentation / ihi0011 / a / and https: / / developer.arm.com / documentation / ihi0033 / a as of January 22, 2024.

[0026] like Figure 1As shown, system 500 includes a control unit 510 and a storage unit 520. Control unit 510 is composed of at least one processor, such as a CPU (Central Processing Unit) or a DSP (Digital Signal Processor). Control unit 510 operates system 500 by executing programs stored in storage unit 520. Storage unit 520 stores programs executed by control unit 510 and necessary data. Storage unit 520 may include, but is not limited to, RAM (Random Access Memory), ROM (Read-Only Memory), and flash memory.

[0027] Furthermore, in the system 500, data is transferred between the high-priority master circuit 200 or the low-priority master circuit 300 and the storage unit 520. In this case, if a conflict arises between the data transfers of the high-priority master circuit 200 and the low-priority master circuit 300, such as when the high-priority master circuit 200 and the low-priority master circuit 300 attempt to access the storage unit 520 simultaneously, the system 500 prioritizes bus access rights so that data transfers of the high-priority master circuit 200 are prioritized.

[0028] In this way, system 500 includes an arbiter to prioritize bus access for bus masters with higher priorities. The arbiter coordinates bus access rights for multiple bus masters connected to bus 400. Specifically, the arbiter receives signals (such as NONSEQ in the transfer type (HTRANS) signal, requesting access to bus 400, referred to herein as access request signals) output from auxiliary bus master circuit 100, high-priority master circuit 200, and low-priority master circuit 300, and determines which bus master is granted access to bus 400. Furthermore, bus 400 can be configured as a bus circuit including an arbiter, rather than simply as a bus.

[0029] For example, when there is only one bus master outputting an access request signal, the arbitrator grants the bus 400 access right to the bus master (that outputs the access request signal).

[0030] Furthermore, if there are multiple bus masters outputting access request signals, the arbitrator grants access rights to the bus 400 to the bus master having the highest priority among the multiple bus masters outputting access request signals. If there are multiple bus masters having the highest priority, the arbitrator sequentially grants access rights to the bus 400 to the multiple bus masters having the highest priority in a round-robin manner.

[0031] Conventionally, when a high-priority master circuit performs multiple burst transmissions, even if the priority is set so as to give priority to the data transmission of the high-priority master circuit (as described later), Figure 7B The auxiliary bus master circuit 100 of the present disclosure prevents the low-priority master circuit 300 from obtaining bus access rights in this case (as described later). Figure 7A (as shown in FIG. 5 ) A circuit is provided to prevent the insertion of a transmission by the low-priority master circuit 300 between the multiple burst transmissions. Therefore, in the system 500, a higher priority than that of the low-priority master circuit (e.g., the same priority as that of the high-priority master circuit 200) is set as the priority of the bus access right of the auxiliary bus master circuit 100.

[0032] like Figure 2 As shown, the auxiliary bus master circuit 100 internally includes a control circuit 110, multiple selectors (selectors 161, 162, 163, and 164), and multiple D flip-flops with a load function (1dD-FFs 171, 172, 173, 174, 175, 176, and 177). The multiple selectors 161, 162, 163, and 164 included in the auxiliary bus master circuit 100 are collectively referred to as selectors 160, and the multiple 1dD-FFs 171, 172, 173, 174, 175, 176, and 177 are collectively referred to as 1dD-FFs 170.

[0033] In addition, a D flip-flop with a load function is a logic circuit that loads (takes in) the input value of the D terminal and latches the input value when a signal (e.g., ld = 1 (HIGH)) is input to the load (ld) terminal. Figure 3 As shown, the D flip-flop with a load function can be composed of a selector 181 and a normal D flip-flop 182 . Figure 3 When a HIGH input is input to the load (ld) terminal of the D flip-flop with load function (ldD-FF180) shown, the input value of the D terminal is loaded (taken) into the internal D flip-flop 182 and latched (held).

[0034] return Figure 2The auxiliary bus master circuit 100 includes: an action mode terminal 121, which serves as an input terminal and is input with a signal indicating the action mode of the switching control circuit 110; a bus clock terminal 122, which is input with a bus clock (HCLK) signal; a bus reset terminal 123, which is input with a bus reset (HRESETn) signal; a high priority master signal acquisition terminal 130, which is input with signals exchanged by the high priority master circuit 200 through the bus 400 (such as HREADY, HTRANS, HWRITE, etc., which are recorded in the above-mentioned AMBA specification, and are also referred to herein as high priority master signals); a bus input terminal 140, which is input with a signal from the bus 400; and a bus output terminal 150, which outputs a signal to the bus 400.

[0035] The schematic diagram of bus 400 is as follows Figure 1As shown, it includes: (1) a first bus line group 400A, which exchanges the following signals, the signals being: control signals, including a high priority master transfer type (HTRANS) signal, a high priority master transfer direction (HWRITE) signal, a high priority master slave select (HSEL) signal, and a high priority master transfer size (HSIZE) signal output from the high priority master circuit 200; a high priority master ready (HREADY) signal input to the high priority master circuit 200; a high priority master address bus (HADDR) signal output from the high priority master circuit 200; Output; High priority master write data bus (HWDATA) signal, output from high priority master circuit 200; High priority read data bus (HRDATA) signal, input to high priority master circuit 200, (2) Second bus line group 400B, the second bus line group 400B exchanges the following signals, the signals are: control signals, including auxiliary bus master transfer type (HTRANS2) signal, auxiliary bus master transfer direction (HWRITE2) signal and auxiliary bus master slave select (HSEL2) signal output from auxiliary bus master circuit 100, auxiliary bus master transfer size (HSIZE2) signal ) signal and auxiliary bus master transfer mode (HBURST2); auxiliary bus master ready completion (HREADY2) signal, input to the auxiliary bus master circuit 100; auxiliary bus master address bus (HADDR2) signal, output from the auxiliary bus master circuit 100; auxiliary bus master write data bus (HWDATA2) signal, output from the auxiliary bus master circuit 100, (3) the third bus line group 400C, the third bus line group 400C exchanges the following signals, the signals being: control signals, including the transfer type (HTRANS3) signal output from the low priority master circuit 300, the low priority Master transfer direction (HWRITE3) signal, low priority master-slave selection (HSEL3) signal, low priority master transfer size (HSIZE3) signal and transfer mode (HBURST3) signal; low priority master ready completion (HREADY3) signal, input to the low priority master circuit 300; low priority master address bus (HADDR3) signal, output from the low priority master circuit 300; low priority master write data bus (HWDATA3) signal, output from the low priority master circuit 300; low priority read data bus (HRDATA3) signal, input to the low priority master circuit 300.

[0036] Here, the first bus line group 400A is connected to the auxiliary bus master circuit 100 so that the control signal, high priority master address bus (HADDR) signal and high priority master write data bus (HWDATA) signal output from the high priority master circuit 200 and the high priority master ready completion (HREADY) signal input to the high priority master circuit 200 are input to the auxiliary bus master circuit 100.

[0037] In addition, Figure 2 In the ARM specification, the bus clock signal is input to the clock terminals of all ldD-FFs 170 and the clock terminals of all trigger clocks in the auxiliary bus master circuit 100 (not shown), including the trigger clock. The auxiliary bus master circuit 100 is reset by the bus reset signal. In addition, the signal (NONSEQUENTIAL) described as the transfer type in the ARM specification is Figure 2 For the convenience of space in the drawings, it is described as "NSQ". NONSEQ means the first or single transmission of a burst transmission.

[0038] In addition, as control input signals, the control circuit 110 accepts an action mode signal, a high priority master ready completion (HREADY) signal, a high priority master transfer type (HTRANS) signal, a high priority master address bus (HADDR) signal, a high priority master slave select (HSEL) signal, a high priority master transfer direction (HWRITE) signal, an auxiliary bus master ready completion (HREADY2) signal, and an auxiliary bus master transfer type (HTRANS2) signal.

[0039] Furthermore, the control circuit 110 outputs a 0th selector signal (sel0), a 1st selector signal (sel1), a 0th load signal (ld0), a 1st load signal (ld1), a 2nd load signal (ld2), and a 3rd load signal (ld3) as control output signals to control the selector 160 and the 1dD-FF 170 included in the auxiliary bus master circuit 100. Based on these control output signals, the control circuit 110 controls the timing at which each 1dD-FF 170 latches a signal such as a high-priority master signal and the timing at which the latched signal is output from the bus output terminal 150.

[0040] In addition, these control input signals and control output signals can be either 1-bit or multi-bit signals depending on the type of signal. For example, the high-priority master transfer type (HTRANS) signal is a 2-bit signal, and the high-priority master address bus (HADDR) signal, the high-priority master write data bus (HWDATA) signal, and the high-priority read data bus (HRDATA) signal are each 32-bit signals. Figure 2In the described ldD-FF170 (to avoid complication), the difference in the number of input bits is not distinguished, but in fact, the Q terminal and D terminal of the ldD-FF170 that inputs a multi-bit signal correspond to multiple bits. For example, the ldD-FF171 that inputs and outputs a 2-bit signal is as follows: Figure 4 As shown, the 2-bit FF 170 is configured using two selectors 181 and two normal D flip-flops 182. The 1dD-FF 170 corresponding to a larger number of bits is also configured using multiple selectors 181 and normal D flip-flops 182.

[0041] Furthermore, the auxiliary bus master circuit 100 always outputs SINGLE (single transfer mode) as the auxiliary bus master transfer mode (HBURST2) signal. Therefore, regardless of the transfer mode (HBURST) signal output by the high priority master circuit 200, the auxiliary bus master circuit 100 always performs single transfer.

[0042] Specifically, the auxiliary bus master circuit 100 acquires the signal exchanged by the high-priority master circuit 200 via the bus 400 and latches it via the ldD-FF 170. The control circuit 110 then controls the timing of latching the signal by the ldD-FF 170 and outputting the signal to the bus 400. Consequently, when the high-priority master circuit 200 begins data transmission, the auxiliary bus master circuit 100 immediately attempts to perform a single transmission of dummy data. This prevents the low-priority master circuit 300 from gaining access to the bus 400 while the high-priority master circuit 200 is continuously performing data transmission.

[0043] The operation of the control circuit 110 will be described in more detail. Among the signals output by the control circuit 110, the 0th selector signal (sel0) and the 0th load signal (ld0) are used to retrieve (load) data for outputting the auxiliary bus master transfer type (HTRANS2), auxiliary bus master transfer direction (HWRITE2), and auxiliary bus master slave select (HSEL2) signals of the auxiliary bus master circuit 100 into the ldD-FFs 171, 172, and 173 based on the high-priority master ready completion (HREADY) signal and the high-priority master transfer type (HTRANS) signal of the high-priority master circuit 200. In addition, the first load (ld1) signal is used to use the high priority master address bus (HADDR) signal obtained from the high priority master circuit 200 as the auxiliary bus master address bus (HADDR2) signal of the auxiliary bus master circuit 100, and the high priority transfer size (HSIZE) signal obtained from the high priority master circuit 200 as the auxiliary bus master transfer size (HSIZE2) signal of the auxiliary bus master circuit 100, which are respectively taken into ldD-FF174 and ldD-FF175 and output respectively.

[0044] In addition, the second load (ld2) signal, the third load (ld3) signal and the first selector (sel1) signal among the signals output by the control circuit 110 are used to adjust the timing of the output of the auxiliary bus master write data bus (HWDATA2) signal as the auxiliary bus master circuit 100 by taking the high priority master write data bus (HWDATA) signal obtained from the high priority master circuit 200 into ldD-FF176 or ldD-FF177.

[0045] The auxiliary bus master circuit 100 begins data transmission after the high-priority master circuit 200 completes write data. However, at this point, the auxiliary bus master circuit 100 writes the data written by the high-priority master circuit 200 (as dummy data) to the address just written by the high-priority master circuit 200. This allows the auxiliary bus master circuit 100 to write the already written data to the same address, thus enabling bus access without affecting devices connected to the bus 400 (such as the storage unit 520). To perform this data transfer, the auxiliary bus master write data bus (HWDATA2) signal of the auxiliary bus master circuit 100 must output the signal before the update, even if the high-priority master write data bus (HWDATA) signal of the high-priority master circuit 200 is updated.

[0046] Therefore, the high-priority master write data bus (HWDATA) signal of the high-priority master circuit 200 is alternately loaded to ldD-FF 176 and ldD-FF 177, and the signal before the update is output as the auxiliary bus master write data bus (HWDATA2) signal. To control the output of signals in this manner, the control circuit 110 periodically inverts the value of the first selector (sel1) signal and determines which of the second load (ld2) and third load (ld3) signals to set high based on the value of the first selector (sel1) signal.

[0047] The operation mode signal is a signal for switching the auxiliary bus master circuit 100 on and off, and includes a total of 36 bits of information: threshold address information (32 bits), threshold address condition information (2 bits), and transmission direction condition information (2 bits).

[0048] The threshold address is set in the threshold address information. Then, depending on whether the first bit of the threshold address condition information is 1 (HIGH) or 0 (LOW), the auxiliary bus master circuit 100 switches whether to operate when the address indicated by the address bus signal is greater than or equal to the threshold address. Depending on whether the second bit of the threshold address condition information is HIGH or LOW, the auxiliary bus master circuit 100 switches whether to operate when the address indicated by the address bus signal is less than the threshold address. This allows, for example, the auxiliary bus master circuit 100 to operate only when a device located at a specific address is performing data transmission.

[0049] Furthermore, the auxiliary bus master circuit 100 switches whether to operate during reading (the high-priority master transmission direction (HWRITE) signal is LOW) depending on whether the first bit of the transmission direction condition information is HIGH or LOW, and switches whether to operate during writing (the high-priority master transmission direction (HWRITE) signal is HIGH) depending on whether the second bit of the transmission direction condition information is HIGH or LOW. This allows, for example, the auxiliary bus master circuit 100 to operate only during read data transmission.

[0050] The auxiliary bus master circuit 100 begins its control program when the 0th selector signal (sel0) of the control circuit 110 goes HIGH. However, if the operation of the auxiliary bus master circuit 100 is stopped based on the conditions set by the operation mode signal, the 0th selector signal (sel0) remains fixed at LOW, and the control program is not generated. As a result, the output terminals of the auxiliary bus master circuit 100 remain in a stopped state, and the operation of the auxiliary bus master circuit 100 ceases.

[0051] When in operation, the auxiliary bus master circuit 100 receives and latches (holds) a signal from the high-priority master signal acquisition terminal 130. Immediately after the high-priority master circuit 200 completes bus access, the auxiliary bus master circuit 100 outputs a signal from the bus output terminal 150 to the bus 400, allowing the auxiliary bus master circuit 100 to obtain bus access rights. This prevents the bus access rights from being acquired by the lower-priority master circuits, allowing the high-priority master circuit 200 (and the auxiliary bus master circuit 100) to occupy the bus.

[0052] If the outline of this structure is explained using the case of write data transmission, when the high-priority master transfer type (HTRANS) signal output from the high-priority master circuit 200 is NONSEQ and the high-priority master ready completion (HREADY) signal is HIGH, the auxiliary bus master circuit 100 takes in and latches the high-priority master address bus (HADDR) signal at the timing of the clock switching in the bus clock (HCLK) signal (for example, switching from LOW to HIGH). After latching, at the timing of the clock switching in the bus clock (HCLK) signal (the same switching as the switching when latching the high-priority master address bus (HADDR) signal, for example, switching from LOW to HIGH), the auxiliary bus master transfer type (HTRANS2) signal output to the bus 400 is set to NONSEQ, and the maintained high-priority master address bus (HADDR) signal is output as the auxiliary bus master address bus (HADDR2) signal. The high-priority master write data bus (HWDATA) signal output from the high-priority master circuit 200 is then received and latched. The latched high-priority master write data bus (HWDATA) signal is then output as the auxiliary-bus master write data bus (HWDATA2) signal at the timing of the next bus clock (HCLK) signal transition (e.g., from LOW to HIGH) after the auxiliary-bus master transfer type (HTRANS2) signal is NONSEQ and the auxiliary-bus master ready (HREADY2) signal transitions from LOW to HIGH during the data phase of the auxiliary-bus master circuit 100. The transition at the next bus clock (HCLK) signal transition refers to a transition after one cycle of the bus clock (HCLK) signal, and refers to a transition from LOW to HIGH or from HIGH to LOW.

[0053] As described above, the arbiter in system 500 grants access to bus 400 to the bus master that outputs the access request signal. Therefore, when the high-priority master circuit 200 outputs the access request signal, the auxiliary bus master circuit 100 receives this signal and outputs the access request signal immediately after the high-priority master circuit 200. This allows the auxiliary bus master circuit 100 to gain access to bus 400 after the high-priority master circuit 200 completes data transmission.

[0054] In this embodiment, each bus master requests access to bus 400 when outputting NONSEQ as the transfer type (HTRANS) signal. Therefore, auxiliary bus master circuit 100 outputting NONSEQ as the auxiliary bus master transfer type (HTRANS2) signal corresponds to outputting an access request signal. Furthermore, high-priority master circuit 200 outputting NONSEQ as the high-priority master transfer type (HTRANS) signal corresponds to outputting a signal requesting access to bus 400 from high-priority master circuit 200. To distinguish this signal from the access request signal output by auxiliary bus master circuit 100, this signal is also referred to as a high-priority master request signal.

[0055] Next, refer to Figure 5 The operation of the control circuit 110 when the high-priority master circuit 200 writes data to the storage unit 520 by continuous burst transfer will be described.

[0056] As a premise, a high priority bus access right is set in the high priority master circuit 200. Therefore, if at the initial time point (one of the moments when the bus clock (HCLK) signal switches from LOW to HIGH), Figure 5 At timing t0 (in the figure), the high-priority master circuit 200 attempts to initiate a write burst transfer and obtains bus access. The burst transfer starts with address A0, followed by A1, A2, and so on. The data at address A0 is D0, and the data at address Ax is also Dx. The high-priority transfer size (HSIZE) signal is set to S0 (for example, half-word (16 bits)), S1, and so on) for every eight addresses Ax, and the transfer mode (HBURST) is INCR8 (8-bit incremental burst transfer mode).

[0057] Then, at timing t0, the high-priority master circuit 200 sets the high-priority master transfer direction (HWRITE) signal to HIGH (indicating a write transfer), sets the high-priority master transfer type (HTRANS) signal to NONSEQ, and outputs A0 to the high-priority master address bus (HADDR) signal, in order to initiate a write burst transfer starting at address A0. At this time, the high-priority master-slave select (HSEL) signal is also output at timing t0 based on the contents of the high-priority master address bus (HADDR) signal (because the HSEL signal is a combination decoder of the address bus).

[0058] Then, at timing t1, which is the switching timing of the next clock after timing t0 in the bus clock (HCLK) signal, the high priority master circuit 200 obtains the bus access right, and the high priority master ready (HREADY) signal from the bus 400 becomes HIGH.

[0059] The control circuit 110 is as follows Figure 5 As shown by the dotted part and the thick dotted line of the timing t1, when the high priority master ready completion (HREADY) signal from the bus 400 becomes HIGH, the high priority master-slave selection (HSEL) signal and the high priority master transmission direction (HWRITE) signal are HIGH and the high priority master transmission type (HTRANS) signal is NONSEQ, so that the 0th selector (sel0) signal, the 0th load (ld0) signal and the 1st load (ld1) signal are HIGH during 1 clock (1 cycle of the bus clock (HCLK) signal).

[0060] As a result, since the first load (ld1) signal goes HIGH, A0, the high-priority master address bus (HADDR) signal of high-priority master circuit 200, is loaded and latched into ldD-FF 174, and S0, the high-priority transfer size (HSIZE) signal of high-priority master circuit 200, is loaded and latched into ldD-FF 175. Then, at timing t2, the switching timing one clock after timing t1, as indicated by the dashed line extending from the portion of address A0 enclosed by the dotted line at timing t1, A0 is latched and output from ldD-FF 174 as the auxiliary bus master address bus (HADDR2) signal of auxiliary bus master circuit 100. Simultaneously, at timing t2, S0, the auxiliary bus master transfer size (HSIZE2) signal of auxiliary bus master circuit 100, is latched and output from ldD-FF 175.

[0061] Furthermore, at timing t1, the 0th selector signal (sel0) and the 0th load signal (ld0) become HIGH, so NONSEQ is loaded and latched into ldD-FF 171. At timing t2, the switching timing of the next clock after timing t1, NONSEQ is latched and output as the auxiliary bus master transfer type (HTRANS2) signal of auxiliary bus master circuit 100. Similarly, the high priority master transfer direction (HWRITE) signal and the high priority master slave select (HSEL) signal of high priority master circuit 200 are also loaded and latched into ldD-FF 172 and ldD-FF 173 at timing t1. At timing t2, which follows timing t1, they are latched and output as the auxiliary bus master transfer direction (HWRITE2) signal and the auxiliary bus master slave select (HSEL2) signal of auxiliary bus master circuit 100.

[0062] Thus, by outputting the auxiliary bus master transfer type (HTRANS2) signal of NONSEQ from the auxiliary bus master circuit 100 to the bus 400, the auxiliary bus master circuit 100 immediately requests access to the bus 400 after the high-priority master circuit 200 initiates a burst transfer (at timing t2, the clock switching timing immediately following timing t1). Similar to the high-priority master circuit 200, the auxiliary bus master circuit 100 sets a higher priority for access to the bus 400 than the other low-priority masters 300. Therefore, even if a low-priority master circuit 300 requests access to the bus 400, the arbitrator prioritizes the next request for access to the bus 400 from the high-priority master circuit 200 while the burst transfer is in progress.

[0063] Moreover, the first selector (sel1) signal periodically inverts its value and becomes HIGH at timing t1, so the control circuit 110 responds to the first load (ld1) signal and the first selector (sel1) signal at timing t1, and makes the second load (ld2) signal HIGH at timing t2, which is the switching timing of the next clock of timing t1.

[0064] Then, the high priority master write data bus (HWDATA) signal D0 of the high priority master circuit 200 is loaded and latched into the ldD-FF 176. However, at this point in time, the first selector (sel1) signal remains HIGH. Therefore, before the timing t4 when the first selector (sel1) signal becomes LOW, the output from the ldD-FF 177 (the previous data bus signal, Figure 5 ” in the figure) is outputted as the auxiliary bus master write data bus (HWDATA2) signal of the auxiliary bus master circuit 100 as it is.

[0065] Then, at the timing (timing t3) when the auxiliary bus master ready (HREADY2) signal of the auxiliary bus master circuit 100, transmitted from the bus 400, switches from LOW to HIGH, in response to the auxiliary bus master transfer type (HTRANS2) signal becoming NONSEQ, the control circuit 110 sets the 0th load (ld0) signal HIGH for one clock (one cycle of the bus clock (HCLK) signal). At this time, since the 0th selector (sel0) signal is LOW, selectors 161, 162, and 163 load IDLE and latch it into ldD-FF 171, and load LOW and latch it into ldD-FF 172 and ldD-FF 173, respectively. These latched signals are then output at the clock switching timing. That is, at the next clock switch after timing t3, that is, timing t4, IDLE is output as the auxiliary bus master transmission type (HTRANS2) signal of the auxiliary bus master circuit 100, and LOW is output as the auxiliary bus master transmission direction (HWRITE2) signal and the auxiliary bus master-slave selection (HSEL2) signal.

[0066] Then, at timing t4, the first selector (sel1) signal goes LOW, and thus D0 latched in ldD-FF 176 is output as the auxiliary bus master write data bus (HWDATA2) signal of auxiliary bus master circuit 100. In other words, auxiliary bus master circuit 100 writes D0, which becomes dummy data, to address A0 in a single transfer.

[0067] As described above, the auxiliary bus master circuit 100 always outputs SINGLE (single transfer mode) as the auxiliary bus master transfer mode (HBURST2) signal. Furthermore, at timing t4, the auxiliary bus master circuit 100 switches the auxiliary bus master transfer type (HTRANS2) signal to IDLE, indicating that no data is being transferred from the NONSEQ burst. Therefore, when the auxiliary bus master circuit 100, having gained access to the bus 400, outputs a D0 single transfer to the auxiliary bus master write data bus (HWDATA2) signal, access to the bus 400 is immediately transferred to another bus master. At timing t2, the high priority master circuit 200 switches the high priority master transfer type (HTRANS) signal from NONSEQ, which indicates the initial burst transfer, to SEQ, which indicates the remaining part of the burst transfer, and outputs the high priority master address bus (HADDR) signal in the order of addresses A1, A2, and A3. After outputting the last address A7 as one of multiple address blocks to the bus 400, the high priority master transfer type (HTRANS) signal is temporarily switched from SEQ to IDLE, which indicates that there is no address for burst transfer.

[0068] Then, in order to initiate a write burst transfer from the next address A8 at timing t5 after the burst transfer of data D7 corresponding to address A7 is completed, the high-priority master circuit 200 switches the high-priority master transfer direction (HWRITE) signal, which was temporarily switched LOW, to HIGH (indicating a write transfer), switches the high-priority master transfer type (HTRANS) signal from IDLE to NONSEQ, and outputs A8 to the high-priority master address bus (HADDR). Subsequently, the auxiliary bus master circuit 100 outputs the same signals at timings t5, t6, t7, t8, and t9, corresponding to the aforementioned timings t0, t1, t2, t3, and t4, respectively. Furthermore, after timing t5, the high-priority transfer size (HSIZE) switches from S0 to S1, but the sizes may remain the same (S0 = S1).

[0069] Thus, the auxiliary bus master circuit 100 outputs the auxiliary bus master transfer type (HTRANS2) signal of NONSEQ to the bus 400 as an access request signal at the same timing (timing t2 of the same clock) as the timing (timing t2) at which the auxiliary bus master circuit 100 acquires the high priority master transfer type (HTRANS) signal of NONSEQ from the high priority master circuit 200 as a high priority master request signal. Furthermore, after acquiring the high priority master request signal, the auxiliary bus master circuit 100 acquires and latches the high priority master address bus (HADDR) signal of the high priority master circuit 200 (a signal indicating the address value accessed by the high priority master circuit 200), i.e., the high priority master address signal. At the same timing (timing t2 of the same clock) as the timing (timing t2) at which the high priority master address signal was acquired, the auxiliary bus master circuit 100 outputs the acquired high priority master address signal as the auxiliary bus master address bus (HADDR2) signal of the auxiliary bus master circuit 100 (a signal indicating the address value accessed by the auxiliary bus master circuit 100), i.e., the address signal, to the bus 400.

[0070] Then, at timing t3 (a predetermined clock after the timing (timing t2) at which the high-priority master address signal was acquired (e.g., one clock cycle later)), the high-priority master write data bus (HWDATA) signal (a signal indicating the data value written by the high-priority master circuit 200), i.e., the high-priority master data signal, is acquired and latched. A predetermined clock after timing t3, when the auxiliary-bus master ready (HREADY2) signal from bus 400 goes high (e.g., one clock cycle later) is output to bus 400 as the auxiliary-bus master write data bus (HWDATA2) signal (a signal indicating the data value written by the auxiliary-bus master circuit). When the high-priority master circuit 200 transmits data by outputting these signals, the auxiliary-bus master circuit 100 transmits dummy data to the same address after the predetermined clock cycle. This allows the bus 400 to be occupied, preventing the low-priority master circuit 300 from interrupting access to the bus 400.

[0071] Reference Figure 7A Description Figure 6 An example of bus access when the auxiliary bus master circuit 100 functions in the system 501 shown in FIG. Figure 6 As shown, the system 501 is constructed to have a high-priority master circuit 200 and an auxiliary bus master circuit 100 with high priorities, and three bus master controllers with low priorities (low-priority master circuit A301, low-priority master circuit B302 and low-priority master circuit C303. The three are collectively referred to as the "low-priority master circuit group" below). When a bus access conflict occurs among multiple bus master controllers with the same priority, the bus access right is obtained in a round-robin manner among the multiple bus master controllers.

[0072] In this example, the high-priority master circuit 200 needs to perform four consecutive burst transfers, and the low-priority master circuits also each hold a large amount of data to be transferred. For example, if the high-priority master circuit 200 processes four channels of stream data in a time-sharing manner, it typically performs four consecutive burst transfers.

[0073] In system 501 , the bus masters with high priority are high priority master circuit 200 and auxiliary bus master circuit 100 . However, auxiliary bus master circuit 100 does not hold data to be transmitted. Therefore, at the initial time point, high priority master circuit 200 starts the first burst transmission.

[0074] Then, if Figure 5 As shown, the auxiliary bus master circuit 100 performs a single transmission of dummy data based on the output signal of the high priority master circuit 200. Figure 7AAs shown, the auxiliary bus master 100 is slightly delayed relative to the low-priority master group and enters a waiting state for transmission. However, since the auxiliary bus master 100 has a higher priority than the low-priority master group, it obtains bus access after the high-priority master 200 completes the burst transmission and performs a single transmission.

[0075] Furthermore, while the auxiliary bus master circuit 100 is performing a single transfer, the high-priority master circuit 200 enters a waiting state for the next burst transfer. Furthermore, since the high-priority master circuit 200 has a higher priority than the low-priority master circuits, it obtains bus access after the auxiliary bus master circuit 100 completes a single transfer and performs a burst transfer.

[0076] Then, when all the high-priority master circuits 200 have completed the continuous burst transmission, the low-priority master circuit group starts transmission in turn in a round-robin manner.

[0077] On the other hand, in the system 501, when the auxiliary bus master circuit 100 is not activated, as in the conventional art, Figure 7B As shown, after the high priority master circuit 200 completes the burst transfer, one of the bus masters included in the low priority master circuit group will obtain the bus access right. Therefore, compared with the case where the auxiliary bus master circuit 100 is activated ( Figure 7A ), the time it takes for the high-priority master circuit 200 to complete consecutive burst transfers is longer. Therefore, it can be seen that the auxiliary bus master circuit 100 operates to complete multiple consecutive data transfers by the high-priority master circuit 200 in a shorter time.

[0078] in addition, Figure 5 1 and 2 , the operation of the auxiliary bus master circuit 100 during continuous write burst transfers has been described. However, the auxiliary bus master circuit 100 also effectively functions during continuous read burst transfers or continuous single transfers.

[0079] For example, refer to Figure 8 The operation of the control circuit 110 when the high-priority master circuit 200 reads data from the storage unit 520 by continuous burst transfer will be described.

[0080] and Figure 5 Similarly, the high-priority master circuit 200 is set with a high-priority bus access right. Therefore, if at the initial time point ( Figure 8At timing t0 (in the figure), the high-priority master circuit 200 attempts to initiate a read burst transfer and obtains bus access. The address that initiates the burst transfer is A0, followed by A1, A2, and so on. The data at address A0 is D0, and the data at address Ax is Dx. The high-priority transfer size (HSIZE) is set to S0 (for example, a halfword (16 bits)), S1, and so on) for every eight addresses Ax, and the transfer mode (HBURST) is INCR8 (8-bit incremental burst transfer mode).

[0081] Then, at timing t0, the high-priority master circuit 200 sets the high-priority master transfer direction (HWRITE) signal to LOW (indicating a read transfer), sets the high-priority master transfer type (HTRANS) signal to NONSEQ, and outputs A0 to the high-priority master address bus (HADDR) signal to start a burst transfer from address A0. At this time, the high-priority master-slave select (HSEL) signal is also output at timing t0 based on the contents of the high-priority master address bus (HADDR) signal (because the HSEL signal is a combination decoder of the address bus).

[0082] Then, at timing t1, which is the switching timing of the next clock after timing t0 in the bus clock (HCLK) signal, the high priority master circuit 200 obtains the bus access right, and the high priority master ready (HREADY) signal from the bus 400 becomes HIGH.

[0083] The control circuit 110 is as follows Figure 8 As shown by the dotted part surrounded by the timing t1 and the thick dotted line, when the high priority master ready completion (HREADY) signal from the bus 400 becomes HIGH, in response to the high priority master-slave selection (HSEL) signal being HIGH, the high priority master transmission direction (HWRITE) signal being LOW, and the high priority master transmission type (HTRANS) signal being NONSEQ, the 0th selector (sel0) signal, the 0th load (ld0) signal, and the 1st load (ld1) signal are each HIGH during 1 clock (1 cycle of the bus clock (HCLK) signal).

[0084] As a result, the first load (ld1) signal goes HIGH, causing A0, the high-priority master address bus (HADDR) signal of high-priority master circuit 200, to be loaded and latched into ldD-FF 174. Furthermore, S0, the high-priority transfer size (HSIZE) signal of high-priority master circuit 200, to be loaded and latched into ldD-FF 175. Then, at timing t2, the switching timing one clock cycle after timing t1, A0, latched at timing t1, is output from ldD-FF 174 as the auxiliary bus master address bus (HADDR2) signal of auxiliary bus master circuit 100, as indicated by the dashed line extending from the portion of address A0 enclosed by the dotted line at timing t1. Simultaneously, at timing t2, S0, the auxiliary bus master transfer size (HSIZE2) signal of auxiliary bus master circuit 100, is latched and output from ldD-FF 175.

[0085] Furthermore, at timing t1, the 0th selector signal (sel0) and the 0th load signal (ld0) become HIGH, so NONSEQ is loaded and latched into ldD-FF 171. At timing t2, the switching timing of the next clock after timing t1, NONSEQ is latched and output as the transfer type (HTRANS2) signal of auxiliary bus master circuit 100. Similarly, the high-priority master transfer direction (HWRITE) signal and the high-priority master-slave select (HSEL) signal of high-priority master circuit 200 are also loaded and latched into ldD-FF 172 and ldD-FF 173 at timing t1. At timing t2, which follows timing t1, they are latched and output as the auxiliary-bus master transfer direction (HWRITE2) signal and the auxiliary-bus master-slave select (HSEL2) signal of auxiliary-bus master circuit 100.

[0086] Thus, by outputting the auxiliary bus master transfer type (HTRANS2) signal of NONSEQ from the auxiliary bus master circuit 100 to the bus 400, the auxiliary bus master circuit 100 immediately requests access to the bus 400 after the high-priority master circuit 200 initiates a burst transfer (at timing t2, the clock switching timing immediately following timing t1). Similar to the high-priority master circuit 200, the auxiliary bus master circuit 100 sets a higher priority for access to the bus 400 than the other low-priority masters 300. Therefore, even if a low-priority master circuit 300 requests access to the bus 400, the arbitrator prioritizes the next request for access to the bus 400 from the high-priority master circuit 200 while the burst transfer is in progress.

[0087] When the high priority master transmission direction (HWRITE) signal of the high priority master circuit 200 is LOW, the auxiliary bus master write data bus (HWDATA2) signal of the auxiliary bus master circuit 100 is not output, so the control circuit 110 does not need to control the first selector (sel1) signal, the second load (ld2) signal and the third load (ld3) signal. Figure 8 The median value is held.

[0088] The high-priority read data bus (HRDATA) signal of the high-priority master circuit 200 becomes data D0, D1, ..., D7 read from the memory unit 520 by burst transfer, but these data are not used by the auxiliary bus master circuit 100. Furthermore, after the high-priority master circuit 200 completes the burst transfer, data D0 is read as the auxiliary bus master read data bus (HRDATA2) signal of the auxiliary bus master circuit 100, but this signal is also not used by the auxiliary bus master circuit 100.

[0089] Then, at the timing (timing t3) when the auxiliary bus master ready (HREADY2) signal input from bus 400 to auxiliary bus master circuit 100 switches from LOW to HIGH, in response to the auxiliary bus master transfer type (HTRANS2) signal becoming NONSEQ, control circuit 110 sets the 0th load (ld0) signal HIGH for one clock (one cycle of the bus clock (HCLK) signal). At this time, since the 0th selector (sel0) signal is LOW, selectors 161, 162, and 163 load IDLE and latch it into ldD-FF 171, and load LOW and latch it into ldD-FF 172 and 173, respectively. These latched signals are then output at the switching timing of the next clock. That is, at timing t4, which is the next clock switching after timing t3, IDLE is output as the auxiliary bus master transfer type (HTRANS2) signal of the auxiliary bus master circuit 100, and LOW is output as the auxiliary bus master transfer direction (HWRITE2) signal and the auxiliary bus master-slave select (HSEL2) signal.

[0090] Furthermore, as described above, the auxiliary bus master circuit 100 always outputs SINGLE (single transfer mode) as the auxiliary bus master transfer mode (HBURST2) signal. Therefore, even when transmitting read data, the auxiliary bus master circuit 100 always performs single transfers, regardless of the transfer mode (HBURST) of the high-priority master circuit 200. Therefore, after obtaining access to the bus 400, the auxiliary bus master circuit 100 immediately transfers access to the bus 400 to another bus master after obtaining (single transfer) D0 as the auxiliary bus master read data bus (HRDATA2) signal.

[0091] Then, in order to start a burst transfer of data D7 corresponding to address A7 at timing t5, the high-priority master circuit 200 maintains the high-priority master transfer direction (HWRITE) signal at LOW (indicating a read transfer), switches the high-priority master transfer type (HTRANS) signal from IDLE to NONSEQ, and outputs A8 to the high-priority master address bus (HADDR) signal. Subsequently, the auxiliary bus master circuit 100 outputs similar signals at timings t5, t6, t7, t8, and t9, corresponding to the aforementioned timings t0, t1, t2, t3, and t4, respectively.

[0092] In this way, it can be confirmed that the auxiliary bus master circuit 100 functions effectively even during the burst transfer of read.

[0093] As described above, an auxiliary bus master circuit 100 is additionally connected to the bus 400 and the high-priority master circuit 200 of systems 500 and 501. The auxiliary bus master circuit 100 performs bus access using dummy data based on the bus access signal from the high-priority master circuit 200. This allows the high-priority master circuit 200 (and the auxiliary bus master circuit) to temporarily occupy access to the bus 400. Simulation results indicate that the function of the auxiliary bus master circuit 100 can reduce data transmission time for the high-priority master circuit 200 by approximately 10% to 50% when the bus 400 is congested.

[0094] In AHB-Lite of the AMBA standard, the data bus is independent for writing and reading. When write access requests in a low-priority main circuit occur frequently in a short period of time, or read access requests occur frequently in a short period of time, the data transmission time in the high-priority main circuit can be significantly shortened.

[0095] Furthermore, the operation mode signal is input to the control circuit 110, and the operation of the auxiliary bus master circuit 100 can be stopped according to the threshold address, threshold address condition, and transmission direction condition contained in the operation mode signal. For example, if the value of "A8" is set as the threshold address, and the operation is performed when "the address indicated by the address bus signal < the threshold address" is set as the threshold address condition, as shown in FIG. Figure 9 In the example of the timing chart shown, the auxiliary bus master circuit 100 operates when the high priority master address bus (HADDR) signal of the high priority master circuit 200 is A0 (A0<threshold address), and stops when it is A8.

[0096] Reference Figure 9 The operation of the auxiliary bus master circuit 100 in this case will be described. In this case, burst transfer from A0 is performed during the period from t0 to t5, so the auxiliary bus master circuit 100 and Figure 5 At timing t5, the high priority master address bus (HADDR) signal of the high priority master circuit 200 becomes A8, which does not satisfy the threshold address condition included in the operation mode signal, so the operation of the auxiliary bus master circuit 100 stops.

[0097] After timing t6, the 0th selector signal (sel0) remains fixed at LOW, and the control program of control circuit 110 does not start. Consequently, the other signals, such as the 0th load (ld0) signal and the 1st load (ld1) signal, also remain fixed at LOW, and the auxiliary bus master transfer type (HTRANS2) signal of auxiliary bus master circuit 100 remains at IDLE. Consequently, auxiliary bus master circuit 100 does not gain access to bus 400.

[0098] In the case where the low priority master circuit group does not hold the data to be transmitted, even if the auxiliary bus master circuit 100 stops, Figure 10 As shown, the high priority master circuit 200 can also perform burst transmission continuously.

[0099] Since the auxiliary bus master circuit 100 always performs single transmission, the time for which the bus 400 is occupied is short. However, even a short time during which the auxiliary bus master circuit 100 is in operation will cause the bus 400 to be occupied. Figure 7A Therefore, when it is known that the high priority master circuit 200 can reliably and continuously perform burst transmission, the operation of the auxiliary bus master circuit 100 is stopped by using the operation mode signal, as shown in FIG. Figure 10 As shown, the continuous burst transfer of the high-priority master circuit 200 can be further accelerated.

[0100] Furthermore, regarding the control program for the control circuit 110 to output control output signals (such as the 0th selector (sel0) signal and the 0th load (ld0) signal) based on control input signals (such as the operation mode signal, the high priority master ready (HREADY) signal, and the auxiliary bus master ready (HREADY2) signal), any digital circuit designer, even a beginner, can design the control circuit based on the timing diagram. As an example, Figure 11 An example of a minimum RTL (Register Transfer Level) description based on Verilog HDL (Verilog Hardware Description Language) is shown.

[0101] In the above embodiment, the operation mode signal includes information totaling 36 bits, including threshold address information (32 bits), threshold address condition information (2 bits), and transmission direction condition information (2 bits). However, this is merely an example of an operation mode signal. For example, the threshold address information may include information totaling 69 bits, including threshold address A information (32 bits), threshold address B information (32 bits), threshold address condition information (3 bits), and transmission direction condition information (2 bits).

[0102] In this example, how to use threshold address A and threshold address B can be freely set. For example, threshold address A can be set to < threshold address B, and whether to act in the case of "address indicated by the address bus signal ≧ threshold address B" can be switched according to whether the first bit of the threshold address condition is HIGH or LOW. Whether to act in the case of "threshold address B>address indicated by the address bus signal ≧threshold address A" can be switched according to whether the second bit of the threshold address condition is HIGH or LOW. Whether to act in the case of "address indicated by the address bus signal < threshold address A" can be switched according to whether the third bit of the threshold address condition is HIGH or LOW.

[0103] In this manner, by including a plurality of threshold addresses in the operation mode signal, the operation of the auxiliary bus master circuit 100 can be switched more flexibly according to the address.

[0104] Next, as an example of applying the auxiliary bus master circuit 100 to an electronic musical instrument, Figure 12 The sound source system 601 shown is described.

[0105] The sound source system 601 includes a sound source core unit 615 and an auxiliary bus master circuit 620 as a bus master with high priority bus access rights. The auxiliary bus master circuit 620 has the same or equivalent circuit structure and function as the auxiliary bus master circuit 100. In addition, the structure of the sound source system 601 is similar to that of Japanese Patent Application Laid-Open No. 2023-140619. Figure 1 The sound source systems 1 shown have the same configuration, so detailed descriptions are omitted.

[0106] However, the CPU 610, RAM 611, ROM 612, GPIO (General Purpose Input / Output) 613, MEMIF (Memory Interface) 614, sound source core unit 615, and bus 616 of the sound source system 601 correspond to the CPU 10, RAM 11, ROM 12, GPIO 13, MEMIF 14, core unit 15, and bus 16 of the sound source system 1 in Japanese Patent Gazette No. 2023-140619, respectively.

[0107] The sound source system 601 is connected to an external DRAM (Dynamic RAM) 602 and an audio system 603. DRAM 602 stores, for example, Standard MIDI Files (SMFs). The audio system 603 includes a D / A (Digital / Analog) converter, an amplifier, and speakers. Digital musical sound data generated by the sound source core 615 is output from the speakers included in the audio system 603.

[0108] The sound source core 615 includes a DSP (Digital Signal Processor). However, if data transmission delays occur within the DSP, the digital musical sound data cannot be properly output from the sound system 603 (e.g., the sound may be interrupted or distorted). Therefore, the bus access rights of the sound source core 615 are given a higher priority than those of other bus masters. Similarly, the bus access rights of the auxiliary bus master circuit 620 are also given a higher priority than those of other bus masters, similar to the sound source core 615.

[0109] Furthermore, when the sound source core unit 615 attempts to continuously occupy the bus (for example, when performing multiple consecutive burst transmissions), the auxiliary bus master circuit 620 operating in conjunction with the sound source core unit 615 prevents other bus masters from using the bus.

[0110] Therefore, by including the auxiliary bus master circuit 620 , the sound source core unit 615 can perform a plurality of continuous data transmissions without being interrupted by other bus masters, and thus can always normally output digital musical sound data.

[0111] Furthermore, for example, since the SRAM 611 built into the sound source system 601 is high-speed, there is no problem even if the auxiliary bus master circuit 100 is not in operation. Consider a case where the auxiliary bus master circuit 100 is desired to be in operation only when accessing the external DRAM 602. In this case, by setting the threshold address information and the threshold address condition information of the operation mode signal, the auxiliary bus master circuit 100 can be operated only when accessing the external DRAM 602.

[0112] Furthermore, in the above embodiment, the bus 400 standard is described as AHB-Lite, but the bus 400 standard is not limited to AHB-Lite and may be, for example, AHB or a bus standard other than AMBA.

[0113] In addition, in this embodiment, the output of NONSEQ as the high-priority master transfer type (HTRANS) signal is regarded as the output of an access request signal. However, the output of an access request signal is not limited to the output of NONSEQ. Consequently, any signal outputted by the arbiter requesting access to the bus 400 can be regarded as the output of an access request signal.

[0114] Furthermore, in this embodiment, when the high-priority master circuit 200 performs a write data transfer, the auxiliary bus master circuit 100 performs a single data transfer to write the start data (D0). However, depending on the system (for example, in a system that meets a specified specification such as requiring that a writable address must be readable), the auxiliary bus master circuit 100 may perform a single data transfer to read from the same address. In other words, if the auxiliary bus master circuit 100 can access the bus through a read data transfer, it is not necessary to perform a write data transfer.

[0115] Furthermore, in the above disclosure, the term “after a clock” is defined as one clock cycle later, but it may be two or more clock cycles later, even if data transmission is slightly later than one clock cycle later.

[0116] Furthermore, the auxiliary bus master circuit in the present disclosure is not limited to the sound source system as an electronic device, but is applicable to any electronic device including a computer that exchanges transmission data with multiple priorities.

[0117] In the above disclosure, the auxiliary bus master circuit may be a circuit physically separable from the system, and may be connected to an interface of a system bus connected to a storage unit of the system as needed.

[0118] In the present disclosure, unless otherwise specified, the term "at least" includes multiple combinations or a number greater than the number shown, for example, "at least one of A, B, and C" means "(A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C)". In addition, for example, if there is a plurality of C, the term "at least one of A, B, and C" means "(A), (B), (at least one or more C), (A and B), (A and at least one or more C), (B and at least one or more C), or (A, B, and at least one or more C)". In the case where there are multiple A or multiple B, it shall be interpreted in the same manner as above.

[0119] In this disclosure, unless otherwise stated, terms such as "or" and "either" are used to refer to non-exclusive situations (objects), for example, the term "A or B" means "any one of (A but not B), (B but not A), and (A and B)".

[0120] In addition, the term “same” used in the present disclosure is not limited to a strict meaning, but is interpreted as including a range to the extent that the same function can be expected.

[0121] As mentioned above, although the preferred embodiment of the present invention was described, the present invention is not limited to the specific embodiment, and the present invention includes the invention described in the claims and the equivalent scope thereof.

Claims

1. An auxiliary bus main circuit, wherein: The auxiliary bus master circuit is connected to or can be connected to a bus of a system, wherein a high-priority master circuit and a low-priority master circuit are connected to one of the bus lines, the high-priority master circuit having a high-priority bus access right, and the low-priority master circuit having a lower-priority bus access right than the high-priority master circuit. The auxiliary bus master circuit includes a control circuit that outputs an access request signal requesting access rights to the bus based on a timing at which at least one of high-priority master signals, which are signals exchanged via the bus, is output from the high-priority master circuit.

2. The auxiliary bus master circuit according to claim 1, wherein: further comprising a logic circuit for latching the high priority master signal obtained from the high priority master circuit, The control circuit controls a timing of latching the high-priority main signal and a timing of outputting the acquired high-priority main signal to the bus as the access request signal.

3. The auxiliary bus master circuit according to claim 2, wherein: The high-priority master signal latched by the logic circuit is at least one of a high-priority master address bus signal and a high-priority master write data bus signal.

4. The auxiliary bus master circuit according to claim 3, wherein: The control circuit controls to output the access request signal to at least one of the bus that exchanges the high-priority master address bus signal and the bus that exchanges the high-priority master write data bus signal.

5. The auxiliary bus master circuit according to claim 1, wherein: The priority of the bus access right of the auxiliary bus master circuit is set to be higher than that of the low-priority master circuit, A high priority master request signal for requesting access to the bus is obtained from the high priority master circuit; The access request signal is output based on the timing of acquiring the high-priority main request signal.

6. The auxiliary bus master circuit according to claim 1, wherein: As the output of the transmission mode signal indicating whether the transmission mode is the single transmission mode or the burst transmission mode, a transmission mode signal indicating the single transmission mode is output regardless of the transmission mode of the high priority master circuit.

7. The auxiliary bus master circuit according to claim 5, wherein: If the high priority master request signal is obtained, a high priority master address signal indicating the address value accessed by the high priority master circuit is obtained and latched. When the access request signal is output, the obtained high-priority master address signal is output as an address signal indicating an address value accessed by the auxiliary bus master circuit.

8. The auxiliary bus master circuit according to claim 7, wherein: obtaining a high priority master transmission direction signal indicating a transmission direction when the high priority master circuit accesses the bus, In the case where the obtained high priority main transfer direction signal indicates writing, After the timing of acquiring the high priority master address signal, a high priority master data signal indicating the data value written by the high priority master circuit is acquired, When the access request signal is output, the same signal as the acquired high-priority master data signal is output as a write data bus signal indicating the data value written by the auxiliary bus master circuit.

9. The auxiliary bus master circuit according to claim 1, wherein: Get the action mode signal, Based on the acquired operation mode signal, whether or not to output the access request signal is switched.

10. The auxiliary bus master circuit according to claim 9, wherein: The action mode signal includes information about the threshold address and information about the threshold address condition. Whether to output the access request signal is switched according to whether the address value indicated by the high priority main address signal, which is a signal of the address bus in the high priority main signal, satisfies the threshold address and the threshold address condition.

11. The auxiliary bus master circuit according to claim 8, wherein: Get the action mode signal, The obtained action mode signal includes information on transmission direction conditions, Whether to output the access request signal is switched based on whether the information indicated by the obtained high-priority main transmission direction signal satisfies the transmission direction condition.

12. An electronic device, wherein: have: The auxiliary bus main circuit according to any one of claims 1 to 11; and The high priority main circuit.

13. A control method for an auxiliary bus main circuit, wherein: The auxiliary bus master circuit is connected to or can be connected to a bus of a system, wherein a high-priority master circuit and a low-priority master circuit are connected to one of the bus lines, the high-priority master circuit having a high-priority bus access right, and the low-priority master circuit having a lower-priority bus access right than the high-priority master circuit. An access request signal requesting access rights is output to the bus based on a timing at which at least one of the high-priority master signals, which are signals exchanged via the bus, is output from the high-priority master circuit.

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