Multi-voltage-domain low-power-consumption chip power supply transmission network design method and related equipment

Abstract

The invention provides a multi-voltage-domain low-power-consumption chip power supply transmission network design method and related equipment, and the method comprises the steps: dividing a multi-voltage-domain low-power-consumption chip into a plurality of nodes according to a preset grid size, and extracting the static power consumption feature, the dynamic instantaneous power consumption feature and the PDN feature of each node; static power consumption features, dynamic power consumption features and PDN features are fused through the input end of the IR Drop prediction model, time synchronization switching activity is captured through a 3D convolutional layer, and IR Drop prediction maps of all areas of the multi-voltage-domain low-power-consumption chip are output; and according to the IR Drop prediction map, iteratively adjusting PDN template parameters through a simulated annealing algorithm until the IR Drop loss and the PDN utilization rate reach optimization thresholds, and generating final power supply transmission network configuration. The method has the beneficial effects that the power supply network design period and the labor cost of the multi-voltage domain chip are remarkably reduced, and the method is suitable for the design of a system-level chip with high complexity and low power consumption requirements in an advanced process.

Description

Technical Field

[0001] The present invention relates to the field of chip circuit design, and in particular to a multi-voltage domain low-power chip power delivery network design method and related equipment. Background Art

[0002] With the continuous evolution of integrated circuit (IC) technology, chip power density and design complexity are growing exponentially. The joint optimization of dynamic and static power has become a core challenge in low-power design. To address this challenge, modern system-on-chip (SoC) designs commonly employ multi-voltage domain (MVD) technology. This technology reduces dynamic power consumption by assigning independent minimum operating voltages to different functional modules, and combines it with power gating technology to cut off power to idle modules to suppress static power consumption. However, the introduction of these low-power technologies significantly increases the complexity of power delivery network (PDN) design: the layout of power switches, the isolation of multiple voltage domains, and the topology of the power supply network must all meet strict IRDrop constraints to avoid timing failures or functional errors caused by local voltage drops.

[0003] At deep submicron process nodes and below, the IR drop problem in power networks is particularly prominent. When high-density logic cells switch simultaneously within a short period of time, the current density on the power network surges, causing the voltage drop (IR drop) caused by the metal interconnect resistance to exceed the threshold. Excessive IR drop reduces the actual operating voltage of the logic cells, increasing signal delays, degrading noise margins, and even causing setup and hold timing violations. Traditional IR drop analysis relies on solving linear equations with billions of variables, requiring full-chip dynamic simulation using commercial electronic design automation (EDA) tools, which can take hours to days to calculate. To meet design convergence requirements, engineers must perform multiple iterations between PDN design, IR drop analysis, and floorplan / placement, resulting in extended chip back-end design cycles and significantly increased costs.

[0004] To address the above issues, there is an urgent need for an innovative method that can quickly perceive the multi-voltage domain power network structure, accurately predict the dynamic IRDrop distribution, and automatically optimize PDN parameters to break through the bottleneck of the traditional design process and improve the efficiency of chip design. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to improve the efficiency of designing a power supply network for a multi-voltage domain low-power chip.

[0006] In order to solve the above technical problems, the present invention adopts a technical solution: a multi-voltage domain low-power chip power delivery network design method, comprising the following steps:

[0007] S10, dividing the multi-voltage domain low-power chip into multiple nodes according to a preset grid size, and extracting static power consumption characteristics, dynamic instantaneous power consumption characteristics, and PDN characteristics of each node, wherein the PDN characteristics include current direction attributes, voltage value attributes, power bar width attributes, and power switch attributes;

[0008] S20, fusing static power consumption characteristics, dynamic power consumption characteristics, and PDN characteristics through the input end of the IR Drop prediction model, capturing time-synchronized switching activities through a 3D convolution layer, and outputting IR Drop prediction maps for each region of the multi-voltage domain low-power chip; the IR Drop prediction model is a U-Net model with an encoder-decoder structure built based on a deep convolutional neural network;

[0009] S30. According to the IR Drop prediction graph, iteratively adjust the PDN template parameters through a simulated annealing algorithm until the IR Drop loss and the PDN utilization reach an optimization threshold, thereby generating a final power delivery network configuration.

[0010] Furthermore, in step S10, the extraction of the current direction attribute includes:

[0011] Determine the horizontal current direction by judging whether there are high-level vertical power strips on the left and right sides of the node;

[0012] By judging whether there is an underlying horizontal power rail above and below the node, the vertical current direction is determined and represented in the form of a one-hot code.

[0013] Furthermore, in step S10, the extraction of the dynamic instantaneous power consumption characteristics includes:

[0014] Combined with the timing window file, a three-dimensional dynamic power consumption feature is generated with the time axis as the third dimension, and the time axis covers multiple time windows within the chip working mode switching cycle.

[0015] Furthermore, in step S20, the structure of the IR Drop prediction model includes:

[0016] A 3D convolutional layer is used in the encoding path to process the temporally synchronous switching activity features;

[0017] Transposed convolution and upsampling layers are used in the decoding path to restore spatial resolution;

[0018] Two layers of shortcut connections are set between the encoder and decoder to preserve position information.

[0019] Furthermore, in step S10, the adjustment of the PDN template parameters includes:

[0020] Jointly optimize power strip width, spacing, and power switch distribution across different voltage domains;

[0021] Based on the areas exceeding the threshold in the IR Drop prediction graph, the power bar width in the corresponding area is increased or the power bar spacing is reduced.

[0022] Furthermore, in step S10, the static power consumption characteristics include: the sum and two-dimensional distribution of internal power consumption, switching power consumption, and leakage power consumption, and the grid size is set based on a standard cell size.

[0023] Furthermore, step S30 further includes:

[0024] After the automatic PDN planning is completed, a process-compatible power network script is generated for direct deployment of power strips and power switch layouts in back-end design tools.

[0025] The present invention also provides a multi-voltage domain low-power chip power delivery network design device, comprising:

[0026] A feature extraction module is used to divide the multi-voltage domain low-power chip into multiple nodes according to a preset grid size, and extract the static power consumption characteristics, dynamic instantaneous power consumption characteristics and PDN characteristics of each node. The PDN characteristics include current direction attributes, voltage value attributes, power bar width attributes and power switch attributes;

[0027] A model prediction module is used to fuse static power consumption characteristics, dynamic power consumption characteristics, and PDN characteristics through the input of the IR Drop prediction model, capture time-synchronized switching activities through a 3D convolutional layer, and output IR Drop prediction maps for each region of the multi-voltage domain low-power chip. The IR Drop prediction model is a U-Net model with an encoder-decoder structure built based on a deep convolutional neural network.

[0028] The PDN optimization module is used to iteratively adjust the PDN template parameters based on the IR Drop prediction graph through the simulated annealing algorithm until the IR Drop loss and PDN utilization reach the optimization threshold, thereby generating the final power delivery network configuration.

[0029] The present invention also provides a computer device, comprising a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the multi-voltage domain low-power chip power delivery network design method as described in any one of the above items is implemented.

[0030] The present invention also provides a storage medium storing a computer program, which, when executed by a processor, can implement the multi-voltage domain low-power chip power delivery network design method as described in any one of the above items.

[0031] The beneficial effects of the present invention are: it can extract the power consumption characteristics and PDN characteristics of multi-voltage domain low-power chips, so that the model has the ability to perceive the PDN structure, and quickly and accurately predict the dynamic IR Drop of multi-voltage domain low-power chips through a deep convolutional neural network. It also optimizes the power delivery network through an optimization algorithm, realizes automatic PDN planning of multi-voltage domain low-power chips, reduces the iteration time in the chip back-end design, and improves the level of design automation. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The specific structure of the present invention is described in detail below with reference to the accompanying drawings.

[0033] Figure 1 This is a flow chart of a method for designing a multi-voltage domain low-power chip power delivery network according to an embodiment of the present invention;

[0034] Figure 2 This is an example diagram of a PDN feature extraction process for a multi-voltage domain low-power chip according to an embodiment of the present invention;

[0035] Figure 3 This is a diagram of the dynamic IR drop prediction architecture of a multi-voltage domain low-power chip according to an embodiment of the present invention;

[0036] Figure 4 This is a structural diagram of a dynamic IR drop prediction model according to an embodiment of the present invention;

[0037] Figure 5 This is an example diagram of IR drop prediction results for different voltage domains in a multi-voltage domain low-power chip according to an embodiment of the present invention;

[0038] Figure 6 A block diagram of a device for designing a multi-voltage domain low-power chip power delivery network according to an embodiment of the present invention;

[0039] Figure 7 A schematic block diagram of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0040] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0041] It will be understood that when used in this specification and the appended claims, the terms “comprises” and “comprising” indicate the presence of described features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0042] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the present invention. As used in the specification and appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0043] It should be further understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0044] like Figure 1 As shown, an embodiment of the present invention is: a multi-voltage domain low-power chip power delivery network design method, comprising the following steps:

[0045] S10, dividing the multi-voltage domain low-power chip into multiple nodes according to a preset grid size, and extracting static power consumption characteristics, dynamic instantaneous power consumption characteristics, and PDN characteristics of each node, wherein the PDN characteristics include current direction attributes, voltage value attributes, power bar width attributes, and power switch attributes;

[0046] Wherein, in step S10, the extraction of the current direction attribute includes:

[0047] Determine the horizontal current direction by judging whether there are high-level vertical power strips on the left and right sides of the node;

[0048] By judging whether there is an underlying horizontal power rail above and below the node, the vertical current direction is determined and represented in the form of a one-hot code.

[0049] In step S10, the extraction of the dynamic instantaneous power consumption characteristics includes:

[0050] Combined with the timing window file, a three-dimensional dynamic power consumption feature is generated with the time axis as the third dimension, and the time axis covers multiple time windows within the chip working mode switching cycle.

[0051] In step S10, the adjustment of the PDN template parameters includes:

[0052] Jointly optimize power strip width, spacing, and power switch distribution across different voltage domains;

[0053] Based on the areas exceeding the threshold in the IR Drop prediction graph, the power bar width in the corresponding area is increased or the power bar spacing is reduced.

[0054] Wherein, in step S10, the static power consumption characteristics include: the sum and two-dimensional distribution of internal power consumption, switching power consumption, and leakage power consumption, and the grid size is set based on the standard cell size.

[0055] In this embodiment, a method for extracting power consumption characteristics and PDN characteristics of a multi-voltage domain low-power chip is designed, which is responsible for extracting power consumption characteristics and PDN distribution characteristics of each power domain in the chip. Specifically, it includes:

[0056] In the pre-placement and subsequent stages of chip back-end design, the overall unit positions of the chip are basically determined. After using tools to simulate the chip's dynamic power consumption, its library exchange format (LEF), design exchange format (DEF), timing window (TWF), and power consumption report files are extracted.

[0057] The two-dimensional distribution of chip features is segmented at a specific tile size, used as pixels in the "image." For example, the size of the chip's global cell is used as the minimum area for feature extraction. Based on this, code is used to extract static power consumption characteristics related to cell location, such as internal chip power consumption, switching power consumption, leakage power consumption, and total power consumption. Combined with the TWF file, these characteristics are used to calculate three-dimensional dynamic instantaneous power consumption characteristics related to space and time.

[0058] PDN feature extraction divides the chip into tile-sized regions and calculates the current direction and stripe width attributes associated with each tile's high-level power rails. This implicitly captures the chip's PDN location and shape. Furthermore, based on the characteristics of multi-voltage domains and low-power designs, power switch attribute extraction and voltage value attribute extraction are designed as another component of PDN feature extraction.

[0059] Please refer to Figure 2 , Figure 2This is an example of the PDN feature extraction process of the multi-voltage domain low-power chip of the present invention. The chip is divided into a chessboard shape with a certain grid size, where each grid is called a node. In the back-end design of the chip, the upper layers of the power delivery network often use thicker metal layers and larger widths, and the IR drop thereon is small and negligible. Therefore, the IR drop of the chip mainly occurs in the power rails of the lower layers, and the power delivery network transmits current from the high-level power rails to the lower-level power rails through vias (via) or power switches (power switch). Without considering macro units, which generally use a special power ring design, the IR drop on an ordinary standard unit is closely related to the distance from the nearest vertical high-level power stripes around it. The present invention uses a unique hot code to characterize the current direction attribute, so as to describe the distance between the node and the stripes and the connection with the surrounding nodes, and designs the voltage value attribute, the power strip width attribute and the power switch attribute as the PDN feature of the chip. The following is combined with Figure 2 Description of each feature:

[0060] 1) To the right: Determines whether the upper-level vertical power strip closest to the node is on the left. If so, set it to 1, indicating that the current direction is from the left to the right of the node; 0 indicates that the node current direction is not from left to right.

[0061] 2) To the left: Determines whether the upper-level vertical power strip closest to the node is on the right. If so, set it to 1, indicating that the current direction flows from the right to the left of the node; 0 indicates that the node current direction is not from right to left.

[0062] 3) To the top: Determines whether there is a bottom-level horizontal power rail above the node. If so, set it to 1, indicating that the current direction flows from the node itself to the top; 0 indicates that there is no horizontal power rail above the node.

[0063] 4) To the bottom: Determines whether there is a bottom horizontal power rail below the node. If so, set it to 1, indicating that the current direction flows from the node itself to the bottom; 0 indicates that there is no horizontal power rail below the node.

[0064] 5) Voltage value: Indicates the voltage value of the power domain where the node is located.

[0065] 6) Stripes width: Indicates the width of the upper-level vertical power strip closest to the node.

[0066] 7) Power switch: Determines whether the node is in a power domain that can be shut off and powered by a power switch. If so, set it to 1; 0 indicates that the node is in a power-on domain.

[0067] As can be seen, by determining the number of consecutive "1s" in the "To the right" and "To the left" current direction attribute graph rows, we can determine the distance to the nearest stripe. Furthermore, the current direction can also be opposite to the actual situation. The practical significance of these features is automatically learned and extracted by the deep learning model.

[0068] S20, fusing static power consumption characteristics, dynamic power consumption characteristics, and PDN characteristics through the input end of the IR Drop prediction model, capturing time-synchronized switching activities through a 3D convolution layer, and outputting IR Drop prediction maps for each region of the multi-voltage domain low-power chip; the IR Drop prediction model is a U-Net model with an encoder-decoder structure built based on a deep convolutional neural network;

[0069] In step S20, the structure of the IR Drop prediction model includes:

[0070] A 3D convolutional layer is used in the encoding path to process the temporally synchronous switching activity features;

[0071] Transposed convolution and upsampling layers are used in the decoding path to restore spatial resolution;

[0072] Two layers of shortcut connections are set between the encoder and decoder to preserve position information.

[0073] In this embodiment, a method for building and training a dynamic IR drop prediction deep learning model is designed, which is responsible for realizing the IR drop prediction of the entire chip. Specifically, it includes:

[0074] A deep convolutional neural network (DCNN) was used to perceive current variations along spatial and temporal axes. A classic U-Net-like encoder-decoder architecture with two layers of shortcut connections was constructed. To achieve temporal awareness, 3D convolutional layers were used in the encoding path to capture time-synchronized switching activity. Furthermore, a training dataset for the model was constructed using backend tools and feature extraction algorithms. Each sample included the multiple features mentioned in Part 1 as input. To adapt the model to varying chip layout sizes, each input feature was resized to a uniform dimension and ultimately concatenated into a single feature. Furthermore, the tool performed power rail analysis on each training sample to obtain a true two-dimensional IR drop map of the chip. After normalization, a label was generated for each sample. For different power networks within the same chip, each network had a separate feature and corresponding label. The model was trained using a backpropagation algorithm. After parameter optimization, it can predict the IR drop of different power networks in multi-voltage domain low-power chips under the corresponding process.

[0075] Please refer to Figure 3 , Figure 3 This is the dynamic IR drop prediction architecture diagram of the multi-voltage domain low-power chip in the present invention. By using commercial tools in the back-end design, the complete layout design process is run on the sample chip of the training data set, and the library exchange format (LEF), design exchange format (DEF), timing window (TWF), and power consumption report file of its signoff stage are extracted. On this basis, the static power consumption characteristics related to the unit position, such as the internal power consumption, switching power consumption, leakage power consumption, and total power consumption of the chip are extracted through Python code, and the three-dimensional dynamic instantaneous power consumption characteristics related to space and time are calculated in combination with the TWF file, and the PDN characteristics of the chip are extracted at the same time. The static power consumption characteristics, dynamic power consumption characteristics, and PDN characteristics are fused and aligned as the features of the model. For the training data set, the tool is also used to run vectorless dynamic power consumption simulation and dynamic power rail simulation to obtain the real dynamic IR drop report of the chip. The IR drop loss map is generated from the report and used as the labels of the model after logarithmic normalization. For different power networks in the same chip, each network has a separate feature and corresponding label. The model is trained using the back-propagation algorithm. After parameter optimization, it can predict the IR drop of different power networks of multi-voltage domain low-power chips under the corresponding process.

[0076] Please refer to Figure 4 , Figure 4 This is a structural diagram of the dynamic IR drop prediction model in the present invention. In order to make the model adapt to different chip layout size inputs, each input feature is resized to a unified dimension, and finally spliced ​​and fused into a single feature input model. A deep convolutional neural network is used to perceive the changes in current along the spatial and temporal axes, and a classic encoder-decoder structure similar to U-Net with two layers of shortcut connections is constructed. In order to achieve time perception, a 3D convolution layer is used in the encoding path to capture time-synchronized switching activities. The decoding path in the EDGe network uses transposed convolution and upsampling layers to reproduce the position information lost during the downsampling process. The model can finally output an IR drop prediction map corresponding to the chip position.

[0077] Please refer to Figure 5 , Figure 5This figure shows an example of IR drop prediction results for different voltage domains in a multi-voltage domain low-power chip. Different power domains use different chip areas and voltages, resulting in different IR drops on their power networks. This method uses a single deep learning model to predict IR drops within different power domains within a chip, including those within power domains that can be turned off. This allows for fast and accurate dynamic IR drop prediction in multi-voltage domain low-power chips.

[0078] S30. According to the IR Drop prediction graph, iteratively adjust the PDN template parameters through a simulated annealing algorithm until the IR Drop loss and the PDN utilization reach an optimization threshold, thereby generating a final power delivery network configuration.

[0079] Wherein, step S30 further includes:

[0080] After the automatic PDN planning is completed, a process-compatible power network script is generated for direct deployment of power strips and power switch layouts in back-end design tools.

[0081] In this embodiment, a method is designed to implement chip PDN design using an optimization algorithm based on IR drop prediction results, which is responsible for achieving automatic PDN planning for the entire chip. Specifically, it includes:

[0082] First, the chip layout is floorplanned and pre-placed. At this point, the overall unit position of the chip has been determined, but the chip PDN network has not yet been created.

[0083] Then, use the tool to perform power analysis and extract the overall power consumption characteristics of the chip. Default PDN templates are set in different voltage domains, including preset parameters such as power stripe width and stripe spacing.

[0084] Then, the chip’s PDN feature map is extracted based on the above PDN information, and it is combined with the power consumption feature map and input into the trained model for IR drop prediction.

[0085] Based on the IR drop prediction results, the PDN template parameters are adjusted using optimization algorithms such as simulated annealing. Multiple cycles are then performed between PDN feature extraction, IR drop prediction, and PDN parameter optimization. The process stops when the IR drop loss and PDN utilization are optimal, thereby achieving automatic PDN planning for the chip.

[0086] Compared with the existing technology, the present invention proposes a multi-voltage domain low-power chip power delivery network design method, which can realize the power consumption characteristics and PDN characteristics extraction of multi-voltage domain low-power chips, so that the model has the ability to perceive the PDN structure. At the same time, it can quickly and accurately predict the dynamic IR Drop of multi-voltage domain low-power chips through deep convolutional neural networks, and optimize the power delivery network through optimization algorithms, realizing automatic PDN planning of multi-voltage domain low-power chips, which can effectively reduce the iteration time of chip back-end PDN design and improve the level of design automation.

[0087] like Figure 6 As shown, the present invention also provides a multi-voltage domain low-power chip power delivery network design device, comprising:

[0088] A feature extraction module 10 is configured to divide the multi-voltage domain low-power chip into multiple nodes according to a preset grid size, and extract the static power consumption characteristics, dynamic instantaneous power consumption characteristics, and PDN characteristics of each node. The PDN characteristics include current direction attributes, voltage value attributes, power bar width attributes, and power switch attributes.

[0089] The model prediction module 20 is configured to fuse static power consumption characteristics, dynamic power consumption characteristics, and PDN characteristics through the input of the IR Drop prediction model, capture time-synchronized switching activities through a 3D convolutional layer, and output an IR Drop prediction map for each region of the multi-voltage domain low-power chip. The IR Drop prediction model is a U-Net model with an encoder-decoder structure built based on a deep convolutional neural network.

[0090] The PDN optimization module 30 is used to iteratively adjust the PDN template parameters through a simulated annealing algorithm according to the IR Drop prediction graph until the IR Drop loss and PDN utilization reach the optimization threshold, thereby generating a final power delivery network configuration.

[0091] It should be noted that those skilled in the art can clearly understand that the specific implementation process of the above-mentioned multi-voltage domain low-power chip power delivery network design device can refer to the corresponding description in the aforementioned method embodiment. For the convenience and brevity of the description, it will not be repeated here.

[0092] The above-mentioned multi-voltage domain low-power chip power delivery network design device can be implemented in the form of a computer program. The computer program can be used in Figure 7 Runs on the computer device shown.

[0093] See also Figure 7 , Figure 7This is a schematic block diagram of a computer device provided in an embodiment of the present application. The computer device 500 can be a terminal or a server. The terminal can be a smart phone, tablet computer, laptop computer, desktop computer, personal digital assistant, wearable device, or other electronic device with communication capabilities. The server can be a standalone server or a server cluster consisting of multiple servers.

[0094] See Figure 7 The computer device 500 includes a processor 502 , a memory, and a network interface 505 connected via a system bus 501 , wherein the memory may include a non-volatile storage medium 503 and an internal memory 504 .

[0095] The non-volatile storage medium 503 can store an operating system 5031 and a computer program 5032. The computer program 5032 includes program instructions, which, when executed, can enable the processor 502 to execute a multi-voltage domain low-power chip power delivery network design method.

[0096] The processor 502 is used to provide computing and control capabilities to support the operation of the entire computer device 500.

[0097] The internal memory 504 provides an environment for running the computer program 5032 in the non-volatile storage medium 503. When the computer program 5032 is executed by the processor 502, the processor 502 can execute a multi-voltage domain low-power chip power delivery network design method.

[0098] The network interface 505 is used to communicate with other devices through the network. Figure 7 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present application, and does not constitute a limitation on the computer device 500 to which the solution of the present application is applied. The specific computer device 500 may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0099] The processor 502 is configured to run a computer program 5032 stored in the memory to implement the multi-voltage domain low-power chip power delivery network design method as described above.

[0100] It should be understood that in the embodiment of the present application, the processor 502 may be a central processing unit (CPU), and the processor 502 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0101] Those skilled in the art will appreciate that all or part of the steps in the method of the above-described embodiment can be implemented by instructing the relevant hardware through a computer program. The computer program includes program instructions, which can be stored in a storage medium that is computer-readable. The program instructions are executed by at least one processor in the computer system to implement the steps in the method of the above-described embodiment.

[0102] Therefore, the present invention also provides a storage medium. The storage medium may be a computer-readable storage medium. The storage medium stores a computer program, wherein the computer program includes program instructions. When executed by a processor, the program instructions cause the processor to execute the above-described multi-voltage domain low-power chip power delivery network design method.

[0103] The storage medium may be any computer-readable storage medium that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a magnetic disk, or an optical disk.

[0104] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the composition and steps of each example according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0105] In the several embodiments provided herein, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the various units is merely a logical functional division, and actual implementation may employ other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be omitted or not implemented.

[0106] The steps in the methods of the embodiments of the present invention may be adjusted in order, combined, or deleted as needed. The units in the devices of the embodiments of the present invention may be combined, divided, or deleted as needed. Furthermore, the functional units in the various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit.

[0107] If this integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the existing technology, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, terminal, or network device, etc.) to execute all or part of the steps of the method described in various embodiments of the present invention.

[0108] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and such modifications or substitutions are intended to be within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A method for designing a multi-voltage domain low-power chip power delivery network, characterized in that: The following steps are involved: S10, dividing the multi-voltage domain low-power chip into multiple nodes according to a preset grid size, and extracting static power consumption characteristics, dynamic instantaneous power consumption characteristics, and PDN characteristics of each node, wherein the PDN characteristics include current direction attributes, voltage value attributes, power bar width attributes, and power switch attributes; S20, fusing static power consumption characteristics, dynamic power consumption characteristics, and PDN characteristics through the input end of the IR Drop prediction model, capturing time-synchronized switching activities through a 3D convolution layer, and outputting IR Drop prediction maps for each region of the multi-voltage domain low-power chip; the IR Drop prediction model is a U-Net model with an encoder-decoder structure built based on a deep convolutional neural network; S30. According to the IR Drop prediction graph, iteratively adjust the PDN template parameters through a simulated annealing algorithm until the IR Drop loss and the PDN utilization reach an optimization threshold, thereby generating a final power delivery network configuration.

2. The method for designing a multi-voltage domain low-power chip power delivery network according to claim 1, characterized in that: In step S10, the extraction of the current direction attribute includes: Determine the horizontal current direction by judging whether there are high-level vertical power strips on the left and right sides of the node; By judging whether there is an underlying horizontal power rail above and below the node, the vertical current direction is determined and represented in the form of a one-hot code.

3. The method for designing a multi-voltage domain low-power chip power delivery network according to claim 1, characterized in that: In step S10, the extraction of the dynamic instantaneous power consumption characteristics includes: Combined with the timing window file, a three-dimensional dynamic power consumption feature is generated with the time axis as the third dimension, and the time axis covers multiple time windows within the chip working mode switching cycle.

4. The method for designing a multi-voltage domain low-power chip power delivery network according to claim 1, wherein: In step S20, the structure of the IR Drop prediction model includes: A 3D convolutional layer is used in the encoding path to process the temporally synchronous switching activity features; Transposed convolution and upsampling layers are used in the decoding path to restore spatial resolution; Two layers of shortcut connections are set between the encoder and decoder to preserve position information.

5. The method for designing a multi-voltage domain low-power chip power delivery network according to claim 1, wherein: In step S10, the adjustment of the PDN template parameters includes: Jointly optimize power strip width, spacing, and power switch distribution across different voltage domains; Based on the areas exceeding the threshold in the IR Drop prediction graph, the power bar width in the corresponding area is increased or the power bar spacing is reduced.

6. The method for designing a multi-voltage domain low-power chip power delivery network according to claim 1, wherein: In step S10 , the static power consumption characteristics include: the sum and two-dimensional distribution of internal power consumption, switching power consumption, and leakage power consumption, and the grid size is set based on a standard cell size.

7. The method for designing a multi-voltage domain low-power chip power delivery network according to claim 1, wherein: Step S30 further includes: After the automatic PDN planning is completed, a process-compatible power network script is generated for direct deployment of power strips and power switch layouts in back-end design tools.

8. A multi-voltage domain low-power chip power delivery network design device, characterized in that: include: A feature extraction module is used to divide the multi-voltage domain low-power chip into multiple nodes according to a preset grid size, and extract the static power consumption characteristics, dynamic instantaneous power consumption characteristics and PDN characteristics of each node. The PDN characteristics include current direction attributes, voltage value attributes, power bar width attributes and power switch attributes; A model prediction module is used to fuse static power consumption characteristics, dynamic power consumption characteristics, and PDN characteristics through the input of the IR Drop prediction model, capture time-synchronized switching activities through a 3D convolutional layer, and output an IRDrop prediction map for each region of the multi-voltage domain low-power chip. The IR Drop prediction model is a U-Net model with an encoder-decoder structure built based on a deep convolutional neural network. The PDN optimization module is used to iteratively adjust the PDN template parameters based on the IR Drop prediction graph through the simulated annealing algorithm until the IR Drop loss and PDN utilization reach the optimization threshold, thereby generating the final power delivery network configuration.

9. A computer device, characterized in that: The computer device includes a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the multi-voltage domain low-power chip power delivery network design method according to any one of claims 1 to 7 is implemented.

10. A storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the method for designing a multi-voltage domain low-power chip power delivery network according to any one of claims 1 to 7 can be implemented.

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