Common mode return loss optimization method and device, computer equipment, medium and program product

Abstract

The invention relates to the technical field of circuit design, and discloses a common mode return loss optimization method and device, computer equipment, a medium and a program product. The method comprises the following steps: acquiring a substrate simulation model; the substrate simulation model is constructed based on a substrate link in advance; the substrate link comprises a substrate wire and a fan-out area; starting the substrate simulation model, and collecting fan-out area common-mode impedance and substrate wiring common-mode impedance; comparing the fan-out area common-mode impedance with the substrate wiring common-mode impedance to adjust an accompanying ground hole design value and / or a core hole design value in the substrate simulation model; acquiring substrate wiring common-mode impedance, fan-out area common-mode impedance and substrate common-mode return loss of the adjusted substrate simulation model; and if the substrate wiring common-mode impedance, the fan-out area common-mode impedance and the substrate common-mode return loss of the adjusted substrate simulation model do not meet the preset conditions, returning to the step of starting the substrate simulation model. The scheme is simple and easy to operate, and the common mode return loss optimization effect is good.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit design, and in particular to a common-mode return loss optimization method, device, computer equipment, medium, and program product. Background Art

[0002] Common-mode return loss (CMRL) refers to the common-mode noise generated by the characteristics of current flow paths in circuit design. Common-mode return loss (CMRL) is a key metric for measuring common-mode signal reflection or loss during transmission, caused by factors such as capacitive coupling or electromagnetic coupling between signal lines and ground. It is defined as the absolute ratio of the power of the reflected wave to the incident wave during common-mode signal transmission.

[0003] In substrate circuits, common-mode return loss can cause signal interference and loss, affecting signal integrity and reliability, degrading signal quality, and ultimately impacting the overall performance of the substrate circuit. Therefore, a solution to optimize common-mode return loss in substrate circuits is urgently needed. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a common-mode return loss optimization method, device, computer equipment, medium and program product to solve the problem that common-mode return loss in substrate circuits causes poor signal quality and affects circuit performance.

[0005] In a first aspect, the present invention provides a common mode return loss optimization method, the method comprising:

[0006] Obtaining a substrate simulation model; the substrate simulation model is pre-built based on a substrate link; the substrate link includes a substrate trace and a fan-out area;

[0007] Starting the substrate simulation model to collect the common-mode impedance of the fan-out area and the common-mode impedance of the substrate traces;

[0008] Comparing the common-mode impedance of the fan-out region with the common-mode impedance of the substrate traces to adjust a design value of a companion ground hole and / or a design value of a core hole in the substrate simulation model;

[0009] Obtain the substrate trace common-mode impedance, fan-out area common-mode impedance, and substrate common-mode return loss of the adjusted substrate simulation model;

[0010] If the substrate trace common-mode impedance, the fan-out area common-mode impedance, and the substrate common-mode return loss of the adjusted substrate simulation model do not meet the preset conditions, the process returns to the step of starting the substrate simulation model.

[0011] In an optional embodiment, comparing the common-mode impedance of the fan-out region with the common-mode impedance of the substrate trace to adjust the accompanying ground hole design value and / or the core hole design value in the substrate simulation model includes:

[0012] If the common-mode impedance of the fan-out area is greater than the common-mode impedance of the substrate traces, increasing the number of accompanying ground holes in the substrate simulation model;

[0013] If the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, the number of accompanying ground holes in the substrate simulation model is reduced.

[0014] In an optional embodiment, comparing the common-mode impedance of the fan-out region with the common-mode impedance of the substrate traces to adjust the accompanying ground hole design value and / or the core hole design value in the substrate simulation model further includes:

[0015] If the common-mode impedance of the fan-out region is greater than the common-mode impedance of the substrate traces, increasing the core hole N / P spacing in the substrate simulation model;

[0016] If the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, the core hole N / P spacing in the substrate simulation model is reduced.

[0017] In an optional embodiment, comparing the common-mode impedance of the fan-out region with the common-mode impedance of the substrate traces to adjust the accompanying ground hole design value and / or the core hole design value in the substrate simulation model further includes:

[0018] If the common-mode impedance of the fan-out area is greater than the common-mode impedance of the substrate traces, increase the number of accompanying ground holes and the core hole N / P spacing in the substrate simulation model;

[0019] If the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, the number of accompanying ground holes and the core hole N / P spacing in the substrate simulation model are reduced.

[0020] In an optional embodiment, if the substrate trace common-mode impedance, the fan-out area common-mode impedance, and the substrate common-mode return loss of the adjusted substrate simulation model do not meet preset conditions, returning to the step of starting the substrate simulation model includes:

[0021] Calculate the difference between the common-mode impedance of the substrate traces and the common-mode impedance of the fan-out area of ​​the adjusted substrate simulation model;

[0022] When the difference exceeds a first preset threshold and / or the substrate common mode return loss exceeds a second preset threshold, the method returns to the step of starting the substrate simulation model.

[0023] In an optional embodiment, the method further includes:

[0024] Gradually adjusting the accompanying ground hole design value and / or the core hole design value in the substrate simulation model to obtain a substrate trace common-mode impedance change curve, a fan-out area common-mode impedance change curve, and a common-mode return loss change curve of the substrate simulation model;

[0025] Based on the common-mode impedance change curve of the substrate trace, the common-mode impedance change curve of the fan-out area, and the common-mode return loss change curve of the substrate simulation model, the optimal design value of the accompanying ground hole and / or the optimal design value of the core hole are determined so that the common-mode impedance of the substrate trace, the common-mode impedance of the fan-out area, and the common-mode return loss of the substrate meet preset conditions.

[0026] In a second aspect, the present invention provides a common mode return loss optimization device, the device comprising:

[0027] A model acquisition module is used to acquire a substrate simulation model; the substrate simulation model is pre-built based on a substrate link; the substrate link includes a substrate routing and a fan-out area;

[0028] An impedance acquisition module, configured to start the substrate simulation model and acquire the common-mode impedance of the fan-out area and the common-mode impedance of the substrate traces;

[0029] an adjustment module, configured to compare the common-mode impedance of the fan-out region with the common-mode impedance of the substrate traces to adjust a design value of the accompanying ground via and / or a design value of the core via in the substrate simulation model;

[0030] A parameter acquisition module is used to obtain the substrate trace common-mode impedance, fan-out area common-mode impedance, and substrate common-mode return loss of the adjusted substrate simulation model;

[0031] The judgment module is configured to return to the step of starting the substrate simulation model if the substrate trace common mode impedance, the fan-out area common mode impedance, and the substrate common mode return loss of the adjusted substrate simulation model do not meet preset conditions.

[0032] In a third aspect, the present invention provides a computer device comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the common-mode return loss optimization method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0033] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the common-mode return loss optimization method of the first aspect or any corresponding embodiment thereof.

[0034] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions, where the computer instructions are used to enable a computer to execute the common-mode return loss optimization method of the first aspect or any corresponding embodiment thereof.

[0035] The technical solution provided by the present invention can have the following beneficial effects:

[0036] The common-mode return loss optimization method provided by the present invention first obtains a substrate simulation model pre-constructed based on a substrate link, then starts the substrate simulation model to perform a simulation operation to collect the common-mode impedance of the fan-out area and the common-mode impedance of the substrate trace. Then, with the goal of reducing the difference between the common-mode impedance of the fan-out area and the common-mode impedance of the substrate trace, the common-mode impedance of the fan-out area is compared with the common-mode impedance of the substrate trace. Based on the comparison result, the design value of the accompanying ground hole and / or the design value of the core hole in the substrate simulation model is adjusted, and the simulation operation is performed again to obtain the common-mode impedance of the substrate trace, the common-mode impedance of the fan-out area, and the common-mode return loss of the substrate after the adjustment. If the common-mode impedance of the substrate trace, the common-mode impedance of the fan-out area, and the common-mode return loss of the substrate after the adjustment do not meet preset conditions, the process returns to the step of starting the substrate simulation model and readjusts until the common-mode impedance of the substrate trace, the common-mode impedance of the fan-out area, and the common-mode return loss of the substrate meet the preset conditions. The above solution adjusts the design value of the accompanying ground via and / or the core via by comparing the difference between the common-mode impedance of the fan-out area and the common-mode impedance of the substrate trace, and repeats the adjustment steps until the preset target is achieved. The solution is simple and easy to operate, and has a good effect in optimizing common-mode return loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0038] Figure 1 is a flow chart of a common mode return loss optimization method according to an embodiment of the present invention;

[0039] Figure 2 is a flow chart of another common mode return loss optimization method according to an embodiment of the present invention;

[0040] Figure 3 is a flow chart of another common mode return loss optimization method according to an embodiment of the present invention;

[0041] Figure 4 is a schematic diagram of differential mode impedance and common mode impedance curves according to an embodiment of the present invention;

[0042] Figure 5 2. This is a schematic diagram of ground hole distribution before the number of return ground holes is adjusted according to an embodiment of the present invention;

[0043] Figure 6 2. is a schematic diagram of ground hole distribution after the number of return ground holes is adjusted according to an embodiment of the present invention;

[0044] Figure 7 is a schematic diagram comparing common-mode return loss curves before and after adjusting the number of return ground holes according to an embodiment of the present invention;

[0045] Figure 8 2 is a schematic diagram comparing the distribution of core holes before and after adjusting the N / P spacing of the signal holes according to an embodiment of the present invention;

[0046] Figure 9 is a schematic diagram of a common mode return loss curve before adjusting the core hole N / P spacing according to an embodiment of the present invention;

[0047] Figure 10 is a schematic diagram of a common mode return loss curve after adjusting the core hole N / P spacing according to an embodiment of the present invention;

[0048] Figure 11 is a structural block diagram of a common mode return loss optimization device according to an embodiment of the present invention;

[0049] Figure 12 Schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0050] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0051] Common-mode return loss (CMRL) refers to the common-mode noise generated by the characteristics of current flow paths in circuit design. Common-mode return loss (CMRL) is a key metric for measuring common-mode signal reflection or loss during transmission, caused by factors such as capacitive coupling or electromagnetic coupling between signal lines and ground. It is defined as the absolute ratio of the power of the reflected wave to the incident wave during common-mode signal transmission.

[0052] SerDes (Serializer / Deserializer) is a mainstream high-speed time-division multiplexing (TDM) and point-to-point (P2P) serial communication technology. Its core function is to convert multiple low-speed parallel signals into high-speed serial signals for transmission and then restore the serial signals to low-speed parallel signals at the receiving end. In substrate SerDes circuits, common-mode return loss can cause signal interference and loss, affecting signal integrity and reliability, degrading signal quality, and ultimately affecting the overall performance of the substrate SerDes circuit.

[0053] According to an embodiment of the present invention, an embodiment of a common-mode return loss optimization method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0054] In this embodiment, a common mode return loss optimization method is provided, which can be used for desktop computers, notebook computers, etc. Figure 1 is a flow chart of a common mode return loss optimization method according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0055] Step S101: obtaining a substrate simulation model.

[0056] In the application scenario of this embodiment, the substrate can be a printed circuit board (PCB). The substrate simulation model is pre-built based on the substrate link, and the corresponding simulation software can be selected as needed to establish the substrate simulation model. The substrate link includes substrate routing and fan-out areas. The fan-out area is the BGA (Ball Grid Array, solder ball array package) area. Fan-out refers to the routing process from the BGA pad to the adjacent via. The BGA is used to make array solder balls at the bottom of the package substrate as the I / O (input / output) end of the circuit to interconnect with the printed circuit board. In the fan-out area of ​​the substrate, impedance discontinuities such as vias and solder balls are included. Impedance discontinuity refers to the phenomenon in which the impedance value in a transmission line, circuit or signal path suddenly changes due to certain factors (physical structure changes, such as changes in wire width, dielectric thickness or material non-uniformity; local capacitance and inductance changes, such as changes in insulation thickness and copper wire diameter; cable aging or defects). This phenomenon can have a significant impact on signal transmission, including signal reflection, energy attenuation, timing problems and electromagnetic interference.

[0057] Step S102 : starting the substrate simulation model to collect the common-mode impedance of the fan-out area and the common-mode impedance of the substrate traces.

[0058] Common-mode signals are signals of equal magnitude and direction acting simultaneously on two or more conductors. Common-mode impedance refers to the impedance presented to a common-mode signal in a circuit. Common-mode impedance is a key parameter that measures a circuit's ability to transmit common-mode signals and directly affects common-mode return loss. Higher common-mode impedance means a circuit's ability to attenuate common-mode signals, resulting in lower common-mode return loss.

[0059] When optimizing common-mode return loss, it's necessary to analyze the common-mode impedance of substrate traces and vias, solder balls, and other locations within the substrate's fan-out area. These impedance discontinuities should be optimized to reduce the common-mode impedance gap between the substrate traces and the fan-out area, improve the common-mode impedance continuity of the substrate link, and thus reduce common-mode return loss. The common-mode impedance of substrate traces is primarily affected by substrate material properties, trace geometry, and routing rules.

[0060] Specifically, a substrate simulation model is started to perform a simulation experiment to collect the common-mode impedance of the fan-out area and the common-mode impedance of the substrate traces.

[0061] Step S103 : comparing the common-mode impedance of the fan-out region with the common-mode impedance of the substrate traces to adjust the design value of the accompanying ground via and / or the design value of the core via in the substrate simulation model.

[0062] Since reducing the gap between the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces is the key to optimizing common-mode return loss in this embodiment, the gap between the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces can be compared, and the design values ​​of the accompanying ground vias and / or core vias in the fan-out region can be adjusted based on this gap, thereby adjusting the common-mode impedance of the fan-out region so that the common-mode impedance of the fan-out region approaches the common-mode impedance of the substrate traces. An accompanying ground via is a grounding via, typically used in place of a signal via. Accompanying ground vias optimize signal integrity by increasing ground connections, providing a signal return path and reducing electromagnetic interference. A core via is a hole that penetrates the core layer of a multi-layer substrate and is typically used to connect electrical connections between different layers. The accompanying ground via design value can include the number and arrangement of accompanying ground vias, and the core via design value can include the number and arrangement of core vias. The accompanying ground via design value and / or core via design value can be adjusted directly in the substrate simulation model as needed.

[0063] Step S104 , obtaining the substrate trace common-mode impedance, fan-out area common-mode impedance, and substrate common-mode return loss of the adjusted substrate simulation model.

[0064] After adjusting the design values ​​of the accompanying ground vias and / or core vias in the substrate simulation model, the common-mode impedance of the substrate traces and the common-mode impedance of the fan-out area change, and thus the common-mode return loss of the substrate. You can run a simulation experiment by starting the adjusted substrate simulation model to collect data on the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out area, and the common-mode return loss of the substrate.

[0065] Step S105 : If the substrate trace common-mode impedance, fan-out area common-mode impedance, and substrate common-mode return loss of the adjusted substrate simulation model do not meet preset conditions, the process returns to the step of starting the substrate simulation model.

[0066] The preset conditions can be set based on actual needs, for example, to ensure that the difference between the common-mode impedance of the substrate traces and the common-mode impedance of the fan-out area is within a preset range and that the substrate common-mode return loss is less than a preset threshold. Meeting the preset conditions indicates that the current common-mode return loss optimization is successful, and the resulting design values ​​for the accompanying ground vias and / or core vias are applied to subsequent substrate circuit designs. Failure to meet the preset conditions indicates that the current common-mode return loss optimization is unsuccessful, and the process returns to the step of initiating the substrate simulation model, i.e., looping through steps S102 to S105 until the adjusted common-mode impedance of the substrate traces, the common-mode impedance of the fan-out area, and the substrate common-mode return loss of the substrate simulation model meet the preset conditions.

[0067] The common-mode return loss optimization method provided in this embodiment first obtains a substrate simulation model pre-built based on a substrate link, then starts the substrate simulation model to perform a simulation operation to collect the common-mode impedance of the fan-out area and the common-mode impedance of the substrate traces. The common-mode impedance of the fan-out area is then compared with the common-mode impedance of the substrate traces, with the goal of reducing the difference between the common-mode impedance of the fan-out area and the common-mode impedance of the substrate traces. Based on the comparison result, the design values ​​of the accompanying ground vias and / or core vias in the substrate simulation model are adjusted, and the simulation operation is performed again to obtain the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out area, and the common-mode return loss of the substrate after the adjustment. If the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out area, and the common-mode return loss of the substrate after the adjustment do not meet preset conditions, the process returns to the step of starting the substrate simulation model and readjusts until the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out area, and the common-mode return loss of the substrate meet the preset conditions. The above solution adjusts the design value of the accompanying ground via and / or the core via by comparing the difference between the common-mode impedance of the fan-out area and the common-mode impedance of the substrate trace, and repeats the adjustment steps until the preset target is achieved. The solution is simple and easy to operate, and has a good effect in optimizing common-mode return loss.

[0068] In this embodiment, a common mode return loss optimization method is provided, which can be used for desktop computers, notebook computers, etc. Figure 2is a flow chart of a common mode return loss optimization method according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0069] Step S201: obtaining a substrate simulation model.

[0070] The substrate simulation model is pre-built based on a substrate link, which includes substrate traces and fan-out areas.

[0071] For details, please see Figure 1 Step S101 of the illustrated embodiment will not be described in detail here.

[0072] Step S202 : starting the substrate simulation model to collect the common-mode impedance of the fan-out area and the common-mode impedance of the substrate traces.

[0073] For details, please see Figure 1 Step S102 of the illustrated embodiment will not be described in detail here.

[0074] Step S203 : comparing the common-mode impedance of the fan-out region with the common-mode impedance of the substrate traces to adjust the design value of the accompanying ground via and / or the design value of the core via in the substrate simulation model.

[0075] Optionally, based on the comparison between the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces, the design value of the accompanying ground holes is individually adjusted. The accompanying ground hole design value includes the number of accompanying ground holes and the spacing between accompanying ground holes. The spacing between accompanying ground holes is the distance between two adjacent accompanying ground holes. Specifically, if the common-mode impedance of the fan-out region is greater than the common-mode impedance of the substrate traces, the number of accompanying ground holes in the substrate simulation model is increased; if the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, the number of accompanying ground holes in the substrate simulation model is reduced. Alternatively, if the common-mode impedance of the fan-out region is greater than the common-mode impedance of the substrate traces, the spacing between accompanying ground holes in the substrate simulation model is increased; if the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, the spacing between accompanying ground holes in the substrate simulation model is reduced. Alternatively, if the common-mode impedance of the fan-out region is greater than the common-mode impedance of the substrate traces, the number and spacing of accompanying ground holes in the substrate simulation model are increased; if the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, the number and spacing of accompanying ground holes in the substrate simulation model are reduced. When adjusting the number or spacing of accompanying ground holes, an adjustment threshold may be set according to experience or historical experimental data, and adjustments may be made gradually according to the adjustment threshold each time, for example, one accompanying ground hole may be added each time, or 100 μm may be added each time.

[0076] Optionally, the core hole design value is adjusted separately based on the comparison result between the common-mode impedance of the fan-out area and the common-mode impedance of the substrate trace. Specifically, if the common-mode impedance of the fan-out area is greater than the common-mode impedance of the substrate trace, the core hole N / P spacing in the substrate simulation model is increased; if the common-mode impedance of the fan-out area is less than the common-mode impedance of the substrate trace, the core hole N / P spacing in the substrate simulation model is reduced. When adjusting the core hole N / P spacing, an adjustment threshold can be set, and the adjustment is gradually made according to the adjustment threshold each time, for example, increasing by 100um each time. Among them, N (negative) and P (positive) are the two poles of the differential signal. The differential signal is transmitted by two transmission lines, one is the N line and the other is the P line. Therefore, the core hole is divided into N holes and P holes. The core hole N / P spacing refers to the pitch between a pair of N holes and P holes, that is, the distance between the center of the N hole and the center of the P hole.

[0077] Optionally, based on the comparison between the common-mode impedance of the fan-out region and the common-mode impedance of the substrate traces, the design values ​​of the accompanying ground vias and / or the core vias are adjusted simultaneously. Specifically, if the common-mode impedance of the fan-out region is greater than the common-mode impedance of the substrate traces, the number and / or spacing of the accompanying ground vias and the N / P spacing of the core vias in the substrate simulation model are increased; if the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, the number and / or spacing of the accompanying ground vias and the N / P spacing of the core vias in the substrate simulation model are reduced.

[0078] Step S204 , obtaining the substrate trace common-mode impedance, fan-out area common-mode impedance, and substrate common-mode return loss of the adjusted substrate simulation model.

[0079] For details, please see Figure 1 Step S104 of the illustrated embodiment will not be described in detail here.

[0080] Step S205 : If the substrate trace common-mode impedance, fan-out area common-mode impedance, and substrate common-mode return loss of the adjusted substrate simulation model do not meet the preset conditions, the process returns to the step of starting the substrate simulation model.

[0081] Specifically, the above step S205 includes:

[0082] Step S2051 , calculating the difference between the common-mode impedance of the substrate traces and the common-mode impedance of the fan-out region in the adjusted substrate simulation model.

[0083] Since the adjustment goal of this embodiment is to make the common-mode impedance of the substrate traces and the common-mode impedance of the fan-out area as equal as possible, the difference between the common-mode impedance of the substrate traces and the common-mode impedance of the fan-out area of ​​the adjusted substrate simulation model is first calculated, and the success of this adjustment is determined based on the difference.

[0084] Step S2052 : When the difference exceeds the first preset threshold and / or the substrate common mode return loss exceeds the second preset threshold, the process returns to the step of starting the substrate simulation model.

[0085] Because it's difficult to completely equalize the common-mode impedance of the substrate traces and the common-mode impedance of the fan-out area in practical applications, this embodiment sets the preset condition as follows: the difference between the common-mode impedance of the substrate traces and the common-mode impedance of the fan-out area is less than a first preset threshold and / or the substrate common-mode return loss does not exceed a second preset threshold. In other words, the difference between the common-mode impedance of the substrate traces and the common-mode impedance of the fan-out area can be used as the adjustment target, the final common-mode return loss can be used as the adjustment target, or both can be used as adjustment targets simultaneously. The first preset threshold is the maximum difference between the common-mode impedance of the substrate traces and the common-mode impedance of the fan-out area, while the second preset threshold is the maximum value of the common-mode return loss, while the substrate circuitry is guaranteed to function properly. The first and second preset thresholds can be determined based on experience or historical experimental data.

[0086] Optionally, simulation software can be used to record the change curves of various parameters during the adjustment process, and adjustments can be made based on the trends of the change curves. Specifically, the design values ​​of the accompanying ground holes and / or the core hole design values ​​in the substrate simulation model are gradually adjusted, and the substrate routing common-mode impedance change curve, the fan-out area common-mode impedance change curve, and the common-mode return loss change curve of the substrate simulation model are obtained through the simulation software. The substrate routing common-mode impedance change curve is used to indicate the change of the substrate routing common-mode impedance over time. The fan-out area common-mode impedance change curve is used to indicate the change of the fan-out area common-mode impedance over time. The common-mode return loss change curve is used to indicate the change of the substrate common-mode return loss over time. Then, based on the trends of the substrate routing common-mode impedance change curve, the fan-out area common-mode impedance change curve, and the common-mode return loss change curve of the substrate simulation model, an analysis is performed to determine the optimal design values ​​of the accompanying ground holes and / or the optimal design values ​​of the core hole so that the substrate routing common-mode impedance, the fan-out area common-mode impedance, and the substrate common-mode return loss meet preset conditions.

[0087] The common-mode return loss optimization method provided in this embodiment first obtains a substrate simulation model pre-built based on a substrate link, then starts the substrate simulation model to perform a simulation operation to collect the common-mode impedance of the fan-out area and the common-mode impedance of the substrate traces. The common-mode impedance of the fan-out area is then compared with the common-mode impedance of the substrate traces, with the goal of reducing the difference between the common-mode impedance of the fan-out area and the common-mode impedance of the substrate traces. Based on the comparison result, the design values ​​of the accompanying ground vias and / or core vias in the substrate simulation model are adjusted, and the simulation operation is performed again to obtain the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out area, and the common-mode return loss of the substrate after the adjustment. If the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out area, and the common-mode return loss of the substrate after the adjustment do not meet preset conditions, the process returns to the step of starting the substrate simulation model and readjusts until the common-mode impedance of the substrate traces, the common-mode impedance of the fan-out area, and the common-mode return loss of the substrate meet the preset conditions. The above solution adjusts the design value of the accompanying ground via and / or the core via by comparing the difference between the common-mode impedance of the fan-out area and the common-mode impedance of the substrate trace, and repeats the adjustment steps until the preset target is achieved. The solution is simple and easy to operate, and has a good effect in optimizing common-mode return loss.

[0088] Furthermore, this embodiment provides a solution for adjusting the design value of the accompanying ground holes by adjusting the number and / or spacing of the accompanying ground holes, and adjusting the design value of the core hole by adjusting the N / P spacing of the core hole, further refining the solution, improving the operability and selectivity of the solution, and thereby improving the common-mode return loss optimization effect.

[0089] Furthermore, this embodiment provides a solution for auxiliary adjustment by establishing the common-mode impedance change curve of the substrate routing, the common-mode impedance change curve of the fan-out area, and the common-mode return loss change curve of the substrate simulation model. This solution can intuitively reflect the parameter changes before and after the adjustment, improve the accuracy and clarity of the solution, and thereby improve the common-mode return loss optimization effect.

[0090] As one or more specific application examples of the embodiments of the present invention, the optimal implementation scheme or the solution that the inventor most wants to embody is described below in combination with specific application scenarios.

[0091] Figure 3It is a flow chart of the common-mode return loss optimization method according to an embodiment of the present invention. In this embodiment, a 3D finite element simulation tool (such as HFSS, etc.) is used to establish a substrate simulation model for the substrate SerDes circuit, and the common-mode impedance of the fan-out area is measured by TDR (Time Domain Reflectometry, a technology for measuring impedance changes during signal transmission). The simulation operation is performed multiple times to obtain the common-mode impedance curve of the substrate trace, the common-mode impedance change curve of the fan-out area, and the common-mode return loss change curve. Based on the common-mode impedance curve of the substrate trace, the common-mode impedance change curve of the fan-out area, and the common-mode return loss change curve, the optimal number of return ground holes (accompanying ground holes) and / or the optimal value of increasing the N / P spacing of the signal hole (core hole) are determined. After each simulation, the common-mode impedance of the substrate trace is first analyzed based on the common-mode impedance curve of the substrate trace, and then the common-mode impedance analysis of the fan-out area is performed to compare the difference between the common-mode impedance of the fan-out area and the common-mode impedance of the substrate trace. When the common-mode impedance of the substrate traces is greater than the common-mode impedance of the fan-out area, reduce the number of return ground vias (accompanying ground vias) and / or reduce the N / P spacing of the signal vias (core vias); when the common-mode impedance of the substrate traces is less than the common-mode impedance of the fan-out area, increase the number of return ground vias (accompanying ground vias) and / or increase the N / P spacing of the signal vias (core vias).

[0092] Figure 4 Schematic diagram of differential mode impedance and common mode impedance curve according to an embodiment of the present invention. Figure 4 As shown, the vertical axis is the impedance value and the horizontal axis is the time value. Since the simulation model includes the routing and fan-out areas, the simulation results also include the routing and fan-out areas. The red curve is the differential impedance curve, and the green curve is the common-mode impedance curve. From the common-mode impedance curve, we can see the change trend of the common-mode impedance of the substrate routing and the change trend of the common-mode impedance of the fan-out area.

[0093] Figure 5 is a schematic diagram of ground hole distribution before the number of return ground holes is adjusted according to an embodiment of the present invention, Figure 6 is a schematic diagram of the distribution of ground holes after the number of return ground holes is adjusted according to an embodiment of the present invention, Figure 7 : is a schematic diagram comparing the common mode return loss curves before and after adjusting the number of return holes according to an embodiment of the present invention. Figure 5 and Figure 6 As shown in Figure 1, 8 return holes are added after the common mode return loss is optimized. Figure 7 As shown in the figure, the horizontal axis is frequency (GHz), the vertical axis is amplitude (dB), the green curve is the common-mode return loss curve before common-mode return loss optimization, and the red curve is the common-mode return loss curve after common-mode return loss optimization. It can be seen that after adding 8 return ground holes, the common-mode return loss is reduced from -6.06dB to -14.73dB when the signal frequency is 28GHz.

[0094] Figure 8 3 is a schematic diagram comparing the distribution of core holes before and after adjusting the N / P spacing of the signal holes according to an embodiment of the present invention. Figure 9 2 is a schematic diagram of a common mode return loss curve before adjusting the core hole N / P spacing according to an embodiment of the present invention. Figure 10 : is a schematic diagram of the common mode return loss curve after adjusting the core hole N / P spacing according to an embodiment of the present invention. Figure 8 As shown in the figure, after the common mode return loss is optimized, the signal hole N / P spacing is increased from 400um to 600um. Figure 9 and Figure 10 As shown in the figure, the horizontal axis is frequency (GHz) and the vertical axis is amplitude (dB). The figure contains multiple pairs of differential lines, and the curves of the same color correspond to each other. It can be seen that after adjusting the signal hole N / P spacing from 400um to 600um, the common mode return loss is reduced from -5dB to -11.3dB when the signal frequency is 28GHz.

[0095] This embodiment also provides a common-mode return loss optimization device for implementing the above-mentioned embodiments and preferred implementations. Details already described will not be repeated. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

[0096] This embodiment provides a common mode return loss optimization device, such as Figure 11 As shown, including:

[0097] The model acquisition module 1101 is used to acquire a substrate simulation model; the substrate simulation model is pre-built based on a substrate link; the substrate link includes substrate routing and fan-out areas;

[0098] Impedance acquisition module 1102, used to start the substrate simulation model and collect the common mode impedance of the fan-out area and the common mode impedance of the substrate trace;

[0099] An adjustment module 1103 is configured to compare the common-mode impedance of the fan-out region with the common-mode impedance of the substrate traces to adjust a design value of the accompanying ground via and / or a design value of the core via in the substrate simulation model;

[0100] The parameter acquisition module 1104 is used to obtain the substrate trace common mode impedance, fan-out area common mode impedance and substrate common mode return loss of the adjusted substrate simulation model;

[0101] The judgment module 1105 is configured to return to the step of starting the substrate simulation model if the substrate trace common mode impedance, fan-out area common mode impedance, and substrate common mode return loss of the adjusted substrate simulation model do not meet preset conditions.

[0102] In an optional embodiment, the adjustment module is further configured to:

[0103] If the common-mode impedance of the fan-out area is greater than the common-mode impedance of the substrate trace, increase the number of accompanying ground holes in the substrate simulation model;

[0104] If the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, the number of accompanying ground holes in the substrate simulation model is reduced.

[0105] In an optional embodiment, the adjustment module is further configured to:

[0106] If the common-mode impedance of the fan-out area is greater than the common-mode impedance of the substrate trace, increase the core hole N / P spacing in the substrate simulation model;

[0107] If the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, the core hole N / P spacing in the substrate simulation model is reduced.

[0108] In an optional embodiment, the adjustment module is further configured to:

[0109] If the common-mode impedance of the fan-out area is greater than the common-mode impedance of the substrate trace, increase the number of accompanying ground holes and the core hole N / P spacing in the substrate simulation model;

[0110] If the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, the number of accompanying ground vias and the core via N / P spacing in the substrate simulation model are reduced.

[0111] In an optional implementation, the judgment module is further configured to:

[0112] Calculate the difference between the common-mode impedance of the substrate traces and the common-mode impedance of the fan-out area of ​​the adjusted substrate simulation model;

[0113] When the difference exceeds a preset threshold and / or the common mode return loss of the substrate exceeds a preset threshold, the method returns to the step of starting the substrate simulation model.

[0114] In an optional embodiment, the device further includes a curve analysis module, which is used to:

[0115] Gradually adjusting the accompanying ground hole design value and / or the core hole design value in the substrate simulation model to obtain a substrate trace common-mode impedance change curve, a fan-out area common-mode impedance change curve, and a common-mode return loss change curve of the substrate simulation model;

[0116] Based on the common-mode impedance change curve of the substrate trace, the common-mode impedance change curve of the fan-out area, and the common-mode return loss change curve of the substrate simulation model, the optimal design value of the accompanying ground hole and / or the optimal design value of the core hole are determined so that the common-mode impedance of the substrate trace, the common-mode impedance of the fan-out area, and the common-mode return loss of the substrate meet the preset conditions.

[0117] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0118] The common-mode return loss optimization device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0119] The embodiment of the present invention also provides a computer device having the above Figure 11 The common-mode return loss optimization device is shown.

[0120] See also Figure 12 , Figure 12 is a structural diagram of a computer device provided by an optional embodiment of the present invention, such as Figure 12 As shown, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components utilize different buses to communicate with each other and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in the memory or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Equally, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 12 A processor 10 is taken as an example.

[0121] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0122] The memory 20 stores instructions that can be executed by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0123] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0124] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0125] The computer device further includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 12 The bus connection is taken as an example.

[0126] The input device 30 can receive input digital or character information and generate key signal input related to user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a trackpad, a touch pad, an indicator stick, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 can include a display device, an auxiliary lighting device (e.g., an LED), and a tactile feedback device (e.g., a vibration motor). The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display, and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0127] The embodiment of the present invention also provides a computer-readable storage medium. The above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0128] A portion of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the form in which the computer program instruction exists in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc. Accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium that can be accessed by the computer.

[0129] Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations shall fall within the scope of protection of the present invention.

Claims

1. A common mode return loss optimization method, characterized in that: The method comprises: Obtaining a substrate simulation model; the substrate simulation model is pre-built based on a substrate link; the substrate link includes a substrate trace and a fan-out area; Starting the substrate simulation model to collect the common-mode impedance of the fan-out area and the common-mode impedance of the substrate traces; Comparing the common-mode impedance of the fan-out region with the common-mode impedance of the substrate traces to adjust a design value of a companion ground hole and / or a design value of a core hole in the substrate simulation model; Obtain the substrate trace common-mode impedance, fan-out area common-mode impedance, and substrate common-mode return loss of the adjusted substrate simulation model; If the substrate trace common-mode impedance, the fan-out area common-mode impedance, and the substrate common-mode return loss of the adjusted substrate simulation model do not meet the preset conditions, the process returns to the step of starting the substrate simulation model.

2. The method according to claim 1, characterized in that The comparing the common-mode impedance of the fan-out region with the common-mode impedance of the substrate traces to adjust the accompanying ground hole design value and / or the core hole design value in the substrate simulation model includes: If the common-mode impedance of the fan-out area is greater than the common-mode impedance of the substrate traces, increasing the number of accompanying ground holes in the substrate simulation model; If the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, the number of accompanying ground holes in the substrate simulation model is reduced.

3. The method according to claim 2, characterized in that The comparing the common-mode impedance of the fan-out region with the common-mode impedance of the substrate traces to adjust the accompanying ground hole design value and / or the core hole design value in the substrate simulation model further includes: If the common-mode impedance of the fan-out region is greater than the common-mode impedance of the substrate traces, increasing the core hole N / P spacing in the substrate simulation model; If the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, the core hole N / P spacing in the substrate simulation model is reduced.

4. The method according to claim 3, characterized in that The comparing the common-mode impedance of the fan-out region with the common-mode impedance of the substrate traces to adjust the accompanying ground hole design value and / or the core hole design value in the substrate simulation model further includes: If the common-mode impedance of the fan-out area is greater than the common-mode impedance of the substrate traces, increase the number of accompanying ground holes and the core hole N / P spacing in the substrate simulation model; If the common-mode impedance of the fan-out region is less than the common-mode impedance of the substrate traces, the number of accompanying ground holes and the core hole N / P spacing in the substrate simulation model are reduced.

5. The method according to any one of claims 1 to 4, characterized in that: If the substrate trace common-mode impedance, the fan-out area common-mode impedance, and the substrate common-mode return loss of the adjusted substrate simulation model do not meet the preset conditions, returning to the step of starting the substrate simulation model includes: Calculate the difference between the common-mode impedance of the substrate traces and the common-mode impedance of the fan-out area of ​​the adjusted substrate simulation model; When the difference exceeds a first preset threshold and / or the substrate common mode return loss exceeds a second preset threshold, the method returns to the step of starting the substrate simulation model.

6. The method according to claim 5, characterized in that The method further comprises: Gradually adjusting the accompanying ground hole design value and / or the core hole design value in the substrate simulation model to obtain a substrate trace common-mode impedance change curve, a fan-out area common-mode impedance change curve, and a common-mode return loss change curve of the substrate simulation model; Based on the common-mode impedance change curve of the substrate trace, the common-mode impedance change curve of the fan-out area, and the common-mode return loss change curve of the substrate simulation model, the optimal design value of the accompanying ground hole and / or the optimal design value of the core hole are determined so that the common-mode impedance of the substrate trace, the common-mode impedance of the fan-out area, and the common-mode return loss of the substrate meet preset conditions.

7. A common mode return loss optimization device, characterized in that: The device comprises: A model acquisition module is used to acquire a substrate simulation model; the substrate simulation model is pre-built based on a substrate link; the substrate link includes a substrate routing and a fan-out area; An impedance acquisition module, configured to start the substrate simulation model and acquire the common-mode impedance of the fan-out area and the common-mode impedance of the substrate traces; an adjustment module, configured to compare the common-mode impedance of the fan-out region with the common-mode impedance of the substrate traces to adjust a design value of the accompanying ground via and / or a design value of the core via in the substrate simulation model; A parameter acquisition module is used to obtain the substrate trace common-mode impedance, fan-out area common-mode impedance, and substrate common-mode return loss of the adjusted substrate simulation model; The judgment module is configured to return to the step of starting the substrate simulation model if the substrate trace common mode impedance, the fan-out area common mode impedance, and the substrate common mode return loss of the adjusted substrate simulation model do not meet preset conditions.

8. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the common-mode return loss optimization method according to any one of claims 1 to 6 by executing the computer instructions.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the common-mode return loss optimization method according to any one of claims 1 to 6.

10. A computer program product, characterized in that The method comprises computer instructions, wherein the computer instructions are used to cause a computer to execute the common mode return loss optimization method according to any one of claims 1 to 6.

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