Association memory architecture and method, storage medium and program product

Abstract

The invention relates to the technical field of artificial neural networks, in particular to an associative memory architecture and method, a storage medium and a program product.The architecture comprises a reserve pool layer, the reserve pool layer comprises a plurality of reserve pool networks, the reserve pool networks use a plurality of randomly-connected neurons to process input data, and the number of the neurons is larger than the number of the reserve pool networks; state vector voltage is obtained through a high-dimensional mapping effect; the output layer is used for generating a target addressing signal according to the state vector voltage, pre-trained weight vectors are stored in the output layer, and the target addressing signal is determined through the weight vectors and the state vector voltage; and the reading head is used for reading the associative memory position coding target output value corresponding to the memristor array according to the target addressing signal so as to realize the continuous associative memory function of the analog domain. Therefore, the problems that associative memory cannot be realized in an analog domain, and potential cannot be brought into full play due to limitation of system frequency and von Noiemann bottleneck and the like in related technologies are solved.

Description

Technical Field

[0001] The present application relates to the field of artificial neural network technology, and in particular to an associative memory architecture, method, storage medium and program product. Background Art

[0002] Associative memory is one of the fundamental thinking abilities of intelligent organisms. This ability requires long-term memory and a certain level of computational power, enabling organisms to access previously stored long-term memories for computation based on received information during the thinking process. Functionally, associative memory is often considered content-addressable storage in computers, meaning that data items can be accessed by their content rather than by predefined addresses. In the field of artificial intelligence, associative memory enables machines to better understand and infer new information by learning and remembering past experiences and information, which helps improve machine performance in tasks such as natural language processing, image recognition, and recommendation systems.

[0003] Related art methods for implementing associative memory include Hopfield (Hopfield Network), LSTM (Long Short-Term Memory Network), RC (Reservoir Computing), NTM (Neural Turing Machine), and methods based on traditional machine learning algorithms such as K-nearest neighbor and support vector machines, as well as some deep learning models such as attention mechanisms and Transformers. However, these methods are based on processing binary discrete data, which means they are concentrated in the digital domain. Limited by system frequency and the von Neumann bottleneck, they cannot fully realize their potential. Furthermore, brain-inspired computing aims to mimic the brain's energy-efficient computing processes. Associative memory, a fundamental function of the brain, is a key component in achieving brain-inspired computing. However, because the brain is a dynamic and complex network operating in the analog domain, related art associative memory methods are concentrated in the digital domain and cannot be implemented in the analog domain. Summary of the Invention

[0004] The present application provides an associative memory architecture, method, storage medium and program product to solve the problems that related technologies cannot realize associative memory in the analog domain and are limited by system frequency and von Neumann bottleneck and cannot fully realize the potential.

[0005] The first aspect of the present application provides an associative memory architecture, including: a reservoir layer, wherein the reservoir layer includes multiple reservoir networks, the reservoir network uses multiple randomly connected neurons to process input data, and obtains a state vector voltage through high-dimensional mapping; an output layer, generates a target addressing signal according to the state vector voltage, wherein the output layer stores a pre-trained weight vector, and uses the weight vector and the state vector voltage to determine the target addressing signal; a read head, reads the associative memory position encoding target output value corresponding to the memristor array according to the target addressing signal, so as to realize the continuous associative memory function in the analog domain.

[0006] Optionally, the implementation method of the reservoir layer includes at least one of a time-delay coupling method, a parallel dynamic device method, and a rotating neuron reservoir.

[0007] Optionally, the input data and the output value are associated data in a one-to-one correspondence.

[0008] Optionally, the weight vector of the output layer is pre-trained using a ridge regression algorithm, wherein the training process includes: obtaining a training data set, wherein the training data set contains multiple input data and corresponding output values; inputting each input data into a reservoir layer, and the reservoir layer outputs a state vector voltage; setting the associative memory position code of the output value corresponding to each input data in the training data set in the memristor array; using the associative memory position code as the target value of the ridge regression algorithm; and calculating the weight vector based on the state vector voltage, the target value, and the ridge regression algorithm.

[0009] Optionally, there are multiple read heads, each of which is responsible for reading the associative memory position encoding output values ​​of different arrays in the memristor array.

[0010] The second aspect of the present application provides an associative memory method, which is implemented based on the associative memory architecture of the above embodiment and includes the following steps: obtaining target input data; inputting the target input data into the associative memory architecture, and the associative memory architecture outputs a target output value corresponding to the target input data, wherein the associative memory architecture includes a reservoir layer, an output layer and a read head.

[0011] Optionally, after inputting the target input data into the associative memory architecture, it also includes: obtaining the data length of the target output value; and inputting an input sequence equal to the data length into the associative memory architecture.

[0012] Optionally, the output layer stores a pre-trained weight vector, and the weight vector of the output layer is pre-trained using a ridge regression algorithm, wherein the training process includes: obtaining a training data set, wherein the training data set contains multiple input data and corresponding output values; inputting each input data into a reservoir layer, and the reservoir layer outputs a state vector voltage; setting the associative memory position encoding of the output value corresponding to each input data in the training data set in the memristor array; using the associative memory position encoding as the target value of the ridge regression algorithm; and calculating the weight vector based on the state vector voltage, the target value, and the ridge regression algorithm.

[0013] The third aspect of the present application provides a computer-readable storage medium on which a computer program or instruction is stored. The computer program or instruction is executed by a processor to perform the associative memory method as described in the above embodiment.

[0014] The fourth embodiment of the present application provides a computer program product, including a computer program or instructions, which, when executed, implements the associative memory method as described in the above embodiment.

[0015] Therefore, this application has at least the following beneficial effects:

[0016] The embodiment of the present application constructs an associative memory architecture, including a reservoir layer, an output layer, and a read head. The reservoir layer includes multiple reservoir networks, and processes input data through randomly connected neurons. A state vector voltage is obtained through high-dimensional mapping. The output layer determines the target addressing signal based on the state vector voltage and the pre-trained weight vector stored in itself. The read head reads the target output value encoded in the corresponding associative memory position in the memristor array according to the target addressing signal, that is, the associative memory content corresponding to the input data, thereby realizing continuous associative memory function in the analog domain. It has highly biomimetic characteristics and can simulate the functions, signal transmission, and calculation processes of the brain. In addition, during the associative memory implementation process, data transmission and calculation processes are in the form of analog signals. The calculation process does not require digital-to-analog conversion, which improves the calculation processing speed, reduces power consumption and calculation, and can fully realize the potential of the technology itself for realizing associative memory. Thus, it solves the technical problems that the related technology cannot realize associative memory in the analog domain and is limited by system frequency and von Neumann bottleneck, and cannot fully realize its potential.

[0017] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0019] Figure 1 A schematic diagram of an associative memory architecture provided according to an embodiment of the present application;

[0020] Figure 2 A schematic diagram of an associative memory architecture provided according to an embodiment of the present application;

[0021] Figure 3 A flowchart of an associative memory method provided according to an embodiment of the present application;

[0022] Figure 4 A flowchart of an associative memory implementation according to an embodiment of the present application;

[0023] Figure 5 Schematic diagram of associative memory input and addressing signals provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0024] The following describes in detail embodiments of the present application, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0025] The associative memory architecture, method, storage medium and program product of the embodiments of the present application are described below with reference to the accompanying drawings. In response to the problem that the associative memory methods in the related art mentioned in the above background technology are concentrated in the digital domain and are based on the processing of binary discrete data, which is limited by the system frequency and the von Neumann bottleneck and cannot fully realize its potential, the present application provides an associative memory architecture, in which the architecture includes a reservoir layer, an output layer and a read head. The reservoir layer includes multiple reservoir networks and processes the input data through randomly connected neurons. The state vector voltage is obtained through high-dimensional mapping. The output layer determines the target addressing signal based on the state vector voltage and the pre-trained weight vector stored in itself. The read head reads the target output value encoded in the corresponding associative memory position in the memristor array according to the target addressing signal, that is, the associative memory content corresponding to the input data, thereby realizing continuous associative memory function in the analog domain. It has highly biomimetic characteristics and can simulate the functions, signal transmission, calculation and other processes of the brain. In addition, in the process of associative memory implementation, the data transmission and calculation process are in the form of analog signals. The calculation process does not require digital-to-analog conversion, which improves the calculation processing speed, reduces power consumption and calculation, and can fully realize the potential of the technology itself for realizing associative memory. This solves the problems that related technologies cannot realize associative memory in the analog domain, and are limited by system frequency and von Neumann bottlenecks and cannot fully realize their potential.

[0026] Specifically, Figure 1A schematic diagram of an associative memory architecture provided in an embodiment of the present application.

[0027] like Figure 1 As shown, the associative memory architecture 10 includes: a reservoir layer 11, an output layer 12 and a read head 13.

[0028] Among them, the reservoir layer 11 includes multiple reservoir networks, which use multiple randomly connected neurons to process input data and obtain a state vector voltage through high-dimensional mapping; the output layer 12 generates a target addressing signal based on the state vector voltage, wherein the output layer 12 stores a pre-trained weight vector, and uses the weight vector and the state vector voltage to determine the target addressing signal; the reading head 13 reads the target output value of the associative memory position encoding corresponding to the memristor array according to the target addressing signal to realize the continuous associative memory function in the analog domain.

[0029] It can be understood that the embodiment of the present application constructs an associative memory architecture 10, including a reservoir layer 11, an output layer 12 and a read head 13. The reservoir layer 11 includes multiple reservoir networks, and processes the input data through randomly connected neurons, and obtains the state vector voltage through high-dimensional mapping. The output layer 12 determines the target addressing signal according to the state vector voltage and the pre-trained weight vector stored in itself. The read head 13 reads the target output value encoded at the corresponding associative memory position in the memristor array according to the target addressing signal, that is, the associative memory content corresponding to the input data, thereby realizing continuous associative memory function in the analog domain, with highly bionic characteristics, and can simulate the functions, signal transmission, calculation and other processes of the brain. In the process of associative memory implementation, data transmission and calculation processes are in the form of analog signals. The calculation process does not require digital-to-analog conversion, which improves the calculation processing speed, reduces power consumption and calculation, and thus can give full play to the potential of the technology itself for realizing associative memory.

[0030] The reservoir layer 11 of the embodiment of the present application is implemented by physical reservoir computing, which is the core of the associative memory architecture and plays the role of processing input and calculating addressing signals. Among them, reservoir computing is a special RNN (Recurrent Neural Network) computing paradigm, which is mainly used to process time series data. The core feature of this method is to use a large, randomly connected neural network (called a reservoir) to process input information, and only train the weights of the output layer. Reservoir computing provides an efficient and flexible method for processing time series data. It can be used as an effective alternative to traditional RNN in some applications, especially in scenarios where computing resources are limited or fast training is required.

[0031] In addition, it should be noted that the associative memory architecture 10 of the embodiment of the present application is implemented based on electronic components.

[0032] In an embodiment of the present application, the implementation method of the reservoir layer 11 includes at least one of a time-delay coupling method, a parallel dynamic device method, and a rotating neuron reservoir.

[0033] In the embodiment of the present application, input data and output values ​​are associated data in a one-to-one correspondence.

[0034] For example, if the input data is A1, the corresponding associative memory content is B1. When the input data is A1, the corresponding output value is B1.

[0035] In the embodiment of the present application, there are multiple reading heads 13, and each reading head 13 is responsible for reading the associative memory position encoding output value of a different array in the memristor array.

[0036] It can be understood that there are multiple read heads 13 in the embodiment of the present application, and each read head 13 is responsible for a different array in the memristor array, that is, each read head 13 is responsible for reading the associative memory position encoding output value stored in a different array in the memristor array. The input of the read head 13 is the analog signal output by the memristor array, and the read head changes its addressing position according to the analog signal.

[0037] For example, read head 1 is responsible for the contents of columns 1 to 20 in the memristor array, read head 2 is responsible for columns 21 to 40 in the memristor array, and so on for other read heads.

[0038] In an embodiment of the present application, the weight vector of the output layer 12 is pre-trained using a ridge regression algorithm, wherein the training process includes: obtaining a training data set, wherein the training data set contains multiple input data and corresponding output values; inputting each input data into the reservoir layer, and the reservoir layer 11 outputs a state vector voltage; setting the associative memory position code of the output value corresponding to each input data in the training data set in the memristor array; using the associative memory position code as the target value of the ridge regression algorithm; and calculating the weight vector based on the state vector voltage, the target value and the ridge regression algorithm.

[0039] It can be understood that the embodiment of the present application can use the ridge regression algorithm to train the weight vector of the output layer 12 by inputting the input data in the training data set into the reservoir layer 11, the reservoir layer 11 outputs the state vector voltage, and sets the output value corresponding to the input data in the associative memory position code in the memristor array, and uses the associative memory position code as the target value of the ridge regression algorithm, and calculates the weight vector based on the state vector voltage, the target value and the ridge regression algorithm.

[0040] The specific training process is as follows: first, the generated input data is input into the reservoir layer 11 in sequence. After the data input is completed, 1 (i.e., the input sequence) of the same length as the associative memory length M is input into the reservoir to obtain a state vector of N rows and M columns. Then, the address position of the memory content corresponding to the input data in the memristor array is manually set to the target value of the ridge regression algorithm. For example, the associative memory content corresponding to the first input data is in the 1st to Mth columns in the memristor array, then the target value of the N-row and M-column vector in the ridge regression algorithm is a natural number that increases from 1 to M in sequence. Assuming there is 1 read head, the ridge regression algorithm can obtain a weight vector of length N, and then write the weight vector into the output layer memristor. For multiple read heads, the target output value is encoded according to the associative memory position corresponding to each read head.

[0041] In addition, it should be noted that the input sequence of the embodiment of the present application may not necessarily be 1, it can be an arbitrary pattern, and the entire architecture is a continuous architecture. When the architecture runs to the "output addressing signal", since the reserve pool network has memory capabilities, it can retain past information, such as A3 information (i.e., input data). Therefore, the address of B3 information corresponding to A3 information (i.e., associative memory information) can be calculated and generated by this memory capability, but this information will weaken over time. At this time, in order to be able to read the A3 information in the memory normally, the input port also needs to give a signal (i.e., input sequence). If 0 is given, most of the operations in it will become 0, resulting in bad results. Giving 1 can keep the reserve pool network active.

[0042] The associative memory architecture of the present application is described below through a specific embodiment. The physical reservoir computing based on electronic components is used as the computing network, and the memristor array is used as the memory. That is, the dynamic neural network (physical reservoir computing) and memristor are used to realize the continuous associative memory function of the analog domain. It can provide an implementation method of associative memory for analog domain neuromorphic computing, which has strong scalability. The principle is as follows: Figure 2 shown.

[0043] Since the functions of the reserve pool computing network can be directly implemented at the physical level by utilizing the dynamic characteristics of the physical system, combined with the output layer based on non-volatile memristors, efficient full-analog neural network computing can be achieved. Therefore, the embodiment of the present application constructs an associative memory architecture to implement associative memory in the analog domain, such as Figure 2As shown, a physical reservoir network with K neurons (n) receives K continuous inputs. Physical reservoir implementation methods include, but are not limited to, time-delay coupling, parallel dynamic device methods, and rotating neuron reservoirs, among other commonly used reservoir layer implementation methods and architectures. Due to the high-dimensional mapping effect of the reservoir layer, a state vector of length N = K * n is generated. This state vector, in the form of a voltage, serves as the reservoir layer's output. This output passes through an output layer based on non-volatile memristors, generating an addressing signal corresponding to the input. Each addressing signal controls a read head, indexing and activating the corresponding position in a memristor array. The output of the memristor array retrieves the information pre-stored in the corresponding column of the memristor array, i.e., the contents of the associative memory.

[0044] According to the associative memory architecture proposed in the embodiment of the present application, it includes a reservoir layer, an output layer and a read head. The reservoir layer includes multiple reservoir networks, and processes the input data through randomly connected neurons. The state vector voltage is obtained through high-dimensional mapping. The output layer determines the target addressing signal according to the state vector voltage and the pre-trained weight vector stored in itself. The read head reads the target output value encoded at the corresponding associative memory position in the memristor array according to the target addressing signal, that is, the associative memory content corresponding to the input data, thereby realizing continuous associative memory function in the analog domain. It has a highly bionic feature and can simulate the functions, signal transmission, calculation and other processes of the brain. In addition, in the process of associative memory implementation, data transmission and calculation processes are in the form of analog signals. The calculation process does not require digital-to-analog conversion, which improves the calculation processing speed and reduces power consumption and calculation.

[0045] Next, the associative memory method proposed according to the embodiment of the present application is described with reference to the accompanying drawings.

[0046] Figure 3 It is a flow chart of the associative memory method of an embodiment of the present application.

[0047] like Figure 3 As shown, the associative memory method is implemented based on the above-mentioned associative memory architecture and includes the following steps:

[0048] In step S101 , target input data is acquired.

[0049] In step S102 , target input data is input into an associative memory architecture, and the associative memory architecture outputs a target output value corresponding to the target input data, wherein the associative memory architecture includes a reservoir layer, an output layer, and a read head.

[0050] It is understandable that the embodiment of the present application can input the target input data into the associative memory architecture, and the associative memory architecture inputs the target output value corresponding to the target input data, that is, the associative memory content.

[0051] In an embodiment of the present application, after inputting the target input data into the associative memory architecture, it also includes: obtaining the data length of the target output value; and inputting an input sequence equal to the data length into the associative memory architecture.

[0052] The input sequence can be multiple 1s.

[0053] It can be understood that, in the embodiment of the present application, after the target input data is input into the associative memory architecture, an input sequence with the same data length as the target output value (i.e., the associative memory content) can be input into the associative memory architecture. For example, if the data length of the associative memory content is 10, after the target input data is input, 10 ones are input into the associative memory architecture.

[0054] In an embodiment of the present application, the output layer stores a pre-trained weight vector, and the weight vector of the output layer is pre-trained using a ridge regression algorithm, wherein the training process includes: obtaining a training data set, wherein the training data set contains multiple input data and corresponding output values; inputting each input data into a reservoir layer, and the reservoir layer outputs a state vector voltage; setting an associative memory position code in the memristor array corresponding to the output value of each input data in the training data set; using the associative memory position code as the target value of the ridge regression algorithm; and calculating the weight vector based on the state vector voltage, the target value, and the ridge regression algorithm.

[0055] It can be understood that the output layer of the embodiment of the present application stores a pre-trained weight vector so that the addressing signal is calculated based on the output of the reservoir layer and the weight vector, wherein the weight vector can be trained using the ridge regression algorithm. The weight vector of the output layer is input into the reservoir layer by inputting the input data in the training data set, and inputting the preset value into the reservoir layer after the data input is completed. The reservoir layer outputs the state vector voltage and sets the associative memory position code of the output value corresponding to the input data in the memristor array, and uses the associative memory position code as the target value of the ridge regression algorithm, and calculates the weight vector based on the state vector voltage, the target value and the ridge regression algorithm.

[0056] The specific training process is as follows: first, the generated input data is input into the reserve pool in sequence. After the data input is completed, 1 with the same length as the associative memory length M is input into the reserve pool to obtain a state vector of N rows and M columns. Then, the address position of the memory content corresponding to the input data in the memristor array is manually set to the target value of the ridge regression algorithm. For example, the associative memory content corresponding to the first input data is in the 1st to Mth columns in the memristor array, then the target value of the N-row and M-column vector in the ridge regression algorithm is a natural number that increases from 1 to M in sequence. Assuming there is 1 read head, the ridge regression algorithm can obtain a weight vector of length N, and then write the weight vector into the output layer memristor. For multiple read heads, the target output value is encoded according to the associative memory position corresponding to each read head.

[0057] In summary, the process of implementing associative memory in this application is as follows: Figure 4 shown.

[0058] The input and output are two sets of one-to-one corresponding associated data. After training (the detailed training process is described below), when the input is a specific data in the input training set, it can drive the automatic calculation in the device to obtain the addressing signal, so that the reading head moves to the specific address signal to read the content and obtain the output, such as Figure 4 shown.

[0059] It should be noted that the aforementioned explanation of the associative memory architecture embodiment is also applicable to the associative memory method of this embodiment and will not be repeated here.

[0060] According to the associative memory method proposed in the embodiment of the present application, data can be input into the associative memory architecture, and the associative memory architecture outputs the output value of the associative memory corresponding to the input data, thereby realizing the continuous associative memory function in the analog domain.

[0061] The following will combine the above-mentioned associative memory architecture to describe the implementation process of the associative memory of this application through a specific implementation, as follows.

[0062] Suppose there are two sets of associative memory-associated data with a length of 5, that is, the input set is {A1, A2, A3, A4, A5}, and the output set is {B1, B2, B3, B4, B5}. The data of the two sets correspond one to one, that is, the input A1 data is required to automatically associate with the B1 data. The length of each data in the input set is 30, and the length of each data in the output set is 20. The number of neurons n in the reserve pool is 50, and k is 8. The associative memory content B1 corresponding to the A1 data set is manually configured to be stored in columns 1 to 20, B2 in columns 21 to 40, and so on. A total of 100 columns of data are stored in the memristor array.

[0063] After configuration and training using the above method, the resulting associative memory effect is as follows: During operation, if any subset of the input set, such as A3, is input, and then a length of 20 1s is input, the addressing signal output will be a value between 41 and 60, with a small error, which is rounded to the integer address position. If other subsets of the input set are input, the corresponding addressing signal is generated to activate the corresponding column of the memristor array, thereby extracting the associative memory content. Figure 5 This is a schematic diagram of associative memory input and addressing signals. During system operation, when the input set data is received at the input end, the corresponding addressing signal will be obtained at the addressing signal end after the input data is completed, which is used to index the associative memory information stored in the memristor array.

[0064] An embodiment of the present application also provides a computer-readable storage medium having a computer program or instruction stored thereon. When the computer program or instruction is executed by a processor, the associative memory method as described above is implemented.

[0065] An embodiment of the present application also provides a computer program product, including a computer program or instructions, which, when executed, implements the above associative memory method.

[0066] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0067] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of this application, "N" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0068] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or N executable instructions for implementing a custom logical function or process step, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed in a different order than shown or discussed, including performing functions in a substantially simultaneous manner or in a reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application pertain.

[0069] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiment, the N steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, it can be implemented using any one or a combination of the following technologies known in the art: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array, a field programmable gate array, etc.

[0070] Those skilled in the art will understand that all or part of the steps in the method of the above embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

Claims

1. An associative memory architecture, characterized in that: include: A reservoir layer, wherein the reservoir layer includes a plurality of reservoir networks, wherein the reservoir network uses a plurality of randomly connected neurons to process input data and obtain a state vector voltage through a high-dimensional mapping effect; an output layer, generating a target addressing signal according to the state vector voltage, wherein the output layer stores a pre-trained weight vector and determines the target addressing signal using the weight vector and the state vector voltage; A read head reads the target output value of the associative memory position code corresponding to the memristor array according to the target addressing signal, so as to realize the continuous associative memory function in the analog domain.

2. The associative memory architecture according to claim 1, characterized in that The implementation method of the reservoir layer includes at least one of a time-delay coupling method, a parallel dynamic device method, and a rotating neuron reservoir.

3. The associative memory architecture according to claim 1, characterized in that The input data and the output value are associated data in a one-to-one correspondence.

4. The associative memory architecture according to claim 1, wherein: The weight vector of the output layer is pre-trained using a ridge regression algorithm, wherein the training process includes: Obtaining a training data set, wherein the training data set includes a plurality of input data and corresponding output values; Input each input data into the reservoir layer, and the reservoir layer outputs a state vector voltage; Setting an associative memory position code in the memristor array for an output value corresponding to each input data in the training data set; Using the associative memory position encoding as the target value of the ridge regression algorithm; The weight vector is calculated based on the state vector voltage, the target value, and the ridge regression algorithm.

5. The associative memory architecture according to claim 1, characterized in that There are multiple reading heads, and each reading head is responsible for reading the associative memory position encoding output value of different arrays in the memristor array.

6. An associative memory method, characterized in that: Implementation based on the associative memory architecture according to any one of claims 1 to 5 includes the following steps: Get target input data; The target input data is input into an associative memory architecture, and the associative memory architecture outputs a target output value corresponding to the target input data, wherein the associative memory architecture includes a reservoir layer, an output layer, and a read head.

7. The associative memory method according to claim 6, characterized in that: After inputting the target input data into the associative memory architecture, the method further includes: Obtaining the data length of the target output value; An input sequence having the same length as the data is input into the associative memory architecture.

8. The associative memory method according to claim 6, characterized in that: The output layer stores a pre-trained weight vector, and the weight vector of the output layer is pre-trained using a ridge regression algorithm, wherein the training process includes: Obtaining a training data set, wherein the training data set includes a plurality of input data and corresponding output values; Input each input data into the reservoir layer, and the reservoir layer outputs a state vector voltage; Setting an associative memory position code in the memristor array for an output value corresponding to each input data in the training data set; Using the associative memory position encoding as the target value of the ridge regression algorithm; The weight vector is calculated based on the state vector voltage, the target value, and the ridge regression algorithm.

9. A computer-readable storage medium having a computer program or instruction stored thereon, characterized in that: The computer program or instruction is executed by a processor to implement the associative memory method according to any one of claims 6 to 8.

10. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instruction is executed, the associative memory method according to any one of claims 6 to 8 is implemented.

Images