Display device and manufacturing method thereof

Abstract

A display device and a method of manufacturing the same are disclosed. The display device includes a substrate including a main area including a display area, a sub-area spaced apart from the main area in a first direction, and a plurality of bending areas connecting the main area and the sub-area; a display panel disposed in the display area on the substrate; and a printed circuit board attached to the sub-region.

Description

Technical Field

[0001] The present invention relates to a display device and a method for manufacturing the same. More particularly, the present invention relates to a display device for providing visual information and a method for manufacturing the same. Background Art

[0002] With the development of the information society, the demand for light-emitting display devices for displaying images is increasing in various forms. Light-emitting display devices are not only increasingly used in larger display devices such as notebook computers, televisions, and monitors, but also in smaller devices such as electronic watches.

[0003] However, as display devices become smaller and their brightness increases, wiring within the display devices is increasingly being arranged close to each other, increasing resistance and causing heat generation during product use. To address this issue, attempts are underway to reduce resistance by increasing the spacing between wiring. Summary of the Invention

[0004] An object of the present invention is to provide a display device with improved reliability.

[0005] Another object of the present invention is to provide a method for manufacturing the display device.

[0006] However, the objects of the present invention are not limited to the above objects, and can be variously expanded within the scope of the concept and scope of the present invention.

[0007] In order to achieve one of the aforementioned purposes of the present invention, a display device according to an embodiment of the present invention may include: a substrate, including a main area, a sub-area and a plurality of curved areas, the main area including a display area, the sub-area being separated from the main area along a first direction, and the plurality of curved areas connecting the main area and the sub-area; a display panel arranged in the display area on the substrate; and a printed circuit board attached to the sub-area.

[0008] In one embodiment, the bending region may include a first bending region and a second bending region, and the second bending region is arranged along a second direction intersecting the first direction and spaced apart from the first bending region.

[0009] In one embodiment, the width of the first curved region may be greater than the width of the second curved region.

[0010] In one embodiment, the display device may further include: a first power wiring extending from the printed circuit board and applying a first power supply to the display panel; and a second power wiring extending from the printed circuit board and applying a second power supply different from the first power supply to the display panel, wherein the first power wiring and the second power wiring may overlap with the curved area.

[0011] In one embodiment, the first power wiring and the second power wiring may overlap with the first bending region.

[0012] In one embodiment, the first power wiring may overlap with the first bending area, and the second power wiring may overlap with the second bending area.

[0013] In one embodiment, the voltage level of the first power supply may be higher than the voltage level of the second power supply.

[0014] In one embodiment, at least one of the bending regions may include more than three bending lines.

[0015] In one embodiment, the second bending area includes: a first bending line; a second bending line, which is separated from the first bending line; and a third bending line, which is located between the first bending line and the second bending line, wherein the first bending line and the second bending line may not overlap in a plane.

[0016] In one embodiment, the display device may further include: a driving unit, disposed in the sub-region, driving the display panel, wherein the driving unit may be mounted on the sub-region in a chip-on-plastic (COP) manner.

[0017] In one embodiment, the sub-region and the curved region may respectively overlap at least partially with the main region in a plane.

[0018] In one embodiment, at least one of the bending regions may be located between the main region and the sub-region.

[0019] In one embodiment, at least one of the curved regions may be located below the sub-region.

[0020] In one embodiment, the substrate may comprise plastic.

[0021] In one embodiment, the display panel may be circular in plan view.

[0022] In one embodiment, the display panel may be a quadrilateral in a plane.

[0023] In order to achieve the aforementioned another object of the present invention, a manufacturing method of a display device according to another embodiment of the present invention includes the following steps: providing a substrate, the substrate including a main area, a sub-area and a plurality of curved areas, the main area including a display area, the sub-area separated from one side of the main area, and the plurality of curved areas connecting the main area and the sub-area; forming a display panel in the display area of ​​the substrate; attaching a printed circuit board to the sub-area; and bending the curved area.

[0024] In one embodiment, in the step of bending the bending regions, at least one of the bending regions is bent more than twice.

[0025] In one embodiment, in the step of bending the bending region, each of the sub-region and the bending region may be bent to at least partially overlap with the main region on a plane.

[0026] In one embodiment, at least one of the bending areas includes: a first bending line; a second bending line, which is arranged separated from the first bending line; and a third bending line, which is located between the first bending line and the second bending line, wherein the first bending line and the second bending line can be bent in a manner that does not overlap in a plane.

[0027] According to an embodiment of the present invention, a display device may include: a substrate, including a main area, a sub-area and a plurality of curved areas, the main area including a display area, the sub-area being separated from the main area along a first direction, and the plurality of curved areas connecting the main area and the sub-area; a display panel arranged in the display area on the substrate; and a printed circuit board attached to the sub-area.

[0028] Therefore, by arranging the multiple curved regions between the main region and the sub-region, the spacing between the power supply wiring lines arranged in the curved regions can be increased. This reduces the resistance to current flow in each of the power supply wiring lines. Furthermore, the reduced resistance of each of the power supply wiring lines can reduce heat generation in the display device.

[0029] However, the effects of the present invention are not limited to the above effects, and can be variously expanded without departing from the concept and scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a perspective view showing a display device according to an embodiment of the present invention.

[0031] Figure 2 is a plan view showing a display device according to an embodiment of the present invention.

[0032] Figure 3 It shows Figure 2 A plan view of a curved display device.

[0033] Figure 4 It is shown that the arrangement is Figure 2 A plan view of an embodiment of power supply wiring on a substrate.

[0034] Figure 5 It is shown that the arrangement is Figure 2 A plan view of another embodiment of power supply wiring on a substrate.

[0035] Figure 6 It is along Figure 2 The cross-sectional view is shown taken along line II'.

[0036] Figure 7 It shows Figure 6 A cross-sectional view of a display panel.

[0037] Figure 8 It shows Figure 2 A circuit diagram of an embodiment of a pixel.

[0038] Figure 9 It shows Figure 3 A cross-sectional view of an embodiment of a curved display device.

[0039] Figure 10 It shows Figure 3 A cross-sectional view of another embodiment of a curved display device.

[0040] Figures 11 to 15 is shown for manufacturing Figure 1 A diagram of a display apparatus and method.

[0041] Figure 16 is a plan view showing a display device according to another embodiment of the present invention.

[0042] Description of Reference Numerals DETAILED DESCRIPTION

[0043] Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and repeated description of the same components will be omitted.

[0044] In this specification, a plane may be defined by a first direction D1 and a second direction D2 intersecting the first direction D1. For example, the second direction D2 may be perpendicular to the first direction D1. Furthermore, a third direction D3 may be a normal direction to the plane. That is, the third direction D3 may be perpendicular to the plane formed by the first direction D1 and the second direction D2.

[0045] Figure 1 is a perspective view showing a display device according to an embodiment of the present invention.

[0046] Reference Figure 1 The display device DD may include a display area DA and a peripheral area SA. The display area DA may be surrounded by the peripheral area SA.

[0047] The display area DA may be an area capable of displaying an image by generating light or adjusting the transmittance of light provided from an external light source. The peripheral area SA may be an area that does not display an image. However, embodiments of the present invention are not limited thereto, and at least a portion of the peripheral area SA may also display an image.

[0048] The display area DA may display a plurality of images IM through which a user may receive information from the display device DD.

[0049] Figure 2 is a plan view showing a display device according to an embodiment of the present invention.

[0050] Reference Figure 2 , the display device DD may include a main region MR, a bending region BR, and a sub-region SR along the first direction D1.

[0051] The main region MR may include Figure 1 The display area DA and the peripheral area SA shown in FIG. The curved area BR may connect the main area MR and the sub-area SR, and may be provided in plurality along the second direction D2. A display panel DP may be arranged in the display area DA of the main area MR. In one embodiment, the display panel DP may be arranged as shown in FIG. Figure 2 The display panel DP may be circular in a plan view. However, the embodiments of the present invention are not limited thereto. The display panel DP may have an elliptical, polygonal, or other shape in a plan view.

[0052] A plurality of pixels PX may be arranged in the main region MR. The pixels PX may be arranged in a matrix along the first direction D1 and / or the second direction D2. The pixels PX may provide a visual image to a user of the display device DD. For example, the pixels PX may emit light composed of a combination of red, green, and blue colors.

[0053] Data lines DL extending along the first direction D1 may be arranged in the main region MR. The data lines DL may be arranged to be spaced apart from each other along the second direction D2. The data lines DL may apply data signals to the pixels PX.

[0054] Gate lines GL extending along the second direction D2 may be arranged in the main region MR. The gate lines GL may be arranged to be spaced apart from each other along the first direction D1. The gate lines GL may apply gate signals to the pixels PX.

[0055] In one embodiment, the bending region BR may include a first bending region BR1, a second bending region BR2, and a third bending region BR3. For example, the bending region BR may include the first bending region BR1 connecting the main region MR and the sub-region SR, the second bending region BR2 spaced apart from the first bending region BR1 in a direction opposite to the second direction D2, and the third bending region BR3 spaced apart from the first bending region BR1 in the second direction D2. However, embodiments of the present invention are not limited thereto. The bending region BR may also include two bending regions or four or more bending regions.

[0056] In one embodiment, each of the second bending region BR2 and the third bending region BR3 may include two bending regions. For example, the second bending region BR2 may include a 2-1 bending region BR2-1 and a 2-2 bending region BR2-2. The third bending region BR3 may include a 3-1 bending region BR3-1 and a 3-2 bending region BR3-2. The 2-1 bending region BR2-1 and the 2-2 bending region BR2-2 may be adjacent to each other along the first direction D1, and the 3-1 bending region BR3-1 and the 3-2 bending region BR3-2 may be adjacent to each other along the first direction D1.

[0057] Each of the bending regions BR may include a bending line BL. Figure 3 As shown, when the display device DD is bent, the display device DD may be bent along the bending line BL.

[0058] In one embodiment, at least one of the bending regions BR may include three or more bending lines BL. For example, the first bending region BR1 may include a 1-1 bending line BL1-1 and a 1-2 bending line BL1-2. The second bending region BR2 may include a 2-1 bending line BL2-1, a 2-2 bending line BL2-2, and a 2-3 bending line BL2-3. The third bending region BR3 may include a 3-1 bending line BL3-1, a 3-2 bending line BL3-2, and a 3-3 bending line BL3-3.

[0059] For example, the 2-2nd bending line BL2-2 may be a line that divides the 2-1st bending region BR2-1 from the 2-2nd bending region BR2-2. The 3-2nd bending line BL3-2 may be a line that divides the 3-1st bending region BR3-1 from the 3-2nd bending region BR3-2. Specifically, the 2-2nd bending line BL2-2 may be located between the 2-1st bending line BL2-1 and the 2-3rd bending line BL2-3, and the 3-2nd bending line BL3-2 may be located between the 3-1st bending line BL3-1 and the 3-3rd bending line BL3-3.

[0060] In one embodiment, the width of the first bending region BR1 in the second direction D2 may be greater than the width of the second bending region BR2 in the second direction D2. Figure 2 As shown, the width of the first bending region BR1 in the second direction D2 may be greater than the width of each of the second bending region BR2 and the third bending region BR3 in the second direction D2. In addition, the width of each of the second bending region BR2 and the third bending region BR3 in the second direction D2 may be the same. However, the embodiments of the present invention are not limited thereto. The width of the first bending region BR1 in the second direction D2, the width of the second bending region BR2 in the second direction D2, and the width of the third bending region BR3 in the second direction D2 may also be the same as each other. Optionally, each of the width of the first bending region BR1 in the second direction D2, the width of the second bending region BR2 in the second direction D2, and the width of the third bending region BR3 in the second direction D2 may also be different from each other.

[0061] A driver IC and a printed circuit board PCB may be arranged in the sub-region SR. Specifically, the driver IC may be arranged in the sub-region SR, and the printed circuit board PCB may be attached to one side of the sub-region SR. The driver IC may be connected to the data line DL to apply a data signal to the pixel PX. The printed circuit board PCB may be connected to the power supply wiring PSL (refer to FIG. Figure 4 ) is connected to apply power to the pixel PX.

[0062] In one embodiment, the driver IC may be mounted on the sub-region SR in a chip-on-plastic (COP) manner. That is, the substrate SUB of the display device DD (see Figure 7 ) may include plastic. For example, the substrate SUB may include polyimide, etc.

[0063] Figure 3 It shows Figure 2 A plan view of a curved display device.

[0064] Reference Figure 3 When the display device DD is curved, the bending region BR and the sub-region SR may be arranged below the main region MR. In this case, the main region MR, the bending region BR, and the sub-region SR may overlap in plan. Specifically, each of the sub-region SR and the bending region BR may at least partially overlap with the main region MR in plan.

[0065] In one embodiment, when the display device DD is bent, the 2-1st bending region BR2-1 and the 2-2nd bending region BR2-2 may have a “ Similarly, the 3-1st bending region BR3-1 and the 3-2nd bending region BR3-2 may have a " ” shape.

[0066] Since the second bending region BR2 has a " " shape, the overlapping area of ​​the 2-1st bending area BR2-1 and the 2-2nd bending area BR2-2 can be minimized. In addition, since the third bending area BR3 has a " " shape, the overlapping area of ​​the 3-1st bending region BR3-1 and the 3-2nd bending region BR3-2 can be minimized. According to this, the power supply wiring PSL (refer to Figure 4 ) between the short circuit phenomenon.

[0067] For example, Figure 3 As shown, when the display device DD is bent, the 2-1st bending line BL2-1 and the 2-3rd bending line BL2-3 may not overlap on a plane. When the display device DD is bent, the 3-1st bending line BL3-1 and the 3-3rd bending line BL3-3 may not overlap on a plane.

[0068] In one embodiment, when the display device DD is curved, each of the bending regions BR may not overlap with the driver IC and the printed circuit board PCB in a plane. That is, each of the bending regions BR may be spaced apart from the driver IC and the printed circuit board PCB in a plane.

[0069] Figure 4 It is shown that the arrangement is Figure 2 A plan view of an embodiment of power supply wiring on a substrate. Figure 5 It is shown that the arrangement is Figure 2 A plan view of another embodiment of power supply wiring on a substrate.

[0070] Combine Figure 2 Reference Figure 4 and Figure 5 In the display device DD, the power supply wiring PSL extending from the printed circuit board PCB and applying the power supply voltage to the pixel PX may be arranged. The power supply wiring PSL may include: a first power supply wiring PSL1 for applying a first power supply voltage to the pixel PX; and a second power supply wiring PSL2 for applying a second power supply voltage to the pixel PX. For example, the first power supply voltage may be a driving voltage, and the second power supply voltage may be a common voltage. The first power supply wiring PSL1 and the second power supply wiring PSL2 may pass through the bending region BR and be arranged in the peripheral region (for example, Figure 1 In the surrounding area SA).

[0071] In one embodiment, if Figure 4As shown, the first power wiring PSL1 and the second power wiring PSL2 may overlap with different bending regions BR. For example, the first power wiring PSL1 may overlap with the first bending region BR1, and the second power wiring PSL2 may overlap with the second bending region BR2 and the third bending region BR3. However, embodiments of the present invention are not limited to this. The first power wiring PSL1 may overlap not only with the first bending region BR1, but also with the second bending region BR2 and / or the third bending region BR3. By overlapping the first power wiring PSL1 and the second power wiring PSL2 with different bending regions BR, a short circuit between the first power wiring PSL1 and the second power wiring PSL2 can be prevented or reduced.

[0072] In one embodiment, if Figure 5 As shown, the first power supply wiring PSL1 and the second power supply wiring PSL2 may also overlap with the same bending region BR. For example, the first power supply wiring PSL1 and the second power supply wiring PSL2 may overlap with the first bending region BR1 to the third bending region BR3, respectively. However, embodiments of the present invention are not limited to this. Alternatively, the first power supply wiring PSL1 may overlap with the first bending region BR1 and the second bending region BR2, and the second power supply wiring PSL2 may overlap with the second bending region BR2 and the third bending region BR3.

[0073] The first power wiring PSL1 and the second power wiring PSL2 may pass through the bending region BR and overlap the main region MR. Specifically, the first power wiring PSL1 and the second power wiring PSL2 may surround the display panel DP in the main region MR and overlap the peripheral region SA.

[0074] In one embodiment, the level of the first power supply voltage applied by the first power supply wiring PSL1 may be higher than the level of the second power supply voltage applied by the second power supply wiring PSL2 .

[0075] As a result, since the plurality of curved regions BR are located between the main region MR and the sub-region SR, the spacing between the power supply wirings PSL arranged in the curved regions BR can be increased. Consequently, the resistance to current flow in each of the power supply wirings PSL can be reduced. Furthermore, the reduced resistance of each of the power supply wirings PSL can reduce heat generation in the display device DD.

[0076] Figure 6 It is along Figure 2The cross-sectional view is shown taken along line II'.

[0077] Reference Figure 6 , the display device DD may include a cover film CF, a plate PT, an adhesive film AF, the display panel DP, a polymer layer POL, a window layer WL, an adhesive layer ADL, and a protective film PL.

[0078] The cover film CF may be disposed on the back side of the display device DD. The cover film CF may mitigate external impacts on the display device DD. The cover film CF may include at least one of sponge, foam plastic, thermoplastic polyurethane, and polydimethylacrylamide. These materials may be used alone or in combination. Optionally, the cover film CF may include a light-blocking material. Thus, the cover film CF may absorb light incident from the back side of the display device DD.

[0079] The plate PT may be disposed on the cover film CF. The plate PT may prevent the display panel DP from bending due to external forces. That is, even when the plate PT is subjected to external forces from outside the display device DD, the display panel DP may remain relatively flat. The plate PT may include a hard or semi-hard material. For example, the plate PT may include at least one of iron, chromium, carbon, nickel, silicon, manganese, and molybdenum. These materials may be used alone or in combination. However, embodiments of the present invention are not limited thereto.

[0080] The adhesive film AF may be disposed on the panel PT. The adhesive film AF may attach the panel PT to the display panel DP. For example, the adhesive film AF may include at least one of a pressure-sensitive adhesive (PSA), an optically clear adhesive (OCA), and an optically clear resin (OCR). However, embodiments of the present invention are not limited thereto.

[0081] The display panel DP may be arranged on the adhesive film AF. The display panel DP may generate light by means of a provided signal. Accordingly, the display panel DP may provide a visual image to a user of the display device DD. Figure 7 This will be described in detail later.

[0082] The polymer layer POL may be disposed on the display panel DP. The polymer layer POL may attach the display panel DP to the window layer WL. Furthermore, the polymer layer POL may support the window layer WL to prevent it from sagging and protect the display panel DP from external impacts. The polymer layer POL may have a single-layer or multi-layer structure.

[0083] The window layer WL may be disposed on the polymer layer POL. The window layer WL may cover the entire surface of the display device DD and protect the display panel DP. The window layer WL may include a substantially transparent material. For example, the window layer WL may be glass or plastic. However, embodiments of the present invention are not limited thereto.

[0084] The adhesive layer ADL may be disposed on the window layer WL. The adhesive layer ADL may attach the window layer WL to the protective film PL. The adhesive layer ADL may include a transparent material. For example, the adhesive layer ADL may include at least one of a pressure-sensitive adhesive (PSA), an optically clear adhesive (OCA), and an optically clear resin (OCR). However, embodiments of the present invention are not limited thereto.

[0085] The protective film PL may be disposed on the adhesive layer ADL. The protective film PL may protect the window layer WL from external impacts and / or scratches. For example, the protective film PL may include a base layer and a hard coating layer. However, embodiments of the present invention are not limited thereto. The protective film PL may also include a low refractive index layer and / or an anti-fingerprint layer.

[0086] Figure 7 It shows Figure 6 A cross-sectional view of a display panel.

[0087] Reference Figure 1 、 Figure 6 as well as Figure 7 The display panel DP includes the substrate SUB, a buffer layer BUF, a gate insulating layer GI, a transistor TR, an interlayer insulating layer IL, a connecting electrode CNE, a first via layer VIA1, a second via layer VIA2, a light emitting element LED, a pixel defining layer PDL, and an encapsulation layer ENC.

[0088] The transistor TR may include an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. The light emitting element LED may include a pixel electrode PE, a light emitting layer EL, and a common electrode CE.

[0089] The substrate SUB may include a glass substrate, a metal substrate, a plastic substrate, etc. However, the embodiments of the present invention are not limited thereto, and the substrate SUB may be an inorganic layer, an organic layer, or a composite material layer.

[0090] The buffer layer BUF may be disposed on the substrate SUB. The buffer layer BUF may be disposed on the substrate SUB. The buffer layer BUF may prevent impurities such as oxygen and moisture from penetrating through the substrate SUB to the upper portion of the substrate SUB. The buffer layer BUF may include an inorganic insulating material.

[0091] The active layer ACT may be disposed on the buffer layer BUF. The active layer ACT may include an oxide semiconductor, a silicon semiconductor, an organic semiconductor, or the like. For example, the oxide semiconductor may include an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The silicon semiconductor may include amorphous silicon, polycrystalline silicon, or the like. The active layer ACT may include a source region, a drain region, and a channel region located between the source and drain regions.

[0092] The gate insulating layer GI may be disposed on the buffer layer BUF. Specifically, the gate insulating layer GI may cover the active layer ACT on the buffer layer BUF. The gate insulating layer GI may include an inorganic insulating material. In one embodiment, the gate insulating layer GI may be formed entirely in the display area DA and the peripheral area SA.

[0093] The gate electrode GE may be disposed on the gate insulating layer GI. At least a portion of the gate electrode GE may overlap the channel region of the active layer ACT. The gate electrode GE may include a conductive material such as a metal, an alloy, a conductive metal nitride, a conductive metal oxide, or a transparent conductive material. Examples of the conductive material that can be used for the gate electrode GE include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), alloys containing aluminum, alloys containing silver, alloys containing copper, alloys containing molybdenum, aluminum nitride (AlN), tungsten nitride (WN), titanium nitride (TiN), chromium nitride (CrN), tantalum nitride (TaN), strontium ruthenium oxide (SrRuO), zinc oxide (ZnO), indium tin oxide (ITO), tin oxide (SnO), indium oxide (InO), gallium oxide (GaO), indium zinc oxide (IZO), etc. These materials can be used alone or in combination. Alternatively, the gate electrode GE can have a single-layer structure or a multilayer structure including multiple conductive layers.

[0094] The interlayer insulating layer IL may be disposed on the gate electrode GE. Specifically, the interlayer insulating layer IL may be disposed on the gate insulating layer GI and may cover the gate electrode GE on the gate insulating layer GI. The interlayer insulating layer IL may include an inorganic insulating material.

[0095] The source electrode SE and the drain electrode DE may be disposed on the interlayer insulating layer IL. The source electrode SE and the drain electrode DE may be respectively connected to the active layer ACT. For example, the source electrode SE may contact the source region of the active layer ACT, and the drain electrode DE may contact the drain region of the active layer ACT. Each of the source electrode SE and the drain electrode DE may include a conductive material. The active layer ACT, the gate electrode GE, the source electrode SE, and the drain electrode DE may form the transistor TR.

[0096] A first via layer VIA1 may be disposed on the source electrode SE and the drain electrode DE. Specifically, the first via layer VIA1 may be disposed on the interlayer insulating layer IL and may cover the source electrode SE and the drain electrode DE on the interlayer insulating layer IL. The first via layer VIA1 may include an organic insulating material. In one embodiment, the first via layer VIA1 may be formed only in the display area DA and a portion of the peripheral area SA adjacent to the display area DA.

[0097] The connection electrode CNE may be disposed on the first via layer VIA1. The connection electrode CNE may transmit a signal transmitted from the transistor TR to the light-emitting element LED. The connection electrode CNE may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These materials may be used alone or in combination. However, embodiments of the present invention are not limited thereto.

[0098] The second via layer VIA2 may be disposed on the connection electrode CNE. Specifically, the second via layer VIA2 may be disposed on the first via layer VIA1 and may cover the connection electrode CNE. The second via layer VIA2 may include substantially the same material as the first via layer VIA1.

[0099] The pixel electrode PE may be disposed on the second via layer VIA2. The pixel electrode PE may include a conductive material. The pixel electrode PE may be connected to the drain electrode DE via the connection electrode CNE. Accordingly, the pixel electrode PE may be electrically connected to the transistor TR.

[0100] The pixel defining layer (PDL) may be disposed on the pixel electrode PE. For example, the pixel defining layer (PDL) may expose at least a portion of the pixel electrode PE. The pixel defining layer (PDL) may include an inorganic insulating material or an organic insulating material.

[0101] The light-emitting layer EL may be disposed on the pixel electrode PE. Specifically, the light-emitting layer EL may be disposed within an opening defined by the pixel-defining layer PDL. That is, the light-emitting layer EL may be surrounded by the pixel-defining layer PDL. The light-emitting layer EL may include at least one of an organic light-emitting material and / or quantum dots. However, embodiments of the present invention are not limited thereto.

[0102] The common electrode CE may be disposed on the light-emitting layer EL. The common electrode CE may also be disposed on the pixel-defining layer PDL. That is, the common electrode CE may be disposed continuously on the light-emitting layer EL and the pixel-defining layer PDL. The common electrode CE may include a conductive material. The light-emitting layer EL may emit light based on a voltage difference between the pixel electrode PE and the common electrode CE.

[0103] The encapsulation layer ENC may be arranged on the common electrode CE. The encapsulation layer ENC may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In one embodiment, the inorganic encapsulation layer and the organic encapsulation layer may be arranged alternately. For example, the organic encapsulation layer may include a polymer cured material such as a polyacrylate resin, an epoxy resin, or a silicone resin. For example, the inorganic encapsulation layer may include silicon oxide, silicon nitride, silicon carbide, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc.

[0104] Figure 8 It shows Figure 2 A circuit diagram of an embodiment of a pixel.

[0105] Reference Figure 8 One of the pixels PX may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a capacitor CST, and the light emitting element LED.

[0106] The first transistor T1 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor T1 may be connected to a first node N1. The first electrode of the first transistor T1 may be connected to a second electrode of the fifth transistor T5. The second electrode of the first transistor T1 may be connected to a second electrode of the third transistor T3.

[0107] The second transistor T2 may include a gate electrode, a first electrode, and a second electrode. A scan signal SS may be applied to the gate electrode of the second transistor T2. A data voltage VDATA may be applied to the first electrode of the second transistor T2. The second electrode of the second transistor T2 may be connected to the first electrode of the first transistor T1.

[0108] The third transistor T3 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the third transistor T3 may be applied with the scan signal SS. The first electrode of the third transistor T3 may be connected to the first electrode of the fourth transistor T4. The second electrode of the third transistor T3 may be connected to the second electrode of the first transistor T1.

[0109] The fourth transistor T4 may include a gate electrode, the first electrode, and a second electrode. A first initialization signal GIS may be applied to the gate electrode of the fourth transistor T4. The first electrode of the fourth transistor T4 may be connected to the first electrode of the third transistor T3. An initialization voltage VINIT may be applied to the second electrode of the fourth transistor T4.

[0110] The fifth transistor T5 may include a gate electrode, a first electrode, and a second electrode. A light emission control signal EM may be applied to the gate electrode of the fifth transistor T5. A first power supply voltage ELVDD may be applied to the first electrode of the fifth transistor T5. The second electrode of the fifth transistor T5 may be connected to the first electrode of the first transistor T1.

[0111] The sixth transistor T6 may include a gate electrode, a first electrode, and a second electrode. The light emission control signal EM may be applied to the gate electrode of the sixth transistor T6. The first electrode of the sixth transistor T6 may be connected to the second electrode of the first transistor T1. The second electrode of the sixth transistor T6 may be connected to the second electrode of the seventh transistor T7.

[0112] The seventh transistor T7 may include a gate electrode, a first electrode, and a second electrode. A second initialization signal GB may be applied to the gate electrode of the seventh transistor T7. The initialization voltage VINIT may be applied to the first electrode of the seventh transistor T7. The second electrode of the seventh transistor T7 may be connected to the second electrode of the sixth transistor T6.

[0113] The capacitor CST may include a first electrode and a second electrode. The first power supply voltage ELVDD may be applied to the first electrode of the capacitor CST. The second electrode of the capacitor CST may be connected to the first electrode of the third transistor T3.

[0114] The light emitting element LED may include a first electrode and a second electrode. The first electrode of the light emitting element LED may be connected to the second electrode of the seventh transistor T7. A second power supply voltage ELVSS may be applied to the second electrode of the light emitting element LED.

[0115] In addition, in this manual Figure 2 FIG. 4 shows one of the pixels PX having a 7T1C structure, but the present invention is not limited thereto. The pixel PX may be configured in various ways, such as 4T2C, 5T2C, 6T2C, 7T2C, and 8T1C.

[0116] Figure 9 It shows Figure 3 A cross-sectional view of an embodiment of a curved display device. Figure 10 It shows Figure 3 A cross-sectional view of another embodiment of a curved display device.

[0117] Reference Figure 3 、 Figure 9 as well as Figure 10 When the display device DD is bent, the bending region BR may overlap with the main region MR in a planar manner. That is, when the display device DD is bent along the bending line BL of the bending region BR, at least one of the bending regions BR may overlap with the main region MR in a planar manner. As the bending region BR is bent, the dead zone area of ​​the display device DD may be reduced.

[0118] In one embodiment, if Figure 9 As shown, when the display device DD is curved, at least one of the bending regions BR may be located below the sub-region SR in cross-section. For example, the second bending region BR2 and the third bending region BR3 may be located below the sub-region SR. In other words, the second bending region BR2 and the third bending region BR3 may be located below the driver IC and the printed circuit board PCB.

[0119] In one embodiment, if Figure 10 As shown, when the display device DD is curved, at least one of the bending regions BR may be located between the main region MR and the sub-region SR in cross-section. For example, the second bending region BR2 and the third bending region BR3 may be located between the main region MR and the sub-region SR. In other words, the second bending region BR2 and the third bending region BR3 may be located between the display panel DP and the driver IC.

[0120] Figures 11 to 15 is shown for manufacturing Figure 1 A diagram of a display apparatus and method.

[0121] Reference Figures 11 to 13 The substrate SUB including the plurality of curved regions BR connecting the main region MR and the sub-region SR may be provided. The display panel DP may then be formed in the main region MR of the display device DD. The driver IC and the printed circuit board PCB may be formed in the sub-region SR of the display device DD.

[0122] Further references Figure 2 and Figure 14 The substrate SUB may be bent along the bending lines BL. For example, the first bending region BR1 may be bent along the 1-1 bending line BL1-1 and the 1-2 bending line BL1-2, the second bending region BR2 may be bent along the 2-2 bending line BL2-2, and the third bending region BR3 may be bent along the 3-2 bending line BL3-2.

[0123] Further references Figure 2 and Figure 15 The second bending region BR2 and the third bending region BR3 may be bent again and arranged below the main region MR. That is, the second bending region BR2 and the third bending region BR3 may be bent more than twice. Specifically, the second bending region BR2 may be bent along the 2-1st bending line BL2-1 and the 2-3rd bending line BL2-3. The third bending region BR3 may be bent along the 3-1st bending line BL3-1 and the 3-3rd bending line BL3-3.

[0124] In one embodiment, as shown in FIG. Figure 9 As described above, the second bending region BR2 and the third bending region BR3 may be arranged at the lower portion of the sub-region SR. Figure 10 The second bending region BR2 and the third bending region BR3 may be disposed between the main region MR and the sub-region SR. That is, each of the sub-region SR and the bending region BR may be bent to at least partially overlap with the main region MR in a plane.

[0125] Figure 16 is a plan view showing a display device according to another embodiment of the present invention.

[0126] Reference Figure 16 , the display panel DP arranged in the main region MR may have a quadrilateral shape on a plane. However, the embodiment of the present invention is not limited thereto. Figure 2 and Figure 16The planar shape of the display panel DP can be various shapes such as circle, quadrilateral, ellipse, and diamond according to user needs.

[0127] Industrial applicability The present invention can be applied to a display device and an electronic device including the display device. For example, the present invention can be applied to high-resolution smartphones, mobile phones, smart tablets, smart watches, tablet PCs, car navigation systems, televisions, computer monitors, laptop computers, etc.

[0128] The above description is based on exemplary embodiments of the present invention, but anyone with ordinary knowledge in the technical field will understand that various modifications and changes can be made to the present invention without departing from the scope of the concept and field of the present invention described in the claims.

Claims

1. A display device comprising: a substrate comprising a main region, a sub-region, and a plurality of curved regions, wherein the main region comprises a display region, the sub-region is separated from the main region along a first direction, and the plurality of curved regions connect the main region and the sub-region; a display panel arranged in the display area on the substrate; as well as A printed circuit board is attached to the sub-area.

2. The display device according to claim 1, wherein The bending region includes a first bending region and a second bending region, and the second bending region is arranged along a second direction crossing the first direction and spaced apart from the first bending region.

3. The display device according to claim 2, wherein The width of the first curved region is greater than the width of the second curved region.

4. The display device according to claim 2, wherein Also includes: a first power wiring extending from the printed circuit board and applying a first power source to the display panel; as well as a second power supply wiring extending from the printed circuit board and applying a second power supply different from the first power supply to the display panel; The first power wiring and the second power wiring overlap with the bending area.

5. The display device according to claim 4, wherein The first power supply wiring and the second power supply wiring overlap with the first bending region.

6. The display device according to claim 4, wherein The first power wiring overlaps with the first bending area, The second power wiring overlaps the second bending region.

7. The display device according to claim 2, wherein: At least one of the bending regions includes three or more bending lines.

8. The display device according to claim 7, wherein: The second bending region includes: First bend line; a second bending line disposed spaced apart from the first bending line; and a third bending line located between the first bending line and the second bending line; The first bending line and the second bending line do not overlap on a plane.

9. The display device according to claim 1, wherein The sub-region and the curved region each overlap at least partially with the main region in a plane.

10. A method for manufacturing a display device, comprising the following steps: Providing a substrate, the substrate comprising a main region, a sub-region, and a plurality of curved regions, the main region comprising a display region, the sub-region being separated from one side of the main region, and the plurality of curved regions connecting the main region and the sub-region; forming a display panel in the display area of ​​the substrate; attaching a printed circuit board to the sub-area; as well as The bending region is bent.

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