Synchronous staggered parallel Buck pulse discharge circuit, pulse discharge system and switching power supply

Abstract

The embodiment of the invention discloses a synchronous staggered parallel Buck pulse discharge circuit, a pulse discharge system and a switching power supply. The circuit comprises a power supply, a bus capacitor, a multi-phase parallel synchronous rectification Buck circuit, an energy feedback circuit and a load, the positive electrode of the power supply is connected with the first ends of the bus capacitor, the synchronous rectification Buck circuit and the energy feedback circuit, the negative electrode of the power supply is connected with the second ends of the bus capacitor, the synchronous rectification Buck circuit, the energy feedback circuit and the load, and the third end of the energy feedback circuit is connected with the output end of the synchronous rectification Buck circuit. The fourth end of the energy feedback circuit is connected with the first end of the load; wherein each phase synchronous rectification Buck circuit is controlled through phase difference and comprises a synchronous rectification switch group formed by SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) devices, and the energy feedback circuit comprises a switch device formed by Si IGBT (Insulated Gate Bipolar Translator) devices. By adopting the embodiment of the invention, the triple requirements of high stability, high reliability and high dynamic response of the high-power semiconductor laser on the driving power supply can be met.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor lasers, and in particular to a synchronous interleaved parallel Buck pulse discharge circuit, a pulse discharge system and a switching power supply. Background Art

[0002] With the advancement of materials science and semiconductor technology, semiconductor lasers have become the core optoelectronic devices for achieving efficient conversion of electrical energy into photons due to their PN junction electroluminescent properties. This device has the advantages of small size, light weight, high luminous efficiency, and wide modulation bandwidth. It has been widely used in optical communications, biomedicine, advanced manufacturing, and national defense and military fields, especially in high-power application scenarios such as high-energy laser weapons and precision laser processing. However, there are two major technical bottlenecks in high-power semiconductor lasers: first, the device itself has physical property limitations such as high cost and poor impact resistance; second, the pulse quality of the driving power supply directly affects the laser output characteristics. Studies have shown that dynamic indicators such as the rise / fall time of the pulse waveform, current ripple coefficient, and reverse overshoot are strongly correlated with the laser life and beam quality.

[0003] Among the current mainstream drive solutions, traditional pulse generators based on linear power supply architectures have significant drawbacks: their power devices operate in the linear amplification region for extended periods, resulting in system efficiency below 40%. Furthermore, limited heat dissipation makes it difficult to achieve repetition rates above the kHz level and narrow pulse widths in the μs. Existing technical improvements, such as the multi-module parallel cascade topology proposed by Zhao Qinglin's team at Yanshan University, published in IEEE Access, titled "Design of Pulse Power Supply for High-Power Semiconductor Laser Diode Array," improve power capacity through a distributed structure. However, this approach utilizes multiple MOSFETs operating in the linear region in parallel as a current return path, leading to increased device losses. Furthermore, this approach requires an independent current-sharing control loop for each MOSFET, which not only increases control complexity but also introduces the risk of current-sharing imbalance due to the discrete nature of device parameters, making it difficult to meet high reliability requirements. Summary of the Invention

[0004] In response to the above technical difficulties, the embodiments of the present application provide a synchronous interleaved parallel Buck pulse discharge circuit, a pulse discharge system and a switching power supply, which can meet the triple requirements of high-power semiconductor lasers for high stability, high reliability and high dynamic response of the driving power supply.

[0005] In a first aspect, an embodiment of the present application provides a synchronous interleaved parallel Buck pulse discharge circuit, comprising a power supply, a bus capacitor, a multi-phase parallel synchronous rectification Buck circuit, an energy feedback circuit, and a load; the positive electrode of the power supply is connected to the first end of the bus capacitor, the first end of the multi-phase parallel synchronous rectification Buck circuit, and the first end of the energy feedback circuit; the negative electrode of the power supply is connected to the second end of the bus capacitor, the second end of the multi-phase parallel synchronous rectification Buck circuit, the second end of the energy feedback circuit, and the second end of the load; the third end of the energy feedback circuit is connected to the output end of the multi-phase parallel synchronous rectification Buck circuit, and the fourth end of the energy feedback circuit is connected to the first end of the load; The synchronous rectification Buck circuit of each phase is controlled by a phase difference, and each phase of the synchronous rectification Buck circuit includes a synchronous rectification switch group composed of SiC MOSFET devices, and the energy feedback circuit includes a switch device composed of Si IGBT devices.

[0006] Optionally, each phase of the synchronous rectification Buck circuit includes a synchronous rectification switch group consisting of two SiC MOSFET devices and an energy storage inductor, wherein the drain of one of the SiC MOSFET devices is connected to the positive electrode of the power supply, the source of one of the SiC MOSFET devices is connected to the drain of the other SiC MOSFET device and one end of the energy storage inductor, and the source of the other SiC MOSFET device is connected to the negative electrode of the power supply; the other ends of the multiple energy storage inductors of the multi-phase parallel synchronous rectification Buck circuit are connected.

[0007] Optionally, the energy feedback circuit includes two switching devices consisting of Si IGBT devices, the cathode of the diode is connected to the positive electrode of the power supply, the anode of the diode is connected to the other end of the energy storage inductor and the collector of one of the Si IGBT devices, the emitter of one of the Si IGBT devices is connected to the collector of the other Si IGBT device and the first end of the load, and the emitter of the other Si IGBT device is connected to the negative electrode of the power supply and the second end of the load.

[0008] Optionally, when one of the SiC MOSFET devices and the two Si IGBT devices are in the on state, and the other SiC MOSFET device is in the off state, the power supply, one of the SiC MOSFET devices, the energy storage inductor and the two Si IGBT devices form an energy storage loop, and the energy storage loop charges the energy storage inductor through the power supply.

[0009] Optionally, when one of the SiC MOSFET devices and one of the Si IGBT devices are in the on state, and the other SiC MOSFET device and the other Si IGBT device are in the off state, the power supply, one of the SiC MOSFET devices, the energy storage inductor, one of the Si IGBT devices and the load form a discharge loop, and the discharge loop discharges to the outside through the load.

[0010] Optionally, when one of the SiC MOSFET devices and the two Si IGBT devices are in the off state, and the other SiC MOSFET device is in the on state, the bus capacitor, the diode, the energy storage inductor and the other SiC MOSFET device form an energy feedback loop, and the energy feedback loop feeds back the energy stored in the energy storage inductor to the bus capacitor.

[0011] A second aspect of the embodiments of the present application provides a pulse discharge system, comprising the synchronous interleaved parallel Buck pulse discharge circuit and a controller as described in the first aspect, wherein the controller comprises: a digital signal processor configured to generate programmable pulse waveform parameters for generating a pulse width modulated signal; a gate driving circuit configured to generate a driving timing control signal, wherein the driving timing control signal is used to generate a voltage signal; The pulse width modulation signal and the voltage signal are used to control the switching state of the SiC MOSFET device, and the voltage signal is also used to control the switching state of the Si IGBT device.

[0012] Optionally, the voltage signal includes a first voltage signal, a second voltage signal, and a third voltage signal, and the pulse width modulation signal includes a first pulse width modulation signal and a second pulse width modulation signal; the first voltage signal and the second voltage signal are respectively used to control the switching state of one of the Si IGBT devices and the other Si IGBT device, the first pulse width modulation signal is used to control the switching state of one of the SiC MOSFET devices, and the second pulse width modulation signal and the third voltage signal are used to control the switching state of the other SiC MOSFET device.

[0013] Optionally, during charging, the first voltage signal and the second voltage signal are high-level signals, the third voltage signal is a low-level signal, the plurality of first pulse-width modulation signals are pulse-width modulation signals output according to a preset duty cycle, and the plurality of second pulse-width modulation signals are complementary pulse-width modulation signals; During discharge, the first voltage signal is a high-level signal, the second voltage signal and the third voltage signal are low-level signals, the first plurality of pulse-width modulation signals are pulse-width modulation signals output according to a duty cycle of a current closed-loop regulator, and the second plurality of pulse-width modulation signals are complementary pulse-width modulation signals; During energy feedback, the first voltage signal is a low-level signal, and the second voltage signal and the third voltage signal are high-level signals.

[0014] A third aspect of the embodiments of the present application provides a switching power supply for a semiconductor laser, comprising the synchronous interleaved parallel Buck pulse discharge circuit as described in the first aspect or the pulse discharge system as described in the second aspect.

[0015] It can be seen that the synchronous interleaved parallel Buck pulse discharge circuit provided in the embodiment of the present application is based on a synchronous rectification drive architecture of Si / SiC hybrid devices and energy feedback. This solution uses silicon carbide SiC MOSFET devices to achieve high-frequency and low-loss switching, and uses SiC IGBTs to undertake large-capacity energy feedback. It also introduces an interleaved parallel topology and synchronous rectification timing control. While improving system efficiency, it ensures that the pulse waveform has nanosecond edge characteristics and sub-ampere ripple accuracy, thereby effectively meeting the triple requirements of high-power semiconductor lasers for the driving power supply: high stability, high reliability, and high dynamic response.

[0016] Based on the same inventive concept, the beneficial effects of a pulse discharge system and a switching power supply provided in the embodiments of the present application refer to the beneficial effects of the synchronous interleaved parallel Buck pulse discharge circuit, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 A schematic diagram of the structure of a synchronous interleaved parallel Buck pulse discharge circuit provided by an embodiment of the present application is shown; Figure 2 A schematic diagram showing the state of a synchronous interleaved parallel Buck pulse discharge circuit during charging provided by an embodiment of the present application is shown; Figure 3 A schematic diagram showing the state of a synchronous interleaved parallel Buck pulse discharge circuit during discharge provided by one embodiment of the present application is shown; Figure 4A schematic diagram showing the state of a synchronous interleaved parallel Buck pulse discharge circuit during energy feedback provided by an embodiment of the present application is shown; Figure 5 A schematic structural diagram of a pulse discharge system provided by an embodiment of the present application is shown; Figure 6 A schematic diagram showing the control timing of each device when the synchronous interleaved parallel Buck pulse discharge circuit provided by one embodiment of the present application is in operation is shown; Figure 7 A schematic diagram of the pulse waveforms of the two-phase inductor shared current and the total output inductor current when the two-phase parallel synchronous interleaved parallel Buck pulse discharge circuit provided by one embodiment of the present application is in operation is shown; Figure 8 Shown Figure 7 Schematic diagram of the pulse waveform of the peak amplified part of the current shared by the two-phase inductors.

[0019] Figure 9 The waveform diagram shows the switching loss comparison between the synchronous rectification technology of the embodiment of the present application and the traditional buck. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0021] Please refer to Figure 1 , which shows a schematic diagram of the structure of a synchronous interleaved parallel Buck pulse discharge circuit provided by an embodiment of the present application. The synchronous interleaved parallel Buck pulse discharge circuit includes a power supply , busbar capacitance , multi-phase parallel synchronous rectification Buck circuit, energy feedback circuit and load LD; the power supply The positive electrode and the bus capacitor The first end of the multi-phase parallel synchronous rectification Buck circuit and the first end of the energy feedback circuit are connected, and the power supply The negative electrode and the bus capacitor The second end of the multi-phase parallel synchronous rectification Buck circuit, the second end of the energy feedback circuit, and the second end of the load LD are connected; the third end of the energy feedback circuit is connected to the output end of the multi-phase parallel synchronous rectification Buck circuit; and the fourth end of the energy feedback circuit is connected to the first end of the load LD; The synchronous rectification Buck circuit of each phase is controlled by a phase difference, and each phase of the synchronous rectification Buck circuit includes a synchronous rectification switch group composed of SiC MOSFET devices, and the energy feedback circuit includes a switch device composed of Si IGBT devices.

[0022] For example, the operating frequency of the SiC MOSFET device may be above 100 kHz, and the on-current capability of the Si IGBT device may be greater than or equal to 600 A.

[0023] For example, the bus capacitor may be a low ESR electrolytic capacitor group for storing feedback energy and providing an initial voltage platform for subsequent pulses.

[0024] For example, when the number of parallel phases is n, the phase difference of the drive signal of the synchronous rectifier Buck circuit of each phase is 360° / n, where n ≥ 2. This multi-phase parallel structure can evenly distribute the load current among the synchronous rectifier Buck circuits of each phase through phase difference distribution, thereby effectively reducing the electrical stress of single-phase devices and reducing output current ripple.

[0025] It can be seen that the synchronous interleaved parallel Buck pulse discharge circuit provided in the embodiment of the present application is based on a synchronous rectification drive architecture of Si / SiC hybrid devices and energy feedback. This solution uses silicon carbide SiC MOSFET devices to achieve high-frequency and low-loss switching, and uses SiC IGBTs to undertake large-capacity energy feedback. It also introduces an interleaved parallel topology and synchronous rectification timing control. While improving system efficiency, it ensures that the pulse waveform has nanosecond edge characteristics and sub-ampere ripple accuracy, thereby effectively meeting the triple requirements of high-power semiconductor lasers for the driving power supply: high stability, high reliability, and high dynamic response.

[0026] See also Figure 1 Each phase of the synchronous rectification Buck circuit includes a synchronous rectification switch group composed of two SiC MOSFET devices and an energy storage inductor L, wherein one of the SiC MOSFET devices The drain and the power supply The positive connection of one of the SiC MOSFET devices The source of the SiC MOSFET device is connected to the The drain of the SiC MOSFET is connected to one end of the energy storage inductor L, and the other end of the SiC MOSFET is connected to the drain of the SiC MOSFET The source of the power supply The other end of the multiple energy storage inductors L of the multi-phase parallel synchronous rectification Buck circuit is connected.

[0027] For example, when the number of parallel phases is n, one of the SiC MOSFET devices include , another SiC MOSFET device include The multi-phase parallel synchronous rectification Buck circuit employs a complementary upper and lower bridge arm structure, both of which are equipped with high-voltage SiC MOSFET devices. The upper arm uses SiC MOSFET devices to replace the freewheeling diode in the Buck circuit. Precise drive timing control eliminates dead-zone losses and significantly reduces reverse recovery losses. The lower arm uses SiC MOSFET devices, whose high-frequency characteristics significantly reduce switching and conduction losses.

[0028] It should be noted that one of the SiC MOSFET devices described here ( ) is the drain of the first end of the multi-phase parallel synchronous rectification Buck circuit, and the other SiC MOSFET device ( ) is the second end of the multi-phase parallel synchronous rectification Buck circuit.

[0029] See also Figure 1 The energy feedback circuit includes two switching devices composed of Si IGBT devices, the diode The negative pole of the power supply The positive terminal of the diode is connected The positive electrode and the other end of the energy storage inductor L and one of the Si IGBT devices The collector connection of one of the Si IGBT devices The emitter of another Si IGBT device The collector of the Si IGBT device is connected to the first end of the load LD. The emitter and the power supply The cathode of the load LD is connected to the second end of the load LD.

[0030] It should be noted that the diode here The negative electrode is the first end of the energy feedback circuit, the other end of the energy storage inductor L is the output end of the multi-phase parallel synchronous rectification Buck circuit, and the diode The positive electrode of one of the Si IGBT devices The collector is the second end of the energy feedback circuit, where one of the Si IGBT devices The emitter of another Si IGBT device The collector is the third terminal of the energy feedback circuit, and the other Si IGBT device The emitter is the fourth end of the energy feedback circuit.

[0031] It can be seen that the energy feedback circuit can feed back the remaining energy of the energy storage inductor to the bus capacitor during the pulse interval, thereby reducing energy consumption.

[0032] Next, combine Figure 2-Figure 4 The working principles of the three stages of charging, discharging and energy feedback of the synchronous interleaved parallel Buck pulse discharge circuit provided in the embodiment of the present application are described.

[0033] Please refer to Figure 2 , which shows a schematic diagram of the state of the synchronous interleaved parallel Buck pulse discharge circuit provided by an embodiment of the present application during charging. In one of the SiC MOSFET devices ( ) with two Si IGBT devices and are both in the on state, and the other SiC MOSFET device ( ) is in the off state, the power , one of the SiC MOSFET devices ), the energy storage inductor L and the two Si IGBT devices and An energy storage circuit is formed, and the energy storage circuit passes through the power supply The energy storage inductor L is charged.

[0034] Please refer to Figure 3 , which shows a schematic diagram of the state of the synchronous staggered parallel Buck pulse discharge circuit provided by an embodiment of the present application during discharge. In one of the SiC MOSFET devices ) with one of the Si IGBT devices are both in the on state, and the other SiC MOSFET device ( ) with another Si IGBT device are in the off state, the power , one of the SiC MOSFET devices, the energy storage inductor, one of the Si IGBT devices ) and the load LD form a discharge loop, and the discharge loop discharges to the outside through the load LD.

[0035] Please refer to Figure 4, which shows a schematic diagram of the state of the energy feedback of the synchronous staggered parallel Buck pulse discharge circuit provided by an embodiment of the present application. In one of the SiC MOSFET devices ) with two Si IGBT devices and are both in the off state, and the other SiC MOSFET device ( ) is in the on state, the bus capacitor , the diode , the energy storage inductor L and another SiC MOSFET device ( ) forms an energy feedback loop, which feeds back the energy stored in the energy storage inductor L to the bus capacitor .

[0036] Please refer to Figure 5 , which shows a schematic diagram of the structure of a pulse discharge system provided by an embodiment of the present application. The pulse discharge system includes Figure 1 The synchronous interleaved parallel Buck pulse discharge circuit and controller shown in the embodiment, Figure 5 In this paper, a two-phase parallel synchronous rectification Buck circuit is taken as an example, that is, one of the SiC MOSFET devices include and , another SiC MOSFET device include and .

[0037] The controller includes: a digital signal processor configured to generate programmable pulse waveform parameters for generating a pulse width modulated signal; The gate driving circuit is configured to generate a driving timing control signal, wherein the driving timing control signal is used to generate a voltage signal.

[0038] Furthermore, the digital signal processor may be a DSP TMS320F28379D, and the controller may further include a monitoring circuit. The monitoring circuit may be, for example, a Hall sensor that can monitor the current flowing through each phase of the energy storage inductor in real time.

[0039] The pulse width modulation signal and the voltage signal are used to control the switching state of the SiC MOSFET device, and the voltage signal is also used to control the switching state of the Si IGBT device.

[0040] The voltage signal includes a first voltage signal, a second voltage signal, and a third voltage signal, and the pulse width modulation signal includes a first pulse width modulation signal and a second pulse width modulation signal; the first voltage signal and the second voltage signal are respectively used to control the switching state of one of the Si IGBT devices and the other Si IGBT device, the first pulse width modulation signal is used to control the switching state of one of the SiC MOSFET devices, and the second pulse width modulation signal and the third voltage signal are used to control the switching state of the other SiC MOSFET device.

[0041] Exemplarily, the voltage signal includes a first voltage signal , the second voltage signal and the third voltage signal The pulse width modulation (PWM) signal includes a first pulse width modulation signal and , the second pulse width modulation signal and The first voltage signal and the second voltage signal are used to control one of the Si IGBT devices and another Si IGBT device The first pulse width modulation signal and are used to control one of the SiC MOSFET devices and The second pulse width modulation signal and and the third voltage signal Used to control another SiC MOSFET device and The switch status.

[0042] Furthermore, the second pulse width modulation signal and and the third voltage signal Used to control another SiC MOSFET device according to an OR operation (or) and The switch status.

[0043] Specifically, combined Figures 2 to 4 This section describes the control signals for the synchronous interleaved parallel Buck pulse discharge circuit. Figure 6 , which shows a schematic diagram of the control timing of each device when the synchronous interleaved parallel Buck pulse discharge circuit provided by an embodiment of the present application is working. The details are as follows: During charging, the first voltage signal and the second voltage signal are high level signals ( = =1), the third voltage signal is a low level signal ( =0), a plurality of the first pulse width modulation signals and is a pulse width modulation signal output according to a preset duty cycle, a plurality of the second pulse width modulation signals and is the output complementary pulse width modulation signal.

[0044] During discharge, the first voltage signal is a high level signal ( =1), the second voltage signal and the third voltage signal are low level signals ( = =0), a plurality of the first pulse width modulation signals and is a pulse width modulation signal output according to the duty cycle of the current closed-loop regulator, and the plurality of second pulse width modulation signals and is the output complementary pulse width modulation signal; Among them, the current closed-loop regulator can monitor the current of each phase in real time through the Hall sensor to achieve dynamic current sharing.

[0045] During energy feedback, the first voltage signal is a low level signal ( =0), the second voltage signal and the third voltage signal are high level signals ( = =1), does not output the first pulse width modulation signal and, that is, = =0, = =0. If the second pulse width modulation signal and and the third voltage signal Used to control another SiC MOSFET device according to an OR operation (or) and The switching state of the SiC MOSFET device and The signal received is a high voltage signal.

[0046] The drive signals for the upper and lower bridge arms are generated by high-speed gate drivers, with a strictly controlled dead-time of less than or equal to one hundredth of the switching period. The specific process is as follows: when the SiC MOSFET device in the upper bridge arm is turned off, the SiC MOSFET device in the lower bridge arm is immediately turned on, utilizing its low on-resistance to freewheel current and avoid excessive conduction losses in the body diode.

[0047] For example, the SiC MOSFET device of the two-phase interleaved parallel Buck pulse discharge circuit can be controlled by a first PWM signal with a phase difference of 180 degrees. The switch tube device of each phase Buck circuit ( and ; and ) alternately conducts, doubling the output current ripple frequency and effectively reducing the output filter inductance. Dynamic current sharing control uses Hall sensors to collect real-time current from each phase. A current closed-loop regulator (PI controller) adjusts the PWM duty cycle to ensure a current sharing error of less than 3%.

[0048] The energy regeneration circuit's operating sequence complements that of the buck circuit. During the pulse output discharge phase (pulse width 300μs), the lower-arm SiC MOSFET remains off. When the pulse ends and the rest period (700μs) begins, the lower-arm SiC MOSFET is triggered to turn on, transferring the remaining energy in the energy storage inductor back to the bus capacitor via the energy regeneration circuit. This regeneration process provides a regeneration path for the remaining energy in the inductor of each phase by providing a drive signal to the lower-arm switching transistor of each buck phase, achieving an energy recovery efficiency exceeding 80%. Simultaneously, the regeneration operation precharges the bus capacitor voltage to the initial value required for the next pulse, shortening the pulse rise time.

[0049] Please refer to Figure 7 and Figure 8 , Figure 7 The figure shows the pulse waveforms of the two-phase inductor shared current and the total output inductor current when the two-phase parallel synchronous interleaved parallel Buck pulse discharge circuit provided by one embodiment of the present application is working. Figure 8 Shown Figure 7 Schematic diagram of the pulse waveform of the peak amplified part of the current shared by the two-phase inductors.

[0050] In order to further simulate and verify the performance, experiments were conducted under the conditions of 1kHz repetition frequency and 300μs pulse width. The results are as follows Figure 9 As shown in the figure, compared with the traditional asynchronous rectification Buck circuit, the synchronous rectification solution of the embodiment of the present application reduces the total switching loss by 59% (from 196W to 81W). The output total current pulse waveform rise / fall time is ≤50ns, and the peak-to-peak current ripple is less than 2A, meeting the high dynamic requirements of semiconductor lasers.

[0051] The embodiment of the present application also provides a switching power supply for a semiconductor laser, the switching power supply comprising: Figure 1 The synchronous interleaved parallel Buck pulse discharge circuit described in the embodiment or Figure 5 The pulse discharge system described in the embodiment.

[0052] It should be understood that the specific examples in this application are only intended to help those skilled in the art better understand the embodiments of this application, rather than to limit the scope of the present invention.

[0053] It can be understood that in the various implementation methods of this application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the implementation method of this application.

[0054] It can be understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited to this.

[0055] Unless otherwise indicated, all technical and scientific terms used in the embodiments of the present application have the same meaning as those commonly understood by those skilled in the art in the technical field of the present application. The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit the scope of this application. The term "and / or" used in this application includes any and all combinations of one or more related listed items. The singular forms "a", "above", and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates otherwise.

[0056] It is understood that the processor in the embodiments of the present application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above-mentioned method embodiment can be completed by hardware integrated logic circuits in the processor or software instructions. The above-mentioned processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The various methods, steps, and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiments of the present application can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium mature in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc. The storage medium is located in the memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above-mentioned method.

[0057] It will be understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (programmable ROM, PROM), an erasable programmable read-only memory (erasable PROM, EPROM), an electrically erasable programmable read-only memory (EEPROM) or flash memory. The volatile memory may be a random access memory (RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0058] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0059] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, devices and units can refer to the corresponding processes in the aforementioned method implementation methods and will not be repeated here.

[0060] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0061] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0062] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0063] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various implementation methods of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0064] The above are only specific embodiments of the present application, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A synchronous interleaved parallel Buck pulse discharge circuit, characterized in that: The device comprises a power supply, a bus capacitor, a multi-phase parallel synchronous rectification Buck circuit, an energy feedback circuit, and a load; the positive electrode of the power supply is connected to the first end of the bus capacitor, the first end of the multi-phase parallel synchronous rectification Buck circuit, and the first end of the energy feedback circuit; the negative electrode of the power supply is connected to the second end of the bus capacitor, the second end of the multi-phase parallel synchronous rectification Buck circuit, the second end of the energy feedback circuit, and the second end of the load; the third end of the energy feedback circuit is connected to the output end of the multi-phase parallel synchronous rectification Buck circuit; and the fourth end of the energy feedback circuit is connected to the first end of the load; The synchronous rectification Buck circuit of each phase is controlled by a phase difference, and each phase of the synchronous rectification Buck circuit includes a synchronous rectification switch group composed of SiC MOSFET devices, and the energy feedback circuit includes a switch device composed of Si IGBT devices.

2. The synchronous interleaved parallel Buck pulse discharge circuit according to claim 1, characterized in that: Each phase of the synchronous rectification Buck circuit includes a synchronous rectification switch group consisting of two SiC MOSFET devices and an energy storage inductor, wherein the drain of one of the SiC MOSFET devices is connected to the positive electrode of the power supply, the source of one of the SiC MOSFET devices is connected to the drain of the other SiC MOSFET device and one end of the energy storage inductor, and the source of the other SiC MOSFET device is connected to the negative electrode of the power supply; the other ends of the multiple energy storage inductors of the multi-phase parallel synchronous rectification Buck circuit are connected.

3. The synchronous interleaved parallel Buck pulse discharge circuit according to claim 2, characterized in that: The energy feedback circuit includes two switching devices consisting of Si IGBT devices, the cathode of the diode is connected to the positive electrode of the power supply, the anode of the diode is connected to the other end of the energy storage inductor and the collector of one of the Si IGBT devices, the emitter of one of the Si IGBT devices is connected to the collector of the other Si IGBT device and the first end of the load, and the emitter of the other Si IGBT device is connected to the negative electrode of the power supply and the second end of the load.

4. The synchronous interleaved parallel Buck pulse discharge circuit according to claim 3, characterized in that: When one of the SiC MOSFET devices and the two Si IGBT devices are in the on state, and the other SiC MOSFET device is in the off state, the power supply, one of the SiC MOSFET devices, the energy storage inductor, and the two Si IGBT devices form an energy storage loop, and the energy storage loop charges the energy storage inductor through the power supply.

5. The synchronous interleaved parallel Buck pulse discharge circuit according to claim 4, characterized in that: When one of the SiC MOSFET devices and one of the Si IGBT devices are both in the on state, and the other SiC MOSFET device and the other Si IGBT device are both in the off state, the power supply, one of the SiC MOSFET devices, the energy storage inductor, one of the Si IGBT devices, and the load form a discharge loop, and the discharge loop discharges to the outside through the load.

6. The synchronous interleaved parallel Buck pulse discharge circuit according to claim 5, characterized in that: When one of the SiC MOSFET devices and the two Si IGBT devices are in the off state, and the other SiC MOSFET device is in the on state, the bus capacitor, the diode, the energy storage inductor and the other SiC MOSFET device form an energy feedback loop, and the energy feedback loop feeds back the energy stored in the energy storage inductor to the bus capacitor.

7. A pulse discharge system, characterized in that: The synchronous interleaved parallel Buck pulse discharge circuit and controller according to claim 6 are characterized in that the controller includes: a digital signal processor configured to generate programmable pulse waveform parameters for generating a pulse width modulated signal; a gate driving circuit configured to generate a driving timing control signal, wherein the driving timing control signal is used to generate a voltage signal; The pulse width modulation signal and the voltage signal are used to control the switching state of the SiC MOSFET device, and the voltage signal is also used to control the switching state of the Si IGBT device.

8. The pulse discharge system according to claim 7, characterized in that: The voltage signal includes a first voltage signal, a second voltage signal, and a third voltage signal, and the pulse width modulation signal includes a first pulse width modulation signal and a second pulse width modulation signal; the first voltage signal and the second voltage signal are respectively used to control the switching state of one of the Si IGBT devices and the other Si IGBT device, the first pulse width modulation signal is used to control the switching state of one of the SiC MOSFET devices, and the second pulse width modulation signal and the third voltage signal are used to control the switching state of the other SiC MOSFET device.

9. The pulse discharge system according to claim 8, characterized in that: During charging, the first voltage signal and the second voltage signal are high-level signals, the third voltage signal is a low-level signal, the plurality of first pulse-width modulation signals are pulse-width modulation signals output according to a preset duty cycle, and the plurality of second pulse-width modulation signals are complementary pulse-width modulation signals; During discharge, the first voltage signal is a high-level signal, the second voltage signal and the third voltage signal are low-level signals, the first plurality of pulse-width modulation signals are pulse-width modulation signals output according to a duty cycle of a current closed-loop regulator, and the second plurality of pulse-width modulation signals are complementary pulse-width modulation signals; During energy feedback, the first voltage signal is a low-level signal, and the second voltage signal and the third voltage signal are high-level signals.

10. A switching power supply for a semiconductor laser, characterized in that: It comprises the synchronous interleaved parallel Buck pulse discharge circuit as described in any one of claims 1 to 6 or the pulse discharge system as described in any one of claims 7 to 9.

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