High-precision clock circuit and control method thereof

Abstract

The invention discloses a high-precision clock circuit and a control method thereof.By arranging a voltage reducing and stabilizing circuit, an oblique wave generating circuit and a hysteresis comparator circuit, an RC charging and discharging unit receives power supply voltage VCC processed by a voltage stabilizing unit and outputs a clock voltage signal to the hysteresis comparator circuit; the comparison unit receives a ramp signal generated by the RC trimming unit controlled by the switch unit, the comparison unit drives the phase adjustment unit to output a target clock signal according to the ramp signal and a clock voltage signal, the power supply interference resistance of the clock circuit is enhanced, and the ramp signal is generated for the RC trimming unit through on-off of the switch unit; the hysteresis comparator uses the ramp signal as the clock frequency deviation caused by the input adjustable process deviation, and the output end of the hysteresis comparator is connected with the phase adjusting unit to output a complete target clock signal, thereby reducing the influence of the input end signal and the power jitter on the generation of the clock signal, avoiding the generation of burrs or mistaken overturning, and improving the reliability of the clock signal. The circuit structure is highly integrated, and the working stability of the circuit is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a high-precision clock circuit and a control method thereof. Background Art

[0002] Clocks are widely used in various chips. To reduce chip power consumption, the circuit requires at least two clocks: a high-speed clock (typically 16 MHz) and a low-frequency clock (e.g., 32 kHz) for waking from sleep mode. Some chips with high oscillator frequency accuracy often use an external crystal oscillator as the clock source. However, crystal oscillators are expensive and consume a lot of power, making their application costly. Furthermore, some chip applications not only require high clock accuracy but are also unsuitable for integrating an external crystal oscillator, making the use of an internal high-precision oscillator inevitable. Currently, most oscillators in existing technologies use either a resistor-capacitor charge-discharge (RC) or constant-current charge-discharge (CC) oscillation structure. However, due to process influences on the resistor-capacitor (RC) structure, clock deviations are significant. Furthermore, clock circuits are also affected by power supply voltage, temperature, reference voltage, and current. The output clock frequency often varies by around 20%, with variations as high as 50% at worst. Fine-tuning the RC or current can reduce this deviation to ±10%, but this ±10% is primarily affected by voltage and temperature, significantly impacting the overall system.

[0003] For example, Figure 1 It is a relatively traditional constant current charge and discharge clock circuit structure. The clock circuit structure mainly consists of three parts: a current mirror circuit, a ramp wave generation circuit and a non-overlapping clock generation circuit. IREF is a bandgap reference current with a temperature coefficient close to zero generated by BGR (Bandgap voltage reference). The current mirror circuit generates a charge and discharge current to charge capacitors C1 and C2, and generates non-overlapping clocks CKA and CKB through triggers NOR1 and NOR2 to feed back to transistors MN1 and MN3, generating a complete clock cycle and a complete clock signal at the output. After the circuit is stable, a fixed-frequency clock signal can be obtained. Figure 2 It is a clock circuit structure that uses a resistor and capacitor charging and discharging method. The clock circuit mainly consists of three parts: a reference voltage generation circuit, a comparison voltage generation circuit, and a comparator circuit. The reference voltage generated by the resistor voltage divider is compared with the voltage obtained by charging and discharging the resistor and capacitor. The comparator outputs a fixed clock signal.

[0004] However, most resistors R and capacitors C have temperature coefficients. In particular, the positive temperature coefficient of resistors can easily cause the clock frequency to change with temperature. Most chips typically have a single power supply, VCC, and rarely use an LDO for power. Consequently, the clock module and other modules of most chips share the same VCC. Sudden changes in VCC can cause the clock output frequency to change, affecting clock accuracy. They can also easily cause output glitches that can affect chip operation. Battery power can lose power during use, and the process of voltage dropping from a higher voltage to a lower voltage can also affect clock accuracy. Therefore, a precise clock frequency is essential for accurate chip operation. A high-precision clock circuit with low temperature drift, minimal voltage fluctuations, and strong anti-interference capabilities is urgently needed for chip development. Summary of the Invention

[0005] In view of this, the present invention provides a high-precision clock circuit and a control method thereof, which can output a clock circuit structure with small frequency, temperature and voltage deviation and strong resistance to power supply interference. The clock circuit structure has high integration and is specifically implemented using the following technical solutions.

[0006] In a first aspect, the present invention provides a high-precision clock circuit, the high-precision clock circuit comprising a step-down voltage regulator circuit, a ramp wave generating circuit, and a hysteresis comparator circuit, wherein the step-down voltage regulator circuit and the ramp wave generating circuit are both connected to the hysteresis comparator circuit;

[0007] The step-down voltage stabilization circuit includes a voltage stabilization unit and an RC charge and discharge unit, the voltage stabilization unit is used to input a power supply voltage VCC, the RC charge and discharge unit is connected to the voltage stabilization unit, and the RC charge and discharge unit is used to receive the power supply voltage VCC processed by the voltage stabilization unit and output a clock voltage signal to the hysteresis comparator circuit;

[0008] The hysteresis comparator circuit includes a comparison unit connected to the RC charge and discharge unit and a phase adjustment unit connected to the comparison unit. The ramp wave generating circuit includes a switch unit and an RC adjustment unit. The switch unit is connected to the comparison unit, the switch unit is connected to one end of the RC adjustment unit, the other end of the RC adjustment unit is connected to the phase adjustment unit, and the switch unit is connected to the phase adjustment unit.

[0009] The comparison unit receives the ramp signal generated by the switch unit to control the RC trimming unit, and the comparison unit drives the phase adjustment unit to output a corresponding target clock signal according to the ramp signal and the clock voltage signal.

[0010] As a preferred embodiment of the above technical solution, the voltage stabilizing unit includes a transistor NM1, a transistor NM2, a transistor NM3, a transistor NM4, a transistor NM5, a transistor NM6, a transistor PM1 and a transistor PM2, the RC charge and discharge unit includes a resistor R1 and a capacitor C1, the source of the transistor NM1 is connected to the source of the transistor PM1, the drain of the transistor NM1 is used to receive the reference current IREF0 provided by the bandgap reference source, the gate of the transistor NM1 is connected to the drain of the transistor NM1 and the source of the transistor PM1, the gate of the transistor PM1 is connected to the gate of the transistor NM3, the drain of the transistor PM1, and the gate of the transistor The drain of transistor NM3 is connected, the source of transistor NM3 is connected to the drain of transistor NM5, the gate of transistor NM5, the gate of transistor NM4, and the gate of transistor NM6, the drain of transistor NM2 is used to input the power supply voltage VCC, the source of transistor NM2 is connected to the source of transistor PM2 and one end of resistor R1, the gate of transistor PM2 is connected to the drain of transistor PM2 and the drain of transistor NM4, the source of transistor NM4 is connected to the drain of transistor NM6, the other end of resistor R1 is connected to capacitor C1 and the comparison unit, the source of transistor NM5 is connected to the source of transistor NM6, capacitor C1 and grounded.

[0011] As a preferred embodiment of the above technical solution, the switching unit includes a transistor NM7, a transistor NM8, a transistor NM9, a transistor NM10, a transistor NM11 and a transistor NM12, the RC trimming unit includes a resistor R2, a capacitor C2 and a capacitor C3, the source of the transistor NM7 is connected to the drain of the transistor NM10 and one end of the capacitor C2, the drain of the transistor NM7 is connected to the reference current IREF1 provided by the bandgap reference source and the drain of the transistor NM8, the gate of the transistor NM8 is connected to the phase adjustment unit, the source of the transistor NM8 is connected to one end of the resistor R2 and the transistor NM9, and the transistor N The drain of M9 is connected to the reference current IREF2 provided by the bandgap reference source and the drain of transistor NM10. The source of transistor NM10 is connected to one end of capacitor C3 and the drain of transistor NM12. The source of transistor NM12 is connected to the other end of capacitor C3, the other end of resistor R2, the other end of capacitor C2, the source of transistor NM11, and the phase adjustment unit and is grounded. The gate of transistor NM7, the gate of transistor NM8, the gate of transistor NM9, the gate of transistor NM9, the gate of transistor NM10, the gate of transistor NM11, and the gate of transistor NM12 are all connected to the phase adjustment unit.

[0012] As a preferred embodiment of the above technical solution, the comparison unit includes a hysteresis comparator, the inverting input terminal of the hysteresis comparator is connected to the reference current IREF1, the drain of the transistor NM7, and the drain of the transistor NM8, and the non-inverting input terminal of the hysteresis comparator is connected to the reference current IREF2, the drain of the transistor NM9, and the drain of the transistor NM10;

[0013] The phase adjustment unit includes an inverter INV1, an inverter INV2, an inverter INV3 and an inverter INV4, an input end of the inverter INV1 is connected to the output end of the hysteresis comparator, an input end of the inverter INV1 is connected to the output end of the hysteresis comparator, an output end of the inverter INV1 is connected to the input end of the inverter INV2, an output end of the inverter INV2 is connected to the input end of the inverter INV3, an output end of the inverter INV3 is connected to the input end of the inverter INV4, and an output end of the inverter INV4 outputs the target clock signal;

[0014] The output end of the inverter INV1 and the input end of the inverter INV2 generate a non-overlapping clock signal CKA and are connected to the gates of the transistors NM7, NM9, and NM12. The output end of the inverter INV2 and the input end of the inverter INV3 generate a non-overlapping clock signal CKB and are connected to the gates of the transistors NM8, NM10, and NM11.

[0015] As a preferred embodiment of the above technical solution, when the voltage stabilizing unit receives the reference current IREF0, the transistor NM6 and the transistor NM5 form a current mirror structure, and the transistor NM6 copies the current of the transistor NM5;

[0016] When the V_CLK voltage corresponding to the clock voltage signal is equal to the source-drain voltage drop of transistor NM5 plus the sum of the threshold voltages of transistors NM3 and PM1, the sizes of transistors PM1 and NM3 are adjusted to obtain clock voltage signals of different voltage values.

[0017] As a preferred embodiment of the above technical solution, the hysteresis comparator is also connected to the reference current IREF3 provided by the bandgap reference source, and the hysteresis comparator controls the reference current IREF3 according to the reference current IREF1 and the reference current IREF2 to perform temperature compensation on the positive temperature coefficient corresponding to the clock voltage signal, wherein the reference current IREF1 and the reference current IREF2 are zero temperature coefficient reference currents, and the reference current IREF3 is a negative temperature coefficient reference current.

[0018] As a preferred embodiment of the above technical solution, when the power supply voltage VCC is powered off, the V_CLK voltage is 2V; when the power supply voltage VCC is lower than 2V, the V_CLK voltage is approximately equal to the power supply voltage VCC, wherein the power supply voltage VCC is 1.8V~5.5V, the resistance value of the resistor R1 is 1KΩ, the resistor R2 is a variable resistor, and the capacitors C2 and C3 are variable capacitors.

[0019] As a preferred embodiment of the above technical solution, the phases of the non-overlapping clock signal CKA and the non-overlapping clock signal CKB are opposite, the switching unit is a symmetrical structure including multiple NMOS tubes, and the non-overlapping clock signal CKA and the non-overlapping clock signal CKB are used to control the switching of multiple NMOS tubes to generate a ramp signal with a duty cycle of 50%.

[0020] As a preferred embodiment of the above technical solution, when the non-overlapping clock signal CKA is at a high level and the non-overlapping clock signal CKB is at a low level, the transistor NM7, the transistor NM9 and the transistor NM12 are turned on, the transistor NM8, the transistor NM10 and the transistor NM11 are turned off, the capacitor C2 is charged and the capacitor C1 is discharged;

[0021] When the non-overlapping clock signal CKA is low and the non-overlapping clock signal CKB is high, transistors NM7 , NM9 and NM12 are turned off, transistors NM8 , NM10 and NM11 are turned on, capacitor C2 is discharged and capacitor C1 is charged.

[0022] In a second aspect, the present invention further provides a control method for a high-precision clock circuit, which is applied to the above-mentioned high-precision clock circuit and comprises the following steps:

[0023] Obtain the power supply voltage VCC received by the RC charge and discharge unit and processed by the voltage stabilizing unit;

[0024] controlling the RC charge and discharge unit to output a clock voltage signal to the hysteresis comparator circuit according to the power supply voltage VCC;

[0025] Acquire the ramp signal generated by the RC trimming unit controlled by the comparison unit receiving the switch unit;

[0026] The phase adjustment unit is driven according to the ramp signal and the clock voltage signal to output a corresponding target clock signal.

[0027] The present invention provides a high-precision clock circuit and a control method thereof. A step-down voltage stabilization circuit, a ramp wave generation circuit, and a hysteresis comparator circuit are provided. An RC charge and discharge unit receives a power supply voltage VCC processed by the voltage stabilization unit and outputs a clock voltage signal to the hysteresis comparator circuit. A comparison unit receives a ramp wave signal generated by an RC trimming unit controlled by a switch unit. The comparison unit drives a phase adjustment unit to output a corresponding target clock signal based on the ramp wave signal and the clock voltage signal. The step-down voltage stabilization circuit includes the voltage stabilization unit and the RC charge and discharge unit, and can effectively filter the input power supply voltage VCC, thereby enhancing the clock circuit's ability to resist power supply interference. The switching unit generates a ramp wave signal for the RC trimming unit when the switch unit is turned on. The hysteresis comparator uses the ramp wave signal as input to adjust the clock frequency deviation caused by process deviation. The output end of the hysteresis comparator is connected to the phase adjustment unit to output a complete target clock signal, thereby reducing the influence of the input end signal and power supply jitter on the clock signal generation, avoiding glitches or false flips, and having a high circuit structure integration, which also improves the working stability of the clock circuit to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0029] Figure 1 A circuit diagram of a constant current charging and discharging clock circuit structure in the prior art;

[0030] Figure 2 A circuit diagram of a clock circuit structure using a resistor-capacitor charge-discharge method in the prior art;

[0031] Figure 3 A structural block diagram of the high-precision clock circuit provided by the present invention;

[0032] Figure 4 A circuit diagram of a high-precision clock circuit provided by the present invention;

[0033] Figure 5 A time relationship diagram of the high-precision clock circuit provided by the present invention;

[0034] Figure 6 A graph showing the relationship between the clock period T1 provided by the present invention and the temperature;

[0035] Figure 7 The waveform diagram of the temperature characteristic simulation result of the prior art;

[0036] Figure 8It is the voltage characteristic simulation waveform diagram;

[0037] Figure 9 Simulation waveform diagram for anti-power interference characteristics;

[0038] Figure 10 The clock temperature characteristic simulation waveform provided by the present invention;

[0039] Figure 11 The clock voltage characteristic simulation waveform diagram provided by the present invention;

[0040] Figure 12 The circuit diagram of the LDO circuit replacing the buck regulator circuit;

[0041] Figure 13 This is a flow chart of the control method of the high-precision clock circuit provided by the present invention.

[0042] The main component symbols are described as follows:

[0043] 10- buck stabilizing circuit; 11- voltage stabilizing unit; 12- RC charging and discharging unit; 20- hysteresis comparator circuit; 21- comparison unit; 22- phase adjustment unit; 30- ramp wave generating circuit; 31- switching unit; 32- RC trimming unit. DETAILED DESCRIPTION

[0044] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0045] See Figure 3 and Figure 4 The present invention provides a high-precision clock circuit, which includes a step-down voltage regulator circuit 10, a ramp wave generating circuit 20, and a hysteresis comparator circuit 30. The step-down voltage regulator circuit 10 and the ramp wave generating circuit 30 are both connected to the hysteresis comparator circuit 20.

[0046] The step-down voltage stabilization circuit 10 includes a voltage stabilization unit 11 and an RC charge-discharge unit 12. The voltage stabilization unit 11 is used to input a power supply voltage VCC. The RC charge-discharge unit 12 is connected to the voltage stabilization unit 11. The RC charge-discharge unit 12 is used to receive the power supply voltage VCC processed by the voltage stabilization unit 11 and output a clock voltage signal to the hysteresis comparator circuit 20.

[0047] The hysteresis comparator circuit 20 includes a comparison unit 21 connected to the RC charge and discharge unit 12 and a phase adjustment unit 22 connected to the comparison unit 21. The ramp wave generating circuit 30 includes a switch unit 31 and an RC adjustment unit 32. The switch unit 31 is connected to the comparison unit 21. The switch unit 31 is connected to one end of the RC adjustment unit 32. The other end of the RC adjustment unit 32 is connected to the phase adjustment unit 22. The switch unit 31 is connected to the phase adjustment unit 22.

[0048] The comparison unit 21 receives the ramp signal generated by the switch unit 31 to control the RC trimming unit 32 , and drives the phase adjustment unit 22 to output a corresponding target clock signal according to the ramp signal and the clock voltage signal.

[0049] In this embodiment, the voltage stabilizing unit 11 includes a transistor NM1, a transistor NM2, a transistor NM3, a transistor NM4, a transistor NM5, a transistor NM6, a transistor PM1 and a transistor PM2, the RC charge and discharge unit includes a resistor R1 and a capacitor C1, the source of the transistor NM1 is connected to the source of the transistor PM1, the drain of the transistor NM1 is used to receive the reference current IREF0 provided by the bandgap reference source, the gate of the transistor NM1 is connected to the drain of the transistor NM1 and the source of the transistor PM1, the gate of the transistor PM1 is connected to the gate of the transistor NM3, the drain of the transistor PM1, and the transistor NM 3, the source of transistor NM3 is connected to the drain of transistor NM5, the gate of transistor NM5, the gate of transistor NM4, and the gate of transistor NM6. The drain of transistor NM2 is used to input the power supply voltage VCC. The source of transistor NM2 is connected to the source of transistor PM2 and one end of resistor R1. The gate of transistor PM2 is connected to the drain of transistor PM2 and the drain of transistor NM4. The source of transistor NM4 is connected to the drain of transistor NM6. The other end of resistor R1 is connected to capacitor C1 and the comparison unit. The source of transistor NM5 is connected to the source of transistor NM6, capacitor C1 and ground.

[0050] Wherein, the comparison unit 21 includes a hysteresis comparator ( Figure 3101), the inverting input terminal of the hysteresis comparator is connected to the reference current IREF1, the drain of the transistor NM7, and the drain of the transistor NM8, and the non-inverting input terminal of the hysteresis comparator is connected to the reference current IREF2, the drain of the transistor NM9, and the drain of the transistor NM10; the phase adjustment unit 22 includes an inverter INV1, an inverter INV2, an inverter INV3 and an inverter INV4, the input terminal of the inverter INV1 is connected to the output terminal of the hysteresis comparator, the input terminal of the inverter INV1 is connected to the output terminal of the hysteresis comparator, and the output terminal of the inverter INV1 is connected to the input terminal of the inverter INV2. The output end of the inverter INV2 is connected to the input end of the inverter INV3, the output end of the inverter INV3 is connected to the input end of the inverter INV4, and the output end of the inverter INV4 outputs the target clock signal; the output end of the inverter INV1 and the input end of the inverter INV2 generate a non-overlapping clock signal CKA and are connected to the gate of the transistor NM7, the gate of the transistor NM9, and the gate of the transistor NM12, the output end of the inverter INV2 and the input end of the inverter INV3 generate a non-overlapping clock signal CKB and are connected to the gate of the transistor NM8, the gate of the transistor NM10, and the gate of the transistor NM11.

[0051] It should be noted that the switch unit 31 includes a transistor NM7, a transistor NM8, a transistor NM9, a transistor NM10, a transistor NM11 and a transistor NM12, the RC trimming unit includes a resistor R2, a capacitor C2 and a capacitor C3, the source of the transistor NM7 is connected to the drain of the transistor NM10 and one end of the capacitor C2, the drain of the transistor NM7 is connected to the reference current IREF1 provided by the bandgap reference source and the drain of the transistor NM8, the gate of the transistor NM8 is connected to the phase adjustment unit, the source of the transistor NM8 is connected to one end of the resistor R2 and the transistor NM9, and the gate of the transistor NM9 is connected to the phase adjustment unit. The drain is connected to the reference current IREF2 provided by the bandgap reference source and the drain of the transistor NM10. The source of the transistor NM10 is connected to one end of the capacitor C3 and the drain of the transistor NM12. The source of the transistor NM12 is connected to the other end of the capacitor C3, the other end of the resistor R2, the other end of the capacitor C2, the source of the transistor NM11, the phase adjustment unit 22 and grounded. The gate of the transistor NM7, the gate of the transistor NM8, the gate of the transistor NM9, the gate of the transistor NM9, the gate of the transistor NM10, the gate of the transistor NM11, and the gate of the transistor NM12 are all connected to the phase adjustment unit 22.

[0052] Among them, the step-down voltage regulator circuit 10 can generate a fixed voltage of about 2.2V, that is, the output V_CLK voltage is guaranteed to be fixed at 2.2V during the power-down process of the power supply voltage VCC from the maximum voltage of 5.5V. When ripple appears on the power supply voltage VCC, the ripple amplitude will be reduced by about 2.5 times after being processed by the step-down voltage regulator circuit 10, which is beneficial to reducing the interference of ripple on the clock. The ramp wave generation circuit 30 generates a ramp wave (ramp wave signal) by charging and discharging the capacitor in the RC trimming unit 32 through the transistors (switches) in the switching unit 31 alternately turning on and off (conducting and disconnecting). The generated ramp wave serves as the positive and negative input signals of the comparison unit 21. The resistance and capacitance of the ramp wave generation circuit 30 are both adjustable resistance and capacitance to adjust the clock frequency deviation caused by process deviation. The hysteresis comparator circuit 20 uses the ramp wave generated by the ramp wave generating circuit 30 as the input signal of the hysteresis comparator, and outputs a complete clock signal (target clock signal) through the hysteresis comparator. The hysteresis comparator can reduce the influence of the input signal and power supply jitter on the clock signal generation, and avoid glitches or false flips.

[0053] It should be understood that by providing the step-down voltage regulator circuit 10, the ramp wave generating circuit 30, and the hysteresis comparator circuit 20, the RC charge and discharge unit 12 receives the power supply voltage VCC processed by the voltage regulator unit 11 and outputs a clock voltage signal to the hysteresis comparator circuit 20. The comparison unit 21 receives the ramp wave signal generated by the RC trimming unit 32 under the control of the switch unit 31. The comparison unit 21 drives the phase adjustment unit 22 according to the ramp wave signal and the clock voltage signal to output the corresponding target clock signal. The step-down voltage regulator circuit 10 includes the voltage regulator unit 11 and the RC charge and discharge unit 12, which can effectively filter the input power supply voltage VCC and enhance the clock circuit's ability to resist power supply interference. The switching of the switch unit 31 generates a ramp wave signal for the RC trimming unit 32. The hysteresis comparator uses the ramp wave signal as input to adjust the clock frequency deviation caused by process deviation. The output end of the hysteresis comparator is connected to the phase adjustment unit 22 to output a complete target clock signal, reducing the impact of the input signal and power supply jitter on the clock signal generation, avoiding glitches or false flips. The circuit structure has a high degree of integration and also improves the operating stability of the clock circuit to a certain extent.

[0054] Optionally, when the voltage stabilizing unit 11 receives the reference current IREF0, transistor NM6 and transistor NM5 form a current mirror structure, and transistor NM6 replicates the current of transistor NM5; when the V_CLK voltage corresponding to the clock voltage signal is equal to the source-drain voltage drop of transistor NM5 plus the sum of the threshold voltages of transistor NM3 and transistor PM1, the sizes of transistor PM1 and transistor NM3 are adjusted to obtain clock voltage signals with different voltage values.

[0055] In this embodiment, the hysteresis comparator is further connected to a reference current IREF3 provided by a bandgap reference source. The hysteresis comparator controls reference current IREF3 based on reference currents IREF1 and IREF2 to perform temperature compensation on the positive temperature coefficient corresponding to the clock voltage signal. Reference currents IREF1 and IREF2 are zero temperature coefficient reference currents, and reference current IREF3 is a negative temperature coefficient reference current. When power supply voltage VCC fails, V_CLK is 2V; when power supply voltage VCC is lower than 2V, V_CLK is approximately equal to power supply voltage VCC. Power supply voltage VCC is between 1.8V and 5.5V. Resistor R1 has a resistance of 1KΩ, resistor R2 is a variable resistor, and capacitors C2 and C3 are variable capacitors.

[0056] It should be noted that the non-overlapping clock signals CKA and CKB have opposite phases. The switch unit 31 is a symmetrical structure comprising multiple NMOS transistors. The non-overlapping clock signals CKA and CKB are used to control the on / off switching of the multiple NMOS transistors to generate a ramp signal with a 50% duty cycle. When the non-overlapping clock signal CKA is high and the non-overlapping clock signal CKB is low, transistors NM7, NM9, and NM12 are turned on, while transistors NM8, NM10, and NM11 are turned off, causing capacitor C2 to charge and capacitor C1 to discharge. When the non-overlapping clock signal CKA is low and the non-overlapping clock signal CKB is high, transistors NM7, NM9, and NM12 are turned off, while transistors NM8, NM10, and NM11 are turned on, causing capacitor C2 to discharge and capacitor C1 to charge.

[0057] Specifically, the reference current IREF0 in the buck regulator circuit 10 is a zero-temperature-coefficient current provided by the reference current source BGR. Transistor NM6 and transistor NM5 form a current mirror structure, and transistor NM6 replicates the current of transistor NM5 to ensure normal operation of the circuit. The V_CLK voltage is equal to the source-drain voltage drop of transistor NM5 plus the sum of the threshold voltages of transistors NM3 and PM1. By adjusting the sizes of transistors PM1 and NM3, different V_CLK voltages can be obtained. Typically, the chip power supply VCC is between 1.8V and 5.5V, and V_CLK is designed to be around 2V.

[0058] When the power supply voltage VCC is powered down, the clock circuit power supply remains at 2V. When the power supply VCC is below 2V, the output voltage V_CLK is approximately equal to the VCC voltage. When the external power supply VCC drops from 5.5V to 1.8V, the voltage change relative to the clock circuit's V_CLK voltage is only approximately 0.2V. This significantly improves the voltage characteristic, i.e., the clock frequency's voltage-dependent behavior. Large power supply voltage changes result in minimal frequency changes. When jitter occurs on the power supply VCC, the ripple amplitude (i.e., the difference between the maximum and minimum ripple voltage values) transmitted to the clock circuit after passing through the buck regulator circuit is reduced by approximately 2.5 times. A low-pass filter is added between the buck regulator circuit 10 and the hysteresis comparator circuit 20. The combined effect of these two factors significantly reduces the impact of power supply jitter on the clock frequency. The resistance of the low-pass filter should be designed to be within 1KΩ.

[0059] Specifically, the ramp wave generating circuit 30 is composed of two symmetrical structures to ensure that the generated clock duty cycle is 50%. (Non-overlapping clock signals) CKA and CKB are two opposite signals that alternately control the on and off of each NMOS transistor in the ramp wave generating circuit. When CKA is high and CKB is low, transistors NM7, NM9, and NM12 are turned on, and transistors NM8, NM10, and NM11 are turned off. Capacitor C2 is charged and capacitor C1 is discharged. The voltage at the MP terminal (non-inverting input terminal) is U = IREF2 * R2, and the voltage at the MN terminal (inverting input terminal) is U = (IREF1 * t1) / C2.

[0060] When CKA is low and CKB is high, transistors NM7, NM9, and NM12 are turned off, transistors NM8, NM10, and NM11 are turned on, capacitor C2 is discharged, and capacitor C1 is charged. The voltage at the MN terminal is U=IREF1*R1, and the voltage at the MP terminal is U=(IREF2*t3) / C3. According to the symmetrical structure of the circuit design, C2=C3; the time of half a cycle T1 is the sum of the capacitor charging time t1(t3) and the delay time t2(t4) of the hysteresis comparator, so T1=t1+t2(T2=t3=t4), and the time of one cycle is T=T1+T2. The time relationship is as follows: Figure 5 shown.

[0061] From the theoretical formula, it can be obtained that t1 / t3=R*C has nothing to do with the reference current, but only with the resistance and capacitance. Then the reference current (reference current) IREF1 and IREF2 are provided by the bandgap reference zero temperature coefficient current, and the (hysteresis) comparator delay time t2, t4 is related to the current. Therefore, the reference current IREF3 is provided by the bandgap reference negative temperature coefficient current; the RC structure composed of resistors and capacitors has a positive temperature coefficient to temperature, then when the temperature rises, the comparator delay time t2, t4 decreases, and the capacitor charging time t1, t3 increases. After offsetting some of the temperature coefficients, T1 and T2 remain basically unchanged under temperature changes, thereby reducing the influence of the temperature coefficient on T1 (T2). The relationship between the resistance and capacitance time t1, the comparator delay time t2, and the clock period T1 with temperature changes is as follows Figure 6 shown.

[0062] in, Figure 7 The temperature characteristic simulation results of the prior art are shown in Figure 2. The temperatures are -40℃, 27℃, and 105℃. The clock frequency at 27℃ and 3.3V is used as the reference frequency f. The deviation of the clock frequencies f1 / f2 relative to the reference frequency f at -40℃ / 105℃ and 3.3V is the temperature characteristic deviation. The temperature characteristic deviation of the prior art is -4.44% to +4.38%. Figure 8 The voltage characteristic simulation results are 1.8V, 3.3V, and 5V respectively. The clock frequency when the voltage is 3.3V and the temperature is 27°C is used as the reference frequency f. The deviation of the clock frequency f1 / f2 relative to the reference when the voltage is 1.8V / 5V and the temperature is 27°C is the voltage characteristic deviation. The voltage characteristic deviation of the prior art is -4.20% to 4.57%. With different processes, the temperature voltage characteristic deviation can even reach ±20%. Therefore, the voltage characteristic deviation of the output clock of the circuit of the present invention is reduced from ±4.5% to within ±1% compared with the prior art optimization. The temperature characteristic deviation of the output clock of the circuit of the present invention is reduced from ±4.4% to within ±1% compared with the prior art optimization.

[0063] in, Figure 9 To simulate the power supply interference resistance characteristics, a square wave with a frequency of 32MHz and a voltage of ±400mV is added to the power supply voltage VCC. The dotted line shows the simulation result of the prior art. The frequency deviation relative to the design value of the output frequency of 16MHz is approximately ±10%, and the greater the interference on the power supply voltage VCC, the greater the deviation. The solid line shows the simulation result of the circuit of the present invention, and the deviation is within ±0.1%. Figure 10 The simulation results of the temperature characteristics of the circuit of the present invention are as follows: the temperature is -40℃, 27℃, and 105℃, and the temperature characteristic deviation is within ±1%; Figure 11The voltage characteristic simulation results are 1.8V, 3.3V, and 5V, and the voltage characteristic deviation is within ±1%. Resistor R2, capacitor C2, and capacitor C3 are designed as variable resistors and capacitors. Their function is to adjust the resistance and capacitance deviation caused by process deviation, that is, to reduce process deviation and increase the accuracy of the output clock. Therefore, the clock power supply interference resistance of the circuit of the present invention is reduced from ±10% to within ±0.1% compared with the existing technology. Trim0 of the ramp wave generation circuit <n:0>Trim1 <n:0>The value of the resistor and capacitor at the nth position represents the adjustable range, and the value of the resistor and capacitor at the 0th position represents the minimum adjustable accuracy.

[0064] In a feasible embodiment, some chips use LDO modules to power the digital part. The LDO module can be used to replace the voltage stabilizing unit 11 in the present invention, and a circuit is separated from the LDO circuit to power the clock circuit. Figure 12 As shown, the LDO output voltage powers the clock circuit. The clock circuit requires low-voltage domain transistors, and the current is provided by the bandgap reference module (source). The bandgap reference uses high-voltage domain transistors and requires attention to level conversion. The working principle of the buck regulator circuit 10 is similar to that of the LDO, both of which generate a fixed output voltage. However, compared to the LDO, the buck regulator circuit area and current of the present invention are much smaller. In addition, the chip using the LDO module usually uses low-voltage domain transistors. When only high-voltage devices are used instead of low-voltage devices, the LDO needs to be redesigned before it can be used. Therefore, the buck regulator circuit of the present invention is simple and has good product consistency. The buck regulator circuit in the circuit of the present invention is more optimized than the LDO circuit area, has a wider range of applications, and can be used in both high-voltage and low-voltage environments. In other words, in this embodiment, adding a buck regulator circuit to the circuit can improve the voltage temperature accuracy characteristics and power supply interference resistance of the clock circuit. The ramp wave generation circuit uses a zero temperature coefficient reference current, the hysteresis comparator circuit uses a negative temperature coefficient current, and uses a temperature compensation method to reduce the influence of temperature. The buck regulator circuit is smaller in area than the LDO circuit and has a wider range of applications.

[0065] See Figure 13 The present invention also provides a control method for a high-precision clock circuit, which is applied to the above-mentioned high-precision clock circuit and includes the following steps:

[0066] S1: Obtain the power supply voltage VCC received by the RC charge and discharge unit and processed by the voltage stabilizing unit;

[0067] S2: controlling the RC charge and discharge unit to output a clock voltage signal to the hysteresis comparator circuit according to the power supply voltage VCC;

[0068] S3: obtaining a ramp signal generated by the RC trimming unit controlled by the comparison unit receiving the switch unit;

[0069] S4: driving the phase adjustment unit to output a corresponding target clock signal according to the ramp signal and the clock voltage signal.

[0070] In all examples shown and described herein, any specific values ​​should be interpreted as merely exemplary and not limiting, and thus other examples of the exemplary embodiments may have different values.

[0071] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0072] The above-described embodiments merely illustrate several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that variations and modifications are possible without departing from the scope of the present invention, and such variations and modifications are fully within the scope of protection of the present invention.

Claims

1. A high-precision clock circuit, characterized in that: The high-precision clock circuit includes a step-down voltage stabilization circuit, a ramp wave generation circuit and a hysteresis comparator circuit, and the step-down voltage stabilization circuit and the ramp wave generation circuit are both connected to the hysteresis comparator circuit; The step-down voltage stabilization circuit includes a voltage stabilization unit and an RC charge and discharge unit, the voltage stabilization unit is used to input a power supply voltage VCC, the RC charge and discharge unit is connected to the voltage stabilization unit, and the RC charge and discharge unit is used to receive the power supply voltage VCC processed by the voltage stabilization unit and output a clock voltage signal to the hysteresis comparator circuit; The hysteresis comparator circuit includes a comparison unit connected to the RC charge and discharge unit and a phase adjustment unit connected to the comparison unit. The ramp wave generating circuit includes a switch unit and an RC adjustment unit. The switch unit is connected to the comparison unit, the switch unit is connected to one end of the RC adjustment unit, the other end of the RC adjustment unit is connected to the phase adjustment unit, and the switch unit is connected to the phase adjustment unit. The comparison unit receives the ramp signal generated by the switch unit to control the RC trimming unit, and the comparison unit drives the phase adjustment unit to output a corresponding target clock signal according to the ramp signal and the clock voltage signal.

2. The high-precision clock circuit according to claim 1, wherein: The voltage stabilizing unit includes a transistor NM1, a transistor NM2, a transistor NM3, a transistor NM4, a transistor NM5, a transistor NM6, a transistor PM1, and a transistor PM2. The RC charge and discharge unit includes a resistor R1 and a capacitor C1. The source of the transistor NM1 is connected to the source of the transistor PM1. The drain of the transistor NM1 is used to receive a reference current IREF0 provided by a bandgap reference source. The gate of the transistor NM1 is connected to the drain of the transistor NM1 and the source of the transistor PM1. The gate of the transistor PM1 is connected to the gate of the transistor NM3, the drain of the transistor PM1, and the drain of the transistor NM3. The source of transistor NM3 is connected to the drain of transistor NM5, the gate of transistor NM5, the gate of transistor NM4, and the gate of transistor NM6. The drain of transistor NM2 is used to input the power supply voltage VCC. The source of transistor NM2 is connected to the source of transistor PM2 and one end of resistor R1. The gate of transistor PM2 is connected to the drain of transistor PM2 and the drain of transistor NM4. The source of transistor NM4 is connected to the drain of transistor NM6. The other end of resistor R1 is connected to capacitor C1 and the comparison unit. The source of transistor NM5 is connected to the source of transistor NM6, capacitor C1 and ground.

3. The high-precision clock circuit according to claim 2, wherein: The switch unit includes a transistor NM7, a transistor NM8, a transistor NM9, a transistor NM10, a transistor NM11 and a transistor NM12. The RC trimming unit includes a resistor R2, a capacitor C2 and a capacitor C3. The source of the transistor NM7 is connected to the drain of the transistor NM10 and one end of the capacitor C2. The drain of the transistor NM7 is connected to the reference current IREF1 provided by the bandgap reference source and the drain of the transistor NM8. The gate of the transistor NM8 is connected to the phase adjustment unit. The source of the transistor NM8 is connected to one end of the resistor R2 and the transistor NM9. The drain of the transistor NM9 is connected to the reference current IREF1 provided by the bandgap reference source and the drain of the transistor NM8. A reference current IREF2 provided by a bandgap reference source is connected to the drain of transistor NM10, the source of transistor NM10 is connected to one end of capacitor C3 and the drain of transistor NM12, the source of transistor NM12 is connected to the other end of capacitor C3, the other end of resistor R2, the other end of capacitor C2, the source of transistor NM11, and the phase adjustment unit and are grounded, and the gate of transistor NM7, the gate of transistor NM8, the gate of transistor NM9, the gate of transistor NM9, the gate of transistor NM10, the gate of transistor NM11, and the gate of transistor NM12 are all connected to the phase adjustment unit.

4. The high-precision clock circuit according to claim 3, wherein: The comparison unit includes a hysteresis comparator, the inverting input terminal of the hysteresis comparator is connected to the reference current IREF1, the drain of the transistor NM7, and the drain of the transistor NM8, and the non-inverting input terminal of the hysteresis comparator is connected to the reference current IREF2, the drain of the transistor NM9, and the drain of the transistor NM10; The phase adjustment unit includes an inverter INV1, an inverter INV2, an inverter INV3 and an inverter INV4, an input end of the inverter INV1 is connected to the output end of the hysteresis comparator, an input end of the inverter INV1 is connected to the output end of the hysteresis comparator, an output end of the inverter INV1 is connected to the input end of the inverter INV2, an output end of the inverter INV2 is connected to the input end of the inverter INV3, an output end of the inverter INV3 is connected to the input end of the inverter INV4, and an output end of the inverter INV4 outputs the target clock signal; The output end of the inverter INV1 and the input end of the inverter INV2 generate a non-overlapping clock signal CKA and are connected to the gates of the transistors NM7, NM9, and NM12. The output end of the inverter INV2 and the input end of the inverter INV3 generate a non-overlapping clock signal CKB and are connected to the gates of the transistors NM8, NM10, and NM11.

5. The high-precision clock circuit according to claim 4, characterized in that: When the voltage stabilizing unit receives the reference current IREF0, the transistor NM6 and the transistor NM5 form a current mirror structure, and the transistor NM6 copies the current of the transistor NM5; When the V_CLK voltage corresponding to the clock voltage signal is equal to the source-drain voltage drop of transistor NM5 plus the sum of the threshold voltages of transistors NM3 and PM1, the sizes of transistors PM1 and NM3 are adjusted to obtain clock voltage signals of different voltage values.

6. The high-precision clock circuit according to claim 5, characterized in that: The hysteresis comparator is also connected to the reference current IREF3 provided by the bandgap reference source. The hysteresis comparator controls the reference current IREF3 according to the reference current IREF1 and the reference current IREF2 to perform temperature compensation on the positive temperature coefficient corresponding to the clock voltage signal, wherein the reference current IREF1 and the reference current IREF2 are zero temperature coefficient reference currents, and the reference current IREF3 is a negative temperature coefficient reference current.

7. The high-precision clock circuit according to claim 5, characterized in that: When the power supply voltage VCC is powered off, the V_CLK voltage is 2V; when the power supply voltage VCC is lower than 2V, the V_CLK voltage is approximately equal to the power supply voltage VCC, wherein the power supply voltage VCC is 1.8V to 5.5V, the resistance value of the resistor R1 is 1KΩ, the resistor R2 is a variable resistor, and the capacitors C2 and C3 are variable capacitors.

8. The high-precision clock circuit according to claim 4, characterized in that: The non-overlapping clock signal CKA and the non-overlapping clock signal CKB have opposite phases. The switching unit is a symmetrical structure including multiple NMOS transistors. The non-overlapping clock signal CKA and the non-overlapping clock signal CKB are used to control the switching of multiple NMOS transistors to generate a ramp signal with a duty cycle of 50%.

9. The high-precision clock circuit according to claim 7, wherein: When the non-overlapping clock signal CKA is at a high level and the non-overlapping clock signal CKB is at a low level, transistors NM7, NM9 and NM12 are turned on, transistors NM8, NM10 and NM11 are turned off, capacitor C2 is charged and capacitor C1 is discharged; When the non-overlapping clock signal CKA is low and the non-overlapping clock signal CKB is high, transistors NM7 , NM9 and NM12 are turned off, transistors NM8 , NM10 and NM11 are turned on, capacitor C2 is discharged and capacitor C1 is charged.

10. A method for controlling a high-precision clock circuit, characterized in that: The high-precision clock circuit according to any one of claims 1 to 9 comprises the following steps: Obtain the power supply voltage VCC received by the RC charge and discharge unit and processed by the voltage stabilizing unit; controlling the RC charge and discharge unit to output a clock voltage signal to the hysteresis comparator circuit according to the power supply voltage VCC; Acquire the ramp signal generated by the RC trimming unit controlled by the comparison unit receiving the switch unit; The phase adjustment unit is driven according to the ramp signal and the clock voltage signal to output a corresponding target clock signal.

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