Control method and control circuit of PWM (Pulse Width Modulation) signal and switching power supply

Abstract

The embodiment of the invention provides a PWM signal control method, a PWM signal control circuit and a switching power supply. The method comprises the following steps: detecting the duration of a first effective level of an effective signal; and when the duration time is greater than or equal to a first specified time, entering a noise reduction adjustment working mode, in which noise reduction adjustment is executed in n adjustment time periods of the effective signal to obtain an adjusted PWM signal, n being greater than or equal to 1. Wherein the noise reduction adjustment working mode comprises the steps that in the current adjustment time period, the duration time of the first effective level is timed, when the duration time reaches the first specified time, the effective signal is controlled to be overturned for m times, the level duration time after the first effective level is overturned is the second specified time, and the second specified time is larger than the first specified time. The overturning times m of the effective signals in the adjacent adjustment time periods or / and the second specified time are different. The embodiment of the invention is suitable for adjusting the PWM signal in the switching power supply.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of switching power supplies, and in particular to a PWM (Pulse Width Modulation) signal control method, a control circuit, and a switching power supply. Background Art

[0002] Switching power supplies are widely used in industrial environments to ensure system safety and reliability.

[0003] When a switching power supply operates continuously at a light load or no load, its switching frequency may be lower than 20kHz, which is within the audible frequency range of 20-20kHz. To prevent audio noise interference, a variable resistor is typically connected in parallel with the switching power supply chip. When the switching power supply operates at a light load, the value of the external parallel resistor is increased, thereby increasing the actual load capacity of the switching power supply chip and preventing it from operating within the audio frequency range. However, this practice significantly increases circuit power consumption. Summary of the Invention

[0004] The purpose of the embodiments of the present disclosure is to provide a PWM signal control method, control circuit, and switching power supply. By adjusting the PWM signal to a non-fixed frequency signal and ensuring that the output frequency of the adjusted PWM signal is not within the sound frequency range audible to the human ear, the resonance of capacitors and inductors in the circuit and the interference of audio noise are avoided, thereby reducing power consumption and EMI.

[0005] To achieve the above-mentioned objectives, a first aspect of an embodiment of the present disclosure provides a method for controlling a PWM signal, the method comprising: detecting the duration of a first effective level of an effective signal; when the duration is greater than or equal to a first specified time, entering a mute adjustment operating mode, wherein mute adjustment is performed within n adjustment time periods of the effective signal to obtain an adjusted PWM signal, where n ≥ 1. The mute adjustment operating mode comprises: timing the duration of the first effective level within the current adjustment time period, and when the duration reaches the first specified time, controlling the effective signal to perform m flips, and the duration of the first effective level after flipping is a second specified time, wherein the number of flips m of the effective signal in adjacent adjustment time periods or / and the second specified time are different.

[0006] In some embodiments of the present disclosure, when the duration of the first effective level of the effective signal is less than the first prescribed time, the effective signal is a PWM signal.

[0007] In some embodiments of the present disclosure, the method further includes: obtaining the effective signal based on the comparison result of the output voltage divider and the reference voltage; the mute adjustment working mode further includes: outputting the voltage divider switching signal required for the mute adjustment to control the output voltage to change within the range of the voltage divider corresponding to the voltage divider switching signal, the voltage divider including a first voltage divider and a second voltage divider, and the first voltage divider and the second voltage divider are respectively the upper and lower limits of the hysteresis band width centered on the reference voltage.

[0008] In some embodiments of the present disclosure, when the adjusted PWM signal is a first level signal, the corresponding voltage divider switching signal is a second voltage divider switching signal to control the output voltage to increase from the second voltage divider to the reference voltage; when the adjusted PWM signal is a second level signal, the corresponding voltage divider switching signal is a first voltage divider switching signal to control the output voltage to decrease from the first voltage divider to the reference voltage.

[0009] In some embodiments of the present disclosure, the method further includes: obtaining the effective signal based on the comparison result of the output voltage or its voltage divider with the reference voltage; the mute adjustment working mode further includes: outputting a switching signal of the reference voltage required for mute adjustment to control the reference voltage to switch between a first reference voltage and a second reference voltage, the first switching signal corresponding to the first reference voltage, and the second switching signal corresponding to the second reference voltage.

[0010] In some embodiments of the present disclosure, when the adjusted PWM signal is a first level signal, the corresponding switching signal is the first switching signal, so as to control the output voltage or its voltage divider to be compared with the first reference voltage; when the adjusted PWM signal is a second level signal, the corresponding switching signal is the second switching signal, so as to control the output voltage or its voltage divider to be compared with the second reference voltage.

[0011] According to a second aspect of the embodiments of the present disclosure, a PWM signal control circuit is provided, the circuit comprising: an effective signal generating circuit and a PWM signal adjusting circuit. The effective signal generating circuit is configured to provide an effective signal; the PWM signal adjusting circuit is configured to detect the duration of a first effective level of the effective signal, and when the duration is greater than or equal to a first prescribed time, enter a mute adjustment working mode, wherein mute adjustment is performed within n adjustment time periods of the effective signal to obtain an adjusted PWM signal, wherein n≥1. The mute adjustment working mode comprises: within the current adjustment time period, timing the duration of the first effective level, and when it reaches the first prescribed time, controlling the effective signal to perform m flips, and the duration of the level after the first effective level flip is a second prescribed time, wherein the number of flips m of the effective signal in adjacent adjustment time periods or / and the second prescribed time are different.

[0012] In some embodiments of the present disclosure, the effective signal generating circuit is further configured to obtain the effective signal based on the comparison result of the voltage divider of the output voltage and the reference voltage; the PWM signal adjustment circuit is further configured to output the voltage divider switching signal required for the mute adjustment to control the output voltage to change within the range of the voltage divider corresponding to the voltage divider switching signal, and the voltage divider includes a first voltage divider and a second voltage divider, and the first voltage divider and the second voltage divider are respectively the upper and lower limits of the hysteresis band width centered on the reference voltage.

[0013] In some embodiments of the present disclosure, the effective signal generating circuit is further configured to obtain the effective signal based on a comparison result of the output voltage or its voltage divider with a reference voltage; the PWM signal adjustment circuit is further configured to output a switching signal of the reference voltage required for mute adjustment to control the reference voltage to switch between a first reference voltage and a second reference voltage, the first switching signal corresponding to the first reference voltage, and the second switching signal corresponding to the second reference voltage.

[0014] According to a third aspect of the embodiments of the present disclosure, a switching power supply is provided. The switching power supply includes the PWM signal control circuit according to the second aspect of the embodiments of the present disclosure.

[0015] Other features and advantages of the embodiments of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the embodiments of the present disclosure, but do not constitute a limitation of the embodiments of the present disclosure. In the accompanying drawings:

[0017] Figure 1 is a flow chart of a PWM signal control method provided according to an embodiment of the present disclosure;

[0018] Figure 2 is a waveform diagram of an adjusted PWM signal provided according to an embodiment of the present disclosure;

[0019] Figure 3 is a waveform diagram of another adjusted PWM signal provided according to an embodiment of the present disclosure;

[0020] Figure 4 is a waveform diagram of another adjusted PWM signal provided according to an embodiment of the present disclosure;

[0021] Figure 5 According to the embodiment of the present disclosure, Figure 2 A waveform diagram showing the change of the corresponding output voltage between the first divided voltage and the second divided voltage;

[0022] Figure 6 According to the embodiment of the present disclosure, Figure 2 A schematic diagram of waveforms of the corresponding output voltage or its divided voltage when compared with the first reference voltage and the second reference voltage;

[0023] Figure 7 is a schematic block diagram of a PWM signal control circuit 700 provided according to an embodiment of the present disclosure;

[0024] Figure 8 is a circuit diagram illustrating an effective signal generating circuit according to an embodiment of the present disclosure;

[0025] Figure 9 is a circuit diagram illustrating an effective signal generating circuit according to an embodiment of the present disclosure;

[0026] Figure 10 is a schematic block diagram of a PWM signal adjustment circuit provided according to an embodiment of the present disclosure;

[0027] Figure 11 is a circuit diagram of a first counting circuit provided according to an embodiment of the present disclosure;

[0028] Figure 12 is a circuit diagram of a second counting circuit provided according to an embodiment of the present disclosure;

[0029] Figure 13 is a circuit diagram of a reset circuit provided according to an embodiment of the present disclosure;

[0030] Figure 14 is a circuit diagram of a logic circuit provided according to an embodiment of the present disclosure;

[0031] Figure 15 is a circuit diagram of a logic circuit provided according to an embodiment of the present disclosure;

[0032] Figure 16 FIG. 4 is a circuit diagram of a PWM signal generating circuit according to an embodiment of the present disclosure.

[0033] Elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0035] In all embodiments of the present disclosure, since the source and drain of a metal oxide semiconductor (MOS) transistor are symmetrical, and the directions of the conduction current between the source and drain of an N-type transistor and a P-type transistor are opposite, in the embodiments of the present disclosure, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. In addition, terms such as "first" and "second" are only used to distinguish one component (or a portion of a component) from another component (or another portion of a component).

[0036] Figure 1 A flow chart of a PWM signal control method according to an embodiment of the present disclosure is shown. The method is applied to a switching power supply and includes the following steps:

[0037] Step S101 , detecting the duration of a first effective level of a valid signal.

[0038] The effective signal is a square wave signal, and the first effective level can be a high level or a low level. In the embodiment of the present disclosure, the noise reduction adjustment can be implemented by detecting the high level or the low level of the effective signal.

[0039] Step S102, determining whether the duration is greater than or equal to a first prescribed time;

[0040] Step S103: When the duration is greater than or equal to the first specified time, a mute adjustment operating mode is entered, in which mute adjustment is performed within n adjustment time periods of the valid signal to obtain an adjusted PWM signal, where n ≥ 1. The mute adjustment operating mode includes: controlling the valid signal to flip m times within the current adjustment time period, and the duration of the first valid level after flipping is a second specified time, wherein the number of flips m of the valid signal in adjacent adjustment time periods and / or the second specified time are different.

[0041] Among them, since the duration of the first effective level of the effective signal detected in the embodiment of the present disclosure is the duration of half a cycle of the effective signal. The sound frequency range audible to the human ear is 20 to 20 kHz, and the corresponding period is 0.05 seconds to 50 microseconds, and half a cycle is 0.025 seconds to 25 microseconds. Therefore, in order to avoid audio noise interference, the duration of the first effective level of the effective signal must be less than 25 microseconds. In the embodiment of the present disclosure, the first specified time can be set to 25 microseconds, and in order to further reduce audio noise interference, the first specified time can also be set to a time less than 25 microseconds, for example, 18 microseconds, 20 microseconds, 22 microseconds, etc., which can be set according to user needs.

[0042] In an embodiment of the present disclosure, when the duration of the first effective level is greater than or equal to the first prescribed time, the mute adjustment working mode will be entered. In this mode, the mute adjustment is performed within n adjustment time periods of the effective signal. Specifically, within the current adjustment time period, the duration of the first effective level is timed, and when it reaches the first prescribed time, the effective signal is controlled to perform m flips, and the duration of the level after the first effective level is flipped is the second prescribed time, wherein the number of flips m of the effective signal in adjacent adjustment time periods or / and the second prescribed time are different. In the disclosed embodiment, the resonance phenomenon and buzzing sound of the PWM signal can be eliminated by adjusting the PWM signal to a periodic signal with a non-fixed frequency and by eliminating the output frequency of the PWM signal from the frequency range audible to the human ear. That is, the period of the adjusted PWM signal is different from that of the PWM signal before adjustment. This is reflected in the fact that the PWM signal before adjustment is a square wave with a fixed period, while the adjusted PWM signal has m flips and the level after the flip of the first effective level lasts for a second specified time. Therefore, the durations of the high and low levels of the waveform output in adjacent adjustment time periods are unequal, thereby avoiding the resonance phenomenon. In addition, the output frequency of the adjusted PWM signal is outside the frequency range audible to the human ear.

[0043] The number of adjustment time periods n is ≥ 1, and can be 1, 2, 3, etc., and can be set according to user needs to eliminate audio noise interference. The second specified time is ≤ the first specified time.

[0044] In one embodiment of the present disclosure, the mute adjustment working mode may include: controlling the effective signal to perform different flipping times in adjacent adjustment time periods, and the second prescribed time for the level after the first effective level is flipped is the same in each adjustment time period. Taking the first effective level as a low level as an example, Figure 2 As shown, the number of flips in the first adjustment period is 1, and the number of flips in the second adjustment period is 2, but the second prescribed time in the two adjustment periods is the same, and as Figure 2 As shown, the first to fifth cycles are not fixed cycles, so the corresponding adjusted PWM signal output frequency (i.e., the inverse of each cycle) is also non-fixed, thus avoiding resonance. When the first effective level is high, the principle is similar to that described above and will not be repeated here.

[0045] In another embodiment of the present disclosure, the mute adjustment working mode may further include: controlling the effective signal to perform the same number of flips in adjacent adjustment time periods, and the second prescribed time for the level after the first effective level is flipped is different in each adjustment time period. Taking the first effective level as a low level as an example, Figure 3 As shown, the number of flips in the first adjustment time period and the second adjustment time period is 1, but the second specified time in the two adjustment time periods is different, and the first cycle to the fourth cycle are not fixed cycles, so the output frequency of the corresponding adjusted PWM signal (that is, the inverse of each cycle) is also a non-fixed frequency.

[0046] In another embodiment of the present disclosure, the mute adjustment working mode may further include: controlling the effective signal to perform different flipping times in adjacent adjustment time periods, and the second prescribed time for the level after the first effective level is flipped is different in each adjustment time period. Taking the first effective level as a low level as an example, Figure 4 As shown, the number of flips in the first adjustment time period is 1, and the number of flips in the second adjustment time period is 2. The second specified time in the two adjustment time periods is different, and the first to fifth cycles are non-fixed cycles. Therefore, the output frequency of the corresponding adjusted PWM signal (that is, the inverse of each cycle) is also a non-fixed frequency.

[0047] In another embodiment of the present disclosure, Figure 1 As shown, the method further includes:

[0048] Step S104: When the duration of the first effective level of the effective signal is less than the first prescribed time, the effective signal is a PWM signal.

[0049] That is, when the output frequency of the effective signal is not within the sound frequency range audible to the human ear, the effective signal is directly output as a PWM signal.

[0050] In one implementation of the embodiment of the present disclosure, the effective signal can be obtained based on the comparison result of the voltage division of the output voltage of the switching power supply with the reference voltage. Correspondingly, the mute adjustment working mode further includes: outputting a voltage division switching signal required for the mute adjustment to control the output voltage to change within the voltage division range corresponding to the voltage division switching signal, wherein the voltage division includes a first voltage division and a second voltage division, and the first voltage division and the second voltage division are respectively the upper and lower limits of the hysteresis band width centered on the reference voltage, that is, the first voltage division is the upper limit of the hysteresis band width centered on the reference voltage, and the second voltage division is the lower limit of the hysteresis band width centered on the reference voltage. When the adjusted PWM signal is a first level signal, the corresponding voltage division switching signal is the second voltage division switching signal to control the output voltage of the switching power supply to increase from the second voltage division to the reference voltage; when the adjusted PWM signal is a second level signal, the corresponding voltage division switching signal is the first voltage division switching signal to control the output voltage of the switching power supply to decrease from the first voltage division to the reference voltage. When the first effective level is a low level in the embodiment of the present disclosure, the first level signal of the adjusted PWM signal is a high level signal, and the second level signal is a low level signal. Figure 2 The waveform of the adjusted PWM signal is as follows: Figure 5 The figure shows the waveform of the output voltage changing between the first divided voltage and the second divided voltage.

[0051] In another implementation of the embodiment of the present disclosure, the effective signal can be obtained based on the comparison result of the output voltage of the switching power supply or its voltage divider with the reference voltage, that is, the effective signal can be obtained based on the comparison result of the output voltage of the switching power supply with the reference voltage, or the comparison result of the voltage divider of the output voltage of the switching power supply with the reference voltage. Correspondingly, the mute adjustment working mode also includes: outputting a switching signal of the reference voltage required for mute adjustment to control the reference voltage to switch between a first reference voltage and a second reference voltage, the first switching signal corresponding to the first reference voltage, and the second switching signal corresponding to the second reference voltage. Wherein, when the adjusted PWM signal is a first level signal, the corresponding switching signal is the first switching signal to control the comparison of the output voltage or its voltage divider with the first reference voltage; when the adjusted PWM signal is a second level signal, the corresponding switching signal is the second switching signal to control the comparison of the output voltage or its voltage divider with the second reference voltage. When the first level signal is a low level and the second level signal is a high level, the first reference voltage is greater than the second reference voltage, corresponding to Figure 2 The waveform of the adjusted PWM signal is as follows: Figure 6 The waveform diagram of the output voltage or its divided voltage when compared with the first reference voltage and the second reference voltage is shown. On the contrary, when the first level signal is high and the second level signal is low, the first reference voltage is lower than the second reference voltage.

[0052] Through the embodiments of the present disclosure, the PWM signal is adjusted to a periodic signal with a non-fixed frequency, and the output frequency of the adjusted PWM signal is not within the sound frequency range audible to the human ear, thereby avoiding the resonance phenomenon caused by capacitors and inductors in the circuit and the interference of audio noise, reducing power consumption and lowering EMI.

[0053] Correspondingly, Figure 7 FIG. 7 shows a schematic block diagram of a PWM signal control circuit 700 provided according to an embodiment of the present disclosure. Figure 7 As shown, the circuit includes: an effective signal generating circuit 701 and a PWM signal adjusting circuit 702 .

[0054] The effective signal generation circuit 701 is configured to provide an effective signal PWM0. The PWM signal adjustment circuit 702 is configured to detect the duration of the first effective level of the effective signal PWM0. When the duration is greater than or equal to a first specified time, the circuit enters a mute adjustment operation mode, in which mute adjustment is performed within n adjustment time periods of the effective signal to obtain an adjusted PWM signal, where n ≥ 1. The mute adjustment operation mode includes: within the current adjustment time period, timing the duration of the first effective level. When the duration reaches the first specified time, the effective signal is controlled to perform m flips, and the duration of the first effective level after flipping is a second specified time. The number of flips m of the effective signal in adjacent adjustment time periods or / and the second specified time are different.

[0055] Wherein, the effective signal is a square wave signal, and the first effective level can be a high level or a low level. In the embodiment of the present disclosure, the high level or the low level of the effective signal can be detected to implement the mute adjustment. In the embodiment of the present disclosure, the first prescribed time can be set to 25 microseconds, and in order to further reduce the audio noise interference, the first prescribed time can also be set to a time less than 25 microseconds, for example, 18 microseconds, 20 microseconds, 22 microseconds, etc., which can be set according to user needs. Wherein, the number of adjustment time periods n≥1, which can be 1, 2, 3, etc., which can be set according to user needs to achieve the elimination of audio noise interference. Wherein, the second prescribed time ≤ the first prescribed time. When the PWM signal adjustment circuit 702 detects that the duration of the first effective level of the effective signal is less than the first prescribed time, there is no need to execute the mute adjustment working mode, and the PWM signal adjustment circuit 702 can directly output the effective signal PWM0 as the PWM signal.

[0056] In one embodiment of the present disclosure, the output voltage of the switching power supply can be maintained within a hysteresis band width centered around a reference voltage. The effective signal generation circuit 701 is further configured to generate the effective signal PWM0 based on a comparison result of the voltage division of the output voltage VOUT with the reference voltage Vref. The PWM signal adjustment circuit 702 is further configured to output a voltage division switching signal (including a first voltage division switching signal KVISO_H and a second voltage division switching signal KVISO_L) required for mute adjustment, thereby controlling the output voltage VOUT to vary within the voltage division range corresponding to the voltage division switching signal. The voltage division includes a first voltage division VISO_H and a second voltage division VISO_L, and the first voltage division VISO_H and the second voltage division VISO_L are the upper and lower limits of the hysteresis band width centered around the reference voltage Vref, respectively.

[0057] Among them, Figure 8As shown, the effective signal generating circuit 701 includes: a comparator COM, a first switch k1, a second switch k2, a first resistor R1, a second resistor R2, and a third resistor R3. The non-inverting input terminal of the comparator COM is coupled to a reference voltage Vref, and the inverting input terminal is coupled to the first end of the first switch k1 and the first end of the second switch k2. The second end of the first switch k1 is coupled to the first end of the second resistor R2 and the second end of the third resistor R3. The control terminal of the first switch k1 is coupled to the first voltage-dividing switching signal KVISO_H output by the PWM signal adjustment circuit 702. The second end of the second switch k2 is coupled to the second end of the second resistor R2 and the first end of the first resistor R1. The control terminal of the second switch k2 is coupled to the second voltage-dividing switching signal KVISO_L output by the PWM signal adjustment circuit 702. The second end of the first resistor R1 is grounded GND. The first end of the third resistor R3 is coupled to the output voltage VOUT.

[0058] Wherein, the first divided voltage VISO_H = VOUT * (R1 + R2) / (R1 + R2 + R3), and the second divided voltage VISO_L = VOUT * R1 / (R1 + R2 + R3). When the first effective level in the embodiment of the present disclosure is a low level, the first level signal of the adjusted PWM signal is a high level signal, and the second level signal is a low level signal. When the adjusted PWM signal is a high level signal, the corresponding divided voltage switching signal is the second divided voltage switching signal KVISO_L. The second divided voltage VISO_L is coupled to the inverting input terminal of the comparator COM to control the output voltage VOUT of the switching power supply to increase from the second divided voltage VISO_L to the reference voltage Vref. When the adjusted PWM signal is at a low level, the corresponding voltage-dividing switching signal is the first voltage-dividing switching signal KVISO_H. The first voltage-dividing switching signal VISO_H is coupled to the inverting input terminal of the comparator COM to control the output voltage VOUT of the switching power supply to decrease from the first voltage-dividing switching signal VISO_H to the reference voltage Vref. This process is repeated, thereby controlling the output voltage to vary between the first voltage-dividing switching signal VISO_H and the second voltage-dividing switching signal VISO_L. When the first active level is at a high level, the principle is similar to that described above.

[0059] In another embodiment of the present disclosure, the effective signal generation circuit 701 is further configured to generate the effective signal PWM0 based on a comparison result between the output voltage VOUT or its divided voltage and a reference voltage. The PWM signal adjustment circuit 702 is further configured to output a switching signal of a reference voltage required for mute adjustment to control the reference voltage to switch between a first reference voltage Vref1 and a second reference voltage Vref2, wherein a first switching signal SW_H corresponds to the first reference voltage Vref1, and a second switching signal SW_L corresponds to the second reference voltage Vref2.

[0060] When the output voltage VOUT is directly compared with the reference voltage, the effective signal generating circuit 701 may include: a comparator COM, a first switch k1, and a second switch k2. The inverting input terminal of the comparator COM is coupled to the output voltage VOUT (e.g. Figure 9 The non-inverting input terminal is coupled to the first terminal of the first switch k1 and the first terminal of the second switch k2. The second terminal of the first switch k1 is coupled to the first reference voltage Vref1, and the control terminal of the first switch k1 is coupled to the first switching signal SW_H output by the PWM signal adjustment circuit 702. The second terminal of the second switch k2 is coupled to the second reference voltage Vref2, and the control terminal of the second switch k2 is coupled to the second switching signal SW_L output by the PWM signal adjustment circuit 702. When the divided voltage of the output voltage VOUT is compared with the reference voltage, as shown in FIG. Figure 9 As shown, the effective signal generating circuit 701 further includes: a fourth resistor R4 and a fifth resistor R5. The inverting input terminal of the comparator COM is coupled to the first terminal of the fourth resistor R4 and the second terminal of the fifth resistor R5. The second terminal of the fourth resistor R4 is grounded to GND. The first terminal of the fifth resistor R5 is coupled to the output voltage VOUT. When the adjusted PWM signal is a first-level signal, the corresponding switching signal is the first switching signal SW_H, and the first reference voltage Vref1 is coupled to the non-inverting input terminal of the comparator COM to control the voltage division of the output voltage VOUT for comparison with the first reference voltage Vref1. When the adjusted PWM signal is a second-level signal, the corresponding switching signal is the second switching signal SW_L, and the second reference voltage Vref2 is coupled to the non-inverting input terminal of the comparator COM to control the voltage division of the output voltage VOUT for comparison with the second reference voltage Vref2. When the first-level signal is low and the second-level signal is high, the first reference voltage Vref1 is greater than the second reference voltage Vref2.

[0061] In one implementation of the present disclosure, Figure 10 As shown, the PWM signal adjustment circuit 702 may include: a first counting circuit 101 , a second counting circuit 102 , a reset circuit 103 , a logic circuit 104 and a PWM signal generation circuit 105 .

[0062] The first counting circuit 101 is configured to count the number H of the adjustment time periods according to the effective signal PWM0. A high level "1" and a reset signal Reset output by the reset circuit 103 are also input to the first counting circuit 101. Taking 1 to 3 adjustment time periods as an example, Figure 11As shown, the first counting circuit 101 may include six D flip-flops coupled in sequence. When there is one adjustment time period, the output H1 is the number of adjustment times H transmitted to the logic circuit 104. When there are two adjustment time periods, the first adjustment time period H1 and the second adjustment time period H2 are transmitted to the logic circuit 104 one by one. When there are three adjustment time periods, the first adjustment time period H1, the second adjustment time period H2, and the third adjustment time period H3 are transmitted to the logic circuit 104 one by one. If there are more adjustment time periods, the same logic applies. Figure 11 The circuit diagram shown is only one possible implementation of the first counting circuit 101 . In the embodiment of the present disclosure, there is no specific limitation on the first counting circuit 101 , and it is sufficient that its functions can be implemented.

[0063] The second counting circuit 102 is configured to time the duration of the first effective level in each adjustment period, and when the duration reaches the first specified time, count the number of flips A of the effective signal, and output a flag signal C when the number of flips reaches the number of flips corresponding to each adjustment period. Figure 12 As shown, the second counting circuit 102 may include four D flip-flops coupled in sequence, each configured to perform 1 to 3 flip-flops, and output flip-flops A1 to A3 accordingly. After three flip-flops, the second counting circuit 102 outputs a flag signal C to the reset circuit 103. If the flip-flops are greater, the same logic applies. Figure 12 The circuit diagram shown is only one possible implementation of the second counting circuit 102 . In the embodiment of the present disclosure, there is no specific limitation on the second counting circuit 102 , and it is sufficient that its functions are implemented.

[0064] The reset circuit 103 is configured to output a reset signal Reset to the first counting circuit 101 and the second counting circuit 102 according to the negated signal PWM0 B of the effective signal PWM0 and the flag signal C. Figure 13 FIG. 1 is a circuit diagram of a possible implementation of the reset circuit 103 , which is not specifically limited in the embodiments of the present disclosure.

[0065] The logic circuit 104 is configured to generate a control signal E1 according to the inverted signal of the adjusted PWM signal, the number of the adjustment time periods, and the number of flips, so that the inverted signal E1 B of the control signal E1 is input to the second counting circuit 102. The following takes an adjustment time period and one flip of the valid signal in the time period as an example. Figure 14 As shown. Take two adjustment time periods, the first adjustment time period performs one flip of the valid signal, and the second adjustment time period performs two flips of the valid signal as an example, as shown Figure 15The above circuit diagram is only an example of the possible implementation of the logic circuit 104 and is not specifically limited in the embodiments of the present disclosure.

[0066] The PWM signal generating circuit 105 is configured to detect the duration of the first effective level of the effective signal and the duration of the level after the first effective level is reversed, and when the duration of the first effective level is greater than or equal to the first specified time, the PWM signal generating circuit 105 outputs the adjusted PWM signal and the voltage division switching signals KVISO_H and KVISO_L (or the reference voltage switching signals SW_H and SW_L) according to the effective signal PWM0 and the control signal E1. Figure 16 As shown, the reference current source Ibias charges the first capacitor C1. When the voltage across the first capacitor C1 exceeds the threshold of the Schmitt trigger, the Schmitt trigger flips, completing the timing process for the first predetermined time. The charging time of the first capacitor C1 corresponds to the timing time of the first active level, for example, the duration of the low level of the active signal PWM0. The active signal PWM0 and the control signal E1, after a logical operation, control the on and off of the switch MN1. When the switch MN1 is on, it provides a discharge path for the first capacitor C1, discharging the first capacitor C1.

[0067] In the embodiment of the present disclosure, by adjusting the PWM signal to a non-fixed frequency signal, and the output frequency of the adjusted PWM signal is not within the sound frequency range audible to the human ear, the resonance phenomenon caused by the capacitors and inductors in the circuit and the interference of audio noise are avoided, power consumption is reduced, and EMI is reduced.

[0068] The present disclosure also provides a switching power supply, which includes the PWM signal control circuit described above. The switching power supply can be an isolated switching power supply or a non-isolated switching power supply.

[0069] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0070] Further aspects and scope of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended to be illustrative only and are not intended to limit the scope of the present application.

[0071] Several embodiments of the present disclosure have been described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A PWM signal control method, characterized in that: The method comprises: detecting a duration of a first valid level of a valid signal; When the duration is greater than or equal to the first specified time, the mute adjustment working mode is entered, in which the mute adjustment is performed within n adjustment time periods of the effective signal to obtain an adjusted PWM signal, wherein n≥1, Among them, the mute adjustment working mode includes: within the current adjustment time period, timing the duration of the first effective level, and when it reaches the first specified time, controlling the effective signal to perform m flips, and the level duration after the first effective level is flipped is the second specified time, wherein the number of flips m of the effective signal in adjacent adjustment time periods or / and the second specified time are different.

2. The PWM signal control method according to claim 1, wherein: When the duration of the first effective level of the effective signal is less than the first prescribed time, the effective signal is a PWM signal.

3. The PWM signal control method according to claim 1, wherein: The method further comprises: Obtaining the effective signal according to a comparison result of the divided output voltage and the reference voltage; The mute adjustment working mode also includes: outputting a voltage divider switching signal required for mute adjustment to control the output voltage to change within the range of the voltage divider corresponding to the voltage divider switching signal, the voltage divider including a first voltage divider and a second voltage divider, and the first voltage divider and the second voltage divider are respectively the upper and lower limits of the hysteresis band width centered on the reference voltage.

4. The PWM signal control method according to claim 3, wherein: When the adjusted PWM signal is a first level signal, the corresponding voltage divider switching signal is a second voltage divider switching signal to control the output voltage to increase from the second voltage divider to the reference voltage; when the adjusted PWM signal is a second level signal, the corresponding voltage divider switching signal is a first voltage divider switching signal to control the output voltage to decrease from the first voltage divider to the reference voltage.

5. The PWM signal control method according to claim 1, wherein: The method further comprises: Obtaining the effective signal according to a comparison result of the output voltage or its divided voltage with a reference voltage; The noise reduction adjustment working mode also includes: outputting a switching signal of the reference voltage required for noise reduction adjustment to control the reference voltage to switch between a first reference voltage and a second reference voltage, the first switching signal corresponding to the first reference voltage, and the second switching signal corresponding to the second reference voltage.

6. The PWM signal control method according to claim 5, wherein: When the adjusted PWM signal is a first level signal, the corresponding switching signal is the first switching signal, so as to control the output voltage or its voltage division to be compared with the first reference voltage; when the adjusted PWM signal is a second level signal, the corresponding switching signal is the second switching signal, so as to control the output voltage or its voltage division to be compared with the second reference voltage.

7. A PWM signal control circuit, characterized in that: The circuit includes: an effective signal generating circuit and a PWM signal adjusting circuit, Wherein, the effective signal generating circuit is configured to provide an effective signal; The PWM signal adjustment circuit is configured to detect the duration of a first effective level of the effective signal, and when the duration is greater than or equal to a first specified time, enter a mute adjustment working mode, in which mute adjustment is performed within n adjustment time periods of the effective signal to obtain an adjusted PWM signal, wherein n≥1, Among them, the mute adjustment working mode includes: within the current adjustment time period, timing the duration of the first effective level, and when it reaches the first specified time, controlling the effective signal to perform m flips, and the level duration after the first effective level is flipped is the second specified time, wherein the number of flips m of the effective signal in adjacent adjustment time periods or / and the second specified time are different.

8. The PWM signal control circuit according to claim 7, characterized in that: The effective signal generating circuit is further configured to obtain the effective signal according to a comparison result of the divided voltage of the output voltage and the reference voltage; The PWM signal adjustment circuit is also configured to output a voltage divider switching signal required for mute adjustment to control the output voltage to change within the voltage divider range corresponding to the voltage divider switching signal, and the voltage divider includes a first voltage divider and a second voltage divider, and the first voltage divider and the second voltage divider are respectively the upper and lower limits of the hysteresis band width centered on the reference voltage.

9. The PWM signal control circuit according to claim 7, characterized in that: The effective signal generating circuit is further configured to obtain the effective signal according to a comparison result between the output voltage or its divided voltage and a reference voltage; The PWM signal adjustment circuit is also configured to output a switching signal of a reference voltage required for mute adjustment to control the reference voltage to switch between a first reference voltage and a second reference voltage, the first switching signal corresponding to the first reference voltage, and the second switching signal corresponding to the second reference voltage.

10. A switching power supply, characterized in that: The switching power supply comprises a PWM signal control circuit according to any one of claims 7 to 9.

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