Level shifter and power driving chip

Abstract

The embodiment of the invention provides a level shifter and a power driving chip. The level shifter comprises a pull-down circuit, a pull-up circuit and an output circuit, two connection points of the pull-down circuit and the pull-up circuit are a first node and a second node respectively, and the potential of the first node and the potential of the second node are logically complementary. The pull-down circuit pulls down one of the first node potential and the second node potential, and the pull-up circuit generates a pull-up control signal according to the pull-down node potential and pulls up the other one of the first node potential and the second node potential according to the pull-up control signal and the pull-down node potential. The output circuit performs logical operation on the inversion signal of the target node potential to obtain an output signal, and the rising speed and the falling speed of the output signal can be improved by improving the rising speed and the falling speed of the first node potential and the second node potential, so that the level conversion speed is improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular to a level converter and a power driver chip. Background Art

[0002] Level converters are often used in the design of high-voltage application chips, such as high-voltage boost converters. Since the swing of the intermediate node of the level converter is very large, for example, the swing is 100V, considering the inherent parasitic capacitance of the high-voltage tube itself and the parasitic capacitance that may exist in the layout, in order to complete a low-voltage to high-voltage level conversion, it is necessary to overcome the influence of the capacitance, which leads to a slow level conversion speed. For example, it takes tens to hundreds of nanoseconds to complete a low-voltage to high-voltage level conversion.

[0003] In the prior art, by properly adjusting the pull-down or pull-up driving capability of the level converter, the output signal rise or fall speed can be accelerated. However, it is not possible to achieve rapid rise and fall of the output signal at the same time, which affects the conversion speed of the level converter. Summary of the Invention

[0004] The present disclosure provides a level converter and a power driver chip, which can simultaneously increase the rising speed and falling speed of an output signal, thereby increasing the level conversion speed.

[0005] In a first aspect, the present disclosure provides a level converter, including a pull-up circuit, a pull-down circuit, and an output circuit, wherein the two connection points of the pull-down circuit and the pull-up circuit are respectively a first node and a second node, and the potential of the first node and the potential of the second node are logically complementary.

[0006] The pull-down circuit is configured to pull down one of the first node potential and the second node potential when a level inversion occurs in an input signal. The pull-up circuit is configured to generate a pull-up control signal based on the pulled-down node potential, and to pull up the other of the first node potential and the second node potential based on the pull-up control signal and the pulled-down node potential. The output circuit is configured to perform a logical operation on an inverted signal of a target node potential to generate an output signal, where the target node potential is one of the first node potential and the second node potential.

[0007] In some embodiments of the present disclosure, the pull-down circuit includes a first pull-down branch and a second pull-down branch. The output end of the first pull-down branch is connected to the first node, the output end of the second pull-down branch is connected to the second node, the input end of the first pull-down branch and the input end of the second pull-down branch are connected to a low-voltage domain reference ground, and the control end of the first pull-down branch and the control end of the second pull-down branch are connected to the input signal.

[0008] The first pull-down branch is configured to pull down the potential of the first node when the input signal flips from a low level to a high level. The second pull-down branch is configured to pull down the potential of the second node when the input signal flips from a high level to a low level.

[0009] In some embodiments of the present disclosure, the pull-up circuit includes a first pull-up branch and a second pull-up branch. An input end of the first pull-up branch and an input end of the second pull-up branch are connected to a high-voltage domain power supply voltage, an output end of the first pull-up branch and a control end of the second pull-up branch are connected to the first node, and an output end of the second pull-up branch and the control end of the first pull-up branch are connected to the second node.

[0010] The first pull-up branch is configured to, when the input signal flips from a high level to a low level, generate the pull-up control signal based on the potential of the second node, and pull up the potential of the first node based on the pull-up control signal and the potential of the second node. The second pull-up branch is configured to, when the input signal flips from a low level to a high level, generate the pull-up control signal based on the potential of the first node, and pull up the potential of the second node based on the pull-up control signal and the potential of the first node.

[0011] In some embodiments of the present disclosure, the first pull-up branch includes a first transistor, a second transistor, a first pulse generator, a first inverter, and a second inverter. The first terminal of the first transistor, the first terminal of the second transistor, a power supply terminal of the first inverter, a power supply terminal of the second inverter, and a power supply terminal of the first pulse generator are connected to the high-voltage domain power supply voltage, and the ground terminal of the first inverter, the ground terminal of the second inverter, and the ground terminal of the first pulse generator are connected to the high-voltage domain reference ground.

[0012] The control end of the second transistor and the input end of the first inverter are connected to the second node, the output end of the first inverter is connected to the control end of the first transistor through the first pulse generator and the second inverter in sequence, and the second end of the first transistor and the second end of the second transistor are connected to the first node.

[0013] In some embodiments of the present disclosure, the second pull-up branch includes a third transistor, a fourth transistor, a second pulse generator, a third inverter, and a fourth inverter. The first terminal of the third transistor, the first terminal of the fourth transistor, a power supply terminal of the third inverter, a power supply terminal of the fourth inverter, and a power supply terminal of the second pulse generator are connected to the high-voltage domain power supply voltage, and the ground terminal of the third inverter, the ground terminal of the fourth inverter, and the ground terminal of the second pulse generator are connected to the high-voltage domain reference ground.

[0014] The control end of the fourth transistor and the input end of the third inverter are connected to the first node, the output end of the third inverter is connected to the control end of the third transistor through the second pulse generator and the fourth inverter in sequence, and the second end of the third transistor and the second end of the fourth transistor are connected to the second node.

[0015] In some embodiments of the present disclosure, the first pull-down branch includes a fifth transistor, a sixth transistor, a fifth inverter, and a sixth inverter. The first terminal of the fifth transistor is connected to the first node, the control terminal of the fifth transistor is connected to the high-voltage domain reference ground, the second terminal of the fifth transistor is connected to the low-voltage domain reference ground through the sixth transistor, and the ground terminal of the fifth inverter and the ground terminal of the sixth inverter are connected to the low-voltage domain reference ground. The power supply terminal of the fifth inverter and the power supply terminal of the sixth inverter are connected to the low-voltage domain power supply voltage, and the input signal is connected to the control terminal of the sixth transistor through the fifth inverter and the sixth inverter in sequence.

[0016] In some embodiments of the present disclosure, the second pull-down branch includes a seventh transistor, an eighth transistor, and a seventh inverter. The first terminal of the seventh transistor is connected to the second node, the control terminal of the seventh transistor is connected to the high-voltage domain reference ground, the second terminal of the seventh transistor is connected to the low-voltage domain reference ground through the eighth transistor, the ground terminal of the seventh inverter is connected to the low-voltage domain reference ground, the power terminal of the seventh inverter is connected to the low-voltage domain power supply voltage, and the input signal is connected to the control terminal of the eighth transistor through the seventh inverter.

[0017] In some embodiments of the present disclosure, the level converter further includes a latch circuit, wherein a first input terminal of the latch circuit is connected to the first node, a second input terminal of the latch circuit is connected to the second node, and an output terminal of the latch circuit is connected to a high-voltage domain reference ground.

[0018] The latch circuit is configured to, when the first node potential increases, pull down the second node potential to lock the level state of the second node potential; when the second node potential increases, pull down the first node potential to lock the level state of the first node potential.

[0019] In some embodiments of the present disclosure, the latch circuit includes a ninth transistor and a tenth transistor. A first terminal of the ninth transistor and a first terminal of the tenth transistor are connected to the high-voltage domain reference ground, a control terminal of the ninth transistor and a second terminal of the tenth transistor are connected to the second node, and the second terminal of the ninth transistor and the control terminal of the tenth transistor are connected to the first node.

[0020] In a second aspect, the present disclosure provides a power driver chip, comprising any level converter provided in the first aspect.

[0021] The technical solution disclosed in the present invention provides a level converter, including a pull-down circuit, a pull-up circuit and an output circuit. The two connection points of the pull-down circuit and the pull-up circuit are a first node and a second node, respectively. The potential of the first node and the potential of the second node are logically complementary. When the level of the input signal is flipped, the pull-down circuit pulls down one of the first node potential and the second node potential. The pull-up circuit generates a pull-up control signal according to the pulled-down node potential, and pulls up the other of the first node potential and the second node potential according to the pull-up control signal and the pulled-down node potential. The output circuit performs a logical operation on the inverted signal of the target node potential to obtain an output signal, thereby realizing the level conversion of the input signal. The rising speed and falling speed of the output signal can be increased by increasing the rising speed and falling speed of the first node potential and the second node potential, thereby increasing the level conversion speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. It should be noted that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure.

[0023] Figure 1 A schematic diagram of the structure of a level converter provided in an embodiment of the present disclosure.

[0024] Figure 2 A circuit diagram of a level converter provided by an embodiment of the present disclosure.

[0025] Figure 3 A schematic diagram of a narrow pulse signal provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0027] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal manner unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" together shall mean that the parts are joined together either directly or through one or more intermediate components.

[0028] References to "embodiments" in this disclosure mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiment" in various places in the specification does not necessarily refer to the same embodiment, nor does it refer to independent or alternative embodiments that are mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described in this disclosure may be combined with other embodiments.

[0029] In addition, the terms "first", "second", etc. in the description and claims of the present disclosure or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more such features.

[0030] In this disclosure, the term "and / or" simply describes an association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship.

[0031] In the description of the present disclosure, unless otherwise specified, "multiple" and "at least two" mean more than two (including two). Similarly, "multiple groups" and "at least two groups" mean more than two groups (including two).

[0032] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0033] Figure 1 A schematic diagram of a level converter according to an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the level converter 100 includes a pull-down circuit 110 and a pull-up circuit 120. The input terminal of the pull-down circuit 110 is connected to the low-voltage domain reference ground LGND, the control terminal of the pull-down circuit 110 is connected to the input signal IN, and the input terminal of the pull-up circuit 120 is connected to the high-voltage domain power supply voltage HVDD.

[0034] The first output terminal of the pull-down circuit 110, the first output terminal of the pull-up circuit 120, and the second control terminal of the pull-up circuit 120 are connected to a first node A. The second output terminal of the pull-down circuit 110, the second output terminal of the pull-up circuit 120, and the first control terminal of the pull-up circuit 120 are connected to a second node B. The potential of the first node VA and the potential of the second node VB are logically complementary.

[0035] The pull-down circuit 110 is configured to pull down one of the first node potential VA and the second node potential VB when the input signal IN undergoes a level inversion. The pull-up circuit 120 is configured to generate a pull-up control signal based on the pulled-down node potential and to pull up the other of the first node potential VA and the second node potential VB based on the pull-up control signal and the pulled-down node potential.

[0036] For example, Figure 2 A circuit diagram of a level converter provided by an embodiment of the present disclosure is shown in FIG. Figure 2 As shown, the pull-up circuit 120 includes a first pull-up branch 121 and a second pull-up branch 122. The input end of the first pull-up branch 121 and the input end of the second pull-up branch 122 are connected to the high-voltage domain power supply voltage HVDD, the output end of the first pull-up branch 121 and the control end of the second pull-up branch 122 are connected to a first node A, and the output end of the second pull-up branch 122 and the control end of the first pull-up branch 121 are connected to a second node B.

[0037] The first pull-up branch 121 includes a first transistor M1, a second transistor M2, a first pulse generator PG1, a first inverter INV1, and a second inverter INV2. The first end of the first transistor M1, the first end of the second transistor M2, the power supply end of the first inverter INV1, the power supply end of the second inverter INV2, and the power supply end of the first pulse generator PG1 are connected to the high-voltage domain power supply voltage HVDD, and the ground end of the first inverter INV1, the ground end of the second inverter INV2, and the ground end of the first pulse generator PG1 are connected to the high-voltage domain reference ground HGND. Wherein, HGND = HVDD-5V, for example, HVDD = 100V, HGND = 95V.

[0038] The control end of the second transistor M2 and the input end of the first inverter INV1 are connected to the second node B, the output end of the first inverter INV1 is connected to the control end of the first transistor M1 through the first pulse generator PG1 and the second inverter INV2 in sequence, and the second end of the first transistor M1 and the second end of the second transistor M2 are connected to the first node A.

[0039] Exemplarily, the first transistor M1 and the second transistor M2 are low-voltage P-type metal-oxide-semiconductor field-effect transistors (PMOS), and the driving capability of the first transistor M1 is much greater than that of the second transistor M2. The first pulse generator PG1 is a oneshot monostable trigger circuit that can generate a pulse signal with a fixed time width that lags behind the trigger pulse.

[0040] The second pull-up branch 122 includes a third transistor M3, a fourth transistor M4, a second pulse generator PG2, a third inverter INV3, and a fourth inverter INV4. A first terminal of the third transistor M3, a first terminal of the fourth transistor M4, a power supply terminal of the third inverter INV3, a power supply terminal of the fourth inverter INV4, and a power supply terminal of the second pulse generator PG2 are connected to the high-voltage domain power supply voltage HVDD. A ground terminal of the third inverter INV3, a ground terminal of the fourth inverter INV4, and a ground terminal of the second pulse generator PG2 are connected to the high-voltage domain reference ground HGND.

[0041] The control end of the fourth transistor M4 and the input end of the third inverter INV3 are connected to the first node A, the output end of the third inverter INV3 is connected to the control end of the third transistor M3 through the second pulse generator PG2 and the fourth inverter INV4 in sequence, and the second end of the third transistor M3 and the second end of the fourth transistor M4 are connected to the second node B.

[0042] Exemplarily, the third transistor M3 and the fourth transistor M4 are low-voltage PMOS transistors. The driving capability of the third transistor M3 is much greater than that of the fourth transistor M4. The first transistor M1 is the same size as the third transistor M3, and the second transistor M2 is the same size as the fourth transistor M4. The second pulse generator PG2 is a one-shot device.

[0043] Continue to see Figure 2 The pull-down circuit 110 includes a first pull-down branch 111 and a second pull-down branch 112. The output of the first pull-down branch 111 is connected to the first node A, the output of the second pull-down branch 112 is connected to the second node B, the input of the first pull-down branch 111 and the input of the second pull-down branch 112 are connected to the low-voltage domain reference ground LGND, and the control of the first pull-down branch 111 and the control of the second pull-down branch 112 are connected to the input signal IN.

[0044] The first pull-down branch 111 includes a fifth transistor M5, a sixth transistor M6, a fifth inverter INV5, and a sixth inverter INV6. A first terminal of the fifth transistor M5 is connected to the first node A, a control terminal of the fifth transistor M5 is connected to the high-voltage domain reference ground HGND, and a second terminal of the fifth transistor M5 is connected to the low-voltage domain reference ground LGND through the sixth transistor M6 (e.g., LGND=0). The ground terminals of the fifth inverter INV5 and the sixth inverter INV6 are connected to the low-voltage domain reference ground LGND, and the power terminals of the fifth inverter INV5 and the sixth inverter INV6 are connected to the low-voltage domain power supply voltage LVDD (e.g., LVDD=5V). An input signal IN is connected to the control terminal of the sixth transistor M6 via the fifth inverter INV5 and the sixth inverter INV6.

[0045] Exemplarily, the fifth transistor M5 is a high-voltage PMOS, the sixth transistor M6 is a high-voltage N-type metal oxide semiconductor field effect transistor (NMOS), the driving capability of the sixth transistor M6 is less than the driving capability of the first transistor M1, the driving capability of the fifth transistor M5 is greater than the driving capability of the sixth transistor M6, and the driving capability of the sixth transistor M6 is much greater than the driving capability of the second transistor M2.

[0046] The second pull-down branch 112 includes a seventh transistor M7, an eighth transistor M8 and a seventh inverter INV7. The first end of the seventh transistor M7 is connected to the second node B, the control end of the seventh transistor M7 is connected to the high-voltage domain reference ground HGND, the second end of the seventh transistor M7 is connected to the low-voltage domain reference ground LGND through the eighth transistor M8, the ground end of the seventh inverter INV7 is connected to the low-voltage domain reference ground LGND, the power supply end of the seventh inverter INV7 is connected to the low-voltage domain power supply voltage LVDD, and the input signal IN is connected to the control end of the eighth transistor M8 through the seventh inverter INV7.

[0047] Exemplarily, the seventh transistor M7 is a high-voltage PMOS transistor, and the eighth transistor M8 is a high-voltage NMOS transistor. The driving capability of the eighth transistor M8 is less than that of the third transistor M3, the driving capability of the seventh transistor M7 is greater than that of the eighth transistor M8, and the driving capability of the eighth transistor M8 is much greater than that of the fourth transistor M4. The size of the sixth transistor M6 is the same as that of the eighth transistor M8, and the size of the fifth transistor M5 is the same as that of the seventh transistor M7.

[0048] When the input signal IN flips from a low level to a high level, the eighth transistor M8 is turned off and the sixth transistor M6 is turned on. Since the driving capability of the sixth transistor M6 is much greater than that of the second transistor M2, the sixth transistor M6 can quickly pull down the potential of the second end of the fifth transistor M5. At the same time, the driving capability of the fifth transistor M5 is greater than that of the sixth transistor M6, so that the potential of the first node VA can quickly follow the decrease in the potential of the second end of the fifth transistor M5, thereby increasing the rate of decrease of the potential of the first node VA.

[0049] In this way, when the input signal IN flips from a low level to a high level, the first pull-down branch 111 can quickly pull down the first node potential VA, so as to increase the falling speed of the first node potential VA.

[0050] To ensure the falling speed of the first node potential VA, the driving capabilities of the fifth transistor M5 and the sixth transistor M6 must be strong, and the parasitic capacitance of the corresponding nodes must be larger. To prevent the area of ​​the high-voltage transistor from being too large, the driving capability of the second transistor M2 needs to be weakened. However, the reduced driving capability of the second transistor M2 will slow the rising speed of the second node potential VB, so the second pull-up branch 122 is provided.

[0051] In the second pull-up branch 122, when the input signal IN switches from a low level to a high level, the potential of the first node VA drops, and the potential of the first node VA switches from a high level to a low level. At this time, the fourth transistor M4 is in the on state, and the fourth transistor M4 can pull up the potential of the second node VB.

[0052] At the same time, the third inverter INV3 logically inverts the first node potential VA, and the obtained inverted signal of the first node potential VA is flipped from a low level to a high level, and the rising edge of the inverted signal of the first node potential VA triggers the second pulse generator PG2 to generate a narrow pulse signal, such as Figure 3 As shown, Figure 3 A schematic diagram of a narrow pulse signal provided in an embodiment of the present disclosure. The fourth inverter INV4 logically inverts the narrow pulse signal to generate a pull-up control signal. At this time, the third transistor M3 is in the on state. Because the driving capability of the third transistor M3 is greater than that of the eighth transistor M8, the third transistor M3 can quickly pull up the potential of the second node VB according to the pull-up control signal.

[0053] In this way, when the input signal IN flips from a low level to a high level, the second pull-up branch 122 generates a pull-up control signal according to the first node potential VA, and pulls up the second node potential VB according to the pull-up control signal and the first node potential VA to increase the rising speed of the second node potential VB.

[0054] When the input signal IN flips from a high level to a low level, the sixth transistor M6 is turned off and the eighth transistor M8 is turned on. Since the driving capability of the eighth transistor M8 is much greater than that of the fourth transistor M4, the eighth transistor M8 can quickly pull down the potential of the second end of the seventh transistor M7. At the same time, the driving capability of the seventh transistor M7 is greater than that of the eighth transistor M8, so that the potential of the second node VB can quickly follow the decrease in the potential of the second end of the seventh transistor M7, thereby increasing the decreasing speed of the potential of the second node VB.

[0055] In this way, when the input signal IN switches from a high level to a low level, the second pull-down branch 112 can quickly pull down the second node potential VB, thereby increasing the falling speed of the second node potential VB.

[0056] To ensure the falling speed of the second node potential VB, the driving capabilities of the seventh transistor M7 and the eighth transistor M8 must be strong, and the parasitic capacitance of the corresponding nodes must be larger. To prevent the area of ​​the high-voltage transistor from being too large, the driving capability of the fourth transistor M4 needs to be weakened. However, the reduced driving capability of the fourth transistor M4 will slow the rising speed of the first node potential VA, so the first pull-up branch 121 is provided.

[0057] In the first pull-up branch 121, when the input signal IN switches from a high level to a low level, the second node potential VB switches from a high level to a low level as the second node potential VB drops. At this time, the second transistor M2 is in the on state and can pull up the first node potential VA.

[0058] At the same time, the first inverter INV1 logically inverts the second node potential VB, and the obtained inverted signal of the second node potential VB flips from a low level to a high level, and the rising edge of the inverted signal of the second node potential VB triggers the first pulse generator PG1 to generate a narrow pulse signal, such as Figure 3 The second inverter INV2 logically inverts the narrow pulse signal to obtain a pull-up control signal. At this time, the first transistor M1 is in the on state. Since the driving capability of the first transistor M1 is greater than the driving capability of the sixth transistor M6, the first transistor M1 can quickly pull up the first node potential VA according to the pull-up control signal.

[0059] In this way, when the input signal IN flips from a high level to a low level, the first pull-up branch 121 generates a pull-up control signal according to the second node potential VB, and pulls up the first node potential VA according to the pull-up control signal and the second node potential VB to increase the rising speed of the first node potential VA.

[0060] Continue to see Figure 1 and Figure 2The level shifter 100 further includes an output circuit 130 , an input terminal of the output circuit 130 can be connected to an inverted signal of the first node potential VA, and an output terminal of the output circuit 130 is connected to an output terminal of the level shifter 100 to output an output signal OUT.

[0061] For example, Figure 2 As shown, the output circuit 130 includes an eighth inverter INV8 and a ninth inverter INV9. The input of the eighth inverter INV8 is connected to the output of the third inverter INV3. The output of the eighth inverter INV8 is connected to the output of the level shifter 100 through the ninth inverter INV9.

[0062] When the input signal IN flips from a low level to a high level, the first node potential VA flips from a high level to a low level, and the inverted signal of the first node potential VA flips from a low level to a high level. The inverted signal of the first node potential VA is logically inverted twice, and the resulting output signal OUT flips from a low level to a high level.

[0063] When the input signal IN flips from a high level to a low level, the second node potential VB flips from a high level to a low level, the first node potential VA flips from a low level to a high level, and the inverted signal of the first node potential VA flips from a high level to a low level. The inverted signal of the first node potential VA is logically inverted twice, and the resulting output signal OUT flips from a high level to a low level.

[0064] In other embodiments, the input terminal of the eighth inverter INV8 is connected to the output terminal of the first inverter INV1 , so that the input terminal of the output circuit 130 receives the inverted signal of the second node potential VB.

[0065] When the input signal IN flips from a low level to a high level, the first node potential VA flips from a high level to a low level, the second node potential VB flips from a low level to a high level, and the inverted signal of the second node potential VB flips from a high level to a low level. The inverted signal of the second node potential VB is logically inverted twice, and the resulting output signal OUT flips from a high level to a low level.

[0066] When the input signal IN flips from a high level to a low level, the second node potential VB flips from a high level to a low level, and the inverted signal of the second node potential VB flips from a low level to a high level. The inverted signal of the second node potential VB is logically inverted twice, and the resulting output signal OUT flips from a low level to a high level.

[0067] In this manner, the output circuit 130 can perform a logical operation on the inverted signal of the target node potential to obtain an output signal OUT, where the target node potential is either the first node potential VA or the second node potential VB. When the input terminal of the output circuit 130 is connected to the inverted signal of the first node potential VA, the output circuit 130 can perform a logical operation on the inverted signal of the first node potential VA to obtain an output signal OUT, thereby achieving level conversion of the input signal IN. When the input terminal of the output circuit 130 is connected to the inverted signal of the second node potential VB, the output circuit 130 can perform a logical operation on the inverted signal of the second node potential VB to obtain an output signal OUT, thereby achieving level conversion of the input signal IN.

[0068] In summary, the level converter in the embodiment of the present disclosure includes a pull-down circuit, a pull-up circuit and an output circuit. The two connection points of the pull-down circuit and the pull-up circuit are the first node and the second node respectively. The first node potential and the second node potential are logically complementary. When the input signal is level-reversed, the pull-down circuit pulls down one of the first node potential and the second node potential. The pull-up circuit generates a pull-up control signal according to the pulled-down node potential, and pulls up the other node potential of the first node potential and the second node potential according to the pull-up control signal and the pulled-down node potential. The output circuit performs a logical operation on the inverted signal of the target node potential to obtain an output signal, thereby realizing the level conversion of the input signal. The rising speed and falling speed of the output signal can be increased by increasing the rising speed and falling speed of the first node potential and the second node potential, thereby increasing the level conversion speed.

[0069] In some embodiments, see Figure 2 The level converter 100 further includes a latch circuit 140. A first input terminal of the latch circuit 140 is connected to the first node A, a second input terminal of the latch circuit 140 is connected to the second node B, and an output terminal of the latch circuit 140 is connected to the high voltage domain reference ground HGND.

[0070] The latch circuit 140 is configured to pull down the second node potential VB to lock the level state of the second node potential VB when the first node potential VA increases; and to pull down the first node potential VA to lock the level state of the first node potential VA when the second node potential VB increases.

[0071] For example, Figure 2 As shown, the latch circuit 140 includes a ninth transistor M9 and a tenth transistor M10, wherein the first end of the ninth transistor M9 and the first end of the tenth transistor M10 are connected to the high-voltage domain reference ground HGND, the control end of the ninth transistor M9 and the second end of the tenth transistor M10 are connected to the second node B, and the second end of the ninth transistor M9 and the control end of the tenth transistor M10 are connected to the first node A.

[0072] Among them, the ninth transistor M9 and the tenth transistor M10 are low-voltage NMOS, the size of the ninth transistor M9 is the same as the size of the tenth transistor M10, and the width-to-length ratio of the ninth transistor M9 and the width-to-length ratio of the tenth transistor M10 are very inversely proportional to avoid a significant impact on the driving capabilities of the third transistor M3 and the fourth transistor M4.

[0073] Since the fifth transistor M5 and the seventh transistor M7 are high-voltage PMOS transistors, the threshold voltages of the fifth transistor M5 and the seventh transistor M7 are higher than the threshold voltages of the low-voltage transistors in the eighth inverter INV8 and the ninth inverter INV9. Therefore, when the input signal IN flips from a low level to a high level, the second node potential VB increases, and the ninth transistor M9 is turned on, which can pull the first node potential VA to a sufficiently low level to lock the level state of the first node potential VA through positive feedback, thereby preventing the level state of the first node potential VA from occurring in an intermediate state.

[0074] When the input signal IN flips from a high level to a low level, the first node potential VA increases, and the tenth transistor M10 is turned on, which can pull the second node potential VB to a sufficiently low level to lock the level state of the second node potential VB through positive feedback, thereby avoiding the level state of the second node potential VB from being in an intermediate state.

[0075] An embodiment of the present disclosure further provides a power driver chip, comprising the level converter 100 provided in any of the above embodiments.

[0076] For example, the power driver chip can drive a high-voltage switching power supply, such as a high-voltage Boost converter, a high-voltage Buck converter, a high-voltage Boost-Buck converter, a charge pump, and a flyback converter. In other embodiments, the power driver chip can also drive a low-voltage switching power supply.

[0077] The power driver chip provided in the embodiment of the present disclosure includes the level converter 100 provided in any of the above embodiments, and has the functional modules and beneficial effects possessed by the level converter 100, which will not be described in detail here.

[0078] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, the "example" is merely illustrative and should not be considered exclusive or comprehensive.

[0079] Several embodiments of the present disclosure have been described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A level converter, characterized in that: It includes a pull-down circuit, a pull-up circuit and an output circuit, wherein two connection points of the pull-down circuit and the pull-up circuit are respectively a first node and a second node, and the potential of the first node and the potential of the second node are logically complementary; The pull-down circuit is configured to pull down one of the first node potential and the second node potential when a level of an input signal is flipped; The pull-up circuit is configured to generate a pull-up control signal according to the pulled-down node potential, and pull up the other node potential of the first node potential and the second node potential according to the pull-up control signal and the pulled-down node potential; The output circuit is configured to perform a logic operation on an inverted signal of a target node potential to obtain an output signal, where the target node potential is one of the first node potential and the second node potential.

2. The level converter according to claim 1, wherein: The pull-down circuit includes a first pull-down branch and a second pull-down branch; The output end of the first pull-down branch is connected to the first node, the output end of the second pull-down branch is connected to the second node, the input end of the first pull-down branch and the input end of the second pull-down branch are connected to the low-voltage domain reference ground, and the control end of the first pull-down branch and the control end of the second pull-down branch are connected to the input signal; The first pull-down branch is configured to pull down the potential of the first node when the input signal flips from a low level to a high level; The second pull-down branch is configured to pull down the second node potential when the input signal switches from a high level to a low level.

3. The level converter according to claim 2, wherein: The pull-up circuit includes a first pull-up branch and a second pull-up branch; The input end of the first pull-up branch and the input end of the second pull-up branch are connected to the high-voltage domain power supply voltage, the output end of the first pull-up branch and the control end of the second pull-up branch are connected to the first node, and the output end of the second pull-up branch and the control end of the first pull-up branch are connected to the second node; The first pull-up branch is configured to, when the input signal flips from a high level to a low level, generate the pull-up control signal according to the second node potential, and pull up the first node potential according to the pull-up control signal and the second node potential; The second pull-up branch is configured to generate a pull-up control signal according to the first node potential when the input signal flips from a low level to a high level, and pull up the second node potential according to the pull-up control signal and the first node potential.

4. The level converter according to claim 3, wherein: The first pull-up branch includes a first transistor, a second transistor, a first pulse generator, a first inverter and a second inverter; The first terminal of the first transistor, the first terminal of the second transistor, the power supply terminal of the first inverter, the power supply terminal of the second inverter, and the power supply terminal of the first pulse generator are connected to the high-voltage domain power supply voltage, and the ground terminal of the first inverter, the ground terminal of the second inverter, and the ground terminal of the first pulse generator are connected to the high-voltage domain reference ground; The control end of the second transistor and the input end of the first inverter are connected to the second node, the output end of the first inverter is connected to the control end of the first transistor through the first pulse generator and the second inverter in sequence, and the second end of the first transistor and the second end of the second transistor are connected to the first node.

5. The level converter according to claim 3, wherein: The second pull-up branch includes a third transistor, a fourth transistor, a second pulse generator, a third inverter and a fourth inverter; The first end of the third transistor, the first end of the fourth transistor, the power supply end of the third inverter, the power supply end of the fourth inverter and the power supply end of the second pulse generator are connected to the high-voltage domain power supply voltage, and the ground end of the third inverter, the ground end of the fourth inverter and the ground end of the second pulse generator are connected to the high-voltage domain reference ground; The control end of the fourth transistor and the input end of the third inverter are connected to the first node, the output end of the third inverter is connected to the control end of the third transistor through the second pulse generator and the fourth inverter in sequence, and the second end of the third transistor and the second end of the fourth transistor are connected to the second node.

6. The level converter according to claim 2, wherein: The first pull-down branch includes a fifth transistor, a sixth transistor, a fifth inverter and a sixth inverter; A first terminal of the fifth transistor is connected to the first node, a control terminal of the fifth transistor is connected to the high-voltage domain reference ground, a second terminal of the fifth transistor is connected to the low-voltage domain reference ground via the sixth transistor, and a ground terminal of the fifth inverter and a ground terminal of the sixth inverter are connected to the low-voltage domain reference ground; The power supply terminal of the fifth inverter and the power supply terminal of the sixth inverter are connected to the low-voltage domain power supply voltage, and the input signal is connected to the control terminal of the sixth transistor through the fifth inverter and the sixth inverter in sequence.

7. The level converter according to claim 2, wherein: The second pull-down branch includes a seventh transistor, an eighth transistor and a seventh inverter; The first end of the seventh transistor is connected to the second node, the control end of the seventh transistor is connected to the high-voltage domain reference ground, the second end of the seventh transistor is connected to the low-voltage domain reference ground through the eighth transistor, the ground end of the seventh inverter is connected to the low-voltage domain reference ground, the power supply end of the seventh inverter is connected to the low-voltage domain power supply voltage, and the input signal is connected to the control end of the eighth transistor through the seventh inverter.

8. The level converter according to any one of claims 2 to 7, wherein: The level converter further includes a latch circuit; The first input terminal of the latch circuit is connected to the first node, the second input terminal of the latch circuit is connected to the second node, and the output terminal of the latch circuit is connected to the high voltage domain reference ground; The latch circuit is configured to pull down the potential of the second node to lock the level state of the potential of the second node when the potential of the first node increases; When the potential of the second node increases, the potential of the first node is pulled down to lock the level state of the potential of the first node.

9. The level converter according to claim 8, wherein: The latch circuit includes a ninth transistor and a tenth transistor; The first end of the ninth transistor and the first end of the tenth transistor are connected to the high-voltage domain reference ground, the control end of the ninth transistor and the second end of the tenth transistor are connected to the second node, and the second end of the ninth transistor and the control end of the tenth transistor are connected to the first node.

10. A power driver chip, characterized in that: The level converter comprises the level converter according to any one of claims 1 to 9.

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