Clock data recovery circuit, clock data recovery method and MIPI C-PHY device

Abstract

The invention relates to a clock data recovery circuit, a clock data recovery method and MIPI C-PHY equipment. The clock data recovery circuit comprises a sampling module and a ring oscillator module. The sampling module is used for receiving a plurality of full-swing data signals so as to output setting signals after detecting edges of the full-swing data signals; the ring oscillator module is connected with the sampling module and is used for respectively outputting a first recovery clock signal and a second recovery clock signal based on the setting signal; the first recovery clock signal acts on the sampling module, so that the sampling module detects the edge of the full-swing data signal based on the first recovery clock signal; the second recovery clock signal corresponds to the delay duration of the ring oscillator module, so that the external processor adjusts the delay duration of the ring oscillator module according to the second recovery clock signal. According to the invention, the initial data signal can be accurately sampled, so that the bit error rate of data acquisition is reduced.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to a clock data recovery circuit, a clock data recovery method, and a MIPI C-PHY device. Background Art

[0002] In modern communication systems, accurate transmission and reception of data signals is crucial. Clock Data Recovery (CDR) technology is one of the key links to achieve this goal.

[0003] The main function of CDR is to extract the clock signal from the received signal and sample and calibrate the data signal according to the clock signal to ensure the correct recovery of the data.

[0004] However, existing CDR technology has obvious limitations in certain scenarios and cannot accurately detect the delay of data signals, which in turn leads to the inability to accurately calibrate data signals. Summary of the Invention

[0005] Based on this, it is necessary to provide a clock data recovery circuit, a clock data recovery method and a MIPI C-PHY device that can improve the data signal sampling accuracy in order to address the above technical problems.

[0006] In a first aspect, the present application provides a clock data recovery circuit, comprising:

[0007] a sampling module, configured to receive a plurality of full-swing data signals, detect edges of the full-swing data signals, output a set signal, and output a recovered data signal;

[0008] A ring oscillator module is connected to the sampling module and is configured to output a first recovered clock signal and a second recovered clock signal, respectively, based on the set signal; the first recovered clock signal acts on the sampling module so that the sampling module samples the edge of the full-swing data signal based on the first recovered clock signal; and the second recovered clock signal corresponds to the delay length of the ring oscillator module so that an external processor adjusts the delay length of the ring oscillator module according to the second recovered clock signal.

[0009] In one embodiment, the ring oscillator module includes:

[0010] A first latch is configured with a set pin, a reset pin and an output pin, wherein the set pin is connected to the sampling module and is used to receive the set signal;

[0011] a first delay unit, wherein an input end of the first delay unit is connected to the output pin and is configured to output a third recovered clock signal;

[0012] a first inverter, wherein an input end of the first inverter is connected to an output end of the first delay unit, and an output end of the first inverter is connected to the reset pin, and is configured to invert the third recovered clock signal and output a reset signal to the reset pin;

[0013] An inverter chain unit is connected to the first delay unit and the sampling module, and is used to output the first recovered clock signal and the second recovered clock signal respectively after inverting the third recovered clock signal for different times.

[0014] In one embodiment, the truth table of the first latch is:

[0015] set=0, reset=0, out=1;

[0016] set=0, reset=1, out=latch;

[0017] set=1, reset=0, out=1;

[0018] set=1, reset=1, out=0;

[0019] Among them, set is the set signal; rest is the reset signal; out is the output signal; latch is to maintain the previous state.

[0020] In one embodiment, the inverter chain unit includes a plurality of inverters connected in series, so as to output the first recovered clock signal and the second recovered clock signal respectively after inverting the third recovered clock signal for different times.

[0021] In one embodiment, the inverter chain unit includes:

[0022] a second inverter, wherein an input end of the second inverter is connected to an output end of the first delay unit, and an output end of the second inverter is connected to the sampling module, and is configured to invert the third recovered clock signal once and then output the first recovered clock signal;

[0023] a third inverter, wherein an input terminal of the third inverter is connected to an output terminal of the second inverter;

[0024] a fourth inverter, wherein an input end of the fourth inverter is connected to an output end of the third inverter, and an output end of the fourth inverter is used to output the second recovered clock signal.

[0025] In one embodiment, the sampling module includes:

[0026] a plurality of pulse generators, each of the plurality of pulse generators correspondingly connected to the plurality of rail-to-rail data signals, detecting edges of the rail-to-rail data signals and outputting a plurality of corresponding detection pulse signals;

[0027] A NAND gate, wherein the multiple input ends of the NAND gate are respectively connected to the multiple pulse generators, and the output end of the NAND gate is connected to the ring oscillator module, and is used to output the set signal after performing a NAND logic operation on the multiple detection pulse signals.

[0028] In one embodiment, the pulse generator comprises:

[0029] A NOR gate, wherein two input terminals of the NOR gate are respectively connected to an enable signal and a full-swing data signal;

[0030] a fifth inverter, wherein an input terminal of the fifth inverter is connected to an output terminal of the NOR gate;

[0031] a multiplexer, wherein two input terminals of the multiplexer are respectively connected to the output terminal of the NOR gate and the output terminal of the fifth inverter, and a controlled terminal of the multiplexer is used to receive the enable signal;

[0032] A second delay unit is connected to the output end of the NOR gate;

[0033] a second latch, connected to the ring oscillator module and the second delay unit, and configured to receive the first recovered clock signal, so as to sample the full-swing data signal after the delay processing by the second delay unit under the action of the first recovered clock signal and output a sampling signal;

[0034] an XNOR gate, wherein two input terminals of the XNOR gate are connected to the output terminal of the multiplexer and the second latch, respectively, so as to perform an XNOR logic operation on the signal output by the multiplexer and the sampling signal and then output the corresponding detection pulse signal;

[0035] A sixth inverter, wherein an input end of the sixth inverter is connected to the second latch, and the sixth inverter is used to invert the sampling signal output by the second latch to output a restored data signal.

[0036] In a second aspect, the present application further provides a clock data recovery method, which is applied to the clock data recovery circuit of the first aspect; comprising:

[0037] Outputting an enable signal to the clock data recovery circuit to sequentially configure the first delay unit of the clock data recovery circuit using different code words in ascending order, so that the clock data recovery circuit outputs the corresponding statically calibrated second recovered clock signal;

[0038] detecting the statically calibrated second recovered clock signal within a first preset time window after a first duration from a moment when the codeword is switched, to obtain a first frequency of the statically calibrated second recovered clock signal;

[0039] A first calibration codeword is acquired according to the first frequency and an input rate of receiving an initial data signal, so that the first delay unit operates under a configuration corresponding to the first calibration codeword.

[0040] In one embodiment, it further includes:

[0041] configuring the first calibration codeword to the first delay unit, and controlling the clock data recovery circuit to operate accordingly to output the dynamically calibrated second recovered clock signal;

[0042] detecting the dynamically calibrated second recovered clock signal within a second preset time window after a second duration of time from when the clock data recovery circuit starts operating under the configuration corresponding to the first calibration codeword to obtain a second frequency of the dynamically calibrated second recovered clock signal;

[0043] A second calibration codeword is acquired according to the first frequency and the second frequency, so that the first delay unit operates under a configuration corresponding to the second calibration codeword.

[0044] In a third aspect, the present application further provides a MIPI C-PHY device, comprising the clock data recovery circuit of the first aspect.

[0045] The clock data recovery circuit, clock data recovery method, and MIPI C-PHY device described above include a sampling module and a ring oscillator module. The sampling module is used to receive multiple full-swing data signals, sample the edges of the full-swing data signals, output a set signal, and output the recovered data signals. The ring oscillator module is connected to the sampling module and is used to output a first recovered clock signal and a second recovered clock signal based on the set signal. The first recovered clock signal acts on the sampling module, causing the sampling module to detect the edges of the full-swing data signals based on the first recovered clock signal. The second recovered clock signal corresponds to the delay length of the ring oscillator module, allowing an external processor to adjust the delay length of the ring oscillator module based on the second recovered clock signal, so that the sampling module can accurately sample the full-swing data signals based on the first recovered clock signal, thereby reducing the bit error rate of data acquisition. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments of the present application or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying any creative work.

[0047] Figure 1 This is one of the structural diagrams of the clock data recovery circuit in one embodiment of the present application;

[0048] Figure 2 Schematic diagram of the structure of a ring oscillator module in one embodiment of the present application;

[0049] Figure 3 This is a schematic structural diagram of a first latch in an embodiment of the present application;

[0050] Figure 4 Schematic diagram of the structure of an inverter chain unit in one embodiment of the present application;

[0051] Figure 5 Schematic diagram of the structure of the sampling module in one embodiment of the present application;

[0052] Figure 6 This is one of the structural diagrams of a pulse generator in one embodiment of the present application;

[0053] Figure 7 This is a second structural diagram of a pulse generator in one embodiment of the present application;

[0054] Figure 8 This is a structural diagram of a first delay unit in an embodiment of the present application;

[0055] Figure 9 This is a second structural diagram of a clock data recovery circuit in an embodiment of the present application;

[0056] Figure 10 1 is a timing diagram of three full-swing data signals, three corresponding detection pulse signals, a set signal, a third recovered clock signal, and a reset signal / first recovered clock signal in an embodiment of the present application;

[0057] Figure 11 Schematic diagram of a flow chart of a clock data recovery method in one embodiment of the present application;

[0058] Figure 12 This is a timing diagram of the enable signal, the codeword sequence of the first delay unit, the time count, and the second recovered clock signal under static calibration in one embodiment of the present application;

[0059] Figure 13This is a timing diagram of the dynamic calibration enable signal, data reception enable signal, second recovered clock signal, codeword sequence of the first delay unit, and time count in one embodiment of the present application.

[0060] Description of Figure Numbers:

[0061] 110: Sampling module; 111: Pulse generator; 1111: NOR gate; 1112: Fifth inverter; 1113: Multiplexer; 1114: Second delay unit; 1115: Second latch; 1116: XNOR gate; 1117: Sixth inverter; 112: NAND gate; 120: Ring oscillator module; 121: First latch; 1211: Seventh inverter; 122: First delay unit; 123: First inverter; 124: Inverter chain unit; 1241: Second inverter; 1242: Third inverter; 1243: Fourth inverter. DETAILED DESCRIPTION

[0062] To make the above-mentioned objects, features, and advantages of the present application more clearly understood, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings. The following description sets forth many specific details to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways than those described herein, and those skilled in the art can make similar improvements without violating the scope of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0063] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0064] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0065] In this application, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two elements or interaction between two elements, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0066] See Figure 1 , Figure 1 FIG1 shows a schematic diagram of a clock data recovery circuit according to an embodiment of the present application. The clock data recovery circuit provided by an embodiment of the present application includes a sampling module 110 and a ring oscillator module 120 .

[0067] The sampling module 110 is used to receive multiple full-swing data signals, sample the edges of the full-swing data signals, output a set signal set, and output a recovered data signal; the ring oscillator module 120 is connected to the sampling module 110, and outputs a first recovered clock signal ckn and a second recovered clock signal cko respectively based on the set signal set; the first recovered clock signal ckn acts on the sampling module 110, so that the sampling module 110 detects the edges of the full-swing data signals based on the first recovered clock signal ckn; the second recovered clock signal cko corresponds to the delay length of the ring oscillator module 120, so that the external processor adjusts the delay length of the ring oscillator module 120 according to the second recovered clock signal cko, so that the sampling module 110 can accurately sample the full-swing data signals based on the first recovered clock signal ckn.

[0068] Multiple full-swing data signals can be generated by a preceding analog front-end differential amplifier (AFE) module, which performs differential amplification on the multiple initial data signals before outputting them. For example, the clock data recovery circuit is used in devices compliant with the MIPI (Mobile Industry Processor Interface) C-PHY (Clocked Physical Layer) standard. These devices receive three data paths (data a, data b, and data c). These three data paths are then differentially amplified by the preceding AFE module to produce the corresponding three full-swing data signals (di_ab, di_bc, and di_ca). Because the data transmission module in MIPI C-PHY devices embeds the clock signal into the data signal through encoding, at least one of the di_ab / di_bc / di_ca edges in each data unit interval (UI) will transition.

[0069] In the embodiment of the present application, the sampling module 110 can detect the edge of the full-swing data signal and then output a set signal set. The set signal set is input to the ring oscillator module 120. The ring oscillator module outputs a first recovered clock signal ckn based on the set signal set. The first recovered clock signal ckn can be understood as an intermediate recovered clock signal used to further determine the delay of the initial data signal. The sampling module 110 performs edge detection on the full-swing data signal based on the first recovered clock signal ckn to realize sampled data input.

[0070] The second recovered clock signal cko can accurately characterize the delay of the initial data signal, so that the external processor can adjust the delay length of the ring oscillator module 120 according to the second recovered clock signal cko, and at the same time enable the sampling module 110 to accurately sample the full-swing data signal based on the first recovered clock signal ckn, thereby reducing the bit error rate of data acquisition.

[0071] Combine Figure 2 As shown, Figure 2 Schematic diagram of the structure of the ring oscillator module 120 in an embodiment of the present application is shown. In some embodiments, the ring oscillator module 120 includes a first latch 121, a first delay unit 122, a first inverter 123 and an inverter chain unit 124.

[0072] The first latch 121 is configured with a set pin, a reset pin, and an output pin. The set pin is connected to the sampling module 110 and is used to receive the set signal set.

[0073] An input end of the first delay unit 122 is connected to the output pin, and is configured to output the third recovered clock signal ckp.

[0074] The first delay unit 122 may be a programmable delay unit (eg, PROG_DELAY).

[0075] The input end of the first inverter 123 is connected to the output end of the first delay unit 122 , and the output end of the first inverter 123 is connected to the reset pin, for inverting the third recovered clock signal ckp and outputting a reset signal rest to the reset pin.

[0076] The inverter chain unit 124 is connected to the first delay unit 122 and the sampling module 110 and is configured to invert the third recovered clock signal ckp for different times and output a first recovered clock signal ckn and a second recovered clock signal cko respectively.

[0077] The inverter chain unit 124 includes a plurality of inverters, the number of which corresponds to a multiple of the oscillation period of the ring oscillator module 120 and the total loop delay of the inverter chain unit 124. For example, the inverter chain unit 124 includes three inverters, and the oscillation period of the ring oscillator module 120 is twice the total loop delay of the inverter chain unit 124.

[0078] In this embodiment, the first latch 121 is configured with a set pin and a reset pin. In other words, the first latch 121 is a latch with asynchronous reset and set functions. The set signal "set" is transmitted to the set pin of the first latch 121. The first delay unit 122 has a tunable delay function and delays the output signal of the first latch 121, thereby outputting a third recovered clock signal "ckp." The first inverter 123 inverts the third recovered clock signal "ckp" to generate a reset signal "rest" that is applied to the reset pin of the first latch 121. The reset signal "rest" is applied to the first latch 121, resetting its output and allowing the first latch 121 to continue receiving the set signal "set" corresponding to the edge of the next set of rail-to-rail data signals detected by the sampling module 110. The inverter chain unit 124 also inverts the third recovered clock signal "ckp" at different times, thereby outputting a first recovered clock signal "ckn" and a second recovered clock signal "cko," respectively.

[0079] In some embodiments, the truth table of the first latch 121 is: set=0, reset=0, out=1; set=0, reset=1, out=latch; set=1, reset=0, out=1; set=1, reset=1, out=0.

[0080] Among them, set is the set signal; rest is the reset signal; out is the output signal; latch is to maintain the previous state.

[0081] Combine Figure 3 As shown, Figure 3 The schematic diagram of the structure of the first latch 121 in one embodiment of the present application is shown. In some embodiments, the first latch 121 may include seven transistors M1 to M7 and a seventh inverter 1211. The first conduction terminal of the first transistor M1 is used to receive the supply voltage V, the second conduction terminal of the first transistor M1 is connected to the second conduction terminal of the second transistor M2, the first conduction terminal of the second transistor M2 is connected to the second conduction terminal of the third transistor M3, the first conduction terminal of the third transistor M3 is connected to the equivalent ground terminal GND, the first conduction terminal of the fourth transistor M4 is used to receive the supply voltage V, the second conduction terminal of the fourth transistor M4 is connected to the first conduction terminal of the fifth transistor M5, the second conduction terminal of the fifth transistor M5 is connected to the second conduction terminal of the sixth transistor M6, the first conduction terminal of the sixth transistor M6 is connected to the second conduction terminal of the seventh transistor M7, and the first conduction terminal of the seventh transistor is connected to the equivalent ground terminal GND. Among them, the second transistor M2, the fourth transistor M4 and the controlled terminal are all used to receive the set signal set. The controlled ends of the first transistor M1, the third transistor M3, and the seventh transistor M7 are all used to receive the reset signal rest. The second conduction end of the first transistor M1, the second conduction end of the second transistor M2, the second conduction end of the fifth transistor M5, and the second conduction end of the sixth transistor M6 are all used to connect to the input end of the seventh inverter 1211. The input end of the seventh inverter 1211 is also connected to the first delay unit 122 as the output pin of the first latch 121. The controlled ends of the fifth transistor M5 and the sixth transistor M6 are both connected to the output end of the seventh inverter 1211.

[0082] In some embodiments, the inverter chain unit includes a plurality of inverters connected in series, so as to respectively output the first recovered clock signal and the second recovered clock signal after inverting the third recovered clock signal for different times.

[0083] Combine Figure 4 As shown, Figure 4The structure of the inverter chain unit 124 in one embodiment of the present application is shown. In some embodiments, the inverter chain unit 124 includes a second inverter 1241, a third inverter 1242, and a fourth inverter 1243. The input of the second inverter 1241 is connected to the output of the first delay unit 122, and the output of the second inverter 1241 is connected to the sampling module 110. The second inverter 1241 is configured to invert the third recovered clock signal ckp and output the first recovered clock signal ckn. The input of the third inverter 1242 is connected to the output of the second inverter 1241. The input of the fourth inverter 1243 is connected to the output of the third inverter 1242. The output of the fourth inverter 1243 is configured to output the second recovered clock signal cko.

[0084] In this embodiment, the second inverter 1241 inverts the third recovered clock signal ckp once and outputs the first recovered clock signal ckn. The first recovered clock is transmitted to the sampling module 110. The input end of the third inverter 1242 is connected to the output end of the second inverter 1241. The third recovered clock signal ckp is inverted twice after passing through the second inverter 1241 and the third inverter 1242. Finally, it is inverted three times after passing through the fourth inverter 1243 to output the final recovered second recovered clock signal cko.

[0085] Combine Figure 5 As shown, Figure 5 The schematic diagram of the structure of the sampling module 110 in one embodiment of the present application is shown. In some embodiments, the sampling module 110 includes a NAND gate 112 and multiple pulse generators 111. The multiple pulse generators 111 are connected to multiple full-swing data signals in a one-to-one correspondence to detect the edges of the full-swing data signals and output multiple corresponding detection pulse signals. The multiple input terminals of the NAND gate 112 are respectively connected to the multiple pulse generators 111, and the output terminal of the NAND gate 112 is connected to the ring oscillator module 120, which is used to perform a NAND logical operation on the multiple detection pulse signals and output a set signal set.

[0086] In this embodiment, the sampling module 110 includes a NAND gate 112 and multiple pulse generators 111. The multiple pulse generators 111 detect the edge transition conditions of multiple full-swing data signals one by one, thereby outputting multiple corresponding detection pulse signals after edge detection. The multiple detection pulse signals are input to the NAND gate 112 for performing a NAND logic operation and are output as a set signal set.

[0087] Illustratively, three full-swing data signals (di_ab, di_bc, and di_ca) are respectively output as three detection pulse signals (ez_ab, ez_bc, and ez_ca) after passing through three pulse generators 111. The three input terminals of the NAND gate 112 are respectively connected to the three pulse generators 111 to perform a NAND logic operation on the three detection pulse signals (ez_ab, ez_bc, and ez_ca) and output a set signal set.

[0088] Combine Figure 6 As shown, Figure 6 One of the structural diagrams of the pulse generator 111 in one embodiment of the present application is shown. In some embodiments, the pulse generator 111 includes a NOR gate 1111, a fifth inverter 1112, a multiplexer 1113, a second delay unit 1114, a second latch 1115 and an exclusive NOR gate 1116. The two input ends of the NOR gate 1111 are respectively connected to the enable signal en_cal and a full-swing data signal; the input end of the fifth inverter 1112 is connected to the output end of the NOR gate 1111; the two input ends of the multiplexer 1113 are respectively connected to the output end of the NOR gate 1111 and the output end of the fifth inverter 1112, and the controlled end of the multiplexer 1113 is used to access the enable signal en_cal; the second delay unit 1114 is connected to the output end of the NOR gate 1111; the second latch 1115 is connected to the ring The oscillator module 120 is connected to the second delay unit 1114, and is used to receive the first recovered clock signal ckn, so as to sample the full-swing data signal after the delay processing of the second delay unit 1114 under the action of the first recovered clock signal ckn and output a sampling signal; the two input ends of the XOR gate 1116 are respectively connected to the output end of the multiplexer 1113 and the second latch 1115, so as to perform an XOR logic operation on the signal output by the multiplexer 1113 and the sampling signal and output a corresponding detection pulse signal.

[0089] In this embodiment, each pulse generator 111 is also controlled by an enable signal en_cal. When the enable signal en_cal is at a first level, an exclusive-NOR logic operation is performed on the signal output from the path of the rail-to-rail data signal via the multiplexer 1113 and the sampled signal output from the path of the second delay unit 1114 and the second latch 1115, respectively, by an exclusive-NOR gate 1116 to generate a detection pulse signal. This detection pulse signal represents edge detection information of the corresponding rail-to-rail data signal. When the enable signal en_cal is at a second level, the rail-to-rail data signal is inverted by a fifth inverter 1112 while passing through the path of the multiplexer 1113, causing the detection pulse signal to remain at a continuously low level, thereby causing the set signal set at the downstream end to remain at a continuously high level.

[0090] Combine Figure 7 As shown, Figure 7 FIG2 shows a second structural diagram of the pulse generator 111 in one embodiment of the present application. In some embodiments, the pulse generator 111 further includes a sixth inverter 1117. The input of the sixth inverter 1117 is connected to the second latch 1115. The sixth inverter 1117 is configured to invert the sampling signal output by the second latch 1115 to output a recovered data signal.

[0091] In this embodiment, the second latch 1115 receives the first recovered clock signal ckn, samples the full-swing data signal processed by the second delay unit 1114 under the action of the first recovered clock signal ckn, and outputs a sampling signal. The sixth inverter 1117 inverts the sampling signal to output a recovered data signal.

[0092] Combined with attachment Figure 8 , attached Figure 8 A schematic diagram of the structure of the first delay unit 122 in one embodiment of the present application is shown. The first delay unit 122 includes an inverter chain consisting of multiple inverters. In this embodiment, the length of the inverter chain is adjusted by adjusting the number of inverters connected from the input to the output of the first delay unit 122, thereby adjusting the delay duration of the first delay unit 122.

[0093] Combine Figure 9 、 Figure 10 As shown, Figure 9 The second structural diagram of the clock data recovery circuit in an embodiment of the present application is shown in FIG. Figure 10 A timing diagram of three full-swing data signals (di_ab, di_bc, and di_ca), three corresponding detection pulse signals (ez_ab, ez_bc, and ez_ca), a set signal set, a third recovered clock signal ckp, and a reset signal rest / first recovered clock signal ckn in one embodiment of the present application is shown.

[0094] The clock recovery circuit in the embodiment of the present application includes three pulse generators 111, a NAND gate 112, a first latch 121, a first delay unit 122, a first inverter 123, a second inverter 1241, a third inverter 1242, and a fourth inverter 1243. The three pulse generators 111 are connected to three rail-to-rail data signals (di_ab, di_bc, and di_ca), respectively. One of the output terminals of the three pulse generators 111 is connected to the three input terminals of the NAND gate 112. Two of the output terminals of the three pulse generators 111 are used to output the recovered data signals (do_ab, do_bc, and do_ca), respectively. The controlled terminals of the three pulse generators 111 are connected to the enable signal en_cal. The three pulse generators 111 are also connected to the output terminal of the second inverter 1241 to receive the first recovered clock signal ckn. The output of NAND gate 112 is connected to the set pin of first latch 121, the output of first inverter 123 is connected to the reset pin of first latch 121, the output pin of first latch 121 is connected to the input of first delay unit 122, the output of first delay unit 122 is connected to the input of first inverter 123 and second inverter 1241, the output of second inverter 1241 is connected to the input of third inverter 1242, the output of third inverter 1242 is connected to the input of fourth inverter 1243, and the output of fourth inverter 1243 outputs the second recovered clock signal cko. First delay unit 122 is also configured with a codeword configuration pin code1 for receiving a codeword configuration signal.

[0095] See attached Figure 10 The set signal set pulled high by the edge of each unit interval of the full-swing data signal will pull high the third recovered clock signal ckp through a loop delay2, and then pull high the reset signal rest through another loop delay2 (synchronous with the first recovered clock signal ckn), so that the first latch 121 enters the latched state. When the next full-swing data signal edge arrives and pulls high the set signal set, the cycle will repeat. The three full-swing data signals di_ab / di_bc / di_ca are sampled by the rising edge of the first recovered clock signal ckn. Figure 10 It can be seen that to achieve optimal sampling (aligning the clock sampling edge with the data midpoint), delay2 must be equal to one-quarter of the unit interval of each full-swing data signal. When the enable signal en_cal is high (enable signal en_cal is at the second level), the oscillation period of the ring oscillator module 120 is equal to 2*delay2. Therefore, by counting the oscillation periods of the ring oscillator module 120 under different delay control conditions, the optimal delay2 value corresponding to each unit interval of each full-swing data signal can be found to achieve optimal sampling and reduce the bit error rate.

[0096] Combine Figure 11 、 Figure 12 As shown, Figure 11 A flow chart of a clock data recovery method in an embodiment of the present application is shown in FIG. Figure 12 A timing diagram of the static calibration enable signal en_cal, the codeword sequence of the first delay unit PROG_DELAY, the time counter T_counter, and the second recovered clock signal cko in an embodiment of the present application is shown.

[0097] The clock data recovery method in the embodiment of the present application is applied to the clock data recovery circuit in any of the above embodiments. The clock data recovery method includes the following steps S1101 to S1103.

[0098] Step S1101, output an enable signal en_cal to the clock data recovery circuit, so as to configure the first delay unit of the clock data recovery circuit using different code words in ascending order, so that the clock data recovery circuit outputs the corresponding statically calibrated second recovered clock signal cko.

[0099] The statically calibrated second recovered clock signal cko may be understood as the second recovered clock signal cko output by the clock data recovery circuit in different codeword configuration periods in ascending order.

[0100] Configuring the first delay unit of the clock and data recovery circuit using different codewords in ascending order means configuring the first delay unit of the clock and data recovery circuit using different codewords in ascending order. For example, for a 4-bit codeword (ranging from 0000 to 1110), the traversal process would start at 0000 and sequentially use 0001, 0010, 0011, and so on, all the way to 1110. Each codeword corresponds to a specific delay length, and each time a new codeword is used, the delay setting of the first delay unit of the clock and data recovery circuit is changed.

[0101] Step S1102 : within a first preset time window t2 after a first duration t1 from the moment of switching the codeword, detecting the statically calibrated second recovered clock signal cko to obtain a first frequency of the statically calibrated second recovered clock signal cko.

[0102] Exemplarily, rising edges of the second recovered clock signal cko may be counted within a first preset time window t2 after a first duration t1 from the moment of codeword switching, thereby calculating and obtaining the first frequency of the statically calibrated second recovered clock signal cko.

[0103] Step S1103 : obtaining a first calibration codeword according to the first frequency and the input rate of the received initial data signal, so that the first delay unit operates under a configuration corresponding to the first calibration codeword.

[0104] Exemplarily, the codeword corresponding to the first frequency having the smallest difference from twice the rate of the data signal may be used as the first calibration codeword.

[0105] In the embodiment of the present application, the input rate of the initial data signal is a known value, so steps S1101 to S1103 can be understood as static calibration of clock data recovery.

[0106] In this embodiment, a first calibration codeword is obtained based on the first frequency and the input rate of the received initial data signal, so that the first delay unit operates under the configuration corresponding to the first calibration codeword, thereby realizing static calibration of the clock data. The data is recovered based on the clock data and operates under the configuration of the first calibration codeword. The initial data is sampled by the corresponding output second recovered clock signal cko, which can improve the sampling accuracy and reduce the bit error rate.

[0107] In one embodiment, the clock data recovery method in this embodiment also includes the following steps: configuring a first calibration codeword to the first delay unit, and controlling the clock data recovery circuit to work accordingly to output a dynamically calibrated second recovered clock signal cko; within a second preset time window t4 after the second time length t3 from when the clock data recovery circuit starts working under the configuration corresponding to the first calibration codeword, detecting the dynamically calibrated second recovered clock signal cko to obtain the second frequency of the dynamically calibrated second recovered clock signal cko; obtaining a second calibration codeword based on the first frequency and the second frequency, so that the first delay unit works under the configuration corresponding to the second calibration codeword.

[0108] Dynamic calibration can be understood as the process of recovering clock data when the input rate of the initial data signal is not constant and is unknown.

[0109] The dynamically calibrated second recovered clock signal cko may be understood as the second recovered clock signal cko output by the clock guard recovery circuit under the configuration of the first calibration codeword.

[0110] Exemplarily, within a second preset time window t4 after the second duration t3 from when the clock data recovery circuit starts working under the configuration corresponding to the first calibration codeword, the rising edges of the dynamically calibrated second recovered clock signal cko can be counted, and the second frequency of the activity can be further calculated.

[0111] Exemplarily, the codeword corresponding to the first frequency having the smallest difference with twice the second frequency may be used as the second calibration codeword.

[0112] See attached Figure 13 , attached Figure 13 A timing diagram illustrating the dynamic calibration enable signal en_cal, the data reception enable signal en_cdr, the second recovered clock signal cko, the codeword sequence of the first delay unit PROG_DELAY, and the time counter T_counter in one embodiment of the present application is shown. In this embodiment, the second frequency can represent the real-time input frequency of the initial data signal, thereby obtaining a second calibration codeword based on the first and second frequencies. This cycle can dynamically implement delay calibration in real time as the input rate of the initial data signal changes, allowing the clock data recovery circuit to output the second recovered clock signal cko to optimally sample the initial data signal.

[0113] In some embodiments, the present application also provides a MIPI C-PHY device, comprising the clock data recovery circuit in any of the above embodiments.

[0114] In this embodiment, the MIPI C-PHY device includes the clock and data recovery circuit of any of the above embodiments. In the clock and data recovery circuit of any of the above embodiments, the second recovered clock signal can accurately represent the delay of the initial data signal. The external sampler samples the initial data signal based on the second recovered clock signal, and can accurately sample the initial data signal, thereby reducing the bit error rate of data acquisition. Therefore, the MIPI C-PHY device also has more accurate data transmission capabilities.

[0115] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0116] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person skilled in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A clock data recovery circuit, characterized in that: include: a sampling module, configured to receive a plurality of full-swing data signals, sample the edges of the full-swing data signals, output a set signal, and output a restored data signal; a ring oscillator module, connected to the sampling module, and configured to output a first recovered clock signal and a second recovered clock signal respectively based on the set signal; The first recovered clock signal acts on the sampling module, so that the sampling module samples the edge of the full-swing data signal based on the first recovered clock signal; The second recovered clock signal corresponds to the delay duration of the ring oscillator module, so that the external processor adjusts the delay duration of the ring oscillator module according to the second recovered clock signal.

2. The clock data recovery circuit according to claim 1, wherein: The ring oscillator module includes: A first latch is configured with a set pin, a reset pin and an output pin, wherein the set pin is connected to the sampling module and is used to receive the set signal; a first delay unit, wherein an input end of the first delay unit is connected to the output pin and is configured to output a third recovered clock signal; a first inverter, wherein an input end of the first inverter is connected to an output end of the first delay unit, and an output end of the first inverter is connected to the reset pin, and is configured to invert the third recovered clock signal and output a reset signal to the reset pin; An inverter chain unit is connected to the first delay unit and the sampling module, and is used to output the first recovered clock signal and the second recovered clock signal respectively after inverting the third recovered clock signal for different times.

3. The clock data recovery circuit according to claim 2, wherein: The truth table of the first latch is: set=0, reset=0, out=1; set=0, reset=1, out=latch; set=1, reset=0, out=1; set=1, reset=1, out=0; Among them, set is the set signal; rest is the reset signal; out is the output signal; latch is to maintain the previous state.

4. The clock data recovery circuit according to claim 2, wherein: The inverter chain unit includes a plurality of inverters connected in series, so as to respectively output the first recovered clock signal and the second recovered clock signal after inverting the third recovered clock signal for different times.

5. The clock data recovery circuit according to claim 4, wherein: The inverter chain unit comprises: a second inverter, wherein an input end of the second inverter is connected to an output end of the first delay unit, and an output end of the second inverter is connected to the sampling module, and is configured to invert the third recovered clock signal once and then output the first recovered clock signal; a third inverter, wherein an input terminal of the third inverter is connected to an output terminal of the second inverter; a fourth inverter, wherein an input end of the fourth inverter is connected to an output end of the third inverter, and an output end of the fourth inverter is used to output the second recovered clock signal.

6. The clock data recovery circuit according to claim 1, wherein: The sampling module includes: a plurality of pulse generators, each of the plurality of pulse generators correspondingly connected to the plurality of rail-to-rail data signals, detecting edges of the rail-to-rail data signals and outputting a plurality of corresponding detection pulse signals; A NAND gate, wherein the multiple input ends of the NAND gate are respectively connected to the multiple pulse generators, and the output end of the NAND gate is connected to the ring oscillator module, and is used to output the set signal after performing a NAND logic operation on the multiple detection pulse signals.

7. The clock data recovery circuit according to claim 6, wherein: The pulse generator comprises: A NOR gate, wherein two input terminals of the NOR gate are respectively connected to an enable signal and a full-swing data signal; a fifth inverter, wherein an input terminal of the fifth inverter is connected to an output terminal of the NOR gate; a multiplexer, wherein two input terminals of the multiplexer are respectively connected to the output terminal of the NOR gate and the output terminal of the fifth inverter, and a controlled terminal of the multiplexer is used to receive the enable signal; A second delay unit is connected to the output end of the NOR gate; a second latch, connected to the ring oscillator module and the second delay unit, and configured to receive the first recovered clock signal, so as to sample the full-swing data signal after the delay processing by the second delay unit under the action of the first recovered clock signal and output a sampling signal; an XNOR gate, wherein two input terminals of the XNOR gate are connected to the output terminal of the multiplexer and the second latch, respectively, so as to perform an XNOR logic operation on the signal output by the multiplexer and the sampling signal and then output the corresponding detection pulse signal; A sixth inverter, wherein an input end of the sixth inverter is connected to the second latch, and the sixth inverter is used to invert the sampling signal output by the second latch to output a restored data signal.

8. A clock data recovery method, characterized in that: A clock data recovery circuit according to any one of claims 1 to 7, comprising: Outputting an enable signal to the clock data recovery circuit to sequentially configure the first delay unit of the clock data recovery circuit using different code words in ascending order, so that the clock data recovery circuit outputs the corresponding statically calibrated second recovered clock signal; detecting the statically calibrated second recovered clock signal within a first preset time window after a first duration from a moment when the codeword is switched, to obtain a first frequency of the statically calibrated second recovered clock signal; A first calibration codeword is acquired according to the first frequency and an input rate of receiving an initial data signal, so that the first delay unit operates under a configuration corresponding to the first calibration codeword.

9. The clock data recovery method according to claim 8, wherein: Also includes: configuring the first calibration codeword to the first delay unit, and controlling the clock data recovery circuit to operate accordingly to output the dynamically calibrated second recovered clock signal; detecting the dynamically calibrated second recovered clock signal within a second preset time window after a second duration of time from when the clock data recovery circuit starts operating under the configuration corresponding to the first calibration codeword to obtain a second frequency of the dynamically calibrated second recovered clock signal; A second calibration codeword is acquired according to the first frequency and the second frequency, so that the first delay unit operates under a configuration corresponding to the second calibration codeword.

10. A MIPI C-PHY device, characterized in that: The method comprises the clock data recovery circuit according to any one of claims 1 to 7.

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