Semiconductor memory device

Abstract

There is provided a semiconductor memory device including: a substrate; a plurality of lower electrodes on the substrate; a support pattern in contact with upper end sidewalls of the plurality of lower electrodes; a capacitor dielectric layer on the plurality of lower electrodes; an upper electrode on the capacitor dielectric layer; a cover insulating layer covering the upper electrode; and a plurality of first wiring contact plugs configured to penetrate the cover insulating layer and extend into the upper electrode, where the plurality of first wiring contact plugs are spaced apart from an edge of the support pattern into the support pattern by at least a first horizontal spacing distance in a plan view, and where the first horizontal spacing distance is greater than the side surface thickness, the side surface thickness is a thickness of a portion of the upper electrode covering a side surface of the support pattern.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priority from Korean Patent Application No. 10-2024-0035433 filed on March 13, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety for all purposes by reference. Technical Field

[0002] The inventive concept relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a wiring contact plug electrically connecting different vertical layers to each other. Background Art

[0003] With the rapid development of the electronics industry and user demands, electronic devices are becoming increasingly compact and lightweight. Consequently, semiconductor memory devices used in electronic devices require high levels of integration, and the design rules for semiconductor memory device configurations have also been reduced. Consequently, ensuring the reliability of semiconductor memory devices has become difficult. Summary of the Invention

[0004] The inventive concept provides a semiconductor memory device including a wiring contact plug to ensure reliability.

[0005] According to one aspect of the present invention, a semiconductor memory device is provided, comprising: a substrate including a memory cell region; a plurality of lower electrodes arranged in the memory cell region of the substrate; a support pattern contacting upper sidewalls of the plurality of lower electrodes to support the plurality of lower electrodes; a capacitor dielectric layer covering the plurality of lower electrodes and the support pattern; an upper electrode covering the plurality of lower electrodes and the support pattern, with the capacitor dielectric layer located therebetween; a covering insulating layer covering the upper electrode; a plurality of first wiring contact plugs configured to penetrate the covering insulating layer and extend into the upper electrode; and a plurality of wirings arranged on the upper electrode and the plurality of first wiring contact plugs, at least some of the plurality of wirings being connected to the plurality of first wiring contact plugs, wherein, in a plan view, the plurality of first wiring contact plugs are spaced apart from an edge of the support pattern into the support pattern by at least a first horizontal spacing distance, and wherein the first horizontal spacing distance is greater than a side surface thickness, which is a thickness in a horizontal direction of a portion of the upper electrode covering the side surface of the support pattern.

[0006] According to another aspect of the present invention, a semiconductor memory device is provided, comprising: a substrate; a plurality of lower electrodes arranged on the substrate; a support pattern contacting upper sidewalls of the plurality of lower electrodes to support the plurality of lower electrodes; a capacitor dielectric layer covering the plurality of lower electrodes and the support pattern; an upper electrode covering the plurality of lower electrodes and the support pattern, with the capacitor dielectric layer located therebetween; a cover insulating layer covering the upper electrode; a plurality of first wiring contact plugs arranged in a plan view to be spaced at least a first horizontal spacing distance from an edge of the support pattern into the support pattern, the plurality of first wiring contact plugs being configured to penetrate the cover insulating layer and extend into the upper electrode; a plurality of second wiring contact plugs arranged in a plan view to be spaced from an edge of the support pattern into the support pattern Separated by a second horizontal spacing distance that is smaller than the first horizontal spacing distance, a plurality of second wiring contact plugs are configured to penetrate the covering insulating layer and extend into the upper electrode; and a plurality of wirings are arranged on the upper electrode, the plurality of first wiring contact plugs and the plurality of second wiring contact plugs, at least some of the plurality of wirings are connected to the plurality of first wiring contact plugs and the plurality of second wiring contact plugs, wherein the first horizontal spacing distance is greater than the side surface thickness, which is the thickness of a portion of the upper electrode covering the side surface of the support pattern in the horizontal direction, and wherein the vertical height of each of the plurality of second wiring contact plugs is less than the vertical height of each of the plurality of first wiring contact plugs.

[0007] According to another aspect of the inventive concept, a semiconductor memory device is provided, comprising: a substrate defining a plurality of active regions; a plurality of word lines configured to respectively span the plurality of active regions and extend along a first horizontal direction; a plurality of bit lines arranged in the plurality of active regions and extending along a second horizontal direction orthogonal to the first horizontal direction; a plurality of buried contacts configured to fill a lower portion of a space between each of the plurality of bit lines, the plurality of buried contacts being connected to the plurality of active regions, respectively; a plurality of landing pads configured to fill an upper portion of a space between each of the plurality of bit lines, the plurality of landing pads extending to the plurality of bit lines, respectively; and a plurality of lower electrodes respectively contacting the plurality of landing pads; a support pattern contacting upper end sidewalls of the plurality of lower electrodes to support the plurality of lower electrodes; a capacitor dielectric layer covering the plurality of lower electrodes and the support pattern; an upper electrode covering the plurality of lower electrodes and the support pattern, with the capacitor dielectric layer located therebetween; a covering insulating layer covering the upper electrode; a plurality of first wiring contact plugs arranged in a plan view to extend from the support pattern to the lower electrode; The edge of the pattern is spaced at least a first horizontal spacing distance into the supporting pattern, and a plurality of first wiring contact plugs are configured to penetrate the covering insulating layer and extend into the upper electrode; a plurality of second wiring contact plugs are arranged in the supporting pattern in a plan view, and are spaced from the edge of the supporting pattern by a second horizontal spacing distance less than the first horizontal spacing distance, and the plurality of second wiring contact plugs are configured to penetrate the covering insulating layer and extend into the upper electrode; and a plurality of wirings are arranged on the upper electrode, the plurality of first wiring contact plugs and the plurality of second wiring contact plugs, at least some of the plurality of wirings are connected to the plurality of first wiring contact plugs and the plurality of second wiring contact plugs, wherein the first horizontal spacing distance is greater than the side surface thickness, which is the thickness in the horizontal direction of the portion of the upper electrode covering the side surface of the supporting pattern, and the second horizontal spacing distance is less than the side surface thickness, and wherein the horizontal area of ​​each of the plurality of second wiring contact plugs is smaller than the horizontal area of ​​each of the plurality of first wiring contact plugs. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1A is a block diagram of a semiconductor memory device according to an embodiment, and Figure 1B is a schematic planar layout of a semiconductor memory device according to an embodiment;

[0010] Figures 2A to 2H is a planar layout of a semiconductor memory device according to an embodiment;

[0011] Figures 3A to 3D 、 Figures 4A to 4D 、 5A to 5D 、 6A to 6D 、 7A to 7D 、 Figures 8A to 8D 、 9A to 9D and 10A to 10D is a cross-sectional view for describing a method for manufacturing a semiconductor memory device according to an embodiment, and Figures 11A to 11E is a cross-sectional view of a semiconductor memory device according to an embodiment; and

[0012] Figure 12 and 13 are corresponding cross-sectional views of a semiconductor memory device according to an embodiment. DETAILED DESCRIPTION

[0013] Figure 1A is a diagram of a semiconductor memory device 1 according to an embodiment, and Figure 1B is a schematic planar layout of the semiconductor memory device 1 according to the embodiment.

[0014] Reference Figure 1A , the semiconductor memory device 1 may include a cell region CLR in which memory cells are arranged, and a main peripheral region PRR surrounding the cell region CLR.

[0015] According to an embodiment, a sub-peripheral region SPR that divides a cell block SCB may be included in the cell region CLR. A plurality of memory cells may be arranged in the cell block SCB. In the present invention, the cell block SCB may be referred to as a region where memory cells are evenly spaced and regularly arranged, and may be referred to as a sub-cell block.

[0016] Logic units for receiving / sending electrical signals from / to memory cells may be arranged in the main peripheral region PRR and the sub-peripheral region SPR. In some embodiments, the main peripheral region PRR may be referred to as a peripheral circuit region, and the sub-peripheral region SPR may be referred to as a core circuit region. The peripheral region PR may include the main peripheral region PRR and the sub-peripheral region SPR. In other words, the peripheral region PR may be a core and peripheral circuit region including a peripheral circuit region and a core circuit region. In some embodiments, at least a portion of the sub-peripheral region SPR may be provided only as a space for distinguishing cell blocks SCB.

[0017] Reference Figure 1B , the semiconductor memory device 1 may include a memory cell region CR and a peripheral region PR. The semiconductor memory device 1 may include a plurality of active regions ACT formed in the memory cell region CR and a plurality of logic active regions ACTP formed in the peripheral region PR. The memory cell region CR may include a plurality of active regions ACT formed in the memory cell region CR and a plurality of logic active regions ACTP formed in the peripheral region PR. Figure 1A The cell block SCB of the plurality of memory cells shown in FIG, and the peripheral region PR may include a peripheral region PR, the peripheral region PR including Figure 1AThe main peripheral region PRR and the sub peripheral region SPR shown in .

[0018] In some embodiments, the plurality of active regions ACT arranged in the memory cell region CR may be arranged to have long axes inclined with respect to the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0019] Multiple word lines WL may extend parallel to one another along a first horizontal direction (X direction) across multiple active areas ACT. A plurality of bit lines BL may extend parallel to one another along a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction) on the multiple word lines WL. The multiple bit lines BL may be connected to the multiple active areas ACT via direct contacts DC.

[0020] In some embodiments, a plurality of buried contacts BC may be formed between two adjacent bit lines BL among the plurality of bit lines BL. In some embodiments, the plurality of buried contacts BC may be arranged in a line in each of a first horizontal direction (X direction) and a second horizontal direction (Y direction).

[0021] A plurality of landing pads LP may be formed on each of the plurality of buried contacts BC. The plurality of landing pads LP may be arranged to at least partially overlap the plurality of buried contacts BC. In some embodiments, the plurality of landing pads LP may extend to an upper portion of any one of two adjacent bit lines BL.

[0022] A plurality of storage nodes SN may be formed on each of the landing pads LP. A plurality of storage nodes SN may be formed on each of the bit lines BL. Each of the plurality of storage nodes SN may include a lower electrode of each of the plurality of capacitors. The storage nodes SN may be connected to the active area ACT via the landing pads LP and the buried contacts BC.

[0023] A plurality of gate line patterns GLP may be arranged on the logic active region ACTP in the peripheral region PR. Figure 1B The plurality of gate line patterns GLP are shown extending parallel to one another along a first horizontal direction (X direction) on the logic active region ACTP and generally having a uniform width along a second horizontal direction (Y direction), but the embodiment is not limited thereto. For example, each of the plurality of gate line patterns GLP may have a different width, have a curvature, or extend in a different direction.

[0024] exist Figure 1B , for ease of explanation, components other than the plurality of logic active regions ACTP and the plurality of gate line patterns GLP in the peripheral region PR are omitted. Figure 1BIt is shown that the plurality of gate line patterns GLP are arranged only on the plurality of logic active regions ACTP, but the embodiment is not limited thereto. For example, at least some of the plurality of gate line patterns GLP may extend outside the logic active region ACTP.

[0025] The plurality of gate line patterns GLP may be formed at the same level as the plurality of bit lines BL. In some embodiments, the plurality of gate line patterns GLP and the plurality of bit lines BL may include the same material, or at least some of the plurality of gate line patterns GLP and the plurality of bit lines BL may include the same material. For example, the process of forming all or part of the plurality of gate line patterns GLP and the process of forming all or part of the plurality of bit lines BL may include the same process.

[0026] Figures 2A to 2H 1000a to 1000h are planar layouts of semiconductor memory devices 1000a to 1000h according to an embodiment. Figures 2A to 2H is with Figure 1A The corresponding floor plan layout in Part II.

[0027] Reference Figure 2A , the semiconductor memory device 1000 a may include a plurality of lower electrodes 210 , an upper support pattern 330 , an upper electrode 230 , a plurality of first wiring contact plugs 410 , and a plurality of wirings 500 .

[0028] The multiple lower electrodes 210 may be arranged in a zigzag pattern in a honeycomb configuration relative to a first horizontal direction (X direction) or a second horizontal direction (Y direction) orthogonal to the first horizontal direction (X direction), but the present embodiment is not limited thereto. In some embodiments, the multiple lower electrodes 210 may be arranged in a linear matrix in each of the first horizontal direction (X direction) and the second horizontal direction (Y direction). The multiple lower electrodes 210 may include impurity-doped polycrystalline silicon, a metal (such as tungsten and copper), or a conductive metal compound (such as titanium nitride). Each of the multiple lower electrodes 210 may have an internally filled columnar shape, i.e., a columnar shape with a circular horizontal cross-section, but is not limited thereto. In some embodiments, each of the multiple lower electrodes 210 may have a cylindrical shape with its lower portion closed.

[0029] The upper support pattern 330 may contact the sidewalls of the plurality of lower electrodes 210 to support the plurality of lower electrodes 210. In a plan view, the plurality of lower electrodes 210 may be spaced apart from the edge of the upper support pattern 330 and may be arranged within the upper support pattern 330. The upper support pattern 330 may contact the upper sidewalls of the plurality of lower electrodes 210. In some embodiments, the upper support pattern 330 may contact the uppermost sidewall of the plurality of lower electrodes 210. For example, the upper surface of the portion of the upper support pattern 330 that contacts the sidewall of any of the plurality of lower electrodes 210 may be at the same vertical level as the upper surface of any of the lower electrodes 210. The upper support pattern 330 may include, but is not limited to, any of silicon nitride (SiN), silicon carbonitride (SiCN), nitrogen-rich SiN, or silicon-rich SiN.

[0030] The upper electrode 230 may cover the plurality of lower electrodes 210 and the upper support pattern 330. The capacitor dielectric layer ( Figures 11A to 11E The upper electrode 230 may be disposed between the plurality of lower electrodes 210 and the upper support pattern 330. The upper electrode 230 may have a stacked structure comprising one or at least two of a doped semiconductor material layer, a main electrode layer, and an interface layer. The doped semiconductor material may include, for example, at least one of doped polysilicon and doped polycrystalline silicon germanium (SiGe). The main electrode layer may include a metal material. The main electrode layer may include, for example, W, Ru, RuO, Pt, PtO, Ir, IrO, SrRuO (SRO), (Ba, Sr)RuO (BSRO), CaRuO (CRO), BaRuO, La(Sr, Co)O, and the like. In some embodiments, the main electrode layer may include W. The interface layer may include at least one of a metal oxide, a metal nitride, a metal carbide, and a metal silicide.

[0031] In a plan view, the upper support pattern 330 may be spaced apart from the edge of the upper electrode 230 and may be arranged within the upper electrode 230. In other words, in a plan view, the edge of the upper support pattern 330 is spaced apart from the edge of the upper electrode 230 and may be arranged within the upper electrode 230. For example, the horizontal width and area of ​​the upper electrode 230 may be greater than the horizontal width and area of ​​the upper support pattern 330, respectively, and all portions of the upper support pattern 330 may overlap within the upper electrode 230 in the vertical direction (Z direction). In a plan view, the edge of the upper electrode 230 and the edge of the upper support pattern 330 may be spaced apart from each other by a side surface thickness TL. The side surface thickness TL may be the horizontal thickness of the portion of the upper electrode 230 that covers the side surface of the upper support pattern 330. The side surface thickness TL may be less than approximately 300 nm. For example, the side surface thickness TL may be approximately 230 nm to approximately 270 nm.

[0032] As used herein, the term "about" is relative to the actual value, as understood by those skilled in the art, and allows for approximations, inaccuracies, and measurement limits in relevant circumstances. In one or more aspects, the terms "about," "substantially," and "approximately" can provide an industry-accepted tolerance for the corresponding term and / or relativity between items, such as a tolerance of less than one percent to ten percent of the actual value, as well as other suitable tolerances.

[0033] A plurality of wirings 500 may be arranged on the upper electrode 230. The plurality of wirings 500 may be spaced apart from the upper electrode 230 in the vertical direction (Z direction). In some embodiments, the plurality of wirings 500 may extend along a first horizontal direction (X direction) and may be spaced apart from each other in a second horizontal direction (Y direction). At least one of the plurality of wirings 500 may be electrically connected to the upper electrode 230 to supply power to the upper electrode 230. In some embodiments, some of the plurality of wirings 500 and other wirings 500 may have different horizontal widths in the second horizontal direction (Y direction). In some embodiments, at least some of the plurality of wirings 500 having a relatively larger horizontal width in the second horizontal direction (Y direction) may be electrically connected to the upper electrode 230 to supply power to the upper electrode 230, but this is not limited thereto. For example, at least one wiring 500 having a relatively larger horizontal width and at least one other wiring 500 having a relatively smaller horizontal width may both be electrically connected to the upper electrode 230 to supply power to the upper electrode 230.

[0034] Each of the plurality of first wiring contact plugs 410 can be arranged between a wiring 500 having a relatively large horizontal width among the plurality of wirings 500 and the upper electrode 230, and can electrically connect the wiring 500 having a relatively large horizontal width among the plurality of wirings 500 to the upper electrode 230. In some embodiments, each of the plurality of first wiring contact plugs 410 can have a rectangular planar shape, or a planar shape similar to a rectangle, for example, a rectangular planar shape with rounded corners. In some embodiments, the long axis of the planar shape of each of the plurality of first wiring contact plugs 410 can include a direction orthogonal to the extending direction of the wiring 500 connected to each of the plurality of first wiring contact plugs 410. For example, the long axis of the planar shape of each of the plurality of first wiring contact plugs 410 can include a second horizontal direction (Y direction) orthogonal to the first horizontal direction (X direction) (i.e., the extending direction of the wiring 500 connected to each of the plurality of first wiring contact plugs 410). For example, each of the plurality of first wiring contact plugs 410 may have a horizontal width in the long axis direction of about 50 nm to about 60 nm, and a horizontal width in the short axis direction of about 30 nm to about 40 nm.

[0035] In a plan view, the plurality of first wiring contact plugs 410 may be spaced at least a first horizontal spacing distance DL1 from the edge of the upper support pattern 330 toward the interior of the upper support pattern 330. In other words, in a plan view, the first wiring contact plug 410 closest to the edge of the upper support pattern 330 among the plurality of first wiring contact plugs 410 may be spaced a first horizontal spacing distance DL1 from the edge of the upper support pattern 330. The first horizontal spacing distance DL1 may be greater than the side surface thickness TL. In a plan view, each of the plurality of first wiring contact plugs 410 may be spaced a spacing distance greater than the side surface thickness TL from the edge of the upper support pattern 330. For example, the first horizontal spacing distance DL1 may be approximately 300 nm. In a plan view, the region from the edge of the upper support pattern 330 to the first horizontal spacing distance DL1 may be referred to as an edge support region SER, and the region from the edge of the upper support pattern 330 to a distance greater than the first horizontal spacing distance DL1 may be referred to as an inner support region SIR. The plurality of first wiring contact plugs 410 may be arranged in the inner support region SIR but may not be arranged in the edge support region SER.

[0036] Reference Figure 2B , the semiconductor memory device 1000 b may include a plurality of lower electrodes 210 , an upper support pattern 330 , an upper electrode 230 , a plurality of first wiring contact plugs 410 , a plurality of second wiring contact plugs 420 , and a plurality of wirings 500 .

[0037] The upper support pattern 330 may contact the sidewalls of the plurality of lower electrodes 210 to support the plurality of lower electrodes 210. The upper electrode 230 may cover the plurality of lower electrodes 210 and the upper support pattern 330. In a plan view, the upper support pattern 330 may be spaced apart from the edge of the upper electrode 230 and may be arranged inside the upper electrode 230. In a plan view, the edge of the upper electrode 230 and the edge of the upper support pattern 330 may be spaced apart from each other by a side surface thickness TL. A plurality of wirings 500 may be arranged on the upper electrode 230. The plurality of wirings 500 may be spaced apart from the upper electrode 230 in the vertical direction (Z direction).

[0038] Each of the plurality of first wiring contact plugs 410 and the plurality of second wiring contact plugs 420 may be arranged between a wiring 500 having a relatively larger horizontal width among the plurality of wirings 500 and the upper electrode 230 , and may electrically connect the wiring 500 having a relatively larger horizontal width among the plurality of wirings 500 to the upper electrode 230 .

[0039] In some embodiments, each of the plurality of first wiring contact plugs 410 and the plurality of second wiring contact plugs 420 may have a rectangular planar shape, or a planar shape similar to a rectangle, for example, a rectangular planar shape with rounded corners. In some embodiments, the long axis of the planar shape of each of the plurality of first wiring contact plugs 410 and the plurality of second wiring contact plugs 420 may include a direction orthogonal to the extending direction of the wiring 500 connected to each of the plurality of first wiring contact plugs 410 and the plurality of second wiring contact plugs 420. For example, the long axis of the planar shape of each of the plurality of first wiring contact plugs 410 and the plurality of second wiring contact plugs 420 may include a second horizontal direction (Y direction) orthogonal to the first horizontal direction (X direction) (i.e., the extending direction of the wiring 500 connected to each of the plurality of first wiring contact plugs 410 and the plurality of second wiring contact plugs 420).

[0040] At the same vertical level, the horizontal area of ​​each of the plurality of second wiring contact plugs 420 may be approximately 60% to approximately 80% of the horizontal area of ​​each of the plurality of first wiring contact plugs 410. The horizontal width in the major axis direction of each of the plurality of second wiring contact plugs 420 may be smaller than the horizontal width in the major axis direction of each of the plurality of first wiring contact plugs 410. The horizontal width in the minor axis direction of each of the plurality of second wiring contact plugs 420 may be smaller than the horizontal width in the minor axis direction of each of the plurality of first wiring contact plugs 410. The horizontal width of each second wiring contact plug in the plurality of second wiring contact plugs 420 in the long-axis direction may be approximately 80% to 90% of the horizontal width of each first wiring contact plug in the plurality of first wiring contact plugs 410 in the long-axis direction, and the horizontal width of each second wiring contact plug in the plurality of second wiring contact plugs 420 in the short-axis direction may be approximately 80% to 90% of the horizontal width of each first wiring contact plug in the short-axis direction in the plurality of first wiring contact plugs 410. For example, the horizontal width of each first wiring contact plug in the plurality of first wiring contact plugs 410 in the long-axis direction may be approximately 50 nm to approximately 60 nm, and the horizontal width in the short-axis direction may be approximately 30 nm to approximately 40 nm. For example, the horizontal width of each second wiring contact plug in the plurality of second wiring contact plugs 420 in the long-axis direction may be approximately 40 nm to approximately 55 nm, and the horizontal width in the short-axis direction may be approximately 25 nm to approximately 35 nm.

[0041] In a plan view, the plurality of first wiring contact plugs 410 are spaced apart from the edge of the upper support pattern 330 toward the interior of the upper support pattern 330 by at least a first horizontal spacing distance DL1. In a plan view, each of the plurality of second wiring contact plugs 420 is spaced apart from the edge of the upper support pattern 330 toward the interior of the upper support pattern 330 by a second horizontal spacing distance DL2. The second horizontal spacing distance DL2 may be less than the first horizontal spacing distance DL1. The first horizontal spacing distance DL1 may be greater than the side surface thickness TL. In some embodiments, the second horizontal spacing distance DL2 may be less than the side surface thickness TL. For example, the first horizontal spacing distance DL1 may be approximately 300 nm, and the second horizontal spacing distance DL2 may be approximately 180 nm to approximately 240 nm.

[0042] In some embodiments, the plurality of second wiring contact plugs 420 may be arranged on one side in the first horizontal direction (X direction) (i.e., the direction in which the wirings 500 extend from the plurality of first wiring contact plugs 410 ), and may be arranged closer to the edge of the upper support pattern 330 than the plurality of first wiring contact plugs 410 .

[0043] The plurality of first wiring contact plugs 410 may be arranged in the inner supporting region SIR but may not be arranged in the edge supporting region SER, and the plurality of second wiring contact plugs 420 may be arranged in the edge supporting region SER but may not be arranged in the inner supporting region SIR.

[0044] Search Figure 2C , the semiconductor memory device 1000 c may include a plurality of lower electrodes 210 , an upper support pattern 330 , an upper electrode 230 , a plurality of first wiring contact plugs 410 , a plurality of third wiring contact plugs 430 , and a plurality of wirings 500 .

[0045] The upper support pattern 330 may contact the sidewalls of the plurality of lower electrodes 210 to support the plurality of lower electrodes 210. The upper electrode 230 may cover the plurality of lower electrodes 210 and the upper support pattern 330. In a plan view, the upper support pattern 330 may be spaced apart from the edge of the upper electrode 230 and may be arranged inside the upper electrode 230. In a plan view, the edge of the upper electrode 230 and the edge of the upper support pattern 330 may be spaced apart from each other by a side surface thickness TL. A plurality of wirings 500 may be arranged on the upper electrode 230. The plurality of wirings 500 may be spaced apart from the upper electrode 230 in the vertical direction (Z direction).

[0046] The plurality of first wiring contact plugs 410, the plurality of second wiring contact plugs 420, and the plurality of third wiring contact plugs 430 may be arranged between at least some of the plurality of wirings 500 and the upper electrode 230, and may electrically connect at least some of the plurality of wirings 500 to the upper electrode 230. In some embodiments, each of the plurality of first wiring contact plugs 410, the plurality of second wiring contact plugs 420, and the plurality of third wiring contact plugs 430 may have a rectangular planar shape, or a planar shape similar to a rectangle, for example, a planar shape with rounded corners. In some embodiments, in a plan view, the long axis direction of the planar shape of each of the plurality of first wiring contact plugs 410, the plurality of second wiring contact plugs 420, and the plurality of third wiring contact plugs 430 may include a direction orthogonal to the extending direction of the wiring 500 connected to each of the plurality of first wiring contact plugs 410, the plurality of second wiring contact plugs 420, and the plurality of third wiring contact plugs 430. For example, in a plan view, the long axis direction of each of the plurality of first wiring contact plugs 410, the plurality of second wiring contact plugs 420, and the plurality of third wiring contact plugs 430 may include a second horizontal direction (Y direction) that is orthogonal to the first horizontal direction (X direction) (i.e., the extension direction of the wiring 500 connected to each of the plurality of first wiring contact plugs 410, the plurality of second wiring contact plugs 420, and the plurality of third wiring contact plugs 430).

[0047] At the same vertical level, the horizontal area of ​​each of the plurality of third wiring contact plugs 430 may be approximately 60% to approximately 80% of the horizontal area of ​​each of the plurality of second wiring contact plugs 420, and the horizontal area of ​​each of the plurality of second wiring contact plugs 420 may be approximately 60% to approximately 80% of the horizontal area of ​​each of the plurality of first wiring contact plugs 410. The horizontal width of each of the plurality of third wiring contact plugs 430 in the longitudinal direction may be smaller than the horizontal width of each of the plurality of first wiring contact plugs 410 in the longitudinal direction, and the horizontal width of each of the plurality of second wiring contact plugs 420 in the longitudinal direction may be smaller than the horizontal width of each of the plurality of first wiring contact plugs 410 in the longitudinal direction. The horizontal width in the short-axis direction of each of the plurality of third wiring contact plugs 430 may be smaller than the horizontal width in the short-axis direction of each of the plurality of first wiring contact plugs 410, and the horizontal width in the short-axis direction of each of the plurality of second wiring contact plugs 420 may be smaller than the horizontal width in the short-axis direction of each of the plurality of first wiring contact plugs 410. The horizontal width in the long-axis direction of each of the plurality of third wiring contact plugs 430 may be approximately 80% to approximately 90% of the horizontal width in the long-axis direction of each of the plurality of second wiring contact plugs 420, and the horizontal width in the short-axis direction of each of the plurality of third wiring contact plugs 430 may be approximately 80% to approximately 90% of the horizontal width in the short-axis direction of each of the plurality of second wiring contact plugs 420. The horizontal width in the long axis direction of each of the multiple second wiring contact plugs 420 can be approximately 80% to approximately 90% of the horizontal width in the long axis direction of each of the multiple first wiring contact plugs 410, and the horizontal width in the short axis direction of each of the multiple second wiring contact plugs 420 can be approximately 80% to approximately 90% of the horizontal width in the short axis direction of each of the multiple first wiring contact plugs 410.

[0048] In plan view, the plurality of first wiring contact plugs 410 are spaced at least a first horizontal spacing distance DL1 from the edge of the upper support pattern 330 toward the interior of the upper support pattern 330. In plan view, each of the plurality of second wiring contact plugs 420 is spaced a second horizontal spacing distance DL2 from the edge of the upper support pattern 330 toward the interior of the upper support pattern 330. In plan view, each of the plurality of third wiring contact plugs 430 is spaced a third horizontal spacing distance DL3 from the edge of the upper support pattern 330 toward the interior of the upper support pattern 330. The third horizontal spacing distance DL3 may be less than the second horizontal spacing distance DL2, and the second horizontal spacing distance DL2 may be less than the first horizontal spacing distance DL1. The first horizontal spacing distance DL1 may be greater than the side surface thickness TL. In some embodiments, both the second horizontal spacing distance DL2 and the third horizontal spacing distance DL3 may be less than the side surface thickness TL. For example, the first horizontal spacing distance DL1 may be approximately 300 nm, the second horizontal spacing distance DL2 may be approximately 180 nm to approximately 240 nm, and the third horizontal spacing distance DL3 may be approximately 60 nm to approximately 200 nm.

[0049] In some embodiments, the plurality of second wiring contact plugs 420 may be arranged on one side in the first horizontal direction (X direction) (i.e., the direction in which the wirings 500 extend from the plurality of first wiring contact plugs 410) and may be arranged closer to the edge of the upper support pattern 330 than the plurality of first wiring contact plugs 410. The plurality of third wiring contact plugs 430 may be arranged on one side in the first horizontal direction (X direction) (i.e., the direction in which the wirings 500 extend from the plurality of first wiring contact plugs 410 and the plurality of second wiring contact plugs 420) and may be arranged closer to the edge of the upper support pattern 330 than the plurality of first wiring contact plugs 410 and the plurality of second wiring contact plugs 420.

[0050] A plurality of first wiring contact plugs 410 may be arranged in the inner supporting region SIR but may not be arranged in the edge supporting region SER, and a plurality of second wiring contact plugs 420 and a plurality of third wiring contact plugs 430 may be arranged in the edge supporting region SER but may not be arranged in the inner supporting region SIR.

[0051] Reference Figure 2D The semiconductor memory device 1000 d may include a plurality of lower electrodes 210 , an upper support pattern 330 , an upper electrode 230 , a plurality of first wiring contact plugs 410 , a plurality of second wiring contact plugs 420 , and a plurality of wirings 500 .

[0052] The upper support pattern 330 may contact the sidewalls of the plurality of lower electrodes 210 to support the plurality of lower electrodes 210. The upper electrode 230 may cover the plurality of lower electrodes 210 and the upper support pattern 330. In a plan view, the upper support pattern 330 may be spaced apart from the edge of the upper electrode 230 and may be arranged inside the upper electrode 230. The plurality of wirings 500 may be spaced apart from the upper electrode 230 in the vertical direction (Z direction).

[0053] The plurality of first wiring contact plugs 410 and the plurality of second wiring contact plugs 420 may be arranged between at least some of the plurality of wirings 500 and the upper electrode 230, and may electrically connect at least some of the plurality of wirings 500 to the upper electrode 230. In some embodiments, the long axis direction of the planar shape of the plurality of first wiring contact plugs 410 may include a direction orthogonal to an extension direction of the wiring 500 connected to each of the plurality of first wiring contact plugs 410, and the long axis direction of the planar shape of the plurality of second wiring contact plugs 420 may include an extension direction of the wiring 500 connected to each of the plurality of second wiring contact plugs 420. For example, the long-axis direction of the planar shape of each of the plurality of first wiring contact plugs 410 may include a second horizontal direction (Y direction) orthogonal to the first horizontal direction (X direction) (i.e., the extension direction of the wiring 500 connected to each of the plurality of first wiring contact plugs 410), and the long-axis direction of the planar shape of each of the plurality of second wiring contact plugs 420 may include the first horizontal direction (X direction), i.e., the extension direction of the wiring 500 connected to each of the plurality of second wiring contact plugs 420.

[0054] Reference Figure 2E , the semiconductor memory device 1000 e may include a plurality of lower electrodes 210 , an upper support pattern 330 , an upper electrode 230 , a plurality of first wiring contact plugs 410 , a plurality of second wiring contact plugs 420 , and a plurality of wirings 500 .

[0055] The upper support pattern 330 may contact the sidewalls of the plurality of lower electrodes 210 to support the plurality of lower electrodes 210. The upper electrode 230 may cover the plurality of lower electrodes 210 and the upper support pattern 330. In a plan view, the upper support pattern 330 may be spaced apart from the edge of the upper electrode 230 and may be arranged inside the upper electrode 230. The plurality of wirings 500 may be spaced apart from the upper electrode 230 in the vertical direction (Z direction).

[0056] The plurality of first wiring contact plugs 410 and the plurality of second wiring contact plugs 420 may be arranged between at least some of the plurality of wirings 500 and the upper electrode 230, and may electrically connect at least some of the plurality of wirings 500 to the upper electrode 230. In some embodiments, the long axis direction of the planar shape of each of the plurality of first wiring contact plugs 410 and the plurality of second wiring contact plugs 420 may include a direction orthogonal to the extending direction of the wiring 500 connected to each of the plurality of first wiring contact plugs 410 and the plurality of second wiring contact plugs 420. For example, the long axis direction of the planar shape of each of the plurality of first wiring contact plugs 410 and the plurality of second wiring contact plugs 420 may include a second horizontal direction (Y direction) orthogonal to the first horizontal direction (X direction) (i.e., the extending direction of the wiring 500 connected to each of the plurality of first wiring contact plugs 410 and the plurality of second wiring contact plugs 420).

[0057] In some embodiments, each of the plurality of second wiring contact plugs 420 may be arranged on one side in the first horizontal direction (X direction) (i.e., the direction in which the wiring 500 extends from the plurality of first wiring contact plugs 410), or may be arranged on one side in the second horizontal direction (Y direction) orthogonal to the extension direction of the wiring 500, and may be arranged closer to the edge of the upper support pattern 330 than the plurality of first wiring contact plugs 410.

[0058] Reference Figure 2F The semiconductor memory device 1000 f may include a plurality of lower electrodes 210 , an upper support pattern 330 , an upper electrode 230 , a plurality of first wiring contact plugs 410 , a plurality of second wiring contact plugs 420 , and a plurality of wirings 500 .

[0059] The upper support pattern 330 may contact the sidewalls of the plurality of lower electrodes 210 to support the plurality of lower electrodes 210. The upper electrode 230 may cover the plurality of lower electrodes 210 and the upper support pattern 330. In a plan view, the upper support pattern 330 may be spaced apart from the edge of the upper electrode 230 and may be arranged inside the upper electrode 230. The plurality of wirings 500 may be spaced apart from the upper electrode 230 in the vertical direction (Z direction).

[0060] The plurality of first wiring contact plugs 410 and the plurality of second wiring contact plugs 420 may be arranged between at least some of the plurality of wirings 500 and the upper electrode 230, and may electrically connect at least some of the plurality of wirings 500 to the upper electrode 230. In some embodiments, the long axis direction of the planar shape of each of the plurality of first wiring contact plugs 410 may include a direction orthogonal to an extension direction of the wiring 500 connected to each of the plurality of first wiring contact plugs 410, and the long axis direction of the planar shape of each of the plurality of second wiring contact plugs 420 may include an extension direction of the wiring 500 connected to each of the plurality of second wiring contact plugs 420. For example, the long-axis direction of the planar shape of each of the plurality of first wiring contact plugs 410 may include a second horizontal direction (Y direction) orthogonal to the first horizontal direction (X direction) (i.e., the extension direction of the wiring 500 connected to each of the plurality of first wiring contact plugs 410), and the long-axis direction of the planar shape of each of the plurality of second wiring contact plugs 420 may include the first horizontal direction (X direction), i.e., the extension direction of the wiring 500 connected to each of the plurality of second wiring contact plugs 420.

[0061] In some embodiments, each of the plurality of second wiring contact plugs 420 may be arranged on one side in the first horizontal direction (X direction) (i.e., the direction in which the wiring 500 extends from the plurality of first wiring contact plugs 410), or may be arranged on one side in the second horizontal direction (Y direction) orthogonal to the extension direction of the wiring 500, and therefore, may be arranged closer to the edge of the upper support pattern 330 than the plurality of first wiring contact plugs 410.

[0062] In some embodiments, the second wiring contact plug 420 arranged on one side of the plurality of second wiring contact plugs 420 along the first horizontal direction (X direction) (i.e., the extension direction of the wiring 500) can be arranged between the wiring 500 having a relatively larger horizontal width among the plurality of wirings 500 and the upper electrode 230, and the second wiring contact plug 420 arranged on one side of the plurality of first wiring contact plugs 410 along the second horizontal direction (Y direction) orthogonal to the extension direction of the wiring 500 can be arranged between the wiring 500 having a relatively smaller horizontal width among the plurality of wirings 500 and the upper electrode 230.

[0063] Reference Figure 2GThe semiconductor memory device 1000 g may include a plurality of lower electrodes 210 , an upper support pattern 330 , an upper electrode 230 , a plurality of first wiring contact plugs 410 , a plurality of second wiring contact plugs 420 , and a plurality of wirings 500 .

[0064] The upper support pattern 330 may contact the sidewalls of the plurality of lower electrodes 210 to support the plurality of lower electrodes 210. The upper electrode 230 may cover the plurality of lower electrodes 210 and the upper support pattern 330. In a plan view, the upper support pattern 330 may be spaced apart from the edge of the upper electrode 230 and may be arranged inside the upper electrode 230. The plurality of wirings 500 may be spaced apart from the upper electrode 230 in the vertical direction (Z direction).

[0065] A plurality of first wiring contact plugs 410 and a plurality of second wiring contact plugs 420 may be disposed between at least some of the plurality of wirings 500 and the upper electrode 230 and may electrically connect at least some of the plurality of wirings 500 to the upper electrode 230 .

[0066] In some embodiments, each of the plurality of second wiring contact plugs 420 may be arranged on one side in the first horizontal direction (X direction) (i.e., the direction in which the wiring 500 extends from the plurality of first wiring contact plugs 410), or may be arranged on one side in the second horizontal direction (Y direction) orthogonal to the extension direction of the wiring 500, and therefore, may be arranged closer to the edge of the upper support pattern 330 than the plurality of first wiring contact plugs 410.

[0067] In some embodiments, the long-axis direction of the planar shape of each of the plurality of first wiring contact plugs 410 may include a direction orthogonal to the extending direction of the wiring 500 connected to each of the plurality of first wiring contact plugs 410. The long-axis direction of the planar shape of the second wiring contact plug 420 arranged on one side of the plurality of first wiring contact plugs 410 along the first horizontal direction (X direction) (i.e., the direction in which the wiring 500 extends from the plurality of first wiring contact plugs 410) may include the first horizontal direction (X direction), i.e., the extending direction of the wiring 500 connected to the second wiring contact plug 420, and the long-axis direction of the planar shape of the second wiring contact plug 420 arranged on one side of the plurality of first wiring contact plugs 410 along the second horizontal direction (Y direction) orthogonal to the direction in which the wiring 500 extends from the plurality of first wiring contact plugs 410 may include the second horizontal direction (Y direction) orthogonal to the extending direction of the wiring 500 connected to the second wiring contact plug 420.

[0068] Reference Figure 2H, the semiconductor memory device 1000 h may include a plurality of lower electrodes 210 , an upper support pattern 330 , an upper electrode 230 , a plurality of first wiring contact plugs 410 , a plurality of second wiring contact plugs 420 , and a plurality of wirings 500 .

[0069] The upper support pattern 330 may contact the sidewalls of the plurality of lower electrodes 210 to support the plurality of lower electrodes 210. The upper electrode 230 may cover the plurality of lower electrodes 210 and the upper support pattern 330. In a plan view, the upper support pattern 330 may be spaced apart from the edge of the upper electrode 230 and may be arranged inside the upper electrode 230. The plurality of wirings 500 may be spaced apart from the upper electrode 230 in the vertical direction (Z direction).

[0070] A plurality of first wiring contact plugs 410 and a plurality of second wiring contact plugs 420 may be disposed between at least some of the plurality of wirings 500 and the upper electrode 230 and may electrically connect at least some of the plurality of wirings 500 to the upper electrode 230 .

[0071] In some embodiments, each of the plurality of second wiring contact plugs 420 may be arranged on one side in the first horizontal direction (X direction) (i.e., the direction in which the wiring 500 extends from the plurality of first wiring contact plugs 410), or may be arranged on one side in the second horizontal direction (Y direction) orthogonal to the extension direction of the wiring 500, and therefore, may be arranged closer to the edge of the upper support pattern 330 than the plurality of first wiring contact plugs 410.

[0072] In some embodiments, the second wiring contact plug 420 arranged on one side of the plurality of second wiring contact plugs 420 along the first horizontal direction (X direction) (i.e., the extension direction of the wiring 500) can be arranged between the wiring 500 having a relatively larger horizontal width among the plurality of wirings 500 and the upper electrode 230, and the second wiring contact plug 420 arranged on one side of the plurality of first wiring contact plugs 410 along the second horizontal direction (Y direction) orthogonal to the extension direction of the wiring 500 can be arranged between the wiring 500 having a relatively smaller horizontal width among the plurality of wirings 500 and the upper electrode 230.

[0073] In some embodiments, the long-axis direction of the planar shape of each of the plurality of first wiring contact plugs 410 may include a direction orthogonal to the extending direction of the wiring 500 connected to each of the plurality of first wiring contact plugs 410. The long-axis direction of the planar shape of the second wiring contact plug 420 arranged on one side of the plurality of first wiring contact plugs 410 along the first horizontal direction (X direction) (i.e., the direction in which the wiring 500 extends from the plurality of first wiring contact plugs 410) may include a second horizontal direction (Y direction), i.e., the direction orthogonal to the extending direction of the wiring 500 connected to the second wiring contact plug 420, and the long-axis direction of the planar shape of the second wiring contact plug 420 arranged on one side of the plurality of first wiring contact plugs 410 along the second horizontal direction (Y direction) orthogonal to the direction in which the wiring 500 extends from the plurality of first wiring contact plugs 410 may include the first horizontal direction (X direction), i.e., the extending direction of the wiring 500 connected to the second wiring contact plug 420.

[0074] Figures 3A to 3D 、 Figures 4A to 4D 、 5A to 5D 、 6A to 6D 、 7A to 7D 、 Figures 8A to 8D 、 9A to 9D and 10A to 10D is a cross-sectional view for describing a method for manufacturing a semiconductor memory device according to an embodiment, and Figures 11A to 11E is a cross-sectional view of a semiconductor memory device 1000 a according to an embodiment. Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 7A 、 Figure 8A 、 Figure 9A and Figure 11A It is along Figure 1B A cross-sectional view taken along line AA'; Figure 4B 、 Figure 5B 、 Figure 6B 、 Figure 7B 、 Figure 8B 、 Figure 9B and Figure 11B It is along Figure 1B A cross-sectional view taken along line BB'; Figure 4C 、 Figure 5C 、 Figure 6C 、 Figure 7C 、 Figure 8C 、 Figure 9C and Figure 11C It is along Figure 1B A cross-sectional view taken along line CC' in FIG. Figure 4D 、 Figure 5D 、 Figure 6D 、 Figure 7D 、 Figure 8D、 Figure 9D and Figure 11D It is along Figure 1B A cross-sectional view taken along line D-D' in FIG. 10A to 10D and Figure 11E It is along Figure 1B and Figures 2A to 2H A cross-sectional view taken along line EE' in FIG. 1 ; and in particular, Figure 11E It is along Figure 2A A cross-sectional view taken along line EE' in FIG.

[0075] Also refer to Figures 3A to 3D , a device separation trench 116T may be formed in the substrate 110, and a device separation layer 116 filling the device separation trench 116T may be formed. In some embodiments, the device separation trench 116T and the plurality of active regions 118 defined by the device separation trench 116T may be formed using an extreme ultraviolet (EUV) lithography process.

[0076] The substrate 110 may include, for example, silicon (Si), crystalline Si, polycrystalline Si, or amorphous Si. In some other embodiments, the substrate 110 may include a semiconductor element such as germanium (Ge) or at least one compound semiconductor selected from silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In some embodiments, the substrate 110 may have a silicon-on-insulator (SOI) structure. For example, the substrate 110 may include a buried oxide (BOX) layer. The substrate 110 may include a conductive region, such as an impurity-doped well or an impurity-doped structure. The device isolation layer 116 may include a material including, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. The device isolation layer 116 may include a single layer including one insulating layer, a double layer including two insulating layers, or a multilayer including a combination of at least three insulating layers. For example, the device isolation layer 116 may include a double layer or multiple layers including an oxide layer and a nitride layer. However, according to the technical concept of the present inventive concept, the configuration of the device isolation layer 116 is not limited thereto.

[0077] A plurality of active regions 118 may be defined in the memory cell region CR on the substrate 110 by the device separation layer 116. In a plan view, the active region 118 may have a relatively long island shape having both a short axis and a long axis, as shown in FIG. Figure 1B The active regions 118 are shown as being arranged in rows along a diagonal direction relative to the first horizontal direction (X direction) and the second horizontal direction (Y direction), and may be arranged in rows along the second horizontal direction (Y direction).

[0078] Also refer to Figures 4A to 4DBy removing a portion of the active region 118 and a portion of the device isolation layer 116, a plurality of word line trenches 120T may be formed in the substrate 110. The plurality of word line trenches 120T may extend parallel to one another in a first horizontal direction (the X direction) and may have a linear shape, wherein each of the plurality of word line trenches 120T is arranged to span the active region 118 and may have substantially equal spacing in a second horizontal direction (the Y direction). In some embodiments, steps may be formed on the lower surfaces of the plurality of word line trenches 120T.

[0079] A gate dielectric layer 122, a plurality of word lines 120, and a plurality of buried insulating layers 124 may be sequentially formed inside the plurality of word line trenches 120T. The plurality of word lines 120 may respectively constitute Figure 1B Multiple word lines WL are shown. Multiple word lines 120 may extend parallel to each other in a first horizontal direction (X direction) and may have a linear shape, wherein each word line in the multiple word lines 120 is arranged to cross the active region 118 and may have substantially equal spacing in a second horizontal direction (Y direction). The upper surface of each word line in the multiple word lines 120 may be at a lower level than the upper surface of the substrate 110. The lower surface of the multiple word lines 120 may have a concave-convex shape, and the multiple active regions 118 may include transistors having a saddle fin structure (or saddle FinFET).

[0080] Each of the plurality of word lines 120 may have a stacked structure comprising a lower word line layer 120 a and an upper word line layer 120 b. For example, the lower word line layer 120 a may include a metal material, a conductive metal nitride, or a combination thereof. In some embodiments, the lower word line layer 120 a may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or a combination thereof. For example, the upper word line layer 120 b may include doped polysilicon. In some embodiments, the lower word line layer 120 a may include a core layer and a barrier layer located between the core layer and the gate dielectric layer 122.

[0081] In some embodiments, before or after forming the plurality of word lines 120 , impurity ions may be implanted into portions of the active region 118 of the substrate 110 located on both sides of the plurality of word lines 120 , and source and drain regions may be formed inside the plurality of active regions 118 .

[0082] Gate dielectric layer 122 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, oxide-nitride-oxide (ONO), and a high-k dielectric having a higher dielectric constant than silicon oxide. For example, gate dielectric layer 122 may have a dielectric constant of about 10 to about 25.

[0083] Upper surfaces of the plurality of buried insulating layers 124 may be substantially at the same level as an upper surface of the substrate 110. The buried insulating layers 124 may include at least one material of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0084] During the process of forming the plurality of gate dielectric layers 122 , the plurality of word lines 120 , and the plurality of buried insulating layers 124 , portions of the upper side of the device separation layer 116 may be removed. A plurality of active regions 118 may be defined by the device separation layer 116 on the substrate 110 .

[0085] Also refer to 5A to 5D , a first insulating layer pattern 112 and a second insulating layer pattern 114 may be formed to cover the device separation layer 116 and the plurality of active regions 118, respectively. For example, the first insulating layer pattern 112 and the second insulating layer pattern 114 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. In some embodiments, the first insulating layer pattern 112 may include a silicon oxide layer, and the second insulating layer pattern 114 may include a silicon nitride layer. In some other embodiments, the first insulating layer pattern 112 may include a non-metallic dielectric layer, and the second insulating layer pattern 114 may include a metal dielectric layer.

[0086] After forming a conductive semiconductor layer 132P on the first and second insulation layer patterns 112 and 114, a direct contact hole 134H may be formed that penetrates the conductive semiconductor layer 132P and the first and second insulation layer patterns 112 and 114 and exposes the source region in the active area 118. A direct contact conductive layer 134P may also be formed to fill the direct contact hole 134H. In some embodiments, the direct contact hole 134H may extend into the active area 118, that is, into the source region. The conductive semiconductor layer 132P may include, for example, doped polysilicon. The direct contact conductive layer 134P may include, for example, doped polysilicon. In some embodiments, the direct contact conductive layer 134P may include an epitaxial silicon layer. In some other embodiments, the direct contact conductive layer 134P may include a metal or a metal compound as the conductive material. For example, the direct contact conductive layer 134P may include a metal (such as Ti and W) or a conductive metal that is a compound of a non-metal (such as Si, C, B, and N). In some embodiments, the direct contact conductive layer 134P may include TiN, WC, or WSi.

[0087] Also refer to 5A to 5D as well as 6A to 6DA metal-based conductive layer and an insulating capping layer may be sequentially formed to cover the conductive semiconductor layer 132P and directly contact the conductive layer 134P and form the bitline structure 140. In some embodiments, the metal-based conductive layer may have a stacked structure including a first metal-based conductive layer and a second metal-based conductive layer. By etching the first metal-based conductive layer, the second metal-based conductive layer, and the insulating capping layer, a plurality of bitlines 147 including a first metal-based pattern 145 and a second metal-based pattern 146 having a linear shape and a plurality of insulating capping lines 148 may be formed.

[0088] In some embodiments, the first metal-based pattern 145 may include titanium nitride (TiN) or Ti-Si-N (TSN), and the second metal-based pattern 146 may include W or tungsten silicide (WSix). In some embodiments, the first metal-based pattern 145 may function as a diffusion barrier. In some embodiments, the plurality of insulating capping lines 148 may include a silicon nitride layer.

[0089] One bit line 147 and one insulating capping line 148 covering one bit line 147 may constitute one bit line structure 140. A plurality of bit line structures 140, each including a bit line 147 and an insulating capping line 148 covering the bit line 147, may extend parallel to each other along a second horizontal direction (Y direction) parallel to the main surface of the substrate 110. A plurality of bit lines 147 may constitute Figure 1B In some embodiments, the bit line structure 140 may further include a conductive semiconductor pattern 132 , which is a portion of the conductive semiconductor layer 132P disposed between the first and second insulation layer patterns 112 and 114 and the first metal base pattern 145 .

[0090] In the etching process for forming the plurality of bit lines 147, a plurality of conductive semiconductor patterns 132 and a plurality of direct contact conductive patterns 134 may be formed by removing portions of the conductive semiconductor layer 132P that do not vertically overlap with the bit lines 147 and a portion of the direct contact conductive layer 134P together using the etching process. In this case, the first insulating layer pattern 112 and the second insulating layer pattern 114 may serve as etching stop layers in the etching process for forming the plurality of bit lines 147, the plurality of conductive semiconductor patterns 132, and the plurality of direct contact conductive patterns 134. The plurality of direct contact conductive patterns 134 may constitute Figure 1BMultiple direct contacts DC are shown in FIG. Multiple bit lines 147 can be electrically connected to multiple active regions 118 via multiple direct contact conductive patterns 134, respectively. The conductive semiconductor pattern 132 may include, for example, doped polysilicon. The direct contact conductive pattern 134 may include doped polysilicon, a metal, or a metal compound including a conductive material. For example, the direct contact conductive pattern 134 may include a metal (such as Ti and W) or a conductive metal that is a compound of a non-metal (such as Si, C, B, and N). In some embodiments, the direct contact conductive pattern 134 may include TiN, WC, or WSi.

[0091] Both sidewalls of each of the plurality of bitline structures 140 may be covered by an insulating spacer structure 150. Each of the plurality of insulating spacer structures 150 may include a first insulating spacer 152, a second insulating spacer 154, and a third insulating spacer 156. The second insulating spacer 154 may include a material having a lower dielectric constant than the first insulating spacer 152 and the third insulating spacer 156. In some embodiments, the first insulating spacer 152 and the third insulating spacer 156 may include a nitride layer, and the second insulating spacer 154 may include an oxide layer. In some embodiments, the first insulating spacer 152 and the third insulating spacer 156 may include a nitride layer, and the second insulating spacer 154 may include a material having an etch selectivity relative to the first insulating spacer 152 and the third insulating spacer 156. For example, when the first insulating spacer 152 and the third insulating spacer 156 include a nitride layer, the second insulating spacer 154 may include an oxide layer, but may be removed in a subsequent process to become an air spacer.

[0092] A plurality of buried contact holes 170H may be formed between each of the plurality of bit lines 147. The plurality of buried contact holes 170H may have an inner space defined by an insulating spacer structure 150 and the active region 118, the insulating spacer structure 150 covering a sidewall of each adjacent bit line 147 between two adjacent bit lines 147 among the plurality of bit lines 147.

[0093] The plurality of buried contact holes 170H can be formed by removing portions of the first and second insulation layer patterns 112, 114, and the active region 118 using the plurality of insulating capping lines 148 and the insulating spacer structures 150 covering both sidewalls of each of the plurality of bit line structures 140 as etching masks. In some embodiments, an anisotropic etching process is first performed to remove portions of the first and second insulation layer patterns 112, 114, and the active region 118 using the plurality of insulating capping lines 148 and the insulating spacer structures 150 covering both sidewalls of each of the plurality of bit line structures 140 as etching masks, and then an isotropic etching process is performed to further remove other portions of the active region 118. This allows the plurality of buried contact holes 170H to have an expanded space defined by the active region 118.

[0094] A plurality of gate line patterns GLP may be formed on Figure 1B In the peripheral region PR shown, a plurality of gate line patterns GLP may be formed together with a plurality of bit lines 147. In other words, the gate line pattern GLP may have a stacked structure of a first metal-based pattern 145 and a second metal-based pattern 146.

[0095] Also refer to 7A to 7D A plurality of buried contacts 170 and a plurality of insulating fences 180 may be formed in the spaces between each of the plurality of insulating spacer structures 150 that respectively cover both sidewalls of the plurality of bitline structures 140. The plurality of buried contacts 170 and the plurality of insulating fences 180 may be alternately arranged along the spaces (i.e., in the second horizontal direction (Y direction)) between a pair of facing insulating spacer structures 150 among the plurality of insulating spacer structures 150 that respectively cover both sidewalls of the plurality of bitline structures 140. For example, the plurality of buried contacts 170 may include polysilicon. For example, the plurality of insulating fences 180 may include a nitride layer.

[0096] In some embodiments, the plurality of buried contacts 170 may be arranged in a line in each of a first horizontal direction (X direction) and a second horizontal direction (Y direction). Each of the plurality of buried contacts 170 may extend from the active region 118 along a vertical direction (Z direction) orthogonal to the substrate 110. The plurality of buried contacts 170 may constitute Figure 1B Multiple buried contacts BC are shown in FIG.

[0097] The plurality of buried contacts 170 may be arranged in a space defined by the plurality of insulating fences 180 and the plurality of insulating spacer structures 150, each of which covers both sidewalls of the plurality of bit line structures 140. The plurality of buried contacts 170 may fill a lower portion of a space between each of the plurality of insulating spacer structures 150, each of which covers both sidewalls of the plurality of bit line structures 140.

[0098] The upper surfaces of buried contacts 170 may be lower than the upper surfaces of insulation capping lines 148. The upper surfaces of insulation fences 180 and insulation capping lines 148 may be at the same level relative to the vertical direction (Z direction).

[0099] The plurality of landing pad holes 190H may be respectively defined by the plurality of insulating spacer structures 150 and the plurality of insulating fences 180. The plurality of buried contacts 170 may be exposed at lower surfaces of the plurality of landing pad holes 190H, respectively.

[0100] In the process of forming multiple buried contacts 170 and / or multiple insulating fences 180, portions of the upper side of the insulating capping line 148 included in the bit line structure 140 and the insulating spacer structure 150 can be removed, and thus, the level of the upper surface of the bit line structure 140 can be lowered.

[0101] Also refer to Figures 8A to 8D A landing pad material layer may be formed to fill the plurality of landing pad holes 190H and cover the plurality of bit line structures 140. In some embodiments, the landing pad material layer may include a conductive barrier layer and a conductive pad material layer on the conductive barrier layer. For example, the conductive barrier layer may include a metal, a conductive metal nitride, or a combination thereof. In some embodiments, the conductive barrier layer may have a Ti / TiN stacked structure. In some embodiments, the conductive pad material layer may include W.

[0102] In some embodiments, before forming the landing pad material layer, a metal silicide layer may be formed on the plurality of buried contacts 170. The metal silicide layer may be disposed between the plurality of buried contacts 170 and the landing pad material layer. The metal silicide layer may include, but is not limited to, cobalt silicide (CoSix), nickel silicide (NiSix), or manganese silicide (MnSix).

[0103] Subsequently, by removing a portion of the landing pad material layer, a plurality of landing pads 190 may be formed, which fill at least a portion of the plurality of landing pad holes 190H, extend onto the plurality of bit line structures 140, and are separated into a plurality by the recessed portion 190R.

[0104] The plurality of landing pads 190 may be spaced apart from each other with the recessed portion 190R located therebetween. The plurality of landing pads 190 may be respectively arranged on the plurality of buried contacts 170 and may respectively extend to the plurality of bit line structures 140. In some embodiments, the plurality of landing pads 190 may respectively extend to the plurality of bit lines 147. The plurality of landing pads 190 may be arranged on the plurality of buried contacts 170, and the plurality of buried contacts 170 and the plurality of landing pads 190 corresponding to each other may be electrically connected to each other. The buried contacts 170 and the landing pads 190 corresponding to each other may be collectively referred to as contact plugs. The plurality of landing pads 190 may be connected to the active region 118 via the plurality of buried contacts 170, respectively. The plurality of landing pads 190 may constitute Figure 1B A plurality of landing pads LP are shown.

[0105] The buried contact 170 may be disposed between two adjacent bit line structures 140 , and the landing pad 190 may extend from the space between the two adjacent bit line structures 140 with the buried contact 170 located therebetween to one bit line structure 140 .

[0106] Reference 9A to 9D , an insulating structure 195 filling the recessed portion 190R may be formed. In some embodiments, the insulating structure 195 may include an interlayer insulating layer and an etch stop layer. For example, the interlayer insulating layer may include oxide, and the etch stop layer may include nitride. Figure 9A and Figure 9C It is shown that the upper surface of the insulating structure 195 and the upper surface of the landing pad 190 are at the same level, but the embodiment is not limited thereto.

[0107] Reference Figure 10A, a plurality of lower electrodes 210 connected to the plurality of landing pads 190, and a plurality of support patterns (i.e., 310, 320, and 330) that contact the sidewalls of the plurality of lower electrodes 210 and support the plurality of lower electrodes 210 may be formed. The plurality of support patterns (i.e., 310, 320, and 330) may include a lower support pattern 310, an intermediate support pattern 320, and an upper support pattern 330, which contact the sidewalls of the plurality of lower electrodes 210 and are located at different vertical levels, thereby being spaced apart from each other in the vertical direction (Z direction). The upper support pattern 310, the intermediate support pattern 320, and the lower support pattern 330 may be referred to as a first support pattern 310, a second support pattern 320, and a third support pattern 330, respectively. After forming a mold layer between each of the upper supporting patterns 310, the middle supporting patterns 320, and the lower supporting patterns 330, and forming a plurality of through holes that penetrate the upper supporting patterns 310, the middle supporting patterns 320, and the lower supporting patterns 330, and then penetrate the mold layer to expose the plurality of landing pads 190 on the lower surfaces thereof, a plurality of lower electrodes 210 can be formed by filling the plurality of through holes with a conductive material and removing the mold layer. In some embodiments, a plurality of openings serving as a path for removing the mold layer may be arranged in each of the upper supporting patterns 310, the middle supporting patterns 320, and the lower supporting patterns 330.

[0108] The lower supporting pattern 310 may be located at a higher vertical level than the plurality of landing pads 190 in the vertical direction (Z direction) to contact the sidewalls of the plurality of lower electrodes 210. The middle supporting pattern 320 may be located at a higher vertical level than the lower supporting pattern 310 in the vertical direction (Z direction) to contact the sidewalls of the plurality of lower electrodes 210. The upper supporting pattern 330 may be located at a higher vertical level than the middle supporting pattern 320 in the vertical direction (Z direction) to contact the sidewalls of the plurality of lower electrodes 210. The lower supporting pattern 310 may contact the sidewalls of the plurality of lower electrodes 210 near their lower end portions in the vertical direction (Z direction). Figure 10AThe lower surface of the lower support pattern 310 and the lower surfaces of the plurality of lower electrodes 210 are shown as being at the same vertical level, but this embodiment is merely an example and is not intended to be limiting. In some embodiments, the lower surface of the lower support pattern 310 may be at a higher vertical level than the lower surfaces of the plurality of lower electrodes 210 and may be spaced apart from the plurality of landing pads 190 and the insulating structure 195 in the vertical direction (Z direction). In some embodiments, the intermediate support pattern 320 may contact the sidewalls of the plurality of lower electrodes 210 at a vertical level higher than the center of the plurality of lower electrodes 210 in the vertical direction (Z direction). For example, the intermediate support pattern 320 may be at a vertical level lower than the uppermost end of the plurality of lower electrodes 210 and higher than the center of the plurality of lower electrodes 210 in the vertical direction (Z direction), and may contact the sidewalls of the plurality of lower electrodes 210. The upper support pattern 330 may contact the upper sidewalls of the plurality of lower electrodes 210. In some embodiments, a top surface of a portion of the upper support pattern 330 that contacts a sidewall of any lower electrode 210 among the plurality of lower electrodes 210 may be at the same vertical level as the top surface of any lower electrode 210. Each of the lower support pattern 310, the intermediate support pattern 320, and the upper support pattern 330 may include any one of silicon nitride (SiN), silicon carbonitride (SiCN), nitrogen-rich SiN, and silicon-rich SiN, but is not limited thereto.

[0109] In a plan view, the upper surface of the upper supporting pattern 330 may be located at a first vertical level LV1 within the upper supporting pattern 330, and the edges of the upper supporting pattern 330 may be located at a second vertical level LV2 that is higher than the first vertical level LV1. For example, the second vertical level LV2 may be located at a vertical level that is approximately 10 nm to approximately 30 nm higher than the first vertical level LV1. In a plan view, the upper supporting pattern 330 may have a first thickness T1 therein, and may have a second thickness T2 that is greater than the first thickness T1 at its edges. For example, the second thickness T2 may be approximately 10 nm to approximately 30 nm greater than the first thickness T1.

[0110] The plurality of lower electrodes 210 can be electrically connected to the plurality of landing pads 190, respectively. Each of the plurality of lower electrodes 210 can have an internally filled cylindrical shape, i.e., a cylindrical shape with a circular horizontal cross-section, but is not limited thereto. In some embodiments, each of the plurality of lower electrodes 210 can have a cylindrical shape with its lower portion closed. In some embodiments, the plurality of lower electrodes 210 can be arranged in a honeycomb zigzag pattern relative to the first horizontal direction (X direction) or the second horizontal direction (Y direction). In some other embodiments, the plurality of lower electrodes 210 can be arranged in a linear matrix in each of the first horizontal direction (X direction) and the second horizontal direction (Y direction). In some embodiments, each of the plurality of lower electrodes 210 can have a tapered shape, wherein each of the plurality of lower electrodes 210 extends from a bottom side to an upper side, with its horizontal width increasing in the vertical direction (Z direction). The plurality of lower electrodes 210 can include, for example, silicon doped with impurities, metals (such as W and copper), or conductive metal compounds (such as titanium nitride).

[0111] Reference Figure 10B , a capacitor dielectric layer 220 and an upper electrode 230 may be sequentially formed on the plurality of lower electrodes 210. The plurality of lower electrodes 210, the capacitor dielectric layer 220, and the upper electrode 230 may constitute a plurality of capacitor structures 200. The capacitor dielectric layer 220 may conformally cover the surfaces of the plurality of lower electrodes 210. In some embodiments, the capacitor dielectric layer 220 and the upper electrode 230 may be formed as one body to provide a plurality of capacitor structures 200 in a specific region (e.g., in a memory cell region). Figure 1B CR in the middle) together covers multiple lower electrodes 210.

[0112] The capacitor dielectric layer 220 may include, for example, TaO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, (Ba,Sr)TiO (BST), SrTiO (STO), BaTiO (BTO), (Pb,Zr,Ti)(PZT)O, (Pb,La)(Zr,Ti)O, Ba(Zr,Ti)O, Sr(Zr,Ti)O, or combinations thereof.

[0113] The upper electrode 230 may include, for example, W, Ru, RuO, Pt, PtO, Ir, IrO, SrRuO (SRO), (Ba, Sr)RuO (BSRO), CaRuO (CRO), BaRuO, La(Sr, Co)O, etc. In some embodiments, the upper electrode 230 may include a metal material. For example, the upper electrode 230 may include W.

[0114] The upper electrode 230 may have a side surface thickness TL on the side surface of the upper support pattern 330 in the horizontal direction. In a plan view, the edge of the upper electrode 230 and the edge of the upper support pattern 330 may be spaced apart from each other by the side surface thickness TL. The side surface thickness TL may be less than about 300 nm. For example, the side surface thickness TL may be about 230 nm to about 270 nm.

[0115] Reference Figure 10C A buried insulating layer 350 may be formed covering the plurality of capacitor structures 200. For example, the buried insulating layer 350 may include an oxide layer or an ultra-low-k (ULK) layer. The oxide layer may be formed from any of a borophosphosilicate glass (BPSG) layer, a phosphosilicate glass (PSG) layer, a borosilicate glass (BSG) layer, an undoped silicate glass (USG) layer, a tetraethyl orthosilicate (TEOS) layer, and a high-density plasma (HDP) layer. The ULK layer may include, for example, any of a SiOC layer and a SiCOH layer, each having an ultra-low dielectric constant K of approximately 2.2 to approximately 2.4. In some embodiments, the upper surface of the buried insulating layer 350 may be at a higher vertical level than the upper surface of the upper electrode 230.

[0116] Also refer to Figure 10C and Figure 10D The upper electrode 230 may be exposed by removing a portion of the upper side of the upper electrode 230 and a portion of the upper side of the buried insulating layer 350. The upper surface of the upper electrode 230 may be planarized by removing a portion of the upper side of the upper electrode 230 and a portion of the upper side of the buried insulating layer 350. For example, the upper surface of the upper electrode 230 and the upper surface of the buried insulating layer 350 may be substantially at the same vertical level to collectively form a coplanar surface.

[0117] Also refer to Figures 11A to 11E , the semiconductor memory device 1000a can be formed by forming a cover insulating layer 400 covering the buried insulating layer 350 and the upper electrode 230, a plurality of first wiring contact plugs 410 penetrating the cover insulating layer 400 and extending into the upper electrode 230, and a plurality of wirings 500 arranged on the cover insulating layer 400 and the plurality of first wiring contact plugs 410 and respectively connected to the plurality of first wiring contact plugs 410.

[0118] For example, the capping insulating layer 400 may include silicon oxide. The capping insulating layer 400 may include, for example, an oxide layer or a ULK layer. After forming a plurality of first contact holes MCH1 that penetrate the capping insulating layer 400 and extend into the upper electrode 230, a plurality of first wiring contact plugs 410 may be formed by filling the plurality of first contact holes MCH1 with a conductive material. The plurality of first wiring contact plugs 410 may include a wiring contact barrier layer covering the exposed surfaces within the plurality of first contact holes MCH1, and a wiring contact charging layer covering the wiring contact barrier layer and filling the plurality of first contact holes MCH1. For example, the wiring contact barrier layer may include a metal (such as Ti, Ta, TiN, and TaN) or a conductive metal nitride. For example, the wiring contact charging layer may include a metal (such as W). Each of the plurality of first contact holes MCH1 and the plurality of first wiring contact plugs 410 may have a tapered shape extending from a lower side to an upper side, with its horizontal width increasing in the vertical direction (Z direction).

[0119] A plurality of wirings 500 may be formed on the capping insulating layer 400. At least some of the plurality of wirings 500 may be connected to the plurality of first contact holes MCH1 and may supply power to the upper electrode 230. The plurality of wirings 500 may include metal, for example, Al, Cu, W, etc.

[0120] Also refer to Figure 2A and Figure 11E In a plan view, the plurality of first wiring contact plugs 410 are spaced apart from the edge of the upper support pattern 330 into the upper support pattern 330 by at least a first horizontal spacing distance DL1. In other words, in a plan view, the first wiring contact plug 410 closest to the edge of the upper support pattern 330 among the plurality of first wiring contact plugs 410 may be spaced apart from the edge of the upper support pattern 330 by the first horizontal spacing distance DL1. The plurality of first wiring contact plugs 410 may be arranged on a portion of the upper support pattern 330 having the first thickness T1. The plurality of first wiring contact plugs 410 may be arranged on a portion of the upper surface of the upper support pattern 330 at a first vertical level LV1.

[0121] The side surface thickness TL (i.e., the horizontal thickness of the portion of the upper electrode 230 covering the side surface of the upper support pattern 330) can be less than approximately 300 nm. For example, the side surface thickness TL can be between approximately 230 nm and approximately 270 nm. The maximum vertical thickness (Z-direction) of the portion of the upper electrode 230 covering the upper surface of the upper support pattern 330 can be a first vertical thickness TV1, and the minimum vertical thickness (TV2) can be a second vertical thickness TV2 that is less than the first vertical thickness TV1. Each of the first vertical thickness TV1 and the second vertical thickness TV2 can be less than the side surface thickness TL. In a plan view, the first vertical thickness TV1 can be the thickness of the portion of the upper electrode 230 connected to the plurality of first wiring contact plugs 410, i.e., the vertical thickness (Z-direction) of the portion of the upper electrode 230 in the inner support region SIR, and the second vertical thickness TV2 can be the vertical thickness (Z-direction) of the portion of the upper electrode 230 on the edge of the upper support pattern 330. The first vertical thickness TV1 may be approximately 10 nm to approximately 30 nm greater than the second vertical thickness TV2. In a plan view, each of the plurality of first wiring contact plugs 410 may be spaced apart from an edge of the upper support pattern 330 by a first horizontal spacing distance DL1 greater than the side surface thickness TL. For example, the first horizontal spacing distance DL1 may be approximately 300 nm.

[0122] Each of the plurality of first wiring contact plugs 410 may have the same first vertical height H1 in the vertical direction (Z direction). The lower surface of each of the plurality of first wiring contact plugs 410 may be spaced apart in the vertical direction (Z direction) by a spacing distance equal to the first vertical spacing distance DV1 from the upper surface of the capacitor dielectric layer 220 covering the upper surface of the upper support pattern 330 and the upper surface of the lower electrode 210. In other words, the vertical thickness of the portion of the upper electrode 230 between the lower surface of each of the plurality of first wiring contact plugs 410 and the upper surface of the portion of the capacitor dielectric layer 220 may generally have the same value, namely, the first vertical spacing distance DV1.

[0123] Also refer to Figure 2A and Figures 11A to 11E Since the spacing distance between each of the multiple first wiring contact plugs 410 and the capacitor dielectric layer 220 is approximately the same, the deviation of the electrical characteristics of each of the multiple capacitor structures 200 constituting the multiple memory cells can be reduced, thereby ensuring the reliability of the semiconductor memory device 1000a.

[0124] Figure 12 and Figure 13 are cross-sectional views of semiconductor memory devices 1000 b and 1000 c according to embodiments, respectively. Figure 12 and Figure 13 Along Figure 1B and Figures 2A to 2H A cross-sectional view taken along line EE' in FIG. 1 , and specifically, Figure 12 It is along Figure 2B A cross-sectional view taken along line EE' in FIG. Figure 13 It is along Figure 2C A cross-sectional view taken along line EE' in FIG.

[0125] Also refer to Figure 2B and Figure 12 , the semiconductor memory device 1000b can be formed by forming a cover insulating layer 400 covering the buried insulating layer 350 and the upper electrode 230, a plurality of first wiring contact plugs 410 and a plurality of second wiring contact plugs 420 penetrating the cover insulating layer 400 and extending into the upper electrode 230, and a plurality of wirings 500 arranged on the cover insulating layer 400, the plurality of first wiring contact plugs 410, and the plurality of second wiring contact plugs 420 and connected to the plurality of first wiring contact plugs 410 and the plurality of second wiring contact plugs 420.

[0126] After forming a plurality of first contact holes MCH1 that penetrate the cover insulating layer 400 and extend into the upper electrode 230, the plurality of first wiring contact plugs 410 may be formed by filling the plurality of first contact holes MCH1. Furthermore, after forming a plurality of second contact holes MCH2 that penetrate the cover insulating layer 400 and extend into the upper electrode 230, the plurality of second wiring contact plugs 420 may be formed by filling the plurality of second contact holes MCH2. The plurality of first contact holes MCH1 and the plurality of second contact holes MCH2 may be formed together using the same etching process, and the plurality of first wiring contact plugs 410 and the plurality of second wiring contact plugs 420 may be formed together by simultaneously filling the plurality of first contact holes MCH1 and the plurality of second contact holes MCH2, respectively. Each of the plurality of first contact holes MCH1, the plurality of second contact holes MCH2, the plurality of first wiring contact plugs 410, and the plurality of second wiring contact plugs 420 may extend from the lower side to the upper side in the vertical direction (Z direction) and have a tapered shape with increasing horizontal width.

[0127] In a plan view, the plurality of first wiring contact plugs 410 may be spaced apart by at least a first horizontal spacing distance DL1 from an edge of the upper support pattern 330 into the upper support pattern 330, and the plurality of second wiring contact plugs 420 may be spaced apart by a second horizontal spacing distance DL2, which is less than the first horizontal spacing distance DL1, from an edge of the upper support pattern 330 into the upper support pattern 330. The first horizontal spacing distance DL1 may be greater than the side surface thickness TL, and the second horizontal spacing distance DL2 may be less than the side surface thickness TL.

[0128] At the same vertical level, the horizontal area of ​​each of the plurality of second contact holes MCH2 and the plurality of second wiring contact plugs 420 may be smaller than the horizontal area of ​​each of the plurality of first contact holes MCH1 and the plurality of first wiring contact plugs 410, respectively. When the plurality of first contact holes MCH1 and the plurality of second contact holes MCH2 are formed together, due to the difference in their horizontal areas, the extension length of the plurality of second contact holes MCH2 may be formed to be shorter than the extension length of the plurality of first contact holes MCH1. Therefore, each of the plurality of first wiring contact plugs 410 may have the same first vertical height H1, and each of the plurality of second wiring contact plugs 420 may have a second vertical height H2 in the vertical direction (Z direction) that is smaller than the first vertical height H1.

[0129] The lower surface of each of the plurality of first wiring contact plugs 410 may be spaced apart in the vertical direction (Z direction) by the same spacing distance as the first vertical spacing distance DV1 from the upper surface of the portion of the capacitor dielectric layer 220 covering the upper surface of the upper support pattern 330 and the upper surface of the lower electrode 210, and the lower surface of each of the plurality of second wiring contact plugs 420 may be spaced apart in the vertical direction (Z direction) by a second vertical spacing distance DV2. The first vertical spacing distance DV1 and the second vertical spacing distance DV2 may have substantially the same value.

[0130] Since the spacing distance between each of the plurality of first wiring contact plugs 410 and the plurality of second wiring contact plugs 420 and the capacitor dielectric layer 220 is approximately the same, the deviation of the electrical characteristics of each of the plurality of capacitor structures 200 constituting the plurality of memory cells can be reduced, thereby ensuring the reliability of the semiconductor memory device 1000b according to the present invention.

[0131] Also refer to Figure 2C and Figure 13 , the semiconductor memory device 1000c can be formed by forming a covering insulating layer 400 covering the buried insulating layer 350 and the upper electrode 230, a plurality of first wiring contact plugs 410, a plurality of second wiring contact plugs 420, and a plurality of third wiring contact plugs 430 penetrating the covering insulating layer 400 and extending into the upper electrode 230, and a plurality of wirings 500 arranged on the covering insulating layer 400, the plurality of first wiring contact plugs 410, the plurality of second wiring contact plugs 420, and the plurality of third wiring contact plugs 430 and connected to the plurality of first wiring contact plugs 410, the plurality of second wiring contact plugs 420, and the plurality of third wiring contact plugs 430.

[0132] A plurality of first wiring contact plugs 410 can be formed by filling the plurality of first contact holes MCH1 with a conductive material after forming a plurality of first contact holes MCH1 that penetrate the cover insulating layer 400 and extend into the upper electrode 230; a plurality of second wiring contact plugs 420 can be formed by filling the plurality of second contact holes MCH2 with a conductive material after forming a plurality of second contact holes MCH2 that penetrate the cover insulating layer 400 and extend into the upper electrode 230; and a plurality of third wiring contact plugs 430 can be formed by filling the plurality of third contact holes MCH3 with a conductive material after forming a plurality of third contact holes MCH3 that penetrate the cover insulating layer 400 and extend into the upper electrode 230. The plurality of first contact holes MCH1, the plurality of second contact holes MCH2, and the plurality of third contact holes MCH3 may be formed together using the same etching process, and the plurality of first wiring contact plugs 410, the plurality of second wiring contact plugs 420, and the plurality of third wiring contact plugs 430 may be formed together by simultaneously filling the plurality of first contact holes MCH1, the plurality of second contact holes MCH2, and the plurality of third contact holes MCH3, respectively, with a conductive material. Each of the plurality of first contact holes MCH1, the plurality of second contact holes MCH2, the plurality of third contact holes MCH3, the plurality of first wiring contact plugs 410, the plurality of second wiring contact plugs 420, and the plurality of third wiring contact plugs 430 may extend from a lower side to an upper side thereof in a vertical direction (Z direction) and have a tapered shape with an increasing horizontal width.

[0133] In a plan view, the plurality of first wiring contact plugs 410 may be spaced apart from the edge of the upper support pattern 330 by a first horizontal spacing distance DL1 within the upper support pattern 330; the plurality of second wiring contact plugs 420 may be spaced apart from the edge of the upper support pattern 330 by a second horizontal spacing distance DL2 within the upper support pattern 330, which is less than the first horizontal spacing distance DL1; and the plurality of third wiring contact plugs 430 may be spaced apart from the edge of the upper support pattern 330 by a third horizontal spacing distance DL3 within the upper support pattern 330, which is less than the second horizontal spacing distance DL2. The first horizontal spacing distance DL1 may be greater than the side surface thickness TL, and each of the second horizontal spacing distance DL2 and the third horizontal spacing distance DL3 may be less than the side surface thickness TL.

[0134] At the same vertical level, the horizontal area of ​​each of the plurality of third contact holes MCH3 and the plurality of third wiring contact plugs 430 may be smaller than the horizontal area of ​​each of the plurality of second contact holes MCH2 and the plurality of second wiring contact plugs 420, respectively, and the horizontal area of ​​each of the plurality of second contact holes MCH2 and the plurality of second wiring contact plugs 420 may be smaller than the horizontal area of ​​each of the plurality of first contact holes MCH1 and the plurality of first wiring contact plugs 410. When the plurality of first contact holes MCH1, the plurality of second contact holes MCH2, and the plurality of third contact holes MCH3 are formed together, due to the difference in their horizontal areas, the extension length of the plurality of third contact holes MCH3 may be formed to be smaller than the extension length of the plurality of second contact holes MCH2, and the extension length of the plurality of second contact holes MCH2 may be smaller than the extension length of the plurality of first contact holes MCH1. Therefore, each of the plurality of first wiring contact plugs 410 may have the same first vertical height H1 in the vertical direction (Z direction), each of the plurality of second wiring contact plugs 420 may have a second vertical height H2 in the vertical direction (Z direction) that is smaller than the first vertical height H1, and each of the plurality of third wiring contact plugs 430 may have a third vertical height H3 in the vertical direction (Z direction) that is smaller than the second vertical height H2.

[0135] The lower surface of each of the plurality of first wiring contact plugs 410 may be spaced apart in the vertical direction (Z direction) from the upper surface of the portion of the capacitor dielectric layer 220 covering the upper surface of the upper support pattern 330 and the upper surface of the lower electrode 210 by a spacing distance equal to the first vertical spacing distance DV1. The lower surface of each of the plurality of second wiring contact plugs 420 may be spaced apart in the vertical direction (Z direction) by a second vertical spacing distance DV2. The lower surface of each of the plurality of third wiring contact plugs 430 may be spaced apart in the vertical direction (Z direction) by a third vertical spacing distance DV3. The first vertical spacing distance DV1, the second vertical spacing distance DV2, and the third vertical spacing distance DV3 may generally have the same value.

[0136] Since the spacing distance between each of the plurality of first wiring contact plugs 410, the plurality of second wiring contact plugs 420, and the plurality of third wiring contact plugs 430 and the capacitor dielectric layer 220 is approximately the same, the deviation of the electrical characteristics of each of the plurality of capacitor structures 200 constituting the plurality of memory cells can be reduced, thereby ensuring the reliability of the semiconductor memory device 1000c conceived according to the present invention.

[0137] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor memory device comprising: a substrate including a memory cell region; a plurality of lower electrodes arranged in the memory cell region of the substrate; a supporting pattern contacting upper sidewalls of the plurality of lower electrodes to support the plurality of lower electrodes; a capacitor dielectric layer covering the plurality of lower electrodes and the support pattern; an upper electrode covering the plurality of lower electrodes and the support pattern, with the capacitor dielectric layer located therebetween; a covering insulating layer covering the upper electrode; a plurality of first wiring contact plugs configured to penetrate the cover insulating layer and extend into the upper electrode; as well as a plurality of wirings arranged on the upper electrode and the plurality of first wiring contact plugs, at least some of the plurality of wirings being connected to the plurality of first wiring contact plugs, wherein, in a plan view, the plurality of first wiring contact plugs are spaced apart from the edge of the support pattern into the support pattern by at least a first horizontal spacing distance, and The first horizontal spacing distance is greater than the side surface thickness, and the side surface thickness is the thickness of a portion of the upper electrode covering the side surface of the support pattern in the horizontal direction.

2. The semiconductor memory device according to claim 1, wherein In a plan view, the support pattern has a first thickness therein and a second thickness greater than the first thickness at an edge thereof.

3. The semiconductor memory device according to claim 2, wherein The plurality of first wiring contact plugs are arranged on a portion of the support pattern having the first thickness.

4. The semiconductor memory device according to claim 1, wherein Each of the plurality of first wiring contact plugs is spaced apart from an upper surface of the capacitor dielectric layer by the same spacing distance in a vertical direction.

5. The semiconductor memory device according to claim 1, wherein At least one of the plurality of wirings has a horizontal width greater than horizontal widths of the remaining wirings, and the plurality of first wiring contact plugs are connected to the at least one of the plurality of wirings having the greater horizontal width. The semiconductor memory device according to claim 1 , wherein: In a plan view, an upper surface of a first portion of the support pattern inside the support pattern is at a first vertical level, and an upper surface of a second portion of the support pattern on an edge of the support pattern is at a second vertical level higher than the first vertical level, and The plurality of first wiring contact plugs are arranged on the first portion of the support pattern.

7. The semiconductor memory device according to claim 1, further comprising: a plurality of second wiring contact plugs configured to penetrate the cover insulating layer and extend into the upper electrode, the plurality of second wiring contact plugs being connected to at least one wiring among the plurality of wirings, In a plan view, the plurality of second wiring contact plugs are spaced apart from the edge of the support pattern into the support pattern by the first horizontal spacing distance and a second spacing distance smaller than the thickness of the side surface.

8. The semiconductor memory device according to claim 7, wherein A horizontal area and a vertical height of each of the plurality of second wiring contact plugs are respectively smaller than a horizontal area and a vertical height of each of the plurality of first wiring contact plugs.

9. The semiconductor memory device according to claim 8, in, Each of the plurality of first wiring contact plugs is spaced apart from an upper surface of the capacitor dielectric layer by the same first vertical spacing distance in a vertical direction, wherein each of the plurality of second wiring contact plugs is spaced apart from the upper surface of the capacitor dielectric layer by a second vertical spacing distance in the vertical direction, and The first vertical spacing distance is the same as the second vertical spacing distance.

10. The semiconductor memory device according to claim 1, wherein The first horizontal spacing distance is 300 nm.

11. A semiconductor memory device comprising: substrate; a plurality of lower electrodes arranged on the substrate; a supporting pattern contacting upper sidewalls of the plurality of lower electrodes to support the plurality of lower electrodes; a capacitor dielectric layer covering the plurality of lower electrodes and the support pattern; an upper electrode covering the plurality of lower electrodes and the support pattern, with the capacitor dielectric layer located therebetween; a covering insulating layer covering the upper electrode; a plurality of first wiring contact plugs arranged in a plan view to be spaced at least a first horizontal spacing distance from an edge of the support pattern into the support pattern, the plurality of first wiring contact plugs being configured to penetrate the cover insulating layer and extend into the upper electrode; a plurality of second wiring contact plugs, arranged in a plan view to be spaced apart from an edge of the support pattern into the support pattern by a second horizontal spacing distance that is smaller than the first horizontal spacing distance, the plurality of second wiring contact plugs being configured to penetrate the cover insulating layer and extend into the upper electrode; as well as a plurality of wirings arranged on the upper electrode, the plurality of first wiring contact plugs, and the plurality of second wiring contact plugs, at least one wiring of the plurality of wirings being connected to the plurality of first wiring contact plugs and the plurality of second wiring contact plugs, Wherein, the first horizontal spacing distance is greater than the side surface thickness, and the side surface thickness is the thickness of the portion of the upper electrode covering the side surface of the support pattern in the horizontal direction, and Wherein, a vertical height of each of the plurality of second wiring contact plugs is smaller than a vertical height of each of the plurality of first wiring contact plugs.

12. The semiconductor memory device according to claim 11, in, In a plan view, the support pattern has a first thickness therein and a second thickness at an edge thereof that is greater than the first thickness, wherein the plurality of first wiring contact plugs are arranged on a portion of the support pattern having the first thickness, and Wherein, the second horizontal spacing distance is smaller than the side surface thickness.

13. The semiconductor memory device according to claim 11, wherein Each first wiring contact plug of the plurality of first wiring contact plugs and each second wiring contact plug of the plurality of second wiring contact plugs are spaced apart from an upper surface of the capacitor dielectric layer by the same vertical spacing distance in a vertical direction.

14. The semiconductor memory device according to claim 13, wherein A horizontal area of ​​each of the plurality of second wiring contact plugs is smaller than a horizontal area of ​​each of the plurality of first wiring contact plugs.

15. The semiconductor memory device according to claim 11, wherein In a plan view, an upper surface of a portion of the supporting pattern inside the supporting pattern is at a first vertical level, and an upper surface of the supporting pattern on an edge of the supporting pattern is at a second vertical level that is 10 nm to 30 nm higher than the first vertical level, and The plurality of first wiring contact plugs are arranged on a portion of the upper surface of the support pattern that is at the first vertical level.

16. The semiconductor memory device according to claim 11, further comprising: a plurality of third wiring contact plugs configured to penetrate the cover insulating layer and extend into the upper electrode, the plurality of third wiring contact plugs being connected to some of the plurality of wirings, wherein, in a plan view, the plurality of third wiring contact plugs are spaced apart from the edge of the support pattern into the support pattern by a third horizontal spacing distance, the third horizontal spacing distance being smaller than each of the second horizontal spacing distance and the side surface thickness, and Wherein, a vertical height of each of the plurality of third wiring contact plugs is smaller than a vertical height of each of the plurality of second wiring contact plugs.

17. The semiconductor memory device according to claim 16, wherein Each of the plurality of first wiring contact plugs, the plurality of second wiring contact plugs, and the plurality of third wiring contact plugs is spaced apart from an upper surface of the capacitor dielectric layer by the same vertical spacing distance in a vertical direction, and Wherein, the horizontal area of ​​each third wiring contact plug among the plurality of third wiring contact plugs is smaller than the horizontal area of ​​each second wiring contact plug among the plurality of second wiring contact plugs, and the horizontal area of ​​each second wiring contact plug among the plurality of second wiring contact plugs is smaller than the horizontal area of ​​each first wiring contact plug among the plurality of first wiring contact plugs.

18. A semiconductor memory device comprising: a substrate having a plurality of active regions defined therein; a plurality of word lines, configured to respectively cross the plurality of active regions and extend along a first horizontal direction; a plurality of bit lines, respectively arranged in the plurality of active regions and extending along a second horizontal direction orthogonal to the first horizontal direction; a plurality of buried contacts configured to fill a lower portion of a space between each of the plurality of bit lines, the plurality of buried contacts being connected to the plurality of active regions, respectively; a plurality of landing pads configured to fill an upper portion of a space between each of the plurality of bit lines, the plurality of landing pads extending onto the plurality of bit lines, respectively; a plurality of lower electrodes, respectively contacting the plurality of landing pads; a supporting pattern contacting upper sidewalls of the plurality of lower electrodes to support the plurality of lower electrodes; a capacitor dielectric layer covering the plurality of lower electrodes and the support pattern; an upper electrode covering the plurality of lower electrodes and the support pattern, with the capacitor dielectric layer located therebetween; a covering insulating layer covering the upper electrode; a plurality of first wiring contact plugs arranged in a plan view to be spaced at least a first horizontal spacing distance from an edge of the support pattern into the support pattern, the plurality of first wiring contact plugs being configured to penetrate the cover insulating layer and extend into the upper electrode; a plurality of second wiring contact plugs, arranged in a plan view to be spaced apart from an edge of the support pattern into the support pattern by a second horizontal spacing distance that is smaller than the first horizontal spacing distance, the plurality of second wiring contact plugs being configured to penetrate the cover insulating layer and extend into the upper electrode; as well as a plurality of wirings arranged on the upper electrode, the plurality of first wiring contact plugs, and the plurality of second wiring contact plugs, at least one wiring of the plurality of wirings being connected to the plurality of first wiring contact plugs and the plurality of second wiring contact plugs, wherein the first horizontal spacing distance is greater than the side surface thickness, the side surface thickness being the thickness of the portion of the upper electrode covering the side surface of the support pattern in the horizontal direction, and the second horizontal spacing distance is less than the side surface thickness, and The horizontal area of ​​each of the plurality of second wiring contact plugs is smaller than the horizontal area of ​​each of the plurality of first wiring contact plugs.

19. The semiconductor memory device according to claim 18, in, A vertical height of each of the plurality of second wiring contact plugs is smaller than a vertical height of each of the plurality of first wiring contact plugs, and Each of the plurality of first wiring contact plugs and each of the plurality of second wiring contact plugs are spaced apart from an upper surface of the capacitor dielectric layer by the same vertical spacing distance in a vertical direction.

20. The semiconductor memory device according to claim 18, in, In a plan view, the support pattern has a first thickness therein and a second thickness at an edge thereof that is greater than the first thickness, wherein the plurality of first wiring contact plugs are arranged on a portion of the support pattern having the first thickness, wherein the second thickness is 10 nm to 30 nm greater than the first thickness, and Wherein, the first horizontal spacing distance is 300 nm.

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