Structures including isotopically

Abstract

The invention relates to structures including isotope depleted semiconductor layers and methods of forming such structures. The structure includes a semiconductor layer including a semiconductor material having a concentration of an isotope that is less than the natural abundance of the first isotope and greater than zero per million.

Description

Technical Field

[0001] The present invention relates generally to semiconductor device and integrated circuit fabrication, and more particularly to structures including isotopically depleted semiconductor layers and methods of forming such structures. Background Art

[0002] Quantum computers built with silicon may be based on controlling the spin of charge carriers in quantum devices, known as spin qubits. Spin qubits can be characterized by a pair of spin states that provide the binary digits "0" or "1," or a superposition of "0" and "1." For example, the spin of an electron in a spin qubit may have both an up and a down spin state, and these two natural states make them attractive candidates for qubits used in quantum computing.

[0003] An isotope is any of a variety of atoms of an element that have the same atomic number and nearly identical chemical behavior, but different mass numbers and different physical properties. Natural silicon is characterized by three stable isotopes with mass numbers 28, 29, and 30. Silicon atoms with mass number 28 are the most abundant isotope and have zero nuclear spin. The less abundant silicon isotope with mass number 30 also has no spin. Neither of these two spinless silicon isotopes interacts with spin qubits. However, silicon atoms with mass number 29 have a non-integer nuclear spin of half, which has been found to degrade the performance of spin qubits. For example, the nuclear spin of silicon atoms with mass number 29 can decohere the qubit spin state and destabilize it. Therefore, reducing the concentration of silicon isotopes with mass number 29 in the channel of the qubit may be beneficial.

[0004] Improved structures including isotopically depleted semiconductor layers and methods of forming such structures are desired. Summary of the Invention

[0005] In one embodiment of the present invention, a structure includes a semiconductor layer comprising a semiconductor material having an atomic concentration of an isotope that is less than the natural abundance of the isotope and greater than zero parts per million.

[0006] In one embodiment of the present invention, a method includes forming a semiconductor layer comprising a semiconductor material having an atomic concentration of an isotope that is less than the natural abundance of the isotope and greater than zero parts per million. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with the above general description of the invention and the following detailed description of the embodiments, serve to explain these embodiments of the invention.

[0008] Figure 1 A cross-sectional view showing a structure at an initial fabrication stage of a processing method according to an embodiment of the present invention.

[0009] Figure 2 Display in Figure 1 A cross-sectional view of the structure at a later stage of fabrication.

[0010] Figure 3 Display in Figure 2 A cross-sectional view of the structure at a later stage of fabrication.

[0011] Figure 3A A cross-sectional view showing an electronic device according to an alternative embodiment of the present invention.

[0012] Figure 4 A cross-sectional view showing a structure in an initial stage of manufacture according to an alternative embodiment of the present invention.

[0013] Figure 5 Display in Figure 4 A cross-sectional view of the structure at a later stage of fabrication. DETAILED DESCRIPTION

[0014] Please refer to Figure 1 According to an embodiment of the present invention, structure 10 may be formed using a silicon-on-insulator substrate including a semiconductor layer 12, a buried insulator layer 14, and a semiconductor substrate 16. Buried insulator layer 14 may be composed of a dielectric material (e.g., silicon dioxide), which is an electrical insulator. Semiconductor substrate 16 may be composed of a semiconductor material, such as single crystal silicon. Buried insulator layer 14 is disposed between semiconductor layer 12 and semiconductor substrate 16. Buried insulator layer 14 has a lower interface interfacing with semiconductor substrate 16 and an upper interface interfacing with semiconductor layer 12.

[0015] Semiconductor layer 12 can be significantly thinner than semiconductor substrate 16. In one embodiment, semiconductor layer 12 can have a thickness T1 in a range from about 3 nanometers to about 8 nanometers. In one embodiment, semiconductor layer 12 can be thinned from an initial greater thickness to thickness T1. Semiconductor layer 12 can be composed of a single crystal semiconductor material, such as single crystal silicon, throughout thickness T1.

[0016] In one embodiment, the single crystal semiconductor material of semiconductor layer 12 may include different stable isotopes present in their respective natural abundances. For example, semiconductor layer 12 may include silicon atoms having a mass number of 28 at a natural abundance of 92.2 atomic percent, silicon atoms having a mass number of 29 at a natural abundance of 4.7 atomic percent (47,000 parts per million), and silicon atoms having a mass number of 30 at a natural abundance of 3.1 atomic percent (31,000 parts per million).

[0017] Semiconductor layer 18 may be formed on semiconductor layer 12 with a thickness T2. In one embodiment, thickness T2 of semiconductor layer 18 may be greater than thickness T1 of semiconductor layer 12. In one embodiment, semiconductor layer 18 may be deposited with a thickness T2 in a range of 50 nanometers to 150 nanometers. Semiconductor layer 18 may be composed of a single crystalline semiconductor material, such as single crystal silicon, throughout thickness T2. In one embodiment, semiconductor layer 18 may be a homoepitaxial layer composed of the same semiconductor material as semiconductor layer 12.

[0018] In one embodiment, semiconductor layer 18 may be composed of single crystal silicon depleted of silicon atoms having a mass number of 29 and a non-integer spin of one-half (1 / 2). In one embodiment, semiconductor layer 18 may be composed of single crystal silicon containing silicon atoms having a mass number of 29 at a concentration less than the natural abundance of silicon atoms having a mass number of 29 and a non-integer spin of one-half (1 / 2). In one embodiment, semiconductor layer 18 may include less than or equal to 100 parts per million of silicon atoms having a mass number of 29. In one embodiment, semiconductor layer 18 may include less than or equal to 50 parts per million of silicon atoms having a mass number of 29. Due to the depletion of silicon atoms having a mass number of 29, semiconductor layer 18 is enriched in silicon atoms having a mass number of 28 above (i.e., greater than) the natural abundance.

[0019] Semiconductor layer 18 may be formed by an epitaxial growth process. The crystal structure of the single crystalline semiconductor material of semiconductor layer 12 serves as a crystallization template during the epitaxial growth of the crystal structure of the single crystalline semiconductor material of semiconductor layer 18. Semiconductor layer 18 may be deposited by chemical vapor deposition using a silicon-containing source depleted in silicon having a mass number of 29. In one embodiment, semiconductor layer 18 may be deposited as an epitaxial coating using a silicon-containing source containing less than or equal to 1000 parts per million of silicon having a mass number of 29. In one embodiment, semiconductor layer 18 may be deposited as an epitaxial coating using a silicon-containing source containing less than or equal to 50 parts per million of silicon having a mass number of 29.

[0020] In an alternative embodiment, buried insulator layer 14 may be composed of silicon dioxide depleted below natural abundance of silicon atoms having a mass number of 29. In an alternative embodiment, semiconductor layer 18 may be deposited and recrystallized by annealing to form a single crystalline semiconductor material.

[0021] Please refer to Figure 2 , wherein similar reference numerals denote Figure 1 , and in the next manufacturing stage, an anneal is performed, which causes silicon atoms with a mass number of 29 to diffuse from the single-crystalline semiconductor material of semiconductor layer 12 to the single-crystalline semiconductor material of semiconductor layer 18, as schematically indicated by a single arrow. In one embodiment, the anneal can be performed in a hydrogen or oxygen atmosphere at a temperature of approximately 1175°C for two minutes. In one embodiment, the temperature of the anneal can range from 950°C to 1100°C. During the anneal, silicon atoms with a mass number of 29 move from a higher concentration region in semiconductor layer 12 to a lower concentration region in semiconductor layer 18 by diffusion.

[0022] The concentration of silicon atoms with a mass number of 29 initially present in thickness T1 of semiconductor layer 12 is redistributed and diluted by diffusion across the sum of thickness T1 of semiconductor layer 12 and thickness T2 of semiconductor layer 18. The concentration of silicon atoms with a mass number of 29 within composite semiconductor layers 12, 18 is less than the natural abundance of silicon atoms with a mass number of 29. In one embodiment, the concentration of silicon atoms with a mass number of 29 within composite semiconductor layers 12, 18 can be uniformly diluted to a value less than the natural abundance of silicon atoms with a mass number of 29. In one embodiment, the concentration of silicon atoms with a mass number of 29 within composite semiconductor layers 12, 18 is less than the natural abundance of silicon atoms with a mass number of 29 and greater than zero atomic percent (0 parts per million). In one embodiment, the concentration of silicon atoms with a mass number of 29 within composite semiconductor layers 12, 18 is less than the natural abundance of silicon atoms with a mass number of 29 and greater than 0.0005 atomic percent (5 parts per million). In one embodiment, the concentration of silicon atoms with a mass number of 29 in compound semiconductor layers 12, 18 is less than half the natural abundance of silicon atoms with a mass number of 29 and greater than zero atomic percent (0 parts per million). In one embodiment, the concentration of silicon atoms with a mass number of 29 in compound semiconductor layers 12, 18 is less than half the natural abundance of silicon atoms with a mass number of 29 and greater than 0.0005 atomic percent (5 parts per million). After the annealing, the single crystal silicon of compound semiconductor layers 12, 18 is enriched in silicon atoms with a mass number of 28 above (i.e., greater than) the natural abundance of silicon atoms with a mass number of 28.

[0023] After the annealing, the concentration of silicon atoms with a mass number of 29 distributed in the composite semiconductor layers 12 and 18 decreases as the thickness T2 of the semiconductor layer 18 increases. Due to the diffusion of silicon atoms with a mass number of 29 from the semiconductor layer 12 into the semiconductor layer 18, the post-annealing concentration of silicon atoms with a mass number of 29 in the semiconductor layer 18 is greater than the pre-annealing concentration of silicon atoms with a mass number of 29 in the semiconductor layer 18. Due to the diffusion of silicon atoms with a mass number of 29 from the semiconductor layer 12 into the semiconductor layer 18, the post-annealing concentration of silicon atoms with a mass number of 29 in the semiconductor layer 12 is less than the pre-annealing concentration of silicon atoms with a mass number of 29 in the semiconductor layer 12.

[0024] In an alternative embodiment, semiconductor layer 12 may initially be composed of single crystal germanium with stable isotopes present at corresponding natural abundances, and semiconductor layer 18 may be composed of single crystal germanium depleted in one or more of these stable isotopes. For example, semiconductor layer 12 may include germanium atoms with a mass number of 70 at a natural abundance of 20.6 atomic percent, germanium atoms with a mass number of 72 at a natural abundance of 27.5 atomic percent, germanium atoms with a mass number of 73 at a natural abundance of 7.8 atomic percent, germanium atoms with a mass number of 74 at a natural abundance of 36.5 atomic percent, and germanium atoms with a mass number of 76 at a natural abundance of 7.7 atomic percent. In an alternative embodiment, semiconductor layer 12 may initially include germanium atoms with a mass number of 73 having a non-integer nuclear spin of 9 / 2 at a concentration equal to the natural abundance of germanium atoms with a mass number of 73. In one embodiment, semiconductor layer 18 may include germanium depleted in germanium atoms with a mass number of 73 below the natural abundance of germanium atoms with a mass number of 73.

[0025] After the annealing, the concentration of germanium atoms with a mass number of 73 within the composite semiconductor layers 12, 18 is reduced to a value less than the natural abundance of germanium atoms with a mass number of 73. In one embodiment, the concentration of germanium atoms with a mass number of 73 within the composite semiconductor layers 12, 18 may be uniformly diluted to a value less than the natural abundance of germanium atoms with a mass number of 73. The composite semiconductor layers 12, 18 may be composed of germanium enriched in one or more stable isotopes with a mass number of zero nuclear spin that is above (i.e., greater than) the natural abundance. In one embodiment, the concentration of germanium atoms with a mass number of 73 in the composite semiconductor layers 12, 18 may be less than the natural abundance of germanium atoms with a mass number of 73 and greater than zero atomic percent (0 parts per million). In one embodiment, the concentration of germanium atoms with a mass number of 73 in the composite semiconductor layers 12, 18 may be less than the natural abundance of germanium atoms with a mass number of 73 and greater than 0.0005 atomic percent (5 parts per million). In one embodiment, the concentration of germanium atoms with a mass number of 73 in the composite semiconductor layers 12, 18 may be less than half the natural abundance of germanium atoms with a mass number of 73 and greater than zero atomic percent (0 parts per million). In one embodiment, the concentration of germanium atoms with a mass number of 73 in the composite semiconductor layers 12, 18 may be less than half the natural abundance of germanium atoms with a mass number of 73 and greater than 0.0005 atomic percent (5 parts per million).

[0026] In an alternative embodiment, semiconductor layer 12 may initially be composed of single-crystal silicon germanium containing stable isotopes of silicon and germanium in their respective natural abundances, and semiconductor layer 18 may be composed of single-crystal silicon germanium depleted in one or more of these stable isotopes. For example, prior to performing the annealing, semiconductor layer 18 may be composed of silicon germanium in which silicon atoms having a mass number of 29 are depleted to a concentration less than the natural abundance of silicon atoms having a mass number of 29, and germanium atoms having a mass number of 73 are depleted to a concentration less than the natural abundance of germanium atoms having a mass number of 73.

[0027] Please refer to Figure 3 , wherein similar reference numerals denote Figure 2, and in a next manufacturing stage, semiconductor layers 12, 18 may be thinned by oxidation, cleaning, and / or chemical mechanical polishing to provide a semiconductor layer 15 that is isotopically depleted and has a thickness T3 suitable for forming an electronic device, such as qubit device 20. In one embodiment, semiconductor layer 18 may be completely removed so that the thickness T3 of semiconductor layer 15 is less than or equal to the thickness T1 of semiconductor layer 12. In one embodiment, semiconductor layer 18 may be partially removed so that the thickness T3 of semiconductor layer 15 is greater than the thickness T1 of semiconductor layer 12. In one embodiment, the thickness T3 of semiconductor layer 15 may range from about 3 nanometers to about 8 nanometers. Semiconductor layer 15 may be composed of a single crystalline semiconductor material, such as single crystalline silicon, throughout the thickness T3.

[0028] The semiconductor layer 15 is disposed on the buried insulator layer 14, and the buried insulator layer 14 is disposed between the semiconductor layer 15 and the semiconductor substrate 16. The buried insulator layer 14 can completely separate the semiconductor layer 15 from the semiconductor substrate 16. The single crystalline semiconductor material of the semiconductor layer 15 can be disposed in direct contact with the buried insulator layer 16.

[0029] Semiconductor layer 15 may be composed of a single crystalline semiconductor material in which the concentration of an isotope with a nuclear spin of one-half (e.g., silicon with a mass number of 29) is equal to the concentration in semiconductor layers 12 and 18 and is therefore less than the natural abundance of the isotope. Semiconductor layer 15 may be composed of a single crystalline semiconductor material enriched with atoms of an isotope with a nuclear spin of zero (e.g., silicon with a mass number of 28) to provide a concentration above (i.e., greater than) the natural abundance.

[0030] In one embodiment, qubit device 20 may include a source region 22, a drain region 24, and gates 26, 28, and 30 disposed laterally between source region 22 and drain region 24. Portions of isotope-depleted semiconductor layer 15 underlying gates 26, 28, and 30 provide a channel region 31 between source region 22 and drain region 24. Source region 22, drain region 24, and channel region 31 are depleted in silicon atoms having a mass number of 29. Each gate 26, 28, and 30 of qubit device 20 may include a gate conductor layer 34 and a gate dielectric layer 32 formed in a layer stack, with gate dielectric layer 32 disposed between gate conductor layer 34 and channel region 31. In one embodiment, gate conductor layer 34 may be composed of a conductor (e.g., doped polysilicon or a work function metal), and gate dielectric layer 32 may be composed of a dielectric material (e.g., silicon dioxide or a high-k dielectric material). The gaps between gates 26, 28, and 30 may be filled with a dielectric material. Source region 22 and drain region 24 of qubit device 20 may be doped regions formed in semiconductor layer 15 by ion implantation of n-type or p-type dopants into semiconductor layer 15. Alternatively, source region 22 and drain region 24 of qubit device 20 may be doped regions of semiconductor material formed on semiconductor layer 15 by epitaxial growth and in-situ doped with n-type or p-type dopants during epitaxial growth. In an alternative embodiment, qubit device 20 may have a different configuration.

[0031] Reducing the concentration of atoms with non-integer nuclear spins in isotopically depleted semiconductor layer 15 (particularly in channel region 31) can improve the functionality of qubit device 20. For at least this reason, the functionality of a quantum computer can be improved by depleting (i.e., reducing) the concentration of isotopes with non-integer nuclear spins (e.g., a nuclear spin of half) and enriching (i.e., increasing) the concentration of isotopes with zero nuclear spin. For example, the stability of qubit device 20 can be improved by reducing decoherence of the qubit spin state that would otherwise be caused by interactions between qubit device 20 and atoms of isotopes with non-integer nuclear spins.

[0032] Please refer to Figure 3A According to alternative embodiments, active electronic devices or passive electronic devices may be formed in a portion of the single crystalline semiconductor material of semiconductor layer 15 that is different from the portion of semiconductor layer 15 used to form qubit device 20. For example, transistor 40 may be formed as an active electronic device in the portion of semiconductor layer 15 by complementary metal oxide semiconductor processing. Such field effect transistor 40 includes a source region 42, a drain region 44, and a gate 46 disposed laterally between source region 42 and drain region 44. The portion of semiconductor layer 15 underlying gate 46 and gate dielectric layer 47 provides a channel region 48 between source region 42 and drain region 44.

[0033] Please refer to Figure 4 According to an alternative embodiment, semiconductor layer 38 can be formed on the single-crystalline semiconductor material of semiconductor layer 15, followed by another annealing. In one embodiment, semiconductor layer 38 can be formed by an epitaxial growth process and have a thickness T4 in the range of 50 nanometers to 150 nanometers. Semiconductor layer 38 can be composed of a single-crystalline semiconductor material (e.g., single-crystalline silicon) that is depleted in silicon having a mass number of 29. In one embodiment, semiconductor layer 38 can be a homoepitaxial layer composed of the same semiconductor material as semiconductor layer 15.

[0034] The annealing causes silicon atoms with a mass number of 29 to diffuse from the semiconductor layer 15 into the semiconductor layer 38, as shown in FIG. Figure 4 As indicated by the single arrow in . As a result of this annealing, the concentration of silicon atoms with a mass number of 29, initially present only in thickness T1 of semiconductor layer 15, is redistributed over the sum of thickness T3 of semiconductor layer 15 and thickness T4 of semiconductor layer 38. After this annealing, the concentration of silicon atoms with a mass number of 29 within composite semiconductor layers 15, 38 is diluted to a value less than the initial concentration of silicon atoms with a mass number of 29 in semiconductor layer 15. The post-annealing concentration of silicon atoms with a mass number of 29 in composite semiconductor layers 15, 38 decreases as the thickness of semiconductor layer 38 increases. In one embodiment, the concentration of silicon atoms with a mass number of 29 in semiconductor layers 15, 38 is less than the natural abundance of silicon atoms with a mass number of 29 and greater than 0.0005 (5 parts per million). The post-annealing concentration of silicon atoms with a mass number of 28 in composite semiconductor layers 15, 38 is greater than the natural abundance of silicon atoms with a mass number of 28.

[0035] In one embodiment, additional iterations of forming an epitaxial semiconductor layer depleted of silicon atoms having a mass number of 29, annealing, and thinning may be performed. Each iteration beyond the initial iteration may further reduce the concentration of silicon atoms having a mass number of 29 so that the final concentration of silicon atoms having a mass number of 29 approaches the concentration of the precursors used in the deposition of semiconductor layer 18 or in the deposition of semiconductor layer 38.

[0036] Please refer to Figure 5 , wherein similar reference numerals denote Figure 4, and in a next manufacturing stage, semiconductor layers 15, 38 may be thinned to provide semiconductor layer 35 that is isotopically depleted and has a thickness T5 suitable for forming an electronic device, such as qubit device 20. Semiconductor layer 35 may be composed of a single crystalline semiconductor material, such as single crystalline silicon, throughout thickness T5. In one embodiment, semiconductor layer 38 may be completely removed so that thickness T5 of semiconductor layer 35 is less than or equal to thickness T3 of semiconductor layer 15. In one embodiment, semiconductor layer 38 may be partially removed so that thickness T5 of semiconductor layer 35 is greater than thickness T3 of semiconductor layer 15. In one embodiment, thickness T5 of semiconductor layer 35 may range from about 3 nanometers to about 8 nanometers. The concentration of silicon atoms with mass number 29 in thinned semiconductor layer 35 is equal to the concentration in semiconductor layers 15, 38. Semiconductor layer 35 may be composed of silicon that is enriched above (i.e., greater than) the natural abundance of silicon atoms with mass number 28.

[0037] The method described above is used to manufacture integrated circuit chips. Manufacturers can distribute the resulting integrated circuit chips in raw wafer form (e.g., as a single wafer containing multiple unpackaged chips), as bare die, or in a packaged form. The chips can be integrated with other chips, discrete circuit components, and / or other signal processing devices as part of an intermediate product or a final product. The final product can be any product that includes an integrated circuit chip, such as a computer product or a smartphone with a central processing unit.

[0038] Terms modified by approximating language such as "about," "approximately," and "substantially" as used herein are not limited to the precise values ​​specified. The approximate language may correspond to the precision of the instrument used to measure the value and may represent + / - 10% of the stated value unless otherwise dependent on the precision of the instrument.

[0039] Terms such as "vertical" and "horizontal" are used herein as examples to establish a frame of reference and are not limiting. As used herein, the term "horizontal" is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional orientation. The terms "vertical" and "orthogonal" refer to directions perpendicular to the horizontal plane as just defined. The term "lateral" refers to a direction within the horizontal plane.

[0040] A feature that is “connected” or “coupled” to another feature may be directly connected or coupled to the other feature, or one or more intervening features may be present. A feature may be “directly connected” or “directly coupled” to another feature if no intervening features are present. A feature may be “indirectly connected” or “indirectly coupled” to another feature if at least one intervening feature is present. A feature that is “on” or “in contact with” another feature may be directly on or in direct contact with the other feature, or one or more intervening features may be present. A feature may be directly “on” or “in direct contact with” another feature if no intervening features are present. A feature may be “not directly” “on” or “not directly in contact with” another feature if at least one intervening feature is present. Different features may “overlap” if one feature extends over and covers a portion of another feature, whether in direct contact or not.

[0041] The description of various embodiments of the present invention is for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially known technologies, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A structure characterized in that: include: A semiconductor layer includes a semiconductor material having a first atomic concentration of a first isotope, the first atomic concentration in the semiconductor material being less than a natural abundance of the first isotope and greater than zero parts per million.

2. The structure according to claim 1, characterized in that The first isotope has a non-integer nuclear spin.

3. The structure according to claim 1, wherein The semiconductor material is silicon, and the first isotope has a mass number of 29.

4. The structure according to claim 1, wherein The semiconductor material is germanium, and the first isotope has a mass number of 73.

5. The structure according to claim 1, wherein: The semiconductor material has a second atomic concentration of a second isotope that is less than the natural abundance of the second isotope and greater than zero parts per million.

6. The structure according to claim 5, characterized in that The semiconductor material is silicon germanium.

7. The structure according to claim 6, characterized in that The first isotope has a mass number of 29, and the second isotope has a mass number of 73.

8. The structure according to claim 5, wherein: The first isotope has a non-integer nuclear spin, and the second isotope has a non-integer nuclear spin.

9. The structure according to claim 8, characterized in that The semiconductor material has a third isotope at a third atomic concentration that is greater than a natural abundance of the third isotope, and the third isotope has zero nuclear spin.

10. The structure according to claim 1, wherein The semiconductor material has a second atomic concentration of a second isotope that is greater than the natural abundance of the second isotope, and the second isotope has zero nuclear spin.

11. The structure according to claim 1, wherein Also includes: A field effect transistor has a channel region located in the semiconductor layer.

12. The structure according to claim 1, wherein Also includes: A quantum bit device has a channel region located in the semiconductor layer.

13. The structure according to claim 1, wherein The semiconductor material of the semiconductor layer is a single crystal semiconductor material.

14. The structure according to claim 1, wherein Also includes: burying an insulator layer; as well as semiconductor substrates, The buried insulator layer is disposed between the semiconductor substrate and the buried insulator layer.

15. The structure according to claim 14, wherein The semiconductor layer has a thickness in a range from about 3 nanometers to about 8 nanometers, and the semiconductor material of the semiconductor layer is a single crystalline semiconductor material.

16. A method, characterized in that include: forming a first semiconductor layer comprising a semiconductor material having a first atomic concentration of a first isotope, The first atomic concentration in the semiconductor material is less than the natural abundance of the first isotope and greater than zero parts per million.

17. The method according to claim 16, wherein Forming the first semiconductor layer comprising the semiconductor material having the first isotope having the first atomic concentration comprises: forming a second semiconductor layer on the third semiconductor layer, The second semiconductor layer has a second atomic concentration of the first isotope of the semiconductor material that is less than the natural abundance, and the third semiconductor layer has a third atomic concentration of the first isotope of the semiconductor material that is equal to the natural abundance.

18. The method according to claim 17, wherein The second semiconductor layer is thicker than the third semiconductor layer.

19. The method according to claim 17, wherein Forming the first semiconductor layer comprising the semiconductor material having the first isotope having the first atomic concentration further comprises: The second semiconductor layer and the third semiconductor layer are annealed.

20. The method according to claim 19, wherein Forming the first semiconductor layer comprising the semiconductor material having the first isotope having the first atomic concentration further comprises: The second semiconductor layer and the third semiconductor layer are thinned to form the first semiconductor layer.

21. The method according to claim 16, wherein Also includes: A qubit device is formed having a channel in the first portion of the first semiconductor layer.

22. The method according to claim 21, wherein Also includes: An active electronic device or a passive electronic device is formed in the second portion of the first semiconductor layer.

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