Integrated chip and forming method thereof

Abstract

Various embodiments of the present application are directed to an integrated chip (IC) including a lower dielectric structure over a semiconductor substrate. The gate structure is over the lower dielectric structure. The gate structure includes a first surface opposite the second surface. The first semiconductor layer is disposed between the first surface of the gate structure and the lower dielectric structure. The second semiconductor layer is over the second surface of the gate structure. The embodiment of the invention also relates to an integrated chip and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to an integrated chip and a method for forming the same. Background Art

[0002] The integrated chip (IC) manufacturing industry has experienced exponential growth over the past several decades. As ICs have evolved, the size of semiconductor devices (e.g., the area of ​​a transistor) has shrunk by, for example, reducing the minimum component size and / or reducing the lateral spacing between adjacent semiconductor devices, which has increased device density (e.g., the number of semiconductor devices integrated in a given area). However, as the lateral spacing between adjacent semiconductor devices continues to decrease, it has become increasingly difficult to increase device density without adversely affecting the performance of the semiconductor devices. Therefore, advancements in the IC manufacturing industry that increase device density without adversely affecting the device performance of the semiconductor devices are desired. Summary of the Invention

[0003] Some embodiments of the present application provide an integrated chip, comprising: a lower dielectric structure located above a semiconductor substrate; a gate structure located above the lower dielectric structure, wherein the gate structure includes a first surface opposite to a second surface; a first semiconductor layer arranged between the first surface of the gate structure and the lower dielectric structure; and a second semiconductor layer located above the second surface of the gate structure.

[0004] Other embodiments of the present application provide an integrated chip, comprising: a lower interconnect structure located above a semiconductor substrate; a first semiconductor device located above the lower interconnect structure, wherein the first semiconductor device comprises a first source / drain structure pair located above the lower interconnect structure, a first semiconductor layer located above the first source / drain structure pair, and a first gate dielectric layer located above the first semiconductor layer; a gate electrode located above the first gate dielectric layer; and a second semiconductor device located above the first semiconductor device, wherein the second semiconductor device comprises a second gate dielectric layer above the gate electrode, a second semiconductor layer above the second gate dielectric layer, and a second source / drain structure pair above the second semiconductor layer.

[0005] Still other embodiments of the present application provide a method for forming an integrated chip, comprising: forming a lower interconnect structure above a semiconductor substrate; forming a first source / drain structure pair above the lower interconnect structure; depositing a first semiconductor layer above the first source / drain structure pair; depositing a first gate dielectric layer above the first semiconductor layer; forming a gate electrode on the first gate dielectric layer; forming a second gate dielectric layer above the gate electrode; forming a second semiconductor layer above the second gate dielectric layer; and forming a second source / drain structure pair above the second semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the disclosed embodiments will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 Cross-sectional views of some embodiments of integrated chips (ICs) having electronic devices including transistors stacked vertically on top of each other above a semiconductor substrate are shown.

[0008] Figure 2 Shown Figure 1 Cross-sectional views of some other embodiments of ICs.

[0009] Figures 3A to 3H Shown Figure 1 Cross-sectional views of some other embodiments of ICs.

[0010] Figures 4A to 4B Shown Figure 1 Cross-sectional views of some other embodiments of ICs.

[0011] Figures 5A to 5B Various cross-sectional views of some embodiments of an IC having an electronic device including transistors vertically stacked with each other in a first region of a semiconductor substrate and laterally adjacent to a second region of the semiconductor substrate are illustrated.

[0012] Figures 5C to 5D Shown along Figure 5A The line A-A' intercepts Figure 5A Various layout diagrams of some embodiments of an IC.

[0013] Figures 6 to 16 Various cross-sectional views of some embodiments of a first method for forming an IC having electronic devices including transistors stacked vertically on each other are shown.

[0014] Figures 17 to 26Various cross-sectional views of some embodiments of a second method for forming an IC having electronic devices including transistors stacked vertically on each other are shown.

[0015] Figures 27 to 38 Various cross-sectional views of some embodiments of a third method for forming an IC having electronic devices including transistors stacked vertically on each other are shown.

[0016] Figure 39 A flow chart illustrating some embodiments of a method for forming an IC having electronic devices including transistors stacked vertically on each other is shown. DETAILED DESCRIPTION

[0017] The present disclosure provides many different embodiments or examples for implementing the different features of the embodiments of the present disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the embodiments of the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another (or more) elements or components as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0019] An integrated chip (IC) may include an electronic device. The electronic device may be, for example, an inverter, a latch, a logic gate, a static random access memory (SRAM), a dynamic random access memory (DRAM), or some other suitable device. The electronic device includes a plurality of semiconductor devices. The plurality of semiconductor devices may be or include one or more n-channel transistors and one or more p-channel transistors electrically coupled in a predetermined manner to form the electronic device. Typically, the transistors of the electronic device are disposed in a front-end-of-line (FEOL) structure on / in a substrate and are formed during the FEOL process.

[0020] To increase device density above a substrate, transistors of an electronic device can be disposed in a back-end-of-line (BEOL) structure above the substrate. For example, the electronic device includes a first gate electrode and a second gate electrode in a dielectric layer above the substrate, wherein the first gate electrode and the second gate electrode are located above one or more conductive interconnect structures. A gate dielectric layer is located above the first gate electrode and the second gate electrode. An n-type semiconductor layer is disposed on the gate dielectric layer above the first gate electrode, and a p-type semiconductor layer is disposed on the gate dielectric layer above the second gate electrode. A first source / drain structure pair is disposed on the n-type semiconductor layer, and a second source / drain structure pair is disposed on the p-type semiconductor layer. The first gate electrode, the n-type semiconductor layer, the first segment of the gate dielectric layer, and the first source / drain structure pair define an n-channel transistor. The second gate electrode, the p-type semiconductor layer, the second segment of the gate dielectric layer, and the second source / drain structure pair define a p-channel transistor. The n-channel transistor is directly laterally adjacent to the p-channel transistor.

[0021] Forming n-channel transistors and p-channel transistors laterally adjacent to each other in a BEOL structure may present challenges. For example, forming a p-type semiconductor layer may include performing a deposition process and / or a doping process at a relatively high temperature (e.g., at a temperature greater than 400 degrees Celsius) that may damage the underlying conductive interconnect structure, the underlying FEOL device / structure, and / or other devices arranged in the BEOL structure (e.g., capacitors, memory devices, etc.). As a result, the yield and / or reliability of the IC may be reduced. In addition, in order to reduce the lateral footprint of the electronic device and increase the device density, the lateral distance between the p-type semiconductor layer and the n-type semiconductor layer is relatively small. However, one or more elements in the p-type semiconductor layer may be easily diffused or transferred to the n-type semiconductor layer due to the relatively small lateral distance and / or due to interaction with the dielectric material between the n-type and p-type semiconductor layers. This may reduce the performance of the n-channel transistor and / or the p-channel transistor (e.g., reducing carrier mobility, changing the threshold voltage, etc.), thereby reducing the overall performance of the electronic device.

[0022] Various embodiments of the present application are directed to an integrated chip (IC) including an electronic device (e.g., an inverter) having transistors stacked vertically above a substrate to increase device density and the overall performance of the electronic device. The transistor of the electronic device includes an n-channel transistor and a p-channel transistor above one or more conductive interconnect structures above the substrate. The p-channel transistor includes a first source / drain structure pair above the one or more conductive interconnect structures, a first semiconductor layer on the first source / drain structure pair, and a first gate dielectric layer above the first semiconductor layer. The gate electrode is located above the first gate dielectric layer. In addition, the n-channel transistor includes a second gate dielectric layer above the gate electrode, a second semiconductor layer on the second gate dielectric layer, and a second source / drain structure pair on the second semiconductor layer. The gate electrode is shared by the p-channel and n-channel transistors.

[0023] Because the n-channel transistor is stacked vertically above the p-channel transistor, the lateral footprint of the electronic device is reduced, thereby increasing the device density of the IC. In addition, the first semiconductor layer of the p-channel transistor is vertically offset by a relatively large distance relative to the n-channel transistor. Therefore, the diffusion of one or more elements from the first semiconductor layer to the second semiconductor layer is prevented or reduced. In addition, the dielectric materials of the first dielectric layer and the second dielectric layer can be different from each other and selected to optimize the performance of the p-channel and n-channel transistors. Therefore, the electronic device including the n-channel transistor stacked vertically above the p-channel transistor improves the performance and reliability of the electronic device and the device density of the IC.

[0024] Figure 1 A cross-sectional view 100 of some embodiments of an integrated chip (IC) having an electronic device 130 including transistors 131a-131b stacked vertically on each other is shown.

[0025] The IC includes a front-end of the line (FEOL) structure 104 disposed in and / or on a semiconductor substrate 102 and a back-end of the line (BEOL) structure 106 above the FEOL structure 104. The semiconductor substrate 102 may be, for example, or include, a bulk substrate (e.g., bulk silicon), single crystal silicon, silicon germanium (SiGe), silicon on insulator (SOI), etc. The FEOL structure 104 includes one or more lower semiconductor devices 108 on the semiconductor substrate 102, an interlayer dielectric (ILD) layer 124 above the semiconductor substrate 102, and one or more conductive contacts 118 in the ILD layer 124.

[0026] In some embodiments, the one or more lower semiconductor devices 108 are each configured as a transistor, such as a metal oxide semiconductor field effect transistor (MOSFET), a fin FET (FinFET), a gate all around FET (GAAFET), etc. In various embodiments, the one or more lower semiconductor devices 108 each include a source / drain region pair 110 located in the semiconductor substrate 102, a lower gate electrode 114 located above the semiconductor substrate 102 and laterally between the source / drain region pair 110, a lower gate dielectric 112 located between the lower gate electrode 114 and the semiconductor substrate 102, and sidewall spacers 116 disposed on sidewalls of the lower gate electrode 114 and the lower gate dielectric 112. The source / drain region can refer to a source or a drain, either individually or collectively depending on the context. The semiconductor substrate 102 can have a first doping type (e.g., p-type). In some embodiments, the source / drain region pair 110 is a doped region of the semiconductor substrate 102 having a second doping type (e.g., n-type) opposite to the first doping type. In various embodiments, the first doping type is p-type and the second doping type is n-type, or vice versa. One or more conductive contacts 118 are located above the semiconductor substrate 102 and are electrically coupled to the one or more lower semiconductor devices 108 .

[0027] The BEOL structure 106 is located above the semiconductor substrate 102 and includes a lower dielectric structure 126, a plurality of dielectric layers 128a-128d, a plurality of conductive lines 120, and a plurality of conductive vias 122. The plurality of conductive lines 120 and the plurality of conductive vias 122 are configured to electrically couple the electronic device 130 to other semiconductor devices (e.g., one or more lower semiconductor devices 108 and / or devices on another IC). The plurality of dielectric layers 128a-128d includes a first dielectric layer 128a above the lower dielectric structure 126, a second dielectric layer 128b above the first dielectric layer 128a, a third dielectric layer 128c above the second dielectric layer 128b, and a fourth dielectric layer 128d above the third dielectric layer 128c.

[0028] The electronic device 130 is disposed in the BEOL structure 106 and is directly located above at least a portion of an independent lower semiconductor device in the one or more lower semiconductor devices 108. The electronic device 130 includes a plurality of transistors 131a-131b stacked vertically on each other. The electronic device 130 may, for example, be or include an inverter. In further embodiments, the electronic device 130 may, for example, be or include a logic gate, a latch, an SRAM cell, some other suitable device, or a combination thereof. In some embodiments, the plurality of transistors 131a-131b include a p-channel transistor 131a and an n-channel transistor 131b located above the p-channel transistor 131a. The p-channel transistor 131a and the n-channel transistor 131b may be referred to as semiconductor devices. In various embodiments, the p-channel transistor 131a and the n-channel transistor 131b are each configured as an oxide semiconductor (OS) transistor, a thin film transistor (TFT), or the like.

[0029] P-channel transistor 131a includes a first source / drain structure pair 132, 134 disposed in second dielectric layer 128b, a first semiconductor layer 144 atop first source / drain structure pair 132, 134, and a first gate dielectric layer 148 atop first semiconductor layer 144. A source / drain structure may be referred to as a source or a drain, either individually or collectively, depending on the context. A gate electrode 136 is disposed in third dielectric layer 128c and atop first gate dielectric layer 148. N-channel transistor 131b includes a second gate dielectric layer 150 atop gate electrode 136, a second semiconductor layer 146 atop second gate dielectric layer 150, and a second source / drain structure pair 140, 142 disposed in fourth dielectric layer 128d and atop second semiconductor layer 146. In addition, a conductive source / drain via 138 extends between the first source / drain structure 132 in the first source / drain structure pair 132, 134 to the first source / drain structure 140 in the second source / drain structure pair 140, 142. The gate electrode 136 is shared by the p-channel transistor 131a and the n-channel transistor 131b. In some embodiments, the first semiconductor layer 144 includes a first conductivity type (e.g., p-type) and the second semiconductor layer 146 includes a second conductivity type (e.g., n-type) that is opposite to the first conductivity type. It should be understood that although in various embodiments of the present disclosure, the n-channel transistor 131b is located above the p-channel transistor 131a, in some embodiments, the vertical stack can be flipped so that the p-channel transistor 131a is located above the n-channel transistor 131b (e.g., as in FIG. 2 ). Figure 3H ).

[0030] The electronic device 130 includes a gate structure 151, which includes a gate electrode 136, a first gate dielectric layer 148, and a second gate dielectric layer 150. The gate structure 151 has a first surface facing the semiconductor substrate 102 and a second surface facing the second source / drain structure pair 140, 142. The first semiconductor layer 144 extends along the first surface of the gate structure 151, and the second semiconductor layer 146 extends along the second surface of the gate structure 151. In various embodiments, during operation of the electronic device 130, a first selective conductive channel may be formed in the first semiconductor layer 144 of the p-channel transistor 131a between the first source / drain structure pair 132, 134. Additionally, a second selective conductive channel may be formed in the second semiconductor layer 146 of the n-channel transistor 131b between the second source / drain structure pair 140, 142.

[0031] Because n-channel transistor 131b is vertically stacked above p-channel transistor 131a, the lateral footprint of electronic device 130 is reduced, thereby increasing the device density of the IC. Furthermore, vertically stacking p-channel transistor 131a and n-channel transistor 131b facilitates offsetting first semiconductor layer 144 relative to second semiconductor layer 146 by a relatively large distance, compared to an embodiment in which baseline p-channel and n-channel transistors are spaced directly adjacent to each other laterally on the same plane (not shown). Consequently, diffusion of one or more elements from first semiconductor layer 144 to second semiconductor layer 146 is mitigated or prevented, thereby improving the performance of p-channel transistor 131a and n-channel transistor 131b. Consequently, electronic device 130 including p-channel transistor 131a vertically stacked with n-channel transistor 131b improves the overall performance and device density of the IC.

[0032] The first semiconductor layer 144 includes a first metal oxide compound having a first conductivity type (eg, p-type). In some embodiments, the first semiconductor layer 144 includes Cu X Ni Y Sn Z NO compounds (wherein X is in the range of 0 to 1, Y is in the range of 0 to 1, and Z is in the range of 0 to 1), Cu X Ni Y Sn Z O compound (wherein X is in the range of 0 to 1, Y is in the range of 0 to 1, and Z is in the range of 0 to 1) or some other suitable material. In various embodiments, Cu is copper; Ni is nickel; Sn is tin; O is oxygen; and N is tellurium (Te), antimony (Sb), magnesium (Mg), boron (B), aluminum (Al), gallium (Ga), or iron (Fe). In some embodiments, the first semiconductor layer 144 includes a single layer (including Cu X Ni Y SnZ NO compound) or include a multilayer stack. In various embodiments, the layers in the multilayer stack include Cu X Ni Y Sn Z Different forms of NO compounds (e.g., each layer includes Cu X Ni Y Sn Z Different elements and / or Cu in NO compounds X Ni Y Sn Z NO compound). For example, the first semiconductor layer 144 can be or include a CuO layer stacked with a NiO layer, a SnO layer stacked with a metal-doped SnO layer, a Cu-rich CuNiO layer stacked with a Cu-poor NiO layer, some other suitable layer stack, etc. The first metal oxide of the first semiconductor layer 144 can be a binary compound, a ternary compound, a quaternary compound, a quinary compound, etc. In further embodiments, the first semiconductor layer 144 includes 1 to 10 metal oxide layers. In further embodiments, the thickness of the first semiconductor layer 144 is in the range of about 3 to 10 nanometers (nm) or some other suitable value. In various embodiments, the mobility of the charge carriers in the first semiconductor layer 144 is equal to or greater than 6 square centimeters per volt-second (cm 2 / Vs).

[0033] In various embodiments, the first semiconductor layer 144 directly contacts the top surfaces of the first source / drain structure pair 132, 134. In further embodiments, the first semiconductor layer 144 directly contacts the opposite sidewalls of the conductive source / drain via 138 and the bottom surface of the first gate dielectric layer 148. The first gate dielectric layer 148 can be, for example, or include aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium zirconium oxide, hafnium lanthanum oxide, hafnium oxide silicate, hafnium titanium oxide, some other suitable dielectric material, or any combination thereof. In various embodiments, the first gate dielectric layer 148 has a dielectric constant greater than 9. In further embodiments, the first gate dielectric layer 148 can be, for example, or include a ferroelectric material (e.g., lead zirconate titanate, barium titanate, etc.), an antiferroelectric material (e.g., lead zirconate, lead hafnium oxide, etc.), or the like. In some embodiments, the first gate dielectric layer 148, which includes a ferroelectric material, facilitates configuring the p-channel transistor 131a as a capacitor-less ferroelectric transistor. The thickness of the first gate dielectric layer 148 is, for example, in the range of 1 to 20 nm or some other suitable value. In various embodiments, the thickness of the first gate dielectric layer 148 is greater than the thickness of the first semiconductor layer 144.

[0034] The second semiconductor layer 146 includes a second metal oxide compound having a second conductivity type (eg, n-type). In various embodiments, the first metal oxide compound of the first semiconductor layer 144 is different from the second metal oxide compound of the second semiconductor layer 146. In some embodiments, the second semiconductor layer 146 includes In X Ga Y Zn Z MO compounds (wherein X is in the range of 0 to 1, Y is in the range of 0 to 1, and Z is in the range of 0 to 1), In X Ga Y Zn Z O compound (wherein X is in the range of 0 to 1, Y is in the range of 0 to 1, and Z is in the range of 0 to 1) or some other suitable material. In various embodiments, In is indium; Ga is gallium; Zn is zinc; O is oxygen; M is titanium (Ti), aluminum (Al), silver (Ag), tungsten (W), cerium (Ce), tin (Sn), vanadium (V), or scandium (Sc). In some embodiments, the second semiconductor layer 146 includes a single layer (including In X Ga Y Zn Z In various embodiments, the layers in the multilayer stack include In X Ga Y Zn Z Different forms of MO compounds (e.g., each layer includes In X Ga Y Zn Z Different elements and / or In in MO compounds X Ga Y Zn Z MO compound). For example, the second semiconductor layer 146 can be or include a GaZnO layer stacked with an InZnO layer, an In1Ga3Zn2O layer (e.g., which is Ga-rich) stacked with an InGaZnO layer (e.g., which is Ga-poor), an InGaZnO layer stacked with a Sn-doped InGaZnO layer, some other suitable layer stack, etc. The second metal oxide of the second semiconductor layer 146 can be a binary compound, a ternary compound, a quaternary compound, a quinary compound, etc. In further embodiments, the second semiconductor layer 146 includes 1 to 10 metal oxide layers. In still further embodiments, the thickness of the second semiconductor layer 146 is in the range of about 3 to 10 nm or some other suitable value. In various embodiments, the mobility of charge carriers in the second semiconductor layer 146 is equal to or greater than 6 cm 2 / Vs. In further embodiments, the first semiconductor layer 144 and the second semiconductor layer 146 each have an amorphous phase (e.g., at least partially amorphous and / or lacking the long-range order found in a crystalline phase), a short-range ordered phase (e.g., having an organization or regularity in the arrangement of atoms or molecules at intervals of a few atoms or molecules), etc. In such embodiments, the first semiconductor layer 144 and the second semiconductor layer 146 having the amorphous phase or the short-range ordered phase reduces damage to the first semiconductor layer 144 and the second semiconductor layer 146 during the thermal annealing process, while reducing device leakage and / or performance degradation in the transistors 131a-131b.

[0035] In some embodiments, the second semiconductor layer 146 directly contacts the bottom surface of the second source / drain structure pair 140, 142. In further embodiments, the second semiconductor layer 146 directly contacts the opposite sidewalls of the conductive source / drain via 138 and the top surface of the second gate dielectric layer 150. The second gate dielectric layer 150 can be, for example, or include Al2O3, HfO2, ZrO2, hafnium zirconium oxide, hafnium lanthanum oxide, hafnium oxide silicate, hafnium titanium oxide, some other suitable dielectric material, or any combination thereof. In various embodiments, the second gate dielectric layer 150 has a dielectric constant greater than 9. In further embodiments, the second gate dielectric layer 150 can be, for example, or include a ferroelectric material (e.g., lead zirconate titanate, barium titanate, etc.), an antiferroelectric material (e.g., lead zirconate, lead hafnium oxide, etc.), or the like. In some embodiments, the second gate dielectric layer 150 comprising a ferroelectric material facilitates configuring the n-channel transistor 131b as a capacitor-less ferroelectric transistor. The thickness of the second gate dielectric layer 150 is, for example, in the range of 1 to 20 nm or some other suitable value. In various embodiments, the thickness of the second gate dielectric layer 150 is greater than the thickness of the second semiconductor layer 146. In further embodiments, the first gate dielectric layer 148 comprises a first material, and the second gate dielectric layer 150 comprises a second material different from the first material.

[0036] The ILD layer 124, the lower dielectric structure 126, and the plurality of dielectric layers 128a-128d can each be, for example, or include an oxide (e.g., silicon dioxide), a low-k dielectric material, undoped silicate glass, undoped silicon dioxide, some other suitable dielectric, or any combination thereof. As used herein, a low-k dielectric material is a dielectric material having a dielectric constant less than 3.9. In various embodiments, the first source / drain structure pair 132, 134, the conductive source / drain via 138, the gate electrode 136, and the second source / drain structure pair 140, 142 can each be, for example, or include tantalum nitride, tantalum, titanium, titanium nitride, tungsten, molybdenum, ruthenium, copper, some other conductive material, or any combination thereof. In some embodiments, the height of the first source / drain structure pair 132, 134, the gate electrode 136, and the second source / drain structure pair 140, 142 can each be, for example, or include tantalum nitride, tantalum, titanium, titanium nitride, tungsten, molybdenum, ruthenium, copper, some other conductive material, or any combination thereof. In some embodiments, the height of each of the first source / drain structure pair 132, 134, the gate electrode 136, and the second source / drain structure pair 140, 142 is in the range of approximately 5 to 50 nm, or some other suitable value. In various embodiments, the height of the gate electrode 136 is greater than a first sum of the thicknesses of the first semiconductor layer 144 and the first gate dielectric layer 148, and greater than a second sum of the thicknesses of the second semiconductor layer 146 and the second gate dielectric layer 150. In further embodiments, the width of the gate electrode 136 is greater than the width of an individual source / drain structure in the first source / drain structure pair 132, 134 or in the second source / drain structure pair 140, 142.

[0037] In various embodiments, the distance between the first semiconductor layer 144 and the second semiconductor layer 146 is relatively large (e.g., greater than the height of the gate electrode 136). Therefore, diffusion of one or more elements from the first semiconductor layer 144 to the second semiconductor layer 146 is reduced, thereby improving the performance of the transistors 131a-131b.

[0038] Figure 2 Shown Figure 1 200 is a cross-sectional view of some other embodiments of an IC.

[0039] In some embodiments, the conductive source / drain via 138 includes a lower via segment 138 a and an upper via segment 138 b located above the lower via segment 138 a. The upper via segment 138 b directly contacts the lower via segment 138 a. The lower via segment 138 a extends through the third dielectric layer 128 c, the first gate dielectric layer 148, and the first semiconductor layer 144. In various embodiments, the top surface of the lower via segment 138 a is coplanar with the top surface of the third dielectric layer 128 c and the top surface of the gate electrode 136. The upper via segment 138 b extends through the second gate dielectric layer 150 and the second semiconductor layer 146. In some embodiments, the top surface of the upper via segment 138 b is coplanar with the top surface of the second semiconductor layer 146. The conductive source / drain via 138 electrically couples the first source / drain structure 132 of the first pair of source / drain structures 132 , 134 directly to the first source / drain structure 140 of the second pair of source / drain structures 140 , 142 .

[0040] In some embodiments, the electronic device 130 is configured as an inverter. The gate electrode 136 is electrically coupled to an input voltage node configured to receive an input voltage Vin. In various embodiments, the gate electrode 136 is electrically coupled to a conductive via (not shown) in a position laterally offset relative to the electronic device 130. The first source / drain structure 132 of the first source / drain structure pair 132, 134 and the first source / drain structure 140 of the second source / drain structure pair 140, 142 are electrically coupled to an output voltage node. The second source / drain structure 134 of the first source / drain structure pair 132, 134 is electrically coupled to a first supply voltage node (e.g., Vdd), which can be coupled to a supply voltage of approximately 1.8 volts (V), 3.3 V, 5 V, a voltage in the range of approximately 1.8 to 15 V, or some other suitable value. The second source / drain structure 142 of the pair of second source / drain structures 140 and 142 is electrically coupled to a reference voltage node (e.g., Vss), which can be ground (e.g., 0 V) ​​or some other suitable value. In some embodiments, the individual source / drain regions of the source / drain region pair 110 of the semiconductor devices in the one or more lower semiconductor devices 108 are electrically coupled directly to the gate electrode 136.

[0041] Figure 3A Shown Figure 1 300a is a cross-sectional view of some other embodiments of an IC.

[0042] In some embodiments, the outer sidewalls of the first semiconductor layer 144 are spaced apart between the first source / drain structure pair 132, 134. The first outer sidewall of the first semiconductor layer 144 is directly above the first source / drain structure 132 of the first source / drain structure pair 132, 134, and the second outer sidewall of the first semiconductor layer 144 is directly above the second source / drain structure 134 of the first source / drain structure pair 132, 134. Furthermore, the first semiconductor layer 144 can be laterally offset by a non-zero distance relative to the conductive source / drain via 138. In such embodiments, this can reduce damage to the first semiconductor layer 144 during the formation of the conductive source / drain via 138 (e.g., damage from the etching process used to form the opening for the conductive source / drain via 138). In various embodiments, the first gate dielectric layer 148 directly contacts the outer sidewalls and top surface of the first semiconductor layer 144. The bottom surface of the first gate dielectric layer 148 can be aligned with the bottom surface of the first semiconductor layer 144. In some embodiments, spacing the outer sidewalls of the first semiconductor layer 144 between the first source / drain structure pair 132 , 134 increases isolation between the p-channel transistor 131 a and other transistors (not shown) disposed in the BEOL structure 106 at the same level as the p-channel transistor 131 a .

[0043] In some embodiments, the outer sidewalls of the second semiconductor layer 146 are spaced apart between the second source / drain structure pair 140, 142. A first outer sidewall of the second semiconductor layer 146 is directly beneath the first source / drain structure 140 of the second source / drain structure pair 140, 142, and a second outer sidewall of the second semiconductor layer 146 is directly beneath the second source / drain structure 142 of the second source / drain structure pair 140, 142. The second semiconductor layer 146 can be laterally offset by a non-zero distance relative to the conductive source / drain via 138. In such embodiments, this can reduce damage to the second semiconductor layer 146 during the formation of the conductive source / drain via 138 (e.g., damage from the etching process used to form the opening for the conductive source / drain via 138). In various embodiments, the fourth dielectric layer 128d directly contacts the outer sidewalls and top surface of the second semiconductor layer 146. The bottom surface of the fourth dielectric layer 128d can be aligned with the bottom surface of the second semiconductor layer 146. In some embodiments, spacing the outer sidewalls of the second semiconductor layer 146 between the second source / drain structure pair 140 , 142 increases isolation between the n-channel transistor 131 b and other transistors (not shown) disposed in the BEOL structure 106 at the same level as the n-channel transistor 131 b .

[0044] The bottom surface of the first gate dielectric layer 148 directly contacts portions of the top surface of the first source / drain structure 132 of the first source / drain structure pair 132, 134 and portions of the top surface of the second source / drain structure 134 of the first source / drain structure pair 132, 134. The fourth dielectric layer 128d directly contacts portions of the bottom surface of the first source / drain structure 140 of the second source / drain structure pair 140, 142 and portions of the bottom surface of the second source / drain structure 142 of the second source / drain structure pair 140, 142. In various embodiments, the thickness of the first gate dielectric layer 148 is greater than the thickness of the second gate dielectric layer 150. In further embodiments, the thickness of the second gate dielectric layer 150 is greater than the thickness of the first semiconductor layer 144 and the thickness of the second semiconductor layer 146. In still further embodiments, the centers of the first semiconductor layer 144 and the second semiconductor layer 146 are aligned with the center of the gate electrode 136.

[0045] Figure 3B Shown Figure 1 300b is a cross-sectional view of some other embodiments of an IC.

[0046] In some embodiments, a first outer sidewall of the first semiconductor layer 144 is aligned with an outer edge and / or outer sidewall of the first source / drain structure 132 in the first source / drain structure pair 132, 134. A second outer sidewall of the first semiconductor layer 144 is aligned with an outer edge and / or outer sidewall of the second source / drain structure 134 in the first source / drain structure pair 132, 134. Furthermore, a first outer sidewall of the second semiconductor layer 146 is aligned with an outer edge and / or outer sidewall of the first source / drain structure 140 in the second source / drain structure pair 140, 142. A second outer sidewall of the second semiconductor layer 146 is aligned with an outer edge and / or outer sidewall of the second source / drain structure 142 in the second source / drain structure pair 140, 142.

[0047] Figure 3C Shown Figure 3A FIG. 3 is a cross-sectional view 300 c of some other embodiments of an IC, wherein an intermediate dielectric layer 302 is disposed around outer sidewalls of the first semiconductor layer 144 .

[0048] In some embodiments, an interlayer dielectric layer 302 is disposed between the first gate dielectric layer 148 and the first source / drain structure pair 132, 134. The interlayer dielectric layer 302 directly contacts the outer sidewalls of the first semiconductor layer 144. The interlayer dielectric layer 302 may be, for example, or include, silicon dioxide, a low-k dielectric material, silicon nitride, silicon carbide, some other suitable dielectric material, or any combination thereof.

[0049] Figure 3D Shown Figure 1FIG3 is a cross-sectional view 300 d of some other embodiments of an IC.

[0050] In some embodiments, the conductive source / drain via 138 includes a first pair of sidewall segments that are curved and intersect the curved sidewalls of the first semiconductor layer 144. Furthermore, the conductive source / drain via 138 includes a second pair of sidewall segments that are curved and intersect the curved sidewalls of the second semiconductor layer 146.

[0051] Figure 3E Shown Figure 1 300e of a cross-sectional view of some other embodiments of an IC.

[0052] In various embodiments, the first semiconductor layer 144 includes a first metal oxide layer 144a and a second metal oxide layer 144b, wherein the second metal oxide layer 144b includes a different material than the first metal oxide layer 144a. In some embodiments, the first metal oxide layer 144a includes CuO and the second metal oxide layer 144b includes NiO; the first metal oxide layer 144a includes SnO and the second metal oxide layer 144b includes metal-doped SnO; the first metal oxide layer 144a includes copper-rich CuNiO and the second metal oxide layer 144b includes copper-poor NiO; etc.

[0053] In further embodiments, the second semiconductor layer 146 includes a first metal oxide layer 146a and a second metal oxide layer 146b, the second metal oxide layer 146b including a different material than the first metal oxide layer 146a. In some embodiments, the first metal oxide layer 146a includes GaZnO and the second metal oxide layer 146b includes InZnO; the first metal oxide layer 146a includes In1Ga3Zn2O and the second metal oxide layer 146b includes InGaZnO; the first metal oxide layer 146a includes InGaZnO and the second metal oxide layer 146b includes Sn-doped InGaZnO; etc. Figure 3E The first semiconductor layer 144 and the second semiconductor layer 146 are shown as having two distinct layers, but it should be understood that this is a non-limiting example and the first semiconductor layer 144 and the second semiconductor layer 146 may include any number of layers.

[0054] Figure 3F Shown Figure 1 300f is a cross-sectional view of some other embodiments of an IC.

[0055] In some embodiments, the outer sidewalls of the first semiconductor layer 144 are spaced between the first source / drain structure pair 132, 134, and the second source / drain structure pair 140, 142 are spaced between the outer sidewalls of the second semiconductor layer 146. The outer sidewalls of the second semiconductor layer 146 are aligned with the outer sidewalls of the second gate dielectric layer 150. In various embodiments, the first semiconductor layer 144 can be configured as follows: Figure 3A In some embodiments, Figure 3F During fabrication of the IC, the first semiconductor layer 144 is deposited and subsequently patterned to define outer sidewalls of the first semiconductor layer 144 between the first pair of source / drain structures 132 , 134 .

[0056] Figure 3G Shown Figure 1 300g of a cross-sectional view of some other embodiments of an IC.

[0057] In some embodiments, the first source / drain structure pair 132, 134 is spaced between the outer sidewalls of the first semiconductor layer 144, and the outer sidewalls of the second semiconductor layer 146 are spaced between the second source / drain structure pair 140, 142. The outer sidewalls of the first semiconductor layer 144 are aligned with the outer sidewalls of the first gate dielectric layer 148. In various embodiments, the second semiconductor layer 146 can be configured as follows: Figure 3A In some embodiments, Figure 3F During fabrication of the IC, the second semiconductor layer 146 is deposited and subsequently patterned to define outer sidewalls of the second semiconductor layer 146 between the second pair of source / drain structures 140 , 142 .

[0058] Figure 3H Shown Figure 1 300h of a cross-sectional view of some other embodiments of an IC.

[0059] In some embodiments, the p-channel transistor 131a is located above the n-channel transistor 131b. In such embodiments, the second semiconductor layer 146 is located above the second source / drain structure pair 140, 142, and the second gate dielectric layer 150 is disposed between the top surface of the second semiconductor layer 146 and the bottom surface of the gate electrode 136. In addition, the first gate dielectric layer 148 is disposed between the top surface of the gate electrode 136 and the bottom surface of the first semiconductor layer 144, and the first source / drain structure pair 132, 134 is located above the first semiconductor layer 144.

[0060] Figure 4A Shown Figure 1 400a is a cross-sectional view of some other embodiments of an IC.

[0061] In some embodiments, the plurality of conductive lines 120 and conductive vias 122, the first source / drain structure pair 132, 134, the gate electrode 136, the conductive source / drain via 138, and the second source / drain structure pair 140, 142, respectively, include a conductive structure 404 and a conductive liner 402. The conductive liner 402 is disposed along opposite sidewalls and a bottom surface of the conductive structure 404. The conductive structure 404 can be, for example, or include copper, aluminum, tungsten, ruthenium, some other conductive material, or any combination thereof. The conductive liner 402 can be, for example, or include titanium, titanium nitride, tantalum, tantalum nitride, some other suitable conductive material, or any combination thereof. The conductive liner 402 can be configured as a diffusion barrier layer and / or an adhesion layer.

[0062] Figure 4B Shown Figure 4A 400b is a cross-sectional view of some other embodiments of an IC.

[0063] In some embodiments, the first source / drain structure pair 132, 134 respectively shares a corresponding conductive body structure 404 and a conductive liner 402 with the underlying conductive via 122. In further embodiments, the first source / drain structure 140 of the second source / drain structure pair 140, 142 shares a corresponding conductive body structure 404 and a conductive liner 402 with the conductive source / drain via 138.

[0064] Figure 5A A cross-sectional view 500a of some embodiments of an IC is shown having an electronic device including transistors vertically stacked one on top of another in a first region of a semiconductor substrate laterally adjacent to a second region of the semiconductor substrate.

[0065] The semiconductor substrate 102 includes a first region 502 laterally adjacent to a second region 504. In some embodiments, the electronic device 130 is disposed in the first region 502. The electronic device 130 includes a p-channel transistor 131a and an n-channel transistor 131b located above the p-channel transistor 131a. The second region 504 may include one or more of the lower semiconductor devices 108 on the semiconductor substrate 102, as well as a second plurality of conductive lines 502a-502d and a second plurality of conductive vias 504a-504c.

[0066] The second plurality of conductive lines 502a-502d and the second plurality of conductive vias 504a-504c are arranged in different levels. For example, the first conductive line 502a is arranged in a first line level, the second conductive line 502b is arranged in a second line level, the third conductive line 502c is arranged in a third line level, and the fourth conductive line 502d is arranged in a fourth line level. In some embodiments, the first source / drain structure pair 132, 134, the gate electrode 136, and the second source / drain structure pair 140, 142 can be configured as conductive lines that align with corresponding conductive lines in the second plurality of conductive lines 502a-502d. In various embodiments, the first source / drain structure pair 132, 134 is aligned with and / or arranged in the second line level. For example, the bottom surface of the second conductive line 502b is aligned with the bottom surface of the first source / drain structure pair 132, 134. In further embodiments, the gate electrode 136 is aligned with and / or arranged in a third line level, and the second source / drain structure pair 140 , 142 is aligned with and / or arranged in a fourth line level.

[0067] Figure 5B Shown Figure 5A 500b is a cross-sectional view of some embodiments of an IC.

[0068] In some embodiments, a BEOL device 506 is disposed in the second region 504 adjacent to the electronic device 130. In some embodiments, the BEOL device 506 is configured as a capacitor, a memory device, or some other electronic device. The BEOL device 506 may, for example, include a dielectric layer 510 disposed between a bottom electrode 508 and a top electrode 512. In various embodiments, the dielectric layer 510 is configured as a data storage layer, a capacitor dielectric, or the like.

[0069] Figure 5C Shown is a view taken along line A-A' Figure 5A Layout diagram 500c of some embodiments of an IC.

[0070] In some embodiments, the IC includes a BEOL structure ( Figure 5A In various embodiments, each of the plurality of electronic devices 130a-130f is configured as follows Figure 1 、 Figure 2 、 Figures 3A to 3E 、 Figures 4A to 4B or Figures 5A to 5BAs shown and / or described in . A plurality of electronic devices 130a-130f include a first column of electronic devices 130a-130c and a second column of electronic devices 130d-130f. The first column of electronic devices 130a-130c shares a first gate electrode 136a that extends across the length of the first column of electronic devices 130a-130c. The second column of electronic devices 130d-130f shares a second gate electrode 136b. The first gate electrode 136a and the second gate electrode 136b are each represented as a dashed box in the layout diagram 500c. In various embodiments, the first gate electrode 136a and the second gate electrode 136b are electrically coupled to a conductive via (not shown) in a position laterally offset relative to the plurality of electronic devices 130a-130f. In some embodiments, the second source / drain structure pair 140, 132 of each of the electronic devices 130a-130f extends in the same direction as the first gate electrode 136a and the second gate electrode 136b extend. In further embodiments, the first source / drain structure pair (eg, Figure 5A 132 , 134 ) are directly below the second source / drain structure pair 140 , 142 .

[0071] Figure 5D Shown Figure 5C Layout diagram 500d of some other embodiments of the IC. Layout diagram 500d is along the Figure 5A The line A-A' is intercepted.

[0072] In some embodiments, a row of a plurality of electronic devices 130a-130f shares corresponding second semiconductor layers 146 and first semiconductor layers (eg, Figure 5A In various embodiments, the first gate electrode 136a and the second gate electrode 136b are elongated in a second direction perpendicular to the first direction.

[0073] Figures 6 to 16 Cross-sectional views 600-1600 illustrate some embodiments of a first method for forming an integrated chip (IC) having an electronic device including transistors stacked vertically on each other according to an embodiment of the present disclosure. Figures 6 to 16 The cross-sectional views 600-1600 shown in FIG are described with reference to the first method, but it should be understood that Figures 6 to 16 The structure shown in is not limited to the first method, but can exist independently of the first method. Figures 6 to 16 Described as a series of steps, it should be understood that these steps are not restrictive, because the order of the steps can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some steps shown and / or described can be omitted in whole or in part.

[0074] like Figure 6 As shown in the cross-sectional view 600 of FIG, a semiconductor substrate 102 is provided, and a FEOL structure 104 and a lower BEOL structure 602 are formed on the semiconductor substrate 102. The semiconductor substrate 102 may be, for example, or include, a bulk substrate (e.g., bulk silicon), single crystal silicon, SiGe, SOI, etc. The FEOL structure 104 includes a semiconductor device 108 on the semiconductor substrate 102, an ILD layer 124 above the semiconductor substrate 102, and one or more conductive contacts 118 in the ILD layer 124. The lower BEOL structure 602 may be referred to as a lower interconnect structure.

[0075] In various embodiments, the semiconductor device 108 includes a pair of source / drain regions 110, a lower gate electrode 114, a lower gate dielectric 112, and sidewall spacers 116. In some embodiments, a process for forming the semiconductor device 108 includes: depositing (e.g., by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, etc.) a gate dielectric material on the semiconductor substrate 102; depositing (e.g., by CVD, PVD, ALD, etc.) a gate electrode material on the gate dielectric material; etching the gate dielectric material and the gate electrode material to form the lower gate electrode 114 and the lower gate dielectric 112; depositing a sidewall spacer material on the lower gate electrode 114 and the lower gate dielectric 112; etching the sidewall spacer material to form the sidewall spacers 116; and performing a selective ion implantation process to form the pair of source / drain regions 110 in the semiconductor substrate 102 on opposite sides of the lower gate electrode 114. The ILD layer 124 is formed on the semiconductor substrate 102, for example, by a CVD process, a PVD process, an ALD process, or some other suitable growth or deposition process. Furthermore, the one or more conductive contacts 118 may be formed by: etching the ILD layer 124 to form an opening in the ILD layer 124; depositing (e.g., by CVD, PVD, ALD, etc.) a conductive material in the opening; and performing a planarization process (e.g., a chemical mechanical planarization (CMP) process) on the conductive material.

[0076] Furthermore, the lower BEOL structure 602 includes a lower dielectric structure 126, a plurality of conductive lines 120, a first dielectric layer 128a, and a plurality of conductive vias 122. The lower dielectric structure 126 and the first dielectric layer 128a can each be formed, for example, by a CVD process, a PVD process, an ALD process, or some other suitable growth or deposition process. The plurality of conductive lines 120 and the plurality of conductive vias 122 can be formed, for example, by a single damascene process, a dual damascene process, or some other suitable process.

[0077] like Figure 7As shown in the cross-sectional view 700 of FIG, a second dielectric layer 128b is formed over the first dielectric layer 128a, and a plurality of openings 702 are formed in the second dielectric layer 128b. The second dielectric layer 128b can be formed, for example, by a CVD process, a PVD process, an ALD process, or some other suitable growth or deposition process. In some embodiments, the process for forming the plurality of openings 702 includes: forming a masking layer (not shown) on the second dielectric layer 128b; etching the second dielectric layer 128b; and performing a removal process to remove the masking layer.

[0078] like Figure 8 As shown in the cross-sectional view 800 of FIG. 1 , a first source / drain structure pair 132, 134 is formed in the second dielectric layer 128b. In some embodiments, the process for forming the first source / drain structure pair 132, 134 includes: forming a plurality of openings ( Figure 7 702) depositing (e.g., by CVD, PVD, ALD, etc.) one or more conductive materials; and performing a planarization process (e.g., a CMP process) on the one or more conductive materials. In various embodiments, depositing the one or more conductive materials includes: depositing the liner opening ( Figure 7 a conductive liner layer (e.g., comprising titanium nitride, tantalum nitride, etc.) of 702; and depositing a conductive core (e.g., copper, aluminum, tungsten, some other conductive material, or any combination thereof) over the conductive liner layer.

[0079] like Figure 9 As shown in the cross-sectional view 900 of , a first semiconductor layer 144 is formed on the first source / drain structure pair 132, 134, and a first gate dielectric layer 148 is formed on the first semiconductor layer 144. In some embodiments, the first semiconductor layer 144 is formed by one or more deposition processes that may include one or more of a PVD process, a CVD process, an ALD process, or some other suitable growth or deposition process. In addition, the one or more deposition processes are implemented at a first deposition temperature of, for example, less than or equal to about 400 degrees Celsius. By forming the first semiconductor layer 144 at the first deposition temperature, damage to structures in the lower BEOL structure 602 and / or FEOL structure 104 can be mitigated or reduced. The first semiconductor layer 144 includes a first conductivity type (e.g., p-type). In various embodiments, the first semiconductor layer 144 is formed to a thickness in the range of about 3 to 10 nm or some other suitable value. In addition, the first semiconductor layer 144 may, for example, be or include Cu X Ni Y Sn Z NO compounds (wherein X is in the range of 0 to 1, Y is in the range of 0 to 1, and Z is in the range of 0 to 1), Cu X Ni Y Sn ZO compound (wherein X is in the range of 0 to 1, Y is in the range of 0 to 1, and Z is in the range of 0 to 1) or some other suitable material. In various embodiments, Cu is copper; Ni is nickel; Sn is tin; O is oxygen; and N is tellurium (Te), antimony (Sb), magnesium (Mg), boron (B), aluminum (Al), gallium (Ga), or iron (Fe). In some embodiments, the first semiconductor layer 144 includes a single layer (including Cu X Ni Y Sn Z NO compound) or comprises a multi-layer stack.

[0080] In some embodiments, the first gate dielectric layer 148 is formed on the first semiconductor layer 144 by, for example, a PVD process, a CVD process, an ALD process, or some other suitable growth or deposition process. The first gate dielectric layer 148 may be, for example, or include, aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium zirconium oxide, hafnium lanthanum oxide, hafnium oxide silicate, hafnium titanium oxide, some other suitable dielectric material, or any combination thereof. In various embodiments, the first gate dielectric layer 148 has a dielectric constant greater than 9. In further embodiments, the first gate dielectric layer 148 may be, for example, or include, a ferroelectric material (e.g., lead zirconate titanate, barium titanate, etc.), an antiferroelectric material (e.g., lead zirconate, lead hafnium oxide, etc.), or the like. In further embodiments, the thickness of the first gate dielectric layer 148 is greater than the thickness of the first semiconductor layer 144.

[0081] In various embodiments, a patterning process may be performed on the first semiconductor layer 144 before forming the first gate dielectric layer 148 on the first semiconductor layer 144. In such an embodiment, the first gate dielectric layer 148 extends along and contacts the outer sidewalls of the first semiconductor layer 144 (e.g., Figure 3A In some embodiments, the patterning process includes: forming a masking layer (not shown) over the first semiconductor layer 144; etching the first semiconductor layer 144 according to the masking layer; and removing the masking layer.

[0082] like Figure 10 As shown in the cross-sectional view 1000 of FIG, a third dielectric layer 128 c is formed over the first gate dielectric layer 148, and an opening 1002 is formed in the third dielectric layer 128 c. The third dielectric layer 128 c can be formed, for example, by a CVD process, a PVD process, an ALD process, or some other suitable growth or deposition process. In some embodiments, the process for forming the opening 1002 includes: forming a masking layer (not shown) on the third dielectric layer 128 c; etching the third dielectric layer 128 c; and performing a removal process to remove the masking layer.

[0083] like Figure 11 As shown in the cross-sectional view 1100 of FIG. 1 , a gate electrode 136 is formed in the third dielectric layer 128 c to form a p-channel transistor 131 a above the lower BEOL structure 602. In some embodiments, the process for forming the gate electrode 136 includes: Figure 10 1002) depositing (e.g., by CVD, PVD, ALD, etc.) one or more conductive materials; and performing a planarization process (e.g., a CMP process) on the one or more conductive materials. In various embodiments, depositing the one or more conductive materials includes: depositing the liner opening ( Figure 10 1002) of a conductive liner layer (e.g., comprising titanium nitride, tantalum nitride, etc.); and depositing a conductive core (e.g., copper, aluminum, tungsten, some other conductive material, or any combination thereof) over the conductive liner layer. In some embodiments, the process for forming the p-channel transistor 131a includes: Figures 7 to 11 The processing steps shown and / or described in .

[0084] like Figure 12 As shown in cross-sectional view 1200 of FIG, a second gate dielectric layer 150 is formed over gate electrode 136, and a second semiconductor layer 146 is formed over second gate dielectric layer 150. In some embodiments, second gate dielectric layer 150 is formed over gate electrode 136 by, for example, a PVD process, a CVD process, an ALD process, or some other suitable growth or deposition process. In some embodiments, second semiconductor layer 146 is formed by one or more deposition processes, which may include one or more of a PVD process, a CVD process, an ALD process, or some other suitable growth or deposition process. Furthermore, the one or more deposition processes are performed at a second deposition temperature, for example, less than or equal to approximately 400 degrees Celsius. By forming second semiconductor layer 146 at the second deposition temperature, damage to the underlying BEOL structure 602, FEOL structure 104, and / or structures in p-channel transistor 131a can be mitigated or reduced. Second semiconductor layer 146 includes a second conductivity type (e.g., n-type). In various embodiments, second semiconductor layer 146 is formed to a thickness in the range of approximately 3 to 10 nm, or some other suitable value. In addition, the second semiconductor layer 146 may be or include, for example, In X Ga Y Zn Z MO compounds (wherein X is in the range of 0 to 1, Y is in the range of 0 to 1, and Z is in the range of 0 to 1), In X Ga Y Zn ZO compound (wherein X is in the range of 0 to 1, Y is in the range of 0 to 1, and Z is in the range of 0 to 1) or some other suitable material. In various embodiments, In is indium; Ga is gallium; Zn is zinc; O is oxygen; and M is titanium (Ti), aluminum (Al), silver (Ag), tungsten (W), cerium (Ce), tin (Sn), vanadium (V), or scandium (Sc). In some embodiments, the first semiconductor layer 144 includes a single layer (including In X Ga Y Zn Z MO compounds) or include multilayer stacks.

[0085] In some embodiments, the second gate dielectric layer 150 may be, for example, or include aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium zirconium oxide, hafnium lanthanum oxide, hafnium oxide silicate, hafnium titanium oxide, some other suitable dielectric material, or any combination thereof. In various embodiments, the second gate dielectric layer 150 has a dielectric constant greater than 9. In further embodiments, the second gate dielectric layer 150 may be, for example, or include a ferroelectric material (e.g., lead zirconate titanate, barium titanate, etc.), an antiferroelectric material (e.g., lead zirconate, lead hafnium oxide, etc.), or the like. In further embodiments, the thickness of the second gate dielectric layer 150 is greater than the thickness of the second semiconductor layer 146.

[0086] In various embodiments, a patterning process may be performed on the second semiconductor layer 146. In such an embodiment, the outer sidewalls of the second semiconductor layer 146 are spaced apart from the outer sidewalls of the second gate dielectric layer 150 (eg, as shown in FIG. 1 ). Figure 3A In some embodiments, the patterning process includes: forming a masking layer (not shown) over the second semiconductor layer 146; etching the second semiconductor layer 146 according to the masking layer; and removing the masking layer.

[0087] like Figure 13 As shown in the cross-sectional view 1300 of FIG, a fourth dielectric layer 128d is formed over the second semiconductor layer 146, and a masking structure 1302 is formed over the fourth dielectric layer 128d. In some embodiments, the masking structure 1302 includes a first hard mask 1304 over the fourth dielectric layer 128d, a first photoresist 1308 over the first hard mask 1304, a patterned hard mask 1306 over the first photoresist 1308, and a second photoresist 1310 over the patterned hard mask 1306. The second photoresist 1310 includes sidewalls that define an opening 1312 over the individual source / drain structures 132 in the first pair of source / drain structures 132 and 134. The fourth dielectric layer 128d can be formed, for example, by a CVD process, a PVD process, an ALD process, or some other suitable growth or deposition process.

[0088] In some embodiments, the first hard mask 1304 and the patterned hard mask 1306 can each be or include, for example, titanium, titanium nitride, tungsten, some other metal, some other suitable material, or any combination thereof. In various embodiments, the process for forming the masking structure 1302 includes: depositing (e.g., by CVD, PVD, etc.) the first hard mask 1304 over the fourth dielectric layer 128 d; depositing (e.g., by spin coating or another suitable process) a first photoresist 1308 over the first hard mask 1304; depositing (e.g., by CVD, PVD, etc.) a second hard mask over the first photoresist 1308; patterning the second hard mask to form or define the patterned hard mask 1306; depositing (e.g., by spin coating or another suitable process) a second photoresist 1310 over the patterned hard mask 1306; and forming (e.g., by a photolithography process or another suitable process) an opening 1312 in the second photoresist 1310.

[0089] like Figure 14 As shown in cross-sectional view 1400 of FIG, a first etching process is performed on the first semiconductor layer 144, the first gate dielectric layer 148, the third dielectric layer 128c, the second gate dielectric layer 150, the second semiconductor layer 146, and the fourth dielectric layer 128d according to the masking structure 1302, thereby forming a via opening 1402. The via opening 1402 exposes the upper surface of the individual source / drain structures 132 in the first source / drain structure pair 132, 134. In some embodiments, the first etching process includes a dry etching process (e.g., a reactive ion etching (RIE) process, a deep reactive ion etching (DRIE) process, a plasma etching process, etc.), a wet etching process, some other suitable etching process, or any combination thereof. In various embodiments, during the first etching process, the first semiconductor layer 144 and the second semiconductor layer 146 can be etched faster (e.g., with a higher etching selectivity) than the first gate dielectric layer 148 and the second gate dielectric layer 150 and / or the third dielectric layer 128c and the fourth dielectric layer 128d. In such an embodiment, the inner sidewalls of the first and second semiconductor layers 144 and 146 defining at least a portion of the via opening 1402 may be recessed (e.g., as shown in FIG. Figure 3D In various embodiments, the first etching process reduces the thickness of the second photoresist 1310 .

[0090] like Figure 15 As shown in the cross-sectional view 1500, according to the masking structure ( Figure 141302) is subjected to a second etching process on the fourth dielectric layer 128d, thereby forming a first opening 1502 and a second opening 1504. The second etching process may include, for example, a dry etching process (e.g., a RIE process, a DRIE process, a plasma etching process, etc.), a wet etching process, some other suitable etching process, or any combination thereof. In addition, after the second etching process, a removal process is performed to remove the masking structure ( Figure 14 1302). The first opening 1502 includes a through hole opening ( Figure 14 1402) is located below the fourth dielectric layer 128d.

[0091] like Figure 16 As shown in the cross-sectional view 1600, at the first opening and the second opening ( Figure 15 Conductive source / drain vias 138 and second source / drain structure pairs 140, 142 are formed in the first opening (1502, 1504) to form an n-channel transistor 131b above the p-channel transistor 131a and define or form the electronic device 130 above the FEOL structure 104. Figure 15 1502) in which a conductive source / drain through hole 138 and a first source / drain structure 140 in the second source / drain structure pair 140, 142 are formed, and in the second opening ( Figure 15 In various embodiments, the lower BEOL structure ( Figure 15 602) and the electronic device 130 are part of the BEOL structure 106. In some embodiments, the process for forming the conductive source / drain via 138 and the second source / drain structure pair 140, 142 includes: Figure 15 Depositing (e.g., by CVD, PVD, ALD, etc.) one or more conductive materials in the first opening and the second opening (e.g., 1502, 1504); and performing a planarization process (e.g., a CMP process) on the one or more conductive materials. In various embodiments, depositing the one or more conductive materials includes: depositing a first opening and a second opening ( Figure 15 1502, 1504) of the conductive liner layer (e.g., including titanium nitride, tantalum nitride, etc.); and depositing a conductive core (e.g., copper, aluminum, tungsten, some other conductive material, or any combination thereof) over the conductive liner layer. In various embodiments, the process for forming the n-channel transistor 131b includes: Figures 10 to 16 The processing steps shown and / or described in .

[0092] In various embodiments, forming n-channel transistor 131b after p-channel transistor 131a reduces the number of thermal annealing processes to which n-channel transistor 131b is exposed. Thus, diffusion of one or more elements from second semiconductor layer 146 into adjacent dielectric materials is mitigated. This improves the reliability and performance of n-channel transistor 131b.

[0093] In some embodiments, additional conductive vias and wiring levels (not shown) may be formed above the electronic device 130. The additional conductive vias and wiring levels are part of the BEOL structure 106. Furthermore, the conductive vias and / or wiring levels may be formed in the BEOL structure 106 simultaneously with the first source / drain structure pair 132, 134, the gate electrode 136, the conductive source / drain via 138, and the second source / drain structure pair 140, 142, and may be formed at levels aligned with the first source / drain structure pair 132, 134, the gate electrode 136, the conductive source / drain via 138, and the second source / drain structure pair 140, 142. For example, the first wiring level (not shown) may be formed in the BEOL structure 106 in a region that is laterally offset relative to the first source / drain structure pair 132, 134, with a bottom surface of the first wiring level aligned with a bottom surface of a source / drain structure in the first source / drain structure pair 132, 134.

[0094] Figures 17 to 26 Cross-sectional views 1700-2600 illustrate some embodiments of a second method for forming an integrated chip (IC) having an electronic device including transistors stacked vertically on each other according to an embodiment of the present disclosure. Figures 17 to 26 The cross-sectional views 1700-2600 shown in FIG are described with reference to the second method, but it should be understood that Figures 17 to 26 The structure shown in is not limited to the second method, but can exist independently of the second method. Figures 17 to 26 Described as a series of steps, it should be understood that these steps are not restrictive, because the order of the steps can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some steps shown and / or described can be omitted in whole or in part.

[0095] like Figure 17 As shown in the cross-sectional view 1700 of FIG. 1 , a semiconductor substrate 102 is provided, and a FEOL structure 104, a lower BEOL structure 602, and a p-channel transistor 131a are formed over the semiconductor substrate 102. In various embodiments, Figure 17 The structure of Figures 6 to 11 are formed as shown and / or described in .

[0096] like Figure 18As shown in cross-sectional view 1800 of FIG. 1 , a first masking structure 1806 is formed over the gate electrode 136 and the third dielectric layer 128 c. In some embodiments, the first masking structure 1806 includes a hard mask 1802 over the third dielectric layer 128 c and a photoresist 1804 over the hard mask 1802. The hard mask 1802 can be formed, for example, by a CVD process, a PVD process, an ALD process, or some other suitable growth or deposition process. The photoresist 1804 can be formed, for example, by spin coating or some other suitable process. The hard mask 1802 can be, for example, or include, titanium, titanium nitride, tungsten, some other metal, some other suitable material, or any combination thereof.

[0097] like Figure 19 As shown in cross-sectional view 1900 of , an opening 1902 is formed in photoresist 1804. In some embodiments, the process for forming opening 1902 includes: exposing photoresist 1804 to a pattern of a photomask (e.g., by ultraviolet (UV) light); and immersing photoresist 1804 in a developer solution.

[0098] like Figure 20 As shown in the cross-sectional view 2000 of FIG, a first etching process is performed on the third dielectric layer 128 c, the first gate dielectric layer 148, and the first semiconductor layer 144 to form an opening 2002 above the independent source / drain structure 132 in the first source / drain structure pair 132, 134. In some embodiments, the first etching process includes exposing the third dielectric layer 128 c, the first gate dielectric layer 148, and the first semiconductor layer 144 to one or more etchants, wherein the first masking structure ( Figure 19 1806) in an appropriate position. The first etching process is, for example, an RIE process, a DRIE process, a plasma etching process, a wet etching process, some other suitable etching process, or any combination thereof. After the first etching process, a removal process is performed to remove the first masking structure ( Figure 19 of 1806).

[0099] like Figure 21 As shown in the cross-sectional view 2100, at the opening ( Figure 20 In some embodiments, the process for forming the lower through-hole section 138a includes: Figure 20 2002), depositing (eg, by CVD, PVD, ALD, etc.) one or more conductive materials; and performing a planarization process (eg, a CMP process) on the one or more conductive materials.

[0100] like Figure 22As shown in the cross-sectional view 2200 of FIG. 2 , a second gate dielectric layer 150 is formed over the gate electrode 136 and the lower via segment 138 a, and a second semiconductor layer 146 is formed on the second gate dielectric layer 150. In various embodiments, the second gate dielectric layer 150 and the second semiconductor layer 146 are formed as shown in FIG. Figure 12 are formed as shown and / or described in .

[0101] like Figure 23 As shown in the cross-sectional view 2300 of FIG, a fourth dielectric layer 128d is formed over the second semiconductor layer 146, and a second masking structure 2302 is formed over the fourth dielectric layer 128d. In some embodiments, the second masking structure 2302 includes a first hard mask 2304 over the fourth dielectric layer 128d, a first photoresist 2308 over the first hard mask 2304, a patterned hard mask 2306 over the first photoresist 2308, and a second photoresist 2310 over the patterned hard mask 2306. The second photoresist 2310 includes sidewalls defining an opening over the lower via segment 138a. The fourth dielectric layer 128d can be formed, for example, by a CVD process, a PVD process, an ALD process, or some other suitable growth or deposition process. In some embodiments, the second masking structure 2302 can be formed by forming a first hard mask 2304 over the first photoresist 2308 .... Figure 13 In some embodiments, the first hard mask 2304 and the patterned hard mask 2306 can each be or include, for example, titanium, titanium nitride, tungsten, some other metal, some other suitable material, or any combination thereof.

[0102] like Figure 24 As shown in the cross-sectional view 2400 of FIG. 2 , a second etching process is performed on the fourth dielectric layer 128 d, the second semiconductor layer 146, and the second gate dielectric layer 150 according to the second masking structure 2302, thereby forming an opening 2402. The opening 2402 exposes the upper surface of the lower via segment 138 a. The second etching process may include, for example, a dry etching process (e.g., an RIE process, a DRIE process, a plasma etching process, etc.), a wet etching process, some other suitable etching process, or any combination thereof.

[0103] like Figure 25 As shown in the cross-sectional view 2500, according to the second masking structure ( Figure 24 2302) is subjected to a third etching process on the fourth dielectric layer 128d, thereby forming a first opening 2502 and a second opening 2504. The third etching process may include, for example, a dry etching process (e.g., a RIE process, a DRIE process, a plasma etching process, etc.), a wet etching process, some other suitable etching process, or any combination thereof. In addition, after the third etching process, a removal process is performed to remove the second masking structure ( Figure 24 2302). The first opening 2502 includes an opening ( Figure 24 2402) is located below the fourth dielectric layer 128d.

[0104] like Figure 26 As shown in the cross-sectional view 2600, at the first opening and the second opening ( Figure 25 The upper via segment 138b and the second source / drain structure pair 140, 142 are formed in the first opening (2502, 2504) to form the n-channel transistor 131b above the p-channel transistor 131a and define or form the electronic device 130 above the FEOL structure 104. Figure 25 2502) in which the upper through hole section 138b and the first source / drain structure 140 in the second source / drain structure pair 140, 142 are formed, and in the second opening ( Figure 25 In various embodiments, the lower BEOL structure ( Figure 25 106) and the electronic device 130 are part of the BEOL structure 106. In some embodiments, the process for forming the upper via segment 138b and the second source / drain structure pair 140, 142 includes: Figure 25 Depositing (e.g., by CVD, PVD, ALD, etc.) one or more conductive materials in the first opening and the second opening ( 2502, 2504 ); and performing a planarization process (e.g., a CMP process) on the one or more conductive materials. In various embodiments, depositing the one or more conductive materials includes: depositing a first opening and a second opening ( Figure 25 2502, 2504) of the conductive liner layer (e.g., including titanium nitride, tantalum nitride, etc.); and depositing a conductive core (e.g., copper, aluminum, tungsten, some other conductive material, or any combination thereof) over the conductive liner layer. In various embodiments, the process for forming the n-channel transistor 131b includes: Figures 18 to 26 The lower via segment 138a and the upper via segment 138b define a conductive source / drain via 138.

[0105] Figures 27 to 38 Cross-sectional views 2700-3800 of some embodiments of a third method for forming an integrated chip (IC) having an electronic device including transistors stacked vertically on each other according to an embodiment of the present disclosure are shown. Figures 27 to 38 The cross-sectional views 2700-3800 shown in FIG are described with reference to the third method, but it should be understood that Figures 27 to 38 The structure shown in is not limited to the third method, but can exist independently of the third method. Figures 27 to 38 Described as a series of steps, it should be understood that these steps are not restrictive, because the order of the steps can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some steps shown and / or described can be omitted in whole or in part.

[0106] like Figure 27 As shown in the cross-sectional view 2700 of FIG. 27 , a semiconductor substrate 102 is provided, and a FEOL structure 104, a lower BEOL structure 602, a second dielectric layer 128b, and a first source / drain structure pair 132, 134 are formed over the semiconductor substrate 102. In some embodiments, Figure 27 The structure of Figures 6 to 8 are formed as shown and / or described in .

[0107] like Figure 28 As shown in the cross-sectional view 2800 of FIG. 28 , a first semiconductor layer 144 is formed on the first source / drain structure pair 132, 134. The first semiconductor layer 144 can be formed, for example, by one or more deposition processes that can include one or more of a PVD process, a CVD process, an ALD process, or some other suitable growth or deposition process. Furthermore, the one or more deposition processes are performed at a first deposition temperature of, for example, less than or equal to approximately 400 degrees Celsius.

[0108] like Figure 29 As shown in the cross-sectional view 2900 of , a patterning process is performed on the first semiconductor layer 144. The patterning process may include, for example: forming a mask layer (not shown) over the first semiconductor layer 144; etching the first semiconductor layer 144 according to the mask layer; and removing the mask layer.

[0109] like Figure 30 As shown in the cross-sectional view 3000 of FIG, a first gate dielectric layer 148 is formed on the first semiconductor layer 144 and the first source / drain structure pair 132, 134. The first gate dielectric layer 148 can be formed, for example, by a PVD process, a CVD process, an ALD process, or some other suitable growth or deposition process. In various embodiments, the first gate dielectric layer 148 directly contacts opposite outer sidewalls of the first semiconductor layer 144 and has a bottom surface aligned with the bottom surface of the first semiconductor layer 144.

[0110] Furthermore, as shown in cross-sectional view 3000, a third dielectric layer 128c is formed over the first gate dielectric layer 148, and an opening 3002 is formed in the third dielectric layer 128c. The third dielectric layer 128c can be formed, for example, by a CVD process, a PVD process, an ALD process, or some other suitable growth or deposition process. In some embodiments, the process for forming the opening 3002 includes: forming a masking layer (not shown) on the third dielectric layer 128c; etching the third dielectric layer 128c according to the masking layer; and performing a removal process to remove the masking layer.

[0111] like Figure 31 As shown in the cross-sectional view 3100 of FIG. 3 , a gate electrode 136 is formed in the third dielectric layer 128 c to form a p-channel transistor 131 a above the lower BEOL structure 602. The gate electrode 136 may be formed as shown in FIG. Figure 11 are formed as shown and / or described in .

[0112] like Figure 32 As shown in the cross-sectional view 3200 of FIG. 3 , a second gate dielectric layer 150 is formed over the gate electrode 136, and a second semiconductor layer 146 is formed on the second gate dielectric layer 150. The second gate dielectric layer 150 and the second semiconductor layer 146 may be formed as shown in FIG. Figure 12 are formed as shown and / or described in .

[0113] like Figure 33 As shown in the cross-sectional view 3300 of , a patterning process is performed on the second semiconductor layer 146. The patterning process may include, for example: forming a mask layer (not shown) over the second semiconductor layer 146; etching the second semiconductor layer 146 according to the mask layer; and removing the mask layer.

[0114] like Figure 34 As shown in the cross-sectional view 3400 of FIG, a fourth dielectric layer 128 d is formed over the second semiconductor layer 146. The fourth dielectric layer 128 d can be formed, for example, by a CVD process, a PVD process, an ALD process, or some other suitable growth or deposition process. In various embodiments, the fourth dielectric layer 128 d directly contacts opposite outer sidewalls of the second semiconductor layer 146, and the bottom surface of the fourth dielectric layer 128 d is aligned with the bottom surface of the second semiconductor layer 146.

[0115] like Figure 35As shown in the cross-sectional view 3500 of FIG. 35, a masking structure 3502 is formed on the fourth dielectric layer 128d. In some embodiments, the masking structure 3502 includes a first hard mask 3504 on the fourth dielectric layer 128d, a first photoresist 3508 on the first hard mask 3504, a patterned hard mask 3506 over the first photoresist 3508, and a second photoresist 3510 over the patterned hard mask 3506. The second photoresist 3510 includes sidewalls defining an opening 3512 over the individual source / drain structures 132 in the first source / drain structure pair 132, 134. In some embodiments, the masking structure 3502 can be formed by Figure 13 In some embodiments, the first hard mask 3504 and the patterned hard mask 3506 can each be or include, for example, titanium, titanium nitride, tungsten, some other metal, some other suitable material, or any combination thereof.

[0116] like Figure 36 As shown in the cross-sectional view 3600 of FIG, a first etching process is performed on the first gate dielectric layer 148, the third dielectric layer 128c, the second gate dielectric layer 150, and the fourth dielectric layer 128d according to the masking structure 3502, thereby forming a via opening 3602. The via opening 3602 exposes the upper surface of the independent source / drain structure 132 in the first source / drain structure pair 132, 134. In some embodiments, the first etching process includes a dry etching process (e.g., a RIE process, a DRIE process, a plasma etching process, etc.), a wet etching process, some other suitable etching process, or any combination thereof.

[0117] like Figure 37 As shown in the cross-sectional view 3700, according to the masking structure ( Figure 36 A second etching process is performed on the fourth dielectric layer 128d (e.g., the first opening 3702 and the second opening 3704) to form the first opening 3702 and the second opening 3704. The second etching process may include, for example, a dry etching process (e.g., a RIE process, a DRIE process, a plasma etching process, etc.), a wet etching process, some other suitable etching process, or any combination thereof. In addition, after the second etching process, a removal process is performed to remove the masking structure ( Figure 36 3502). The first opening 3702 includes a through hole opening ( Figure 36 3602) is located below the fourth dielectric layer 128d.

[0118] like Figure 38 As shown in the cross-sectional view 3800, at the first opening and the second opening ( Figure 37Conductive source / drain vias 138 and second source / drain structure pairs 140, 142 are formed in the substrate 3702, 3704) to form an n-channel transistor 131b above the p-channel transistor 131a and define or form the electronic device 130 above the FEOL structure 104. The conductive source / drain vias 138 and second source / drain structure pairs 140, 142 may be as shown. Figure 16 are formed as shown and / or described in .

[0119] Figure 39 A flow chart of some embodiments of a method 3900 for forming an integrated chip (IC) having an electronic device including transistors stacked vertically on each other according to an embodiment of the present disclosure is shown. Although method 3900 is shown and / or described as a series of steps or events, it should be understood that the method is not limited to the order or steps shown. Therefore, in some embodiments, the steps may be performed in an order different from that shown, and / or may be performed simultaneously. In addition, in some embodiments, the steps or events shown may be subdivided into multiple steps or events, which may be performed at a separate time or simultaneously with other steps or sub-steps. In some embodiments, some of the steps or events shown may be omitted, and other steps or events not shown may be included.

[0120] In step 3902, a FEOL structure is formed on a semiconductor substrate, and a lower BEOL structure is formed on the FEOL structure. The FEOL structure includes one or more lower semiconductor devices on the semiconductor substrate. Figure 6 A cross-sectional view 600 corresponding to various embodiments of step 3902 is shown.

[0121] In step 3904, a first source / drain structure pair is formed in a first dielectric layer over the lower BEOL structure. Figure 7 and Figure 8 Cross-sectional views 700 and 800 corresponding to various embodiments of step 3904 are shown.

[0122] In step 3906 , a first semiconductor layer is formed on the first source / drain structure pair, wherein the first semiconductor layer comprises a first conductivity type. Figure 9 A cross-sectional view 900 corresponding to various embodiments of step 3906 is shown. Figure 28 and Figure 29 Cross-sectional views 2800 and 2900 corresponding to some other embodiments of step 3906 are shown.

[0123] In step 3908, a first gate dielectric layer is formed on the first semiconductor layer. Figure 9 A cross-sectional view 900 corresponding to various embodiments of step 3908 is shown. Figure 30A cross-sectional view 3000 corresponding to some other embodiments of step 3908 is shown.

[0124] In step 3910, a gate electrode is formed in a second dielectric layer on the first gate dielectric layer, thereby defining a p-channel transistor over the lower BEOL structure. Figure 10 and Figure 11 Cross-sectional views 1000 and 1100 corresponding to some embodiments of step 3910 are shown. Figure 30 and Figure 31 Cross-sectional views 3000 and 3100 corresponding to some other embodiments of step 3910 are shown.

[0125] In step 3912, a second gate dielectric layer is formed on the gate electrode and the second dielectric layer. Figure 12 A cross-sectional view 1200 corresponding to various embodiments of step 3912 is shown. Figure 22 A cross-sectional view 2200 corresponding to some other embodiments of step 3912 is shown. Figure 32 A cross-sectional view 3200 corresponding to a further embodiment of step 3912 is shown.

[0126] In step 3914 , a second semiconductor layer is formed on the second gate dielectric layer, wherein the second semiconductor layer comprises a second conductivity type opposite to the first conductivity type. Figure 12 A cross-sectional view 1200 corresponding to various embodiments of step 3914 is shown. Figure 22 A cross-sectional view 2200 corresponding to some other embodiments of step 3914 is shown. Figure 32 and Figure 33 Cross-sectional views 3200 and 3300 corresponding to some other embodiments of step 3914 are shown.

[0127] In step 3916, a conductive source / drain via is formed on a first source / drain structure in a first source / drain structure pair. Figures 13 to 16 Cross-sectional views 1300 - 1600 corresponding to various embodiments of step 3916 are shown. Figures 18 to 21 and Figures 23 to 26 Cross-sectional views 1800 - 2100 and 2300 - 2600 corresponding to some other embodiments of step 3916 are shown. Figures 35 to 38 Cross-sectional views 3500 - 3800 corresponding to further embodiments of step 3916 are shown.

[0128] In step 3918, a second pair of source / drain structures is formed in a third dielectric layer over the second semiconductor layer to form n-channel transistors and electronic devices in the BEOL structure over the FEOL structure. A first source / drain structure of the second pair of source / drain structures is positioned over the conductive source / drain via. Figure 15 and Figure 16 Cross-sectional views 1500 and 1600 corresponding to various embodiments of step 3918 are shown. Figure 25 and Figure 26 Cross-sectional views 2500 and 2600 corresponding to some other embodiments of step 3918 are shown. Figure 37 and Figure 38 Cross-sectional views 3700 and 3800 corresponding to further embodiments of step 3918 are shown.

[0129] Thus, in some embodiments, the present application relates to an IC including an electronic device disposed in a BEOL structure above a semiconductor substrate, wherein the electronic device includes an n-channel transistor above a p-channel transistor.

[0130] In some embodiments, the present application provides an integrated chip (IC) comprising: a lower dielectric structure located above a semiconductor substrate; a gate structure located above the lower dielectric structure, wherein the gate structure comprises a first surface opposite to a second surface; a first semiconductor layer disposed between the first surface of the gate structure and the lower dielectric structure; and a second semiconductor layer disposed above the second surface of the gate structure. In an embodiment, the IC further comprises: a plurality of conductive lines and a plurality of conductive vias disposed in the lower dielectric structure and below the first semiconductor layer and the second semiconductor layer. In an embodiment, the gate structure comprises a gate electrode, a first gate dielectric layer, and a second gate dielectric layer, wherein the first gate dielectric layer is disposed between the gate electrode and the first semiconductor layer, and wherein the second gate dielectric layer is disposed between the gate electrode and the second semiconductor layer. In an embodiment, the IC further comprises: a first source / drain structure pair disposed on the first semiconductor layer and spaced apart on opposite sides of the gate electrode; and a second source / drain structure pair disposed above the second semiconductor layer and spaced apart on opposite sides of the gate electrode. In an embodiment, the IC further comprises: a conductive via extending vertically from a first source / drain structure in the first source / drain structure pair to a first source / drain structure in the second source / drain structure pair. In an embodiment, the conductive via directly contacts opposing sidewalls of the first semiconductor layer and opposing sidewalls of the second semiconductor layer. In an embodiment, outer sidewalls of the first semiconductor layer are spaced apart between the first source / drain structure pair, wherein outer sidewalls of the second semiconductor layer are spaced apart between the second source / drain structure pair. In an embodiment, the first semiconductor layer comprises a first material, the second semiconductor layer comprises a second material, and the semiconductor substrate comprises a third material, wherein the first material, the second material, and the third material are different from one another.

[0131] In some embodiments, the present application provides an integrated chip (IC) comprising: a lower interconnect structure located above a semiconductor substrate; a first semiconductor device located above the lower interconnect structure, wherein the first semiconductor device comprises a first source / drain structure pair above the lower interconnect structure, a first semiconductor layer above the first source / drain structure pair, and a first gate dielectric layer above the first semiconductor layer; a gate electrode located above the first gate dielectric layer; and a second semiconductor device located above the first semiconductor device, wherein the second semiconductor device comprises a second gate dielectric layer above the gate electrode, a second semiconductor layer above the second gate dielectric layer, and a second source / drain structure pair above the second semiconductor layer. In some embodiments, the IC further comprises: a first dielectric layer disposed between the first gate dielectric layer and the second gate dielectric layer, wherein the first dielectric layer laterally wraps around the gate electrode. In some embodiments, the first semiconductor device is configured as a p-channel transistor, and the second semiconductor device is configured as an n-channel transistor. In some embodiments, outer sidewalls of the first semiconductor layer are spaced apart between the first source / drain structure pair, and outer sidewalls of the second semiconductor layer are spaced apart between the second source / drain structure pair. In an embodiment, the first gate dielectric layer directly contacts opposite sidewalls of the first semiconductor layer. In an embodiment, the first semiconductor layer includes a first metal oxide, and the second semiconductor layer includes a second metal oxide different from the first metal oxide. In an embodiment, the IC further includes: a transistor disposed on the semiconductor substrate, wherein the transistor includes a pair of source / drain regions disposed in the semiconductor substrate and a lower gate electrode on the semiconductor substrate located between the pair of source / drain regions, wherein an independent source / drain region in the pair of source / drain regions is electrically coupled to a first source / drain structure in the pair of first source / drain structures via a lower interconnect structure.

[0132] In some embodiments, the present application provides a method for forming an integrated chip (IC), the method comprising: forming a lower interconnect structure above a semiconductor substrate; forming a first source / drain structure pair above the lower interconnect structure; depositing a first semiconductor layer above the first source / drain structure pair; depositing a first gate dielectric layer above the first semiconductor layer; forming a gate electrode on the first gate dielectric layer; forming a second gate dielectric layer above the gate electrode; forming a second semiconductor layer above the second gate dielectric layer; and forming a second source / drain structure pair above the second semiconductor layer. In some embodiments, the method further comprises: forming a conductive via between the first source / drain structure in the first source / drain structure pair and the second source / drain structure in the second source / drain structure pair. In some embodiments, the conductive via and the second source / drain structure are formed simultaneously. In some embodiments, forming the gate electrode comprises: depositing a dielectric layer on the first gate dielectric layer; etching the dielectric layer to form an opening in the dielectric layer; depositing one or more conductive materials in the opening; and performing a planarization process on the one or more conductive materials. In an embodiment, depositing the one or more conductive materials includes depositing a liner layer in the opening and depositing a conductive core over the liner layer.

[0133] Some embodiments of the present application provide an integrated chip, comprising: a lower dielectric structure located above a semiconductor substrate; a gate structure located above the lower dielectric structure, wherein the gate structure includes a first surface opposite to a second surface; a first semiconductor layer arranged between the first surface of the gate structure and the lower dielectric structure; and a second semiconductor layer located above the second surface of the gate structure.

[0134] In some embodiments, the integrated circuit further comprises: a plurality of conductive lines and a plurality of conductive vias disposed in the lower dielectric structure and below the first semiconductor layer and the second semiconductor layer. In some embodiments, the gate structure comprises a gate electrode, a first gate dielectric layer, and a second gate dielectric layer, wherein the first gate dielectric layer is disposed between the gate electrode and the first semiconductor layer, and wherein the second gate dielectric layer is disposed between the gate electrode and the second semiconductor layer. In some embodiments, the integrated circuit further comprises: a first source / drain structure pair disposed on the first semiconductor layer and spaced apart on opposite sides of the gate electrode; and a second source / drain structure pair disposed above the second semiconductor layer and spaced apart on opposite sides of the gate electrode. In some embodiments, the integrated circuit further comprises: a conductive via extending vertically from a first source / drain structure in the first source / drain structure pair to a first source / drain structure in the second source / drain structure pair. In some embodiments, the conductive via directly contacts opposing sidewalls of the first semiconductor layer and opposing sidewalls of the second semiconductor layer. In some embodiments, an outer sidewall of the first semiconductor layer is spaced apart between the first source / drain structure pair, wherein an outer sidewall of the second semiconductor layer is spaced apart between the second source / drain structure pair. In some embodiments, the first semiconductor layer comprises a first material, the second semiconductor layer comprises a second material, and the semiconductor substrate comprises a third material, wherein the first material, the second material, and the third material are different from each other.

[0135] Other embodiments of the present application provide an integrated chip, comprising: a lower interconnect structure located above a semiconductor substrate; a first semiconductor device located above the lower interconnect structure, wherein the first semiconductor device comprises a first source / drain structure pair located above the lower interconnect structure, a first semiconductor layer located above the first source / drain structure pair, and a first gate dielectric layer located above the first semiconductor layer; a gate electrode located above the first gate dielectric layer; and a second semiconductor device located above the first semiconductor device, wherein the second semiconductor device comprises a second gate dielectric layer above the gate electrode, a second semiconductor layer above the second gate dielectric layer, and a second source / drain structure pair above the second semiconductor layer.

[0136] In some embodiments, the integrated circuit further comprises: a first dielectric layer disposed between the first gate dielectric layer and the second gate dielectric layer, wherein the first dielectric layer laterally wraps around the gate electrode. In some embodiments, the first semiconductor device is configured as a p-channel transistor, and the second semiconductor device is configured as an n-channel transistor. In some embodiments, outer sidewalls of the first semiconductor layer are spaced between the first source / drain structure pair, wherein outer sidewalls of the second semiconductor layer are spaced between the second source / drain structure pair. In some embodiments, the first gate dielectric layer directly contacts opposing sidewalls of the first semiconductor layer. In some embodiments, the first semiconductor layer comprises a first metal oxide, and the second semiconductor layer comprises a second metal oxide different from the first metal oxide. In some embodiments, the integrated circuit further comprises: a transistor disposed on the semiconductor substrate, wherein the transistor comprises a pair of source / drain regions disposed in the semiconductor substrate and a lower gate electrode on the semiconductor substrate located between the pair of source / drain regions, wherein the individual source / drain regions in the pair of source / drain regions are electrically coupled to the first source / drain structure in the first pair of source / drain structures via the lower interconnect structure.

[0137] Still other embodiments of the present application provide a method for forming an integrated chip, comprising: forming a lower interconnect structure above a semiconductor substrate; forming a first source / drain structure pair above the lower interconnect structure; depositing a first semiconductor layer above the first source / drain structure pair; depositing a first gate dielectric layer above the first semiconductor layer; forming a gate electrode on the first gate dielectric layer; forming a second gate dielectric layer above the gate electrode; forming a second semiconductor layer above the second gate dielectric layer; and forming a second source / drain structure pair above the second semiconductor layer.

[0138] In some embodiments, the method further comprises: forming a conductive via between a first source / drain structure in the first source / drain structure pair and a second source / drain structure in the second source / drain structure pair. In some embodiments, the conductive via and the second source / drain structure are formed simultaneously with each other. In some embodiments, forming the gate electrode comprises: depositing a dielectric layer on the first gate dielectric layer; etching the dielectric layer to form an opening in the dielectric layer; depositing one or more conductive materials in the opening; and performing a planarization process on the one or more conductive materials. In some embodiments, depositing the one or more conductive materials comprises depositing a liner layer in the opening and depositing a conductive core above the liner layer.

[0139] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art will appreciate that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. An integrated chip comprising: a lower dielectric structure located above the semiconductor substrate; a gate structure located above the lower dielectric structure, wherein the gate structure includes a first surface opposite to a second surface; a first semiconductor layer disposed between the first surface of the gate structure and the lower dielectric structure; and The second semiconductor layer is located above the second surface of the gate structure.

2. The integrated circuit according to claim 1 , further comprising: A plurality of conductive lines and a plurality of conductive vias are disposed in the lower dielectric structure and below the first semiconductor layer and the second semiconductor layer.

3. The integrated circuit according to claim 1, wherein: The gate structure includes a gate electrode, a first gate dielectric layer, and a second gate dielectric layer, wherein the first gate dielectric layer is disposed between the gate electrode and the first semiconductor layer, and wherein the second gate dielectric layer is disposed between the gate electrode and the second semiconductor layer.

4. The integrated circuit of claim 3 , further comprising: a first source / drain structure pair disposed on the first semiconductor layer and spaced apart on opposite sides of the gate electrode; as well as A second pair of source / drain structures is located over the second semiconductor layer and spaced apart on the opposite sides of the gate electrode.

5. The integrated circuit of claim 4 , further comprising: A conductive via vertically extends from the first source / drain structure in the first source / drain structure pair to the first source / drain structure in the second source / drain structure pair.

6. The integrated circuit according to claim 5, wherein: The conductive vias directly contact opposite sidewalls of the first semiconductor layer and opposite sidewalls of the second semiconductor layer.

7. The integrated circuit according to claim 4, wherein: The outer sidewalls of the first semiconductor layer are spaced apart between the first source / drain structure pairs, and the outer sidewalls of the second semiconductor layer are spaced apart between the second source / drain structure pairs.

8. The integrated circuit according to claim 1, wherein: The first semiconductor layer includes a first material, the second semiconductor layer includes a second material, and the semiconductor substrate includes a third material, wherein the first material, the second material, and the third material are different from each other.

9. An integrated chip comprising: a lower interconnect structure located above the semiconductor substrate; a first semiconductor device located above the lower interconnect structure, wherein the first semiconductor device comprises a first source / drain structure pair located above the lower interconnect structure, a first semiconductor layer located above the first source / drain structure pair, and a first gate dielectric layer located above the first semiconductor layer; a gate electrode located above the first gate dielectric layer; and A second semiconductor device is located above the first semiconductor device, wherein the second semiconductor device includes a second gate dielectric layer above the gate electrode, a second semiconductor layer above the second gate dielectric layer, and a second source / drain structure pair above the second semiconductor layer.

10. A method for forming an integrated chip, comprising: forming a lower interconnect structure over the semiconductor substrate; forming a first source / drain structure pair over the lower interconnect structure; depositing a first semiconductor layer over the first source / drain structure pair; depositing a first gate dielectric layer over the first semiconductor layer; forming a gate electrode on the first gate dielectric layer; forming a second gate dielectric layer over the gate electrode; forming a second semiconductor layer over the second gate dielectric layer; as well as A second source / drain structure pair is formed above the second semiconductor layer.

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