Display panel, method of manufacturing display panel, and electronic device

Abstract

The invention relates to a display panel, a method of manufacturing the same, and an electronic device. The display panel includes: a circuit element layer including a transistor; a common electrode on the circuit element layer; a conductive barrier wall on the common electrode and defining an outer barrier wall opening and an inner barrier wall opening; a barrier insulating layer on the conductive barrier wall; a first electrode on the barrier insulating layer and in the inner barrier wall opening and electrically connected to the transistor; a light emitting pattern on the first electrode and covering a portion of the conductive barrier wall and the barrier insulating layer; and a second electrode covering the light emitting pattern and electrically connected to the conductive barrier wall. The inner barrier wall opening of the conductive barrier wall overlaps a center of the light emitting pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0036706, filed on March 15, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to display panels and methods of manufacturing the same. For example, embodiments of the present disclosure relate to display panels with improved display quality and methods of manufacturing the same. Background Art

[0004] A display device that provides images to a user, such as a television, monitor, smartphone, and / or tablet computer, may include a display panel to display the images. Various types of display panels are being developed, such as liquid crystal display panels, organic light emitting display panels, electrowetting display panels, and / or electrophoretic display panels.

[0005] The organic light emitting display panel may include an anode, a cathode, and a light emitting pattern. The light emitting pattern may be divided into a plurality of parts arranged in a plurality of light emitting regions, and the cathode may provide a common voltage to each of the plurality of light emitting regions. Summary of the Invention

[0006] Aspects of one or more embodiments of the present disclosure are directed to a display panel including a light emitting element formed without using a metal mask and having improved display quality.

[0007] Aspects of one or more embodiments of the present disclosure relate to a method of manufacturing the display panel.

[0008] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be taught by practice of the presented embodiments of the disclosure.

[0009] One or more embodiments of the present disclosure provide a display panel, comprising: a circuit element layer including a transistor; a common electrode on the circuit element layer; a conductive barrier wall on the common electrode and defining an outer barrier wall opening and an inner barrier wall opening; a blocking insulating layer on the conductive barrier wall; a first electrode on the blocking insulating layer and in the inner barrier wall opening and electrically connected to the transistor; a light emitting pattern on the first electrode and covering a portion of the conductive barrier wall and the blocking insulating layer; and a second electrode covering the light emitting pattern and electrically connected to the conductive barrier wall. The inner barrier wall opening of the conductive barrier wall overlaps with the center of the light emitting pattern.

[0010] In one or more embodiments, the inner barrier wall opening may have a polygonal shape.

[0011] In one or more embodiments, the inner barrier wall opening may have a circular shape.

[0012] In one or more embodiments, the conductive barrier wall may include a first barrier wall layer on the common electrode and a second barrier wall layer on the first barrier wall layer.

[0013] In one or more embodiments, the first barrier wall layer may include a first inner surface, the second barrier wall layer may include a second inner surface, and the first inner surface and the second inner surface may define the inner barrier wall opening and may be aligned with each other.

[0014] In one or more embodiments, the outer barrier wall opening may include a first region defined by a first outer side surface of the first barrier wall layer and a second region defined by a second outer side surface of the second barrier wall layer, the length of the first region in the first direction may be greater than the length of the second region in the first direction, and the first direction may be orthogonal (for example, perpendicular) to the thickness direction of the circuit element layer.

[0015] In one or more embodiments, the light emitting pattern may cover at least a portion of the second outer side surface of the second barrier wall layer.

[0016] In one or more embodiments, the display panel may further include an auxiliary electrode covering the second electrode and directly contacting the conductive barrier wall.

[0017] In one or more embodiments, the auxiliary electrode may cover a lower surface of the second barrier wall layer.

[0018] In one or more embodiments, the auxiliary electrode may be in contact with the first outer side surface of the first barrier wall layer.

[0019] In one or more embodiments, the auxiliary electrode may be electrically connected to the conductive barrier wall and the second electrode.

[0020] In one or more embodiments, the display panel may further include a lower encapsulation inorganic pattern covering the auxiliary electrode, and when viewed in cross-section (for example, in a direction intersecting the first direction or the second direction or in a cross-sectional view of the display panel), the lower encapsulation inorganic pattern may be separated and / or separated (for example, spaced apart or separated) from the common electrode.

[0021] In one or more embodiments, the display panel may further include a pixel defining layer, which is on the blocking insulating layer and defines a light-emitting opening passing through the pixel defining layer to expose at least a portion of the first electrode, and the light-emitting opening may overlap with the inner barrier wall opening.

[0022] One or more embodiments of the present disclosure provide a method for manufacturing a display panel. The method includes: forming a circuit element layer including a transistor and a common electrode on a base layer; forming a preliminary conductive barrier wall on the common electrode; forming an inner barrier wall opening through the preliminary conductive barrier wall; forming a blocking insulating layer on the preliminary conductive barrier wall and in the inner barrier wall opening; forming a first electrode electrically connected to the transistor on the blocking insulating layer and in the inner barrier wall opening; forming a pixel defining layer covering the first electrode and on the blocking insulating layer; etching the preliminary conductive barrier wall to form a conductive barrier wall defining an outer barrier wall opening; forming a light emitting pattern covering the first electrode and a portion of the conductive barrier wall; and forming a second electrode electrically connected to the conductive barrier wall on the light emitting pattern.

[0023] In one or more embodiments, forming the inner barrier wall opening through the preliminary conductive barrier wall may include etching the preliminary conductive barrier wall to define the inner barrier wall opening to have a polygonal shape or a circular shape.

[0024] In one or more embodiments, forming the preliminary conductive barrier wall on the common electrode may include forming a first preliminary barrier wall layer on the common electrode, and may include forming a second preliminary barrier wall layer on the first preliminary barrier wall layer. Forming the inner barrier wall opening through the preliminary conductive barrier wall may include etching the preliminary conductive barrier wall so that a first inner surface of the first preliminary barrier wall layer is aligned with a second inner surface of the second preliminary barrier wall layer.

[0025] In one or more embodiments, etching the preliminary conductive barrier wall to form the conductive barrier wall defining the outer barrier wall opening may include: performing a first etching on the first preliminary barrier wall layer and the second preliminary barrier wall layer; and performing a second etching on the first preliminary barrier wall layer to form a first barrier wall layer and a second barrier wall layer.

[0026] In one or more embodiments, the method may further include forming an auxiliary electrode, wherein the auxiliary electrode covers the second electrode, the auxiliary electrode may be in direct contact with the conductive barrier wall, and the auxiliary electrode may electrically connect the conductive barrier wall and the second electrode.

[0027] In one or more embodiments, the method may further include forming a lower encapsulation inorganic pattern covering the auxiliary electrode and being spaced apart and / or separated (eg, spaced apart or separated) from the common electrode when viewed in a cross-section.

[0028] One or more embodiments of the present disclosure provide an electronic device, the electronic device comprising: a circuit element layer including a transistor; a common electrode on the circuit element layer; a conductive barrier wall including a first barrier wall layer on the common electrode and a second barrier wall layer on the first barrier wall layer, and defining an outer barrier wall opening and an inner barrier wall opening through the conductive barrier wall; a first electrode on the conductive barrier wall and in the inner barrier wall opening, and electrically connected to the transistor through the inner barrier wall opening; a light emitting pattern on the first electrode and covering a portion of the second barrier wall layer; a second electrode covering the light emitting pattern; and an auxiliary electrode covering the second electrode and contacting a lower surface of the second barrier wall layer and a first outer side surface of the first barrier wall layer. When viewed in a plane (e.g., in a plan view of a display panel of the electronic device), the outer barrier wall opening is around (e.g., surrounds) the inner barrier wall opening, and the auxiliary electrode is electrically connected to the conductive barrier wall and the second electrode.

[0029] According to one or more embodiments, an inner barrier wall opening is formed to overlap with a light-emitting area, and the first electrode is electrically connected to the circuit element layer through the inner barrier wall opening of the conductive barrier wall. Because the light-emitting area and the inner barrier wall opening overlap, the size of the area from which light is emitted increases. Furthermore, because the light-emitting element is formed in the inner barrier wall opening without a tip portion and on the conductive barrier wall, shadow areas during the deposition process are reduced or prevented. Thus, a display panel capable of (easily) achieving high resolution is provided while reducing the thickness of the conductive barrier wall. The lower encapsulation inorganic pattern covering the light-emitting element formed on the conductive barrier wall has a more stable and robust structure and does not protrude from the center. In other words, the inner barrier wall opening can overlap with the light-emitting area, allowing the first electrode to be connected to the circuit element layer through this opening. This overlap increases the light-emitting area. Furthermore, forming the light-emitting element within the inner barrier wall opening and on the conductive barrier wall reduces shadow areas during deposition. Therefore, the display panel supports high resolution and reduces the thickness of the conductive barrier wall. The lower encapsulation inorganic pattern covering the light-emitting element located on the conductive barrier wall is more stable and robust and does not protrude from the center. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects, features and / or principles of the embodiments of the present disclosure will become more apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings. In the accompanying drawings:

[0031] Figure 1A is a perspective view of a display device according to one or more embodiments of the present disclosure;

[0032] Figure 1B is an exploded perspective view of a display device according to one or more embodiments of the present disclosure;

[0033] Figure 2 is a cross-sectional view of a display module according to one or more embodiments of the present disclosure;

[0034] Figure 3 is a plan view of a display panel according to one or more embodiments of the present disclosure;

[0035] Figure 4 is an enlarged plan view of a portion of a display area of ​​a display panel according to one or more embodiments of the present disclosure;

[0036] Figure 5 According to one or more embodiments of the present disclosure Figure 4 A cross-sectional view taken along line II';

[0037] Figure 6 According to one or more embodiments of the present disclosure Figure 4 a cross-sectional view of a portion of the display panel taken along line II-II'; and

[0038] Figures 7A to 7N are cross-sectional views illustrating processes of a method of manufacturing a display panel according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0039] The present disclosure can be modified in many alternative forms, and therefore specific embodiments will be shown in the drawings and described in more detail. However, it should be understood that this is not intended to limit the present disclosure to the particular forms disclosed, but is intended to cover all modifications, equivalents and substitutes falling within the spirit and scope of the present disclosure.

[0040] Hereinafter, example embodiments will be described in more detail with reference to the accompanying drawings. However, the present disclosure may be implemented in a variety of different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that the present disclosure will be thorough and complete and will fully convey the aspects and features of the present disclosure to those skilled in the art. Therefore, processes, elements, and techniques that are not necessary for a person of ordinary skill in the art to fully understand the various aspects and features of the present disclosure may not be described.

[0041] It will be understood that when an element, such as a region, layer, film, area, or portion, is referred to as being “on,” “connected to,” or “coupled to” another element, the element can be directly on, directly connected to, or coupled to the other element, or one or more intervening elements may be present. In contrast, when an element or layer is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another element or layer, no intervening elements or layers are present. Additionally, it will be understood that when an element is referred to as being “between” two elements, the element can be the only element between the two elements, or one or more intervening elements may also be present.

[0042] Unless otherwise specified, the same reference numerals denote the same elements throughout the drawings and the written description, and therefore, a repeated description thereof may not be provided. In the drawings, the thickness, proportions, and sizes of components may be exaggerated for the sake of efficient description and / or clarity. In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for the sake of efficient description and / or clarity.

[0043] As used herein, the term "and / or" may include any and all combinations of one or more of the associated listed items.

[0044] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section described below may be referred to as a second element, component, region, layer, or section without departing from the spirit and scope of the present disclosure.

[0045] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0046] For ease of explanation, spatially relative terms such as “on,” “below,” “below,” “below,” “above,” and “on” may be used herein to describe the relationship of one element or feature to other elements or features as shown in the figures. It will be understood that the spatially relative terms are intended to cover different orientations of the device in use or in operation in addition to the orientations depicted in the accompanying drawings. For example, if the device in the figure is turned over, the elements described as “below” or “beneath” or “below” other elements or features will be oriented as “above” other elements or features. Thus, the example terms “below” and “below” can cover both orientations of above and below. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative terms used in this article should be interpreted accordingly.

[0047] It will be further understood that when the terms “comprises / comprising,” “includes / including,” and “have / having” are used in this specification, they indicate the presence of stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0048] Unless otherwise apparent from the present disclosure, expressions such as “at least one of,” “a plurality of,” “one of,” and other prepositional phrases, when preceding or following a list of elements, should be understood to include a disjunctive list if written as a conjunction, and vice versa. For example, the expression “at least one of a, b, and c,” “one selected from the group consisting of a, b, and c,” “at least one selected from a, b, and c,” “at least one of a, b, and c,” “one of a, b, and c,” “at least one of a through c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0049] As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that, unless expressly defined as such herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense.

[0051] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0052] Figure 1A is a perspective view of a display device DD according to one or more embodiments of the present disclosure. Figure 1B is an exploded perspective view of a display device DD according to one or more embodiments of the present disclosure.

[0053] The display device DD can be applied to large-sized electronic devices such as televisions, monitors, or outdoor billboards. Furthermore, the display device DD can be applied to medium-sized and small-sized electronic devices such as personal computers, notebook computers, personal digital assistants, car navigation units, gaming units, smartphones, tablet computers, and / or cameras. However, these are merely examples, and the display device DD can be employed in other display devices without departing from the spirit and scope of the present disclosure. Figure 1A and Figure 1B A smartphone is shown as a representative example of the display device DD.

[0054] refer to Figure 1A and Figure 1B The display device DD may display an image IM through a display surface FS substantially parallel to each of the first direction DR1 and the second direction DR2, and may display the image IM toward a third direction DR3. The image IM may include a still image as well as a video. Figure 1A A clock widget and application icons are shown as representative examples of the image IM. The display surface FS through which the image IM is displayed may correspond to the front surface of the display device DD.

[0055] In one or more embodiments, the front (or upper) surface and the rear (or lower) surface of each component of the display device DD can be defined relative to the direction in which the display image IM is located. The front surface and the rear surface may face away from each other in the third direction DR3, and the normal (vertical) direction of each of the front surface and the rear surface may be substantially parallel to the third direction DR3. In one or more embodiments, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 may be relative to each other, and therefore, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 may be changed to other directions. In the following description, the expression "when viewed in a plane" refers to a state viewed from the top (e.g., upper surface) of the device in the third direction DR3, that is, a plan view.

[0056] The display device DD may include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU may be coupled to each other to provide an exterior of the display device DD.

[0057] The window WP may include an optically transparent insulating material. For example, the window WP may include glass or plastic. The front surface of the window WP may define a display surface FS of the display device DD. The display surface FS may include a transmissive area TA and a bezel area BZA. The transmissive area TA may be an optically transparent area. As an example, the transmissive area TA may have a visible light transmittance of approximately 90% or greater.

[0058] The border area BZA may be a region having a transmittance relatively lower than that of the transmission area TA. The border area BZA may define the shape of the transmission area TA. The border area BZA may be arranged adjacent to the transmission area TA and may be around the transmission area TA (e.g., may surround the transmission area TA). However, this is merely an example, and the border area BZA may not be provided in the window WP. The window WP may include at least one functional layer selected from an anti-fingerprint layer, a hard coating layer, and an anti-reflection layer. However, the present disclosure is not limited thereto.

[0059] The display module DM may be arranged below the window WP. The display module DM may have a configuration that (substantially) generates an image IM. The image IM generated by the display module DM may be displayed through the display surface IS of the display module DM and may be viewed by a user through the transmissive area TA.

[0060] The display surface IS of the display module DM may include a display area DA and a non-display area NDA. The display area DA may be activated in response to an electrical signal. The non-display area NDA may be adjacent to the display area DA. The non-display area NDA may be around (e.g., surround) the display area DA. The non-display area NDA may be covered by a bezel area BZA and may not be visible from the outside.

[0061] The housing HAU may be coupled to the window WP. The housing HAU and the window WP coupled to each other may provide a set or predetermined inner space. The display module DM may be accommodated in the inner space.

[0062] The housing HAU may be made of a relatively rigid material. For example, the housing HAU may include multiple frames and / or panels made of glass, plastic, or metal, or a combination thereof. The housing HAU can stably protect the components of the display device DD housed within the interior space from external impacts.

[0063] Figure 2 is a cross-sectional view of a display module DM according to one or more embodiments of the present disclosure.

[0064] refer to Figure 2 , the display module DM may include a display panel DP and an input sensor INS. In one or more embodiments, the display device DD (see, for example, Figure 1A ) may further include a protection member disposed on the lower surface of the display panel DP or an anti-reflection member and / or a window member disposed on the upper surface of the input sensor INS.

[0065] The display panel DP may be a display panel of a light-emitting type or kind; however, the present disclosure is not limited thereto. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include quantum dots, quantum rods, or micro light-emitting diodes (LEDs). Hereinafter, the organic light-emitting display panel will be described as the display panel DP.

[0066] The display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin-film encapsulation layer TFE. The circuit element layer DP-CL, the display element layer DP-OLED, and the thin-film encapsulation layer TFE may be arranged on the base layer BL. The input sensor INS may be arranged directly on the thin-film encapsulation layer TFE. In the present disclosure, the phrase "component A is arranged directly on component B" means that there is no adhesive layer between components A and B.

[0067] The base layer BL may include at least one plastic film. The base layer BL may be a flexible substrate and may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite material substrate. Figure 1B The described display area DA and non-display area NDA may also be defined in the base layer BL.

[0068] The circuit element layer DP-CL may include at least one insulating layer and circuit elements. The insulating layer may include at least one inorganic layer and at least one organic layer. The circuit elements may include signal lines and pixel driving circuits.

[0069] The display element layer DP-OLED may include a conductive barrier and a light emitting element. The light emitting element may include an anode, an intermediate layer, and a cathode.

[0070] The thin film encapsulation layer TFE may include a plurality of thin layers, some of which may be arranged to improve optical efficiency, and some of which may be arranged to protect the organic light emitting diode.

[0071] The input sensor INS can obtain coordinate information of an external input. The input sensor INS can have a multi-layer structure. The input sensor INS can include a conductive layer having a single layer or a multi-layer structure. The input sensor INS can include an insulating layer having a single layer or a multi-layer structure. The input sensor INS can sense the external input using a capacitive method; however, the present disclosure should not be limited thereto or thereby. As an example, the input sensor INS can sense the external input using an electromagnetic induction method or a pressure sensing method. In one or more embodiments, the input sensor INS may not be provided.

[0072] Figure 3 is a plan view of a display panel DP according to one or more embodiments of the present disclosure.

[0073] refer to Figure 3 The display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA. The display panel DP may include pixels PX and signal lines SGL electrically connected to the pixels PX. The display panel DP may include a drive circuit GDC and a pad portion PLD. The display area DA and the non-display area NDA may be distinguished from each other by the presence or absence of the pixels PX. The pixels PX may be arranged in the display area DA. The drive circuit GDC and the pad portion PLD may be arranged in the non-display area NDA.

[0074] The pixels PX may be arranged in the first direction DR1 and the second direction DR2. The pixels PX may include a plurality of pixel rows extending in the first direction DR1 and arranged in the second direction DR2, and a plurality of pixel columns extending in the second direction DR2 and arranged in the first direction DR1.

[0075] The signal lines SGL may include gate lines GL, data lines DL, power lines PL, and control signal lines CSL. Each of the plurality of gate lines GL may be connected to a corresponding pixel among the pixels PX, and each of the plurality of data lines DL may be connected to a corresponding pixel among the pixels PX. The power lines PL may be electrically connected to the pixels PX. The control signal lines CSL may be connected to the drive circuit GDC and may provide control signals to the drive circuit GDC.

[0076] The driving circuit GDC may include a gate driving circuit. The gate driving circuit may generate a plurality of gate signals and sequentially output the gate signals to the gate lines GL. The gate driving circuit may also output other control signals to the pixel driving circuit.

[0077] The pad portion PLD may be connected to a flexible circuit board. The pad portion PLD may include pixel pads D-PD, and the pixel pads D-PD may be pads for connecting the flexible circuit board to the display panel DP. Each of the plurality of pixel pads D-PD may be connected to a corresponding signal line among the signal lines SGL. The pixel pads D-PD may be connected to the corresponding pixel PX via the signal lines SGL. In addition, the drive circuit GDC may be connected to one of the pixel pads D-PD.

[0078] In addition, the pad portion PLD may further include an input pad. The input pad may be used to connect the flexible circuit board to the input sensor INS (see, for example, Figure 2 ) pads; however, the present disclosure should not be limited thereto or thereby. According to one or more embodiments, the input pads may be arranged on the input sensor INS (see, for example Figure 2 ) and may be connected to a circuit board different from the circuit board to which the pixel pad D-PD is connected. According to one or more embodiments, the input sensor INS may not be provided (see, for example Figure 2 ), and the pad portion PLD may not further include an input pad.

[0079] Figure 4 is a display panel DP according to one or more embodiments of the present disclosure (see, for example, Figure 2 ) of the display area DA (see, for example, Figure 2 ) is an enlarged plan view of a portion of the ). Figure 4 is shown when the display module DM (see for example Figure 1B ) of the display surface IS (see e.g. Figure 1B ) is a plan view of the display module DM when viewed from an upper side of FIG. 4 , and shows the arrangement of the light emitting areas PXA-R, PXA-G and PXA-B and the conductive barrier walls PW.

[0080] refer to Figure 4, the display area DA may include a first light-emitting area PXA-R, a second light-emitting area PXA-G, and a third light-emitting area PXA-B, and a peripheral area NPXA around the first light-emitting area PXA-R, the second light-emitting area PXA-G, and the third light-emitting area PXA-B (for example, surrounding the first light-emitting area PXA-R, the second light-emitting area PXA-G, and the third light-emitting area PXA-B). The first light-emitting area PXA-R, the second light-emitting area PXA-G, and the third light-emitting area PXA-B may respectively correspond to areas from which light provided by the light-emitting element is emitted. The first light-emitting area PXA-R, the second light-emitting area PXA-G, and the third light-emitting area PXA-B may be provided by a display module DM (see, for example, FIG. 2 ). Figure 2 )The colors of the light emitted outward are distinguished from each other.

[0081] The first light-emitting area PXA-R, the second light-emitting area PXA-G, and the third light-emitting area PXA-B can respectively provide a first color light, a second color light, and a third color light having different colors from each other. As an example, the first color light can be red light, the second color light can be green light, and the third color light can be blue light. However, the first color light, the second color light, and the third color light should not be limited to this or thereby.

[0082] Each of the first, second, and third light-emitting regions PXA-R, PXA-G, and PXA-B can be defined as a region through which the upper surface of the anode is exposed by a light-emitting opening, which will be described in more detail later. The peripheral region NPXA can define a boundary between the first, second, and third light-emitting regions PXA-R, PXA-G, and PXA-B, and can prevent or reduce mixing of colors of light between the first, second, and third light-emitting regions PXA-R, PXA-G, and PXA-B. In other words, the peripheral region NPXA can prevent or reduce the possibility of light (e.g., light of different colors) from the first, second, and third light-emitting regions PXA-R, PXA-G, and PXA-B mixing in the region between the first, second, and third light-emitting regions PXA-R, PXA-G, and PXA-B.

[0083] Each of the first light-emitting areas PXA-R, the second light-emitting areas PXA-G, and the third light-emitting areas PXA-B may be provided in plural numbers and may be repeatedly arranged in a set or predetermined arrangement within the display area DA. As an example, the first light-emitting areas PXA-R and the third light-emitting areas PXA-B may be arranged alternately with each other in the first direction DR1 to form a first group. The second light-emitting areas PXA-G may be arranged in the first direction DR1 to form a second group. Each of the first group and the second group may be provided in plural numbers, and the first group may be arranged alternately with the second group in the second direction DR2.

[0084] One second light emitting area PXA-G may be arranged to be spaced apart and / or separated (eg, spaced apart or separated) from one first light emitting area PXA-R or one third light emitting area PXA-B in a fourth direction DR4. The fourth direction DR4 may correspond to a direction between the first direction DR1 and the second direction DR2.

[0085] For example, Figure 4 1 and 2 are representative examples of the arrangement of the first light-emitting area PXA-R, the second light-emitting area PXA-G, and the third light-emitting area PXA-B, and the arrangement of the first light-emitting area PXA-R, the second light-emitting area PXA-G, and the third light-emitting area PXA-B can be changed in one or more suitable ways and should not be particularly limited. The first light-emitting area PXA-R, the second light-emitting area PXA-G, and the third light-emitting area PXA-B can be arranged as follows: Figure 4 The five-tile pattern shown in ( is an officially registered trademark of Samsung Display Co., Ltd.) is arranged. According to one or more embodiments, the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B may be arranged in a stripe pattern or a diamond pattern. is an officially registered trademark of Samsung Display Co., Ltd.) layout.

[0086] When viewed in a plane, each of the first light-emitting area PXA-R, the second light-emitting area PXA-G, and the third light-emitting area PXA-B may have various shapes. As an example, each of the first light-emitting area PXA-R, the second light-emitting area PXA-G, and the third light-emitting area PXA-B may have a polygonal shape, a circular shape, or an elliptical shape. Figure 4 , as a representative example, a first light emitting region PXA-R, a second light emitting region PXA-G, and a third light emitting region PXA-B, each having a circular shape, are illustrated.

[0087] When viewed in a plane (e.g., in a plan view), the first light-emitting area PXA-R, the second light-emitting area PXA-G, and the third light-emitting area PXA-B may have substantially the same shape as one another, or at least one of the first light-emitting area PXA-R, the second light-emitting area PXA-G, and the third light-emitting area PXA-B may have a shape different from that of the other light-emitting areas. Figure 4 The structure in which the first light-emitting area PXA-R, the second light-emitting area PXA-G, and the third light-emitting area PXA-B have the same shape as each other when viewed in a plane is shown; however, the present disclosure should not be limited thereto or thereby. As an example, when viewed in a plane, as a representative example, the first light-emitting area PXA-R and the third light-emitting area PXA-B may have the same shape as each other, and the second light-emitting area PXA-G may have a shape different from the shapes of the first light-emitting area PXA-R and the third light-emitting area PXA-B.

[0088] Figure 4 The first, second, and third light-emitting regions PXA-R, PXA-G, and PXA-B are shown as having substantially the same size when viewed in a planar manner; however, the present disclosure should not be limited thereto or thereby. As an example, when viewed in a planar manner, at least one of the first, second, and third light-emitting regions PXA-R, PXA-G, and PXA-B may have a size that is different from that of the other light-emitting regions. According to one or more embodiments, the size of the first light-emitting region PXA-R, which emits red light, may be larger than the size of the second light-emitting region PXA-G, which emits green light, and may be smaller than the size of the third light-emitting region PXA-B, which emits blue light.

[0089] In one or more embodiments, the display module DM (see e.g. Figure 2 ) of the first light emitting area PXA-R, the second light emitting area PXA-G and the third light emitting area PXA-B can be shaped, sized and arranged in accordance with the color of the emitted light, the display module DM (see, for example Figure 2 ) and the dimensions of the display module DM (see e.g. Figure 2 ) are designed in one or more suitable ways, and they should not be limited to Figure 4 One or more embodiments shown in .

[0090] The conductive barrier wall PW may be provided with an inner barrier wall opening OP-PI and an outer barrier wall opening OP-PO defined therethrough. When viewed in a plane, the inner barrier wall opening OP-PI may overlap with the center of each of the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B. For example, when viewed in a plane, the inner barrier wall opening OP-PI may overlap with the first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3 (see, for example, FIG. 1 ), which will be described in more detail later. Figure 6 ) overlaps with the center of each of the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B in a plan view. For example, in a plan view, the inner barrier wall opening OP-PI may overlap with the center of each of the first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3 (see, for example Figure 6 ) overlaps with the center of each of them.

[0091] When viewed in a plane, the inner barrier wall opening OP-PI and the outer barrier wall opening OP-PO may have various shapes. As an example, each of the inner barrier wall opening OP-PI and the outer barrier wall opening OP-PO may have a polygonal shape, a circular shape, or an elliptical shape. Figure 4, as a representative example, an inner barrier wall opening OP-PI and an outer barrier wall opening OP-PO each having a circular shape when viewed in a plane are shown.

[0092] When viewed in a plane, the inner barrier wall opening OP-PI of the conductive barrier wall PW may be aligned with the first electrode AE ​​(or anode AE, see e.g. Figure 5 ), and the outer barrier wall opening OP-PO of the conductive barrier wall PW may be spaced and / or separated (e.g., spaced apart or separated) from the first electrode AE, which will be described in more detail later. When viewed in a plane, the outer barrier wall opening OP-PO may be around (e.g., surround) the inner barrier wall opening OP-PI.

[0093] Figure 5 According to one or more embodiments of the present disclosure Figure 4 A cross-sectional view taken along line II'. Figure 5 In the Figure 2 , and therefore, a detailed description of the same elements may not be provided.

[0094] Figure 5 is the display area DA (see e.g. Figure 4 ) is an enlarged view of a light emitting area PXA, and Figure 5 The light emitting area PXA corresponds to the first light emitting area PXA-R, the second light emitting area PXA-G and the third light emitting area PXA-B (see, for example Figure 4 ).

[0095] refer to Figure 5 The display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and a thin film encapsulation layer TFE.

[0096] The display panel DP may include multiple insulating layers, semiconductor patterns, and conductive patterns such as signal lines. The insulating layers, semiconductor layers, and conductive layers may be formed through coating or deposition processes. The insulating layers, semiconductor layers, and conductive layers may then be selectively patterned through photolithography and etching processes. The semiconductor patterns and conductive patterns such as signal lines included in the circuit element layer DP-CL and the display element layer DP-OLED may be formed through the above processes.

[0097] The circuit element layer DP-CL may be disposed on the base layer BL. The circuit element layer DP-CL may include a buffer layer BFL, a transistor TR1, a signal transmission region SCL, a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, and a fifth insulating layer 50, an electrode EE, and a plurality of connection electrodes CNE1 and CNE2.

[0098] The buffer layer BFL may be disposed on the base layer BL. The buffer layer BFL may increase adhesion between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer, and the silicon oxide layer and the silicon nitride layer may be alternately stacked with each other.

[0099] The semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon; however, the present disclosure should not be limited thereto or thereby. The semiconductor pattern may include amorphous silicon or metal oxide. Figure 5 A portion of the semiconductor pattern is shown, and the semiconductor pattern may be further arranged in the light emitting regions PXA-R, PXA-G, and PXA-B (see, for example Figure 4 ). The semiconductor pattern may be arranged in a specific pattern throughout the light-emitting regions PXA-R, PXA-G, and PXA-B. The semiconductor pattern may have different electrical properties depending on whether it is doped. The semiconductor pattern may include a first region having a relatively high doping concentration and a second region having a relatively low doping concentration. The first region may be doped with an N-type (kind) dopant or a P-type (kind) dopant. A P-type (kind) transistor may include a first region doped with a P-type (kind) dopant.

[0100] The first region may have a greater conductivity than the second region and may be substantially used as an electrode or signal line. The second region may substantially correspond to an active portion (e.g., an active region or channel) of a transistor. For example, a portion of the semiconductor pattern may be the active portion of a transistor, another portion of the semiconductor pattern may be the source or drain of the transistor, and the remaining portion of the semiconductor pattern may be a conductive region.

[0101] The source S, the active portion (eg, active region) A, and the drain D of the transistor TR1 may be formed of a semiconductor pattern. Figure 5 A portion of a signal transmission region SCL formed of a semiconductor pattern is shown. In one or more embodiments, the signal transmission region SCL may be connected to the drain D of the transistor TR1 in a plane (e.g., along the same plane). For example, the signal transmission region SCL may be connected to the drain D of the transistor TR1 in the same plane.

[0102] The first to fifth insulating layers 10, 20, 30, 40, and 50 may be disposed on the buffer layer BFL. Each of the first to fifth insulating layers 10 to 50 may be an inorganic layer or an organic layer.

[0103] A first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the source S, active portion A, drain D, and signal transmission region SCL of the transistor TR1. The gate G (e.g., gate electrode G) of the transistor TR1 may be disposed on the first insulating layer 10. A second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the gate G. The electrode EE may be disposed on the second insulating layer 20. A third insulating layer 30 may be disposed on the second insulating layer 20 and may cover the electrode EE.

[0104] The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal transmission region SCL via a contact hole CNT-1 defined by the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30. The fourth insulating layer 40 may be disposed on the third insulating layer 30 and may cover the first connection electrode CNE1. The fourth insulating layer 40 may be an organic layer.

[0105] The second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 via a contact hole CNT-2 defined through the fourth insulating layer 40. A fifth insulating layer 50 may be disposed on the fourth insulating layer 40 and may cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer. The fifth insulating layer 50 may include a contact hole CNT-3 defined therethrough. The first electrode AE, which will be described in more detail later, may be connected to the second connection electrode CNE2 through the contact hole CNT-3.

[0106] The display element layer DP-OLED may be disposed on the circuit element layer DP-CL and may include an insulating layer IL, a common electrode BE, a conductive barrier wall PW, a blocking insulating layer IP, a light emitting element ED, and an auxiliary electrode SE.

[0107] The insulating layer IL may be disposed on the circuit element layer DP-CL. For example, the insulating layer IL may be disposed on the fifth insulating layer 50 and may cover the fifth insulating layer 50.

[0108] The common electrode BE may be disposed on the insulating layer IL. As an example, the common electrode BE may be disposed on the circuit element layer DP-CL. The common electrode BE may completely extend over the display area DA (see, for example, FIG. 2 ). Figure 4 ) is arranged (for example, arranged throughout the entire display area DA) and a common voltage can be applied. As an example, the common electrode BE can be arranged to be connected to all of the first light-emitting area PXA-R, the second light-emitting area PXA-G, and the third light-emitting area PXA-B (see, for example Figure 6 )overlapping.

[0109] The conductive barrier wall PW may be disposed on the common electrode BE. The conductive barrier wall PW may be provided with an inner barrier wall opening OP-PI and an outer barrier wall opening OP-PO. The inner barrier wall opening OP-PI may be an opening for connecting the anode AE ​​to the second connection electrode CNE2, and the outer barrier wall opening OP-PO may be an opening for patterning the light emitting pattern EP and the cathode CE without using a fine metal mask (FMM).

[0110] The inner barrier wall opening OP-PI may overlap with the center of each of the anode AE ​​and the light emitting pattern EP, and the outer barrier wall opening OP-PO may not overlap with the center of each of the anode AE ​​and the light emitting pattern EP. For example, the inner barrier wall opening OP-PI may overlap with the light emitting opening OP-E described in more detail later, and the outer barrier wall opening OP-PO may not overlap with the light emitting opening OP-E.

[0111] When viewed in a cross section (e.g., when viewed in a direction intersecting the first direction DR1 or the second direction DR2 or in a cross-sectional view), the outer barrier wall opening OP-PO of the conductive barrier wall PW may have an undercut shape. The conductive barrier wall PW may include a plurality of layers stacked sequentially, and at least one of the plurality of layers may be recessed relative to the other layers. Therefore, the conductive barrier wall PW may have a pointed portion. As a representative example, Figure 5 One undercut shape is shown, however, the shape of the outer barrier wall opening OP-PO should not be limited thereto or thereby. As an example, the outer barrier wall opening OP-PO may have two or more undercut shapes.

[0112] The conductive barrier wall PW may include a first barrier wall layer L1 and a second barrier wall layer L2. The first barrier wall layer L1 may be disposed on the common electrode BE, and the second barrier wall layer L2 may be disposed on the first barrier wall layer L1. Figure 5 As shown in , the first barrier wall layer L1 may have a thickness greater than that of the second barrier wall layer L2, but the present disclosure should not be limited thereto or thereby. According to one or more embodiments, as a representative example, Figure 5 The structure in which each of the common electrode BE, the first barrier wall layer L1, and the second barrier wall layer L2 is provided as a single layer is shown; however, the present disclosure should not be limited thereto or thereby. As an example, each of the common electrode BE, the first barrier wall layer L1, and the second barrier wall layer L2 may include two or more layers.

[0113] The first inner surface IS-L1 of the first barrier wall layer L1 and the second inner surface IS-L2 of the second barrier wall layer L2 defining the inner barrier wall opening OP-PI may be aligned with each other. For example, the inner barrier wall opening OP-PI may not have a protruding shape and may be defined by the inner surfaces IS-L1 and IS-L2 formed continuously (for example, formed to provide a continuous surface in which the first inner surface IS-L1 and the second inner surface IS-L2 are flush and flat with each other).

[0114] The first barrier wall layer L1 may be more recessed relative to the peripheral area NPXA than the second barrier wall layer L2. The first barrier wall layer L1 may be undercut relative to the second barrier wall layer L2. A portion of the second barrier wall layer L2 that protrudes from the first barrier wall layer L1 toward the center of the outer barrier wall opening OP-PO may be defined as a tip portion in the conductive barrier wall PW.

[0115] The outer barrier wall opening OP-PO may include a first area A1 defined by the first outer side surface OS-L1 of the first barrier wall layer L1 (see, eg, Figure 6 ) and a second area A2 defined by the second outer side surface OS-L2 of the second barrier wall layer L2 (see, for example Figure 6 ). The first area A1 and the second area A2 may be provided integrally with each other. The first area A1 may have a width different from that of the second area A2. As an example, the length of the first area A1 in one direction may be greater than the length of the second area A2 in the one direction (e.g., the same direction). The one direction may be orthogonal (e.g., perpendicular) to the thickness direction of the circuit element layer DP-CL (e.g., the third direction DR3). The one direction may be the first direction DR1 or the second direction DR2. For example, the second area A2 of the outer barrier wall opening OP-PO may be a region defining a tip portion. Due to the tip portion, the second area A2 may have a width smaller than the width of the first area A1.

[0116] Each of the first barrier wall layer L1, the second barrier wall layer L2, and the common electrode BE may include a conductive material. As an example, the conductive material may include a metal, a transparent conductive oxide (TCO), an organic material, an inorganic material, and / or one or more (e.g., any suitable) combinations thereof. As an example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), and / or alloys thereof. The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), and / or aluminum zinc oxide. The inorganic material may include titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), and tungsten carbide (WC). The organic material may include PEDOT:PSS, polyaniline (PANI), polypyrrole (PPy), polythiophene (PT), carbon nanotubes (CNT), and graphene. The barrier wall layer including the inorganic material may have a refractive index ranging from about 1.3 to about 2.3.

[0117] The second barrier wall layer L2 may include the same material as the common electrode BE, and the first and second barrier wall layers L1 and L2 may include different materials from each other; however, this is merely an example, and the present disclosure is not limited thereto or thereby.

[0118] Figure 5 As a representative example, the conductive barrier wall PW is shown in a structure in which each of the inner side surfaces IS-L1 and IS-L2 or each of the outer side surfaces OS-L1 and OS-L2 is perpendicular (e.g., perpendicular) to the upper surface of the common electrode BE; however, the present disclosure should not be limited thereto or thereby. As an example, the conductive barrier wall PW may have a tapered (conical) shape or a reverse tapered (inverted tapered) shape.

[0119] The blocking insulating layer IP may be disposed on the conductive barrier wall PW. The blocking insulating layer IP disposed on the conductive barrier wall PW may prevent or reduce the possibility of the conductive barrier wall PW being electrically connected to the anode AE ​​(or the first electrode). The blocking insulating layer IP may cover the conductive barrier wall PW, the common electrode BE, and the side surface of the insulating layer IL defining the inner barrier wall opening OP-PI.

[0120] The light emitting element ED may include an anode AE ​​(or a first electrode AE), a light emitting pattern EP, and a cathode CE (or a second electrode CE).

[0121] The anode AE ​​may be disposed on the blocking insulating layer IP and within the inner barrier wall opening OP-PI. When viewed in cross-section, the anode AE ​​may be disposed between the common electrode BE and the cathode CE. The anode AE ​​may be disposed on the blocking insulating layer IP and may be connected to the second connection electrode CNE2 via a contact hole CNT-3 not covered by the blocking insulating layer IP. Thus, the anode AE ​​may be electrically connected to the signal transmission region SCL via the first connection electrode CNE1 and the second connection electrode CNE2, and thus may be electrically connected to a corresponding circuit element, such as the transistor TR1.

[0122] The anode AE ​​may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The anode AE ​​may have a single-layer or multi-layer structure. The anode AE ​​may include multiple layers containing indium tin oxide (ITO) or silver (Ag). As an example, the anode AE ​​may include a layer containing indium tin oxide (ITO) (also referred to as a lower ITO layer), a layer disposed on the lower ITO layer and containing silver (Ag) (hereinafter referred to as an Ag layer), and a layer disposed on the Ag layer and containing indium tin oxide (ITO) (referred to as an upper ITO layer).

[0123] The light-emitting pattern EP may be disposed on the anode AE. The light-emitting pattern EP may include a light-emitting layer containing a light-emitting material. The light-emitting pattern EP may further include a hole injection layer (HIL) and a hole transport layer (HTL) disposed between the anode AE ​​and the light-emitting layer, and may further include an electron transport layer (ETL) and an electron injection layer (EIL) disposed on the light-emitting layer. The light-emitting pattern EP may be referred to as an organic layer or an intermediate layer.

[0124] The light emitting pattern EP may be patterned by a tip portion defined in the conductive barrier wall PW. The light emitting pattern EP may be formed on the anode AE ​​to cover a portion of the conductive barrier wall PW and the blocking insulating layer IP. As an example, the light emitting pattern EP may be patterned by a tip portion defined in the conductive barrier wall PW and may cover a side surface of the blocking insulating layer IP and at least a portion of the second outer side surface OS-L2 of the second barrier wall layer L2.

[0125] The cathode CE may be patterned by a tip portion defined in the conductive barrier wall PW. The cathode CE may cover at least a portion of the light emitting pattern EP. The cathode CE may be electrically connected to the conductive barrier wall PW through the auxiliary electrode SE.

[0126] The cathode CE may include a conductive material (e.g., a conductor). The cathode CE may be formed of one or more suitable materials having electrical conductivity (such as a metal, a transparent conductive oxide (TCO), or a conductive polymer material). As an example, the cathode CE may include silver (Ag), magnesium (Mg), lead (Pb), copper (Cu), and / or compounds thereof. The cathode CE may be electrically connected to the conductive barrier wall PW. Details of the cathode CE will be described in more detail later.

[0127] The auxiliary electrode SE may be arranged on the cathode CE (or the second electrode CE). The auxiliary electrode SE may cover the cathode CE and may be in direct contact with the conductive barrier wall PW. The auxiliary electrode SE may be in contact with the lower surface B-L2 of the second barrier wall layer L2 and the first outer side surface OS-L1 of the first barrier wall layer L1. As an example, the auxiliary electrode SE may cover the cathode CE and extend along the lower surface B-L2 of the second barrier wall layer L2 and the first outer side surface OS-L1 of the first barrier wall layer L1; however, the shape of the auxiliary electrode SE should not be limited thereto or thereby. According to one or more embodiments, the auxiliary electrode SE may include a portion covering the cathode CE and the lower surface B-L2 of the second barrier wall layer L2, and a portion that does not extend from the lower surface B-L2 of the second barrier wall layer L2 and is in contact with the first outer side surface OS-L1 of the first barrier wall layer L1.

[0128] The auxiliary electrode SE may include a conductive material. As an example, the conductive material may include a metal, a transparent conductive oxide (TCO), and / or one or more (e.g., any suitable) combinations thereof. As an example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), and / or alloys thereof. The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), and / or aluminum zinc oxide.

[0129] The auxiliary electrode SE may contact the cathode CE and the conductive barrier wall PW to electrically connect the cathode CE and the conductive barrier wall PW. The conductive barrier wall PW may receive a driving voltage (or bias voltage), and thus, the cathode CE may receive a driving voltage (or bias voltage).

[0130] The display element layer DP-OLED may further include a pixel defining layer PDL. The pixel defining layer PDL may be arranged on the blocking insulating layer IP. The pixel defining layer PDL may be provided with a light emitting opening OP-E defined therethrough to expose at least a portion of the anode AE. The light emitting opening OP-E may overlap (or correspond to) the anode AE, and at least a portion of the anode AE ​​may be exposed through the light emitting opening OP-E of the pixel defining layer PDL. The light emitting opening OP-E may overlap with the inner barrier wall opening OP-PI of the conductive barrier wall PW. The pixel defining layer PDL may include an inorganic insulating material. As an example, the pixel defining layer PDL may include silicon nitride (SiN x , where 0<x≤2).

[0131] The thin film encapsulation layer TFE may be disposed on the display element layer DP-OLED. The thin film encapsulation layer TFE may include a lower encapsulation inorganic pattern LIL, an encapsulation organic layer OL, and an upper encapsulation inorganic layer UIL.

[0132] The lower encapsulation inorganic pattern LIL may be formed to correspond to (or overlap) the light emitting opening OP-E or the inner barrier wall opening OP-PI. For example, the lower encapsulation inorganic pattern LIL may be formed to overlap the light emitting element ED. The lower encapsulation inorganic pattern LIL may be arranged on the auxiliary electrode SE and may cover the auxiliary electrode SE. When viewed in cross section, the lower encapsulation inorganic pattern LIL may be spaced and / or separated (e.g., spaced apart or separated) from the common electrode BE.

[0133] The encapsulation organic layer OL may be arranged on the lower encapsulation inorganic pattern LIL, may cover the lower encapsulation inorganic pattern LIL, and may provide a flat upper surface thereon. A portion of the encapsulation organic layer OL may be filled in a region (hereinafter referred to as a dummy region) in which the lower encapsulation inorganic pattern LIL is spaced and / or separated (e.g., spaced apart or separated) from the common electrode BE when viewed in a cross-section. However, the shape of the encapsulation organic layer OL is merely an example, and the present disclosure should not be limited thereto or thereby. As an example, the encapsulation organic layer OL may not be filled in the dummy region, and the dummy region may remain empty.

[0134] The upper encapsulation inorganic layer UIL may be disposed on the encapsulation organic layer OL. The upper encapsulation inorganic layer UIL may include an inorganic material.

[0135] The lower encapsulation inorganic pattern LIL and the upper encapsulation inorganic layer UIL may protect the display element layer DP-OLED from moisture and oxygen, and the encapsulation organic layer OL may protect the display element layer DP-OLED from foreign substances such as dust particles.

[0136] According to an embodiment of the present disclosure, the inner barrier wall opening OP-PI can be formed to overlap the light-emitting area PXA, and the first electrode AE ​​can be electrically connected to the circuit element layer DP-CL via the inner barrier wall opening OP-PI of the conductive barrier wall PW. Because the light-emitting area PXA overlaps with the inner barrier wall opening OP-PI, the light-emitting area can be increased. In addition, because the light-emitting element ED is formed in the inner barrier wall opening OP-PI without a tip portion and above the conductive barrier wall PW, the occurrence of shadow areas during the deposition process can be reduced or prevented. Therefore, a display panel DP that can easily achieve high resolution can be provided, and the thickness of the conductive barrier wall PW can be reduced. The lower encapsulation inorganic pattern LIL covering the light-emitting element ED formed on the conductive barrier wall PW can have a more stable and robust structure and does not have a shape protruding from the center.

[0137] Figure 6 According to one or more embodiments of the present disclosure Figure 4 FIG. 1 is a cross-sectional view of a portion of the display panel DP taken along line II-II′. Figure 6 is an enlarged cross-sectional view of a first light emitting area PXA-R, a second light emitting area PXA-G, and a third light emitting area PXA-B, and Figure 5 The description of the luminous area PXA can be applied to Figure 6 The first light emitting area PXA-R, the second light emitting area PXA-G and the third light emitting area PXA-B are formed.

[0138] refer to Figure 5 and Figure 6 The display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The display element layer DP-OLED may include an insulating layer IL, a common electrode BE, a conductive barrier wall PW, a blocking insulating layer IP, a pixel defining layer PDL, light-emitting elements ED1, ED2, and ED3, and auxiliary electrodes SE1, SE2, and SE3.

[0139] The light-emitting elements ED1, ED2, and ED3 may include a first light-emitting element ED1, a second light-emitting element ED2, and a third light-emitting element ED3. The first light-emitting element ED1 may include a first anode AE1, a first light-emitting pattern EP1, and a first cathode CE1. The second light-emitting element ED2 may include a second anode AE2, a second light-emitting pattern EP2, and a second cathode CE2. The third light-emitting element ED3 may include a third anode AE3, a third light-emitting pattern EP3, and a third cathode CE3. The first anode AE1, the second anode AE2, and the third anode AE3 may be provided in a pattern. The first light-emitting pattern EP1 may provide red light, the second light-emitting pattern EP2 may provide green light, and the third light-emitting pattern EP3 may provide blue light.

[0140] The display element layer DP-OLED may further include a pixel defining layer (PDL). The pixel defining layer (PDL) may be disposed on the blocking insulating layer (IP). The pixel defining layer (PDL) may include a first light emitting opening (OP1-E), a second light emitting opening (OP2-E), and a third light emitting opening (OP3-E) defined therethrough. At least a portion of the first anode (AE1) may be exposed through the first light emitting opening (OP1-E). At least a portion of the second anode (AE2) may be exposed through the second light emitting opening (OP2-E). At least a portion of the third anode (AE3) may be exposed through the third light emitting opening (OP3-E).

[0141] In the present disclosure, the first light-emitting region PXA-R may be defined as a region of the upper surface of the first anode AE1 that is exposed through the first light-emitting opening OP1-E. The second light-emitting region PXA-G may be defined as a region of the upper surface of the second anode AE2 that is exposed through the second light-emitting opening OP2-E. The third light-emitting region PXA-B may be defined as a region of the upper surface of the third anode AE3 that is exposed through the third light-emitting opening OP3-E.

[0142] The first inner barrier wall opening OP1-PI, the second inner barrier wall opening OP2-PI and the third inner barrier wall opening OP3-PI corresponding to the first light-emitting opening OP1-E, the second light-emitting opening OP2-E and the third light-emitting opening OP3-E, respectively, can be defined by a conductive barrier wall PW, and the outer barrier wall opening OP-PO that does not overlap with the first light-emitting opening OP1-E, the second light-emitting opening OP2-E and the third light-emitting opening OP3-E can be defined by (by) the conductive barrier wall PW.

[0143] The first inner barrier wall opening OP1-PI, the second inner barrier wall opening OP2-PI, and the third inner barrier wall opening OP3-PI may overlap with the centers of the first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3. As an example, the first inner barrier wall opening OP1-PI may overlap with the center of the first light emitting pattern EP1, the second inner barrier wall opening OP2-PI may overlap with the center of the second light emitting pattern EP2, and the third inner barrier wall opening OP3-PI may overlap with the center of the third light emitting pattern EP3.

[0144] The first inner side surface IS-L1 of the first barrier wall layer L1 and the second inner side surface IS-L2 of the second barrier wall layer L2 defining the first inner barrier wall opening OP1-PI, the second inner barrier wall opening OP2-PI, and the third inner barrier wall opening OP3-PI may be aligned with each other. For example, the inner barrier wall opening OP-PI may not have a protruding shape and may be defined by the inner side surfaces IS-L1 and IS-L2 formed continuously (for example, formed to provide a continuous surface in which the first inner side surface IS-L1 and the second inner side surface IS-L2 are flush and flat with each other).

[0145] The outer barrier wall opening OP-PO may overlap with the peripheral area NPXA around (e.g., surrounding) the first light-emitting area PXA-R, the second light-emitting area PXA-G, and the third light-emitting area PXA-B. When viewed in a cross-section, the outer barrier wall opening OP-PO may have an undercut shape.

[0146] The outer barrier wall opening OP-PO may include a first area A1 defined by the first outer side surface OS-L1 of the first barrier wall layer L1 and a second area A2 defined by the second outer side surface OS-L2 of the second barrier wall layer L2. The first area A1 and the second area A2 may be provided integrally with each other as openings. The length of the first area A1 in one direction may be greater than the length of the second area A2 in the one direction (e.g., the same direction). The one direction may be the first direction DR1 or the second direction DR2. For example, the second area A2 of the outer barrier wall opening OP-PO may be an area defining a tip portion. Due to the tip portion, the second area A2 may have a width smaller than the width of the first area A1.

[0147] The first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3 may be physically separated from each other by the second barrier wall layer L2 forming the tip portion, and may be formed to cover the second outer side surface OS-L2 of the second barrier wall layer L2. In addition, the first cathode CE1, the second cathode CE2, and the third cathode CE3 may be physically separated from each other by the second barrier wall layer L2 forming the tip portion, and each of the first cathode CE1, the second cathode CE2, and the third cathode CE3 may be formed to cover at least a portion of the corresponding light emitting pattern EP1, EP2, or EP3.

[0148] According to one or more embodiments of the present disclosure, the first light emitting pattern EP1 may be patterned in units of pixels by the tip portion defined in the conductive barrier wall PW and may be deposited. For example, the first light emitting pattern EP1 may be formed together using an open mask, but may be easily separated in units of pixels by the conductive barrier wall PW.

[0149] In contrast, when patterning the first light-emitting pattern EP1 using a fine metal mask (FMM), support spacers protruding from the conductive barrier wall can be used to support the fine metal mask. Furthermore, because the fine metal mask is isolated and / or separated (e.g., spaced apart or separated) from the substrate surface on which the patterning process is performed by the height of the barrier wall and the spacer, there may be limitations in achieving high resolution. Furthermore, because the fine metal mask contacts the spacer, foreign matter may remain on the spacer after the patterning process of the first light-emitting pattern EP1, or the spacer may be damaged by the fine metal mask. As a result, a defective display panel may be formed.

[0150] According to one or more embodiments, since the display panel DP includes the conductive barrier wall PW, the light emitting elements ED1, ED2, and ED3 can be easily physically separated from each other. Therefore, leakage current or driving error between adjacent light emitting areas PXA-R, PXA-G, and PXA-B can be prevented or reduced, and the light emitting elements ED1, ED2, and ED3 can be driven independently of each other.

[0151] For example, because the first light emitting pattern EP1 is not provided in the display area DA (see for example Figure 1B ) is patterned without using a mask that contacts components within the conductive barrier wall PW, so the defect rate of the display panel DP can be reduced, and thus, an electronic device with improved process reliability can be provided. Even without providing a support spacer protruding from the conductive barrier wall PW, the first light-emitting pattern EP1 can be patterned. Therefore, the light-emitting areas PXA-R, PXA-G, and PXA-B can be formed with fineness in their size, and thus, a display panel DP that can easily achieve high resolution can be provided.

[0152] In addition, since a large-sized mask may not be used when manufacturing a large-sized display panel (for example, when manufacturing a large-sized display panel), process costs can be reduced, and since the display panel is not affected by defects that occur due to the large-sized mask, process reliability of the display panel can be improved. The description of the first light emitting pattern EP1 can be applied to the second light emitting pattern EP2 and the third light emitting pattern EP3.

[0153] The auxiliary electrodes SE1, SE2, and SE3 may include a first auxiliary electrode SE1, a second auxiliary electrode SE2, and a third auxiliary electrode SE3. The first auxiliary electrode SE1 may cover the first cathode CE1, the second auxiliary electrode SE2 may cover the second cathode CE2, and the third auxiliary electrode SE3 may cover the third cathode CE3. The first auxiliary electrode SE1, the second auxiliary electrode SE2, and the third auxiliary electrode SE3 may directly contact the lower surface B-L2 of the second barrier wall layer L2 and may cover the lower surface B-L2 of the second barrier wall layer L2.

[0154] The first auxiliary electrode SE1 may be in contact with the first cathode CE1 and the conductive barrier wall PW to electrically connect the first cathode CE1 and the conductive barrier wall PW. The conductive barrier wall PW may receive a driving voltage (or bias voltage), and thus, the first cathode CE1 may receive the driving voltage (or bias voltage). The second auxiliary electrode SE2 may be in contact with the second cathode CE2 and the conductive barrier wall PW to electrically connect the second cathode CE2 and the conductive barrier wall PW. The conductive barrier wall PW may receive a driving voltage (or bias voltage), and thus, the second cathode CE2 may receive the driving voltage (or bias voltage). The third auxiliary electrode SE3 may be in contact with the third cathode CE3 and the conductive barrier wall PW to electrically connect the third cathode CE3 and the conductive barrier wall PW. The conductive barrier wall PW may receive a driving voltage (or bias voltage), and thus, the third cathode CE3 may receive the driving voltage (or bias voltage).

[0155] The thin film encapsulation layer TFE may include a lower encapsulation inorganic pattern LIL, an encapsulation organic layer OL, and an upper encapsulation inorganic layer UIL.

[0156] The lower encapsulation inorganic pattern LIL may include a first lower encapsulation inorganic pattern LIL1, a second lower encapsulation inorganic pattern LIL2, and a third lower encapsulation inorganic pattern LIL3. When viewed in a cross-section, the first lower encapsulation inorganic pattern LIL1, the second lower encapsulation inorganic pattern LIL2, and the third lower encapsulation inorganic pattern LIL3 may be spaced apart and / or separated (e.g., spaced apart or separated) from the common electrode BE.

[0157] The first lower encapsulation inorganic pattern LIL1 may be formed to correspond to the first light emitting opening OP1-E (or overlap with the first light emitting opening OP1-E in a plan view). The first lower encapsulation inorganic pattern LIL1 may be arranged on the first auxiliary electrode SE1 and may cover the first auxiliary electrode SE1. The second lower encapsulation inorganic pattern LIL2 may be formed to correspond to the second light emitting opening OP2-E (or overlap with the second light emitting opening OP2-E in a plan view). The second lower encapsulation inorganic pattern LIL2 may be arranged on the second auxiliary electrode SE2 and may cover the second auxiliary electrode SE2. The third lower encapsulation inorganic pattern LIL3 may be formed to correspond to the third light emitting opening OP3-E (or overlap with the third light emitting opening OP3-E in a plan view). The third lower encapsulation inorganic pattern LIL3 may be arranged on the third auxiliary electrode SE3 and may cover the third auxiliary electrode SE3.

[0158] 7A to 7N is a cross-sectional view illustrating a process of a method for manufacturing a display panel according to one or more embodiments of the present disclosure. 7A to 7N In the Figures 1A to 6, and therefore, a detailed description of the same / similar elements may not be provided.

[0159] A method for manufacturing a display panel may include: forming a circuit element layer including a transistor and a common electrode on a base layer; forming a preliminary conductive barrier wall on the common electrode; forming an inner barrier wall opening passing through the preliminary conductive barrier wall; forming a blocking insulating layer on the preliminary conductive barrier wall and in the inner barrier wall opening; forming a first electrode electrically connected to the transistor in the inner barrier wall opening, and forming a pixel defining layer covering the first electrode on the blocking insulating layer; etching the preliminary conductive barrier wall to form a conductive barrier wall defining an outer barrier wall opening therethrough; forming a light emitting pattern covering the first electrode and a portion of the conductive barrier wall; and forming a second electrode electrically connected to the conductive barrier wall on the light emitting pattern.

[0160] In the following, reference will be made to 7A to 7N Describes the process of forming a light emitting element (eg, first light emitting element ED1 (see eg, Figure 6 )), a lower encapsulation inorganic pattern covering the first light emitting element ED1 (eg, a first lower encapsulation inorganic pattern LIL1 (see eg, Figure 6 )) Method for encapsulating an organic layer OL and an inorganic layer UIL. Figures 7A to 7N The display panel formed by the process may correspond to Figure 5 display panel DP.

[0161] refer to Figure 7A The manufacturing method of the display panel may include forming a transistor TR1 (see, for example, Figure 5 ) circuit element layer DP-CL and common electrode BE.

[0162] The circuit element layer DP-CL including the transistor TR1 can be formed using a commonly available and / or commonly utilized manufacturing process for circuit elements, which forms an insulating layer, a semiconductor layer, and a conductive layer through a coating or deposition process and selectively patterns the insulating layer, the semiconductor layer, and the conductive layer using photolithography and etching processes to form a semiconductor pattern and a conductive pattern such as a signal line. The method of manufacturing a display panel may further include depositing an insulating layer IL on the circuit element layer DP-CL.

[0163] The common electrode BE may be formed on the base layer BL. For example, the common electrode BE may be formed on the insulating layer IL. The common electrode BE may be commonly distributed throughout the display area DA (see, for example, FIG. 2 ). Figure 4 ) arrangement and can be formed to provide a common voltage.

[0164] refer to Figure 7BThe method for manufacturing a display panel may include forming a preliminary conductive barrier wall PW-I on a common electrode BE. The formation of the preliminary conductive barrier wall PW-I may include forming a first preliminary barrier wall layer L1-I on the common electrode BE and forming a second preliminary barrier wall layer L2-I on the first preliminary barrier wall layer L1-I.

[0165] The formation of the first preliminary barrier wall layer L1-1 and the second preliminary barrier wall layer L2-1 can be performed by a process of depositing a conductive material. As an example, the conductive material may include a metal, a transparent conductive oxide (TCO), an organic material, an inorganic material, and / or one or more (e.g., any suitable) combinations thereof. As an example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), and / or alloys thereof. The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide. The inorganic material may include titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), and tungsten carbide (WC). The organic material may include PEDOT:PSS, polyaniline (PANI), polypyrrole (PPy), polythiophene (PT), carbon nanotubes (CNT), and graphene. The preliminary barrier wall layer including the inorganic material may have a refractive index in the range from about 1.3 to about 2.3.

[0166] The second preliminary barrier wall layer L2-I may include the same material as the common electrode BE, and the first and second preliminary barrier wall layers L1-I and L2-I may include different materials from each other; however, this is merely an example and the present disclosure is not limited thereto.

[0167] refer to Figure 7C The method for manufacturing a display panel may further include forming a first photoresist layer PR1 on the preliminary conductive barrier wall PW-1. The first photoresist layer PR1 may be formed by forming a preliminary photoresist layer on the preliminary conductive barrier wall PW-1 and patterning the preliminary photoresist layer using a photomask. A first optical opening OP-PR1 may be formed through the first photoresist layer PR1 through a patterning process. When viewed in plan, the first optical opening OP-PR1 may have a polygonal shape or a circular shape.

[0168] Then, the method for manufacturing a display panel may include forming an inner barrier wall opening OP-PI through the preliminary conductive barrier wall PW-1 after removing the first photoresist layer PR1. The formation of the inner barrier wall opening OP-PI may include etching the preliminary conductive barrier wall PW-1 using the first photoresist layer PR1 as a mask. As an example, the preliminary conductive barrier wall PW-1 may be dry-etched to form the inner barrier wall opening OP-PI having a polygonal or circular shape.

[0169] In addition, forming the inner barrier wall opening OP-PI may include etching the preliminary conductive barrier wall PW-I so that the first inner side surface IS-L1 of the first preliminary barrier wall layer L1-I is aligned (e.g., flat or flush) with the second inner side surface IS-L2 of the second preliminary barrier wall layer L2-I. The dry etching process for forming the inner barrier wall opening OP-PI may be performed under an environment in which the first preliminary barrier wall layer L1-I has substantially the same etching selectivity relative to the second preliminary barrier wall layer L2-I. Therefore, the first inner side surface IS-L1 of the first preliminary barrier wall layer L1-I is substantially aligned with the second inner side surface IS-L2 of the second preliminary barrier wall layer L2-I.

[0170] refer to Figure 7D and Figure 7E , the manufacturing method of the display panel may include forming a blocking insulating layer IP on the preliminary conductive barrier wall PW-I and in the inner barrier wall opening OP-PI.

[0171] refer to Figure 7D The formation of the blocking insulating layer IP may include forming a preliminary blocking insulating layer IP-I on the preliminary conductive barrier wall PW-I. The preliminary blocking insulating layer IP-I may be formed on the preliminary conductive barrier wall PW-I. For example, the preliminary blocking insulating layer IP-I may be formed to cover the upper surface of the second preliminary barrier wall layer L2-I, the side surfaces of the second preliminary barrier wall layer L2-I, the side surfaces of the first preliminary barrier wall layer L1-I, the side surfaces of the common electrode BE, the side surfaces of the insulating layer IL, and the upper surface of the circuit element layer DP-CL. For example, the preliminary blocking insulating layer IP-I may be formed to cover the inner barrier wall opening OP-PI.

[0172] Then, refer to Figure 7E The manufacturing method of the display panel may further include preparing a blocking insulating layer IP-I (see, for example Figure 7D). A second photoresist layer PR2 is formed on the preliminary barrier insulating layer IP-1. The second photoresist layer PR2 may be formed by forming a preliminary photoresist layer on the preliminary barrier insulating layer IP-1 and patterning the preliminary photoresist layer using a photomask. A second optical opening OP-PR2 may be formed through the second photoresist layer PR2 by a patterning process. The second optical opening OP-PR2 may overlap with the inner barrier wall opening OP-PI.

[0173] The method for manufacturing a display panel may include etching a preliminary blocking insulating layer IP-I to form a blocking insulating layer opening OP-IP. A portion of the preliminary blocking insulating layer IP-I that covers the upper surface of the circuit element layer DP-CL may be removed by an etching process. The blocking insulating layer opening OP-IP may be formed in a region corresponding to the removed portion, and the blocking insulating layer IP may be formed from the preliminary blocking insulating layer IP-I. A portion of the upper surface of the circuit element layer DP-CL may be exposed through the blocking insulating layer opening OP-IP.

[0174] refer to Figure 7F , the method of manufacturing a display panel may include forming a first electrode AE ​​(or anode AE) and a pixel defining layer PDL covering the first electrode AE ​​after removing the second photoresist layer PR2.

[0175] The first electrode AE ​​may be formed on the blocking insulating layer IP and in the inner barrier wall opening OP-PI (or the blocking insulating layer opening OP-IP). The first electrode AE ​​may be electrically connected to the circuit element layer DP-CL via the inner barrier wall opening OP-PI. For example, the first electrode AE ​​may be in contact with the upper surface of the circuit element layer DP-CL that is not covered by the blocking insulating layer IP, and may be connected to the circuit element layer DP-CL via the contact hole CNT-3 (see, for example, Figure 5 ) is connected to the second connection electrode CNE2 (see for example Figure 5 ). Therefore, the first electrode AE ​​can be connected to the first connection electrode CNE1 (see, for example Figure 5 ) and the second connection electrode CNE2 are electrically connected to the signal transmission region SCL (see, for example Figure 5 ), and can be electrically connected to corresponding circuit elements, such as transistor TR1 (see e.g. Figure 5 ).

[0176] A pixel defining layer PDL may be formed on the blocking insulating layer IP and the first electrode AE ​​to cover the first electrode AE.

[0177] refer to Figure 7GThe method for manufacturing a display panel may include forming a third photoresist layer PR3 on the pixel defining layer PDL. The third photoresist layer PR3 may be formed by forming a preliminary photoresist layer on the pixel defining layer PDL and patterning the preliminary photoresist layer using a photomask. A third optical opening OP-PR3 may be formed through the third photoresist layer PR3 by a patterning process to overlap the anode AE.

[0178] The method of manufacturing the display panel may include etching the pixel defining layer PDL to form a light emitting opening OP-E to overlap the anode electrode AE ​​(or the first electrode AE).

[0179] The pixel defining layer PDL may be etched by dry-etching a portion of the pixel defining layer PDL using the third photoresist layer PR3 as a mask. The etched portion of the pixel defining layer PDL may be removed to form an emission opening OP-E, which may overlap the anode AE ​​(or first electrode AE).

[0180] refer to Figure 7H and Figure 7I The manufacturing method of the display panel may include etching the preliminary conductive barrier wall PW-1 (see, for example, Figure 7G ) to form a conductive barrier wall PW, and an outer barrier wall opening OP-PO is formed through the conductive barrier wall PW.

[0181] refer to Figure 7H The formation of the conductive barrier wall PW may include first etching the first preliminary barrier wall layer L1-I and the second preliminary barrier wall layer L2-I. The first etching may be performed by dry etching the first preliminary barrier wall layer L1-I and the second preliminary barrier wall layer L2-I using the fourth photoresist layer PR4 as a mask. The etched portion of the preliminary conductive barrier wall PW-I may be removed, and a preliminary barrier wall opening OP-POI may be formed through the preliminary conductive barrier wall PW-I. During the first etching, the blocking insulating layer IP and the pixel defining layer PDL may be etched using the fourth photoresist layer PR4 as a mask.

[0182] The dry etching process for forming the preliminary barrier wall opening OP-POI may be performed under an environment in which the first preliminary barrier wall layer L1-I has substantially the same etching selectivity relative to the second preliminary barrier wall layer L2-I. Therefore, the outer surface of the first preliminary barrier wall layer L1-I may be substantially aligned with the outer surface of the second preliminary barrier wall layer L2-I.

[0183] like Figure 7I As shown in FIG, the formation of the conductive barrier wall PW may include forming a first preliminary barrier wall layer L1-I (see, for example, Figure 7H) is subjected to a second etching to form a first barrier wall layer L1 and a second barrier wall layer L2. The second etching may be performed by wet etching the first preliminary barrier wall layer L1-I using the fourth photoresist layer PR4 as a mask. The etched portion of the first preliminary barrier wall layer L1-I may be removed, and the first barrier wall layer L1 and the second barrier wall layer L2 may be formed. The first barrier wall layer L1 and the second barrier wall layer L2 may be referred to as a conductive barrier wall PW. An outer barrier wall opening OP-PO may be formed through the conductive barrier wall PW.

[0184] The outer barrier wall opening OP-PO may include a first area A1 defined by the first outer side surface OS-L1 of the first barrier wall layer L1 (see, eg, Figure 5 and Figure 6 ) and a second area A2 defined by the second outer side surface OS-L2 of the second barrier wall layer L2 (see, for example Figure 5 and Figure 6 ). The first area A1 and the second area A2 may be integrally provided as an opening. The first area A1 may have a width different from that of the second area A2. As an example, the length of the first area A1 in one direction may be greater than the length of the second area A2 in the one direction (e.g., the same direction). The one direction may be orthogonal (e.g., perpendicular) to the thickness direction (e.g., the third direction DR3) of the circuit element layer DP-CL. For example, the one direction may be the first direction DR1 or the second direction DR2.

[0185] In one or more embodiments, the wet etching process may be performed on the first preliminary barrier wall layer L1-I relative to the second preliminary barrier wall layer L2-I (see, for example, Figure 7H ) is performed under an environment with etching selectivity. Therefore, when viewed in cross section, the conductive barrier wall PW defining the outer barrier wall opening OP-PO can have an undercut shape. For example, the etching rate of the first preliminary barrier wall layer L1-1 defining the outer barrier wall opening OP-PO relative to the etching solution can be greater than the etching rate of the second preliminary barrier wall layer L2-1 defining the outer barrier wall opening OP-PO relative to the etching solution, and therefore, the first preliminary barrier wall layer L1-1 can be mainly etched. Therefore, the first outer side surface OS-L1 of the first barrier wall layer L1 can be recessed inwardly toward the anode AE ​​relative to the second outer side surface OS-L2 of the second barrier wall layer L2. A tip portion can be formed in the conductive barrier wall PW by the portion of the second barrier wall layer L2 that protrudes outwardly relative to the first barrier wall layer L1.

[0186] refer to Figure 7J The manufacturing method of the display panel may include removing the fourth photoresist layer PR4 (see, for example Figure 7I ) is then formed to form a light emitting pattern EP covering a portion of the first electrode AE ​​and the conductive barrier wall PW.

[0187] The formation of the light-emitting pattern EP may include a deposition process for the light-emitting layer. The deposition process for the light-emitting layer may be a thermal evaporation process, however, this is merely an example. The deposition process for the light-emitting layer should not be limited to or thereby. The light-emitting layer may be divided into multiple sections by the tip portion formed in the conductive barrier wall PW, and the light-emitting pattern EP and the first dummy layer D1 may be formed. The light-emitting pattern EP may be formed to cover the side surfaces of the blocking insulating layer IP and the side surfaces of the second barrier wall layer L2, and the first dummy layer D1 may be formed on the common electrode BE.

[0188] For example, a first dummy layer D1 that is separated and / or apart (e.g., spaced apart or separated) from the light emitting pattern EP may be formed together with the light emitting pattern EP. The first dummy layer D1 may include an organic material. As an example, the first dummy layer D1 may include the same material as the light emitting pattern EP. The first dummy layer D1 may be formed substantially concurrently (e.g., substantially simultaneously) with the light emitting pattern EP through a single process and may be separated from the light emitting pattern EP by the undercut shape of the outer barrier wall opening OP-PO.

[0189] Then, the manufacturing method of the display panel may include forming a second electrode CE electrically connected to the conductive barrier wall PW on the light emitting pattern EP.

[0190] The formation of the cathode CE may include a cathode layer deposition process. The cathode layer deposition process may be a thermal evaporation process; however, this is merely an example. The cathode layer deposition process should not be limited thereto or thereby. The cathode layer may be divided into multiple sections by the tip portion formed in the conductive barrier wall PW, and may form the cathode CE and a second dummy layer D2. The cathode CE may be formed to cover at least a portion of the upper surface and side surfaces of the light emitting pattern EP, and the second dummy layer D2 may be disposed on the first dummy layer D1.

[0191] For example, the second dummy layer D2 separated from the cathode CE can be formed together with the cathode CE during the formation of the cathode CE. The second dummy layer D2 may include a conductive material. As an example, the second dummy layer D2 may include the same material as the cathode CE. The second dummy layer D2 may be formed substantially concurrently (e.g., substantially simultaneously) with the cathode CE through a single process and may be separated from the cathode CE by the undercut shape of the outer barrier wall opening OP-PO.

[0192] The anode AE, the light emitting pattern EP, and the cathode CE may be sequentially stacked in the third direction DR3. The anode AE, the light emitting pattern EP, and the cathode CE may form a light emitting element ED. The first dummy layer D1 and the second dummy layer D2 may be sequentially stacked in the third direction DR3.

[0193] refer to Figure 7K , the method of manufacturing the display panel may include forming an auxiliary electrode SE covering the second electrode CE.

[0194] The formation of the auxiliary electrode SE may include a deposition process for the auxiliary electrode layer. The deposition process for the auxiliary electrode layer may be a sputtering process; however, this is only an example. The deposition process for the auxiliary electrode layer should not be limited thereto or thereby.

[0195] The auxiliary electrode layer may include a conductive material. As an example, the conductive material may include a metal, a transparent conductive oxide (TCO), and / or one or more (e.g., any suitable) combinations thereof. As an example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), and / or alloys thereof. The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide.

[0196] The auxiliary electrode SE may cover the second electrode CE (or cathode CE) and may be in direct contact with the conductive barrier wall PW to electrically connect the conductive barrier wall PW and the second electrode CE. The auxiliary electrode SE may be in contact with the lower surface B-L2 of the second barrier wall layer L2 (see, for example, FIG. Figure 5 ) and the first outer side surface OS-L1 of the first barrier wall layer L1 (see, for example Figure 5 ) in contact. As an example, the auxiliary electrode SE may cover the cathode CE and may extend along the lower surface B-L2 of the second barrier wall layer L2 and the first outer side surface OS-L1 of the first barrier wall layer L1. However, this is merely an example, and the shape of the auxiliary electrode SE should not be limited thereto or thereby. In one or more embodiments, the auxiliary electrode SE may include a portion covering the cathode CE and the lower surface B-L2 of the second barrier wall layer L2, and a portion that does not extend from the lower surface B-L2 of the second barrier wall layer L2 and is in contact with the first outer side surface OS-L1 of the first barrier wall layer L1.

[0197] refer to Figure 7L and Figure 7M The method for manufacturing a display panel may include forming a lower encapsulation inorganic pattern LIL covering the auxiliary electrode SE. The formation of the lower encapsulation inorganic pattern LIL may include depositing a lower encapsulation inorganic layer LIL-I and removing a portion of the lower encapsulation inorganic layer LIL-I that does not overlap with the light emitting element ED.

[0198] refer to Figure 7L , the lower package inorganic pattern LIL (see for example Figure 7M) may include depositing a lower encapsulation inorganic layer LIL-1. The lower encapsulation inorganic layer LIL-1 may be formed by a deposition process. The lower encapsulation inorganic layer LIL-1 may be formed by a chemical vapor deposition (CVD) process. The lower encapsulation inorganic layer LIL-1 may be formed to cover the auxiliary electrode SE.

[0199] refer to Figure 7M The formation of the lower encapsulation inorganic pattern LIL may include forming a fifth photoresist layer PR5 and removing the lower encapsulation inorganic layer LIL-I (see, for example, Figure 7L ) does not overlap with the light emitting element ED.

[0200] The fifth photoresist layer PR5 may be formed by forming a preliminary photoresist layer and patterning the preliminary photoresist layer using a photomask. The fifth photoresist layer PR5 may be formed in a pattern corresponding to the light emitting element ED through a patterning process.

[0201] The portion of the lower encapsulation inorganic layer LIL-I that does not overlap with the light emitting element ED can be removed by dry etching the lower encapsulation inorganic layer LIL-I using the patterned fifth photoresist layer PR5 as a mask. The lower encapsulation inorganic pattern LIL overlapping with the light emitting element ED can be formed by the patterned lower encapsulation inorganic layer LIL-I.

[0202] The method for manufacturing a display panel may further include removing the dummy layers D1 and D2 (see, for example, Figure 7L ) to form a dummy region. The second dummy layer D2 of the dummy layers D1 and D2 can be removed by a wet etching process, and the first dummy layer D1 of the dummy layers D1 and D2 can be removed by a stripping process. In this case, because the dummy layers D1 and D2 are removed, the lower encapsulation inorganic pattern LIL can be separated and / or apart (e.g., spaced apart or separated) from the common electrode BE when viewed in a cross-section. The region where the lower encapsulation inorganic pattern LIL is separated and / or apart (e.g., spaced apart or separated) from the common electrode BE when viewed in a cross-section can be referred to as a dummy region.

[0203] refer to Figure 7N The manufacturing method of the display panel may include removing the fifth photoresist layer PR5 (see, for example, Figure 7M ) Afterwards, an encapsulation organic layer OL and an upper encapsulation inorganic layer UIL are formed to complete the display panel DP. The encapsulation organic layer OL may be formed by applying an organic material using an inkjet method; however, the present disclosure is not limited thereto or thereby. The encapsulation organic layer OL may provide a flat upper surface. The dummy area may be filled with the encapsulation organic layer OL; however, the present disclosure is not limited thereto or thereby. As an example, the dummy area may not be filled or may be partially filled with the encapsulation organic layer OL.

[0204] Then, an upper encapsulation inorganic layer UIL may be formed by depositing an inorganic material, thereby forming a display panel DP including a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE.

[0205] Between forming the lower encapsulation inorganic pattern LIL and completing the display panel DP, a process of forming barrier wall openings and light-emitting openings corresponding to light-emitting areas of other colors through the conductive barrier wall PW and the pixel defining layer PDL, a process of forming light-emitting elements providing other colors, and a process of forming auxiliary electrodes covering the light-emitting elements providing other colors and a lower encapsulation inorganic pattern covering the auxiliary electrodes can be further performed. Figure 6 , a display panel DP including first, second, and third light emitting elements ED1, ED2, and ED3, first, second, and third auxiliary electrodes SE1, SE2, and SE3, and first, second, and third lower encapsulation inorganic patterns LIL1, LIL2, and LIL3.

[0206] As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation rather than terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that one of ordinary skill in the art would recognize. Taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system), "substantially" as used herein includes the stated value and means within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0207] In addition, any numerical range disclosed and / or described in this article is intended to include all sub-ranges of the same numerical precision contained in the range of the description. For example, the range of "1.0 to 10.0" is intended to include all sub-ranges between the minimum value 1.0 described and the maximum value 10.0 described (and including the endpoint values), that is, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, for example, 2.4 to 7.6. Any maximum numerical limit described in this article is intended to include all smaller numerical limits contained therein, and any minimum numerical limit described in this specification is intended to include all larger numerical limits contained therein. Therefore, the applicant reserves the right to amend this specification (including claims) to explicitly describe any sub-range contained in the range explicitly described in this article.

[0208] Additionally, the use of "may" when describing embodiments of the present disclosure refers to "one or more embodiments of the present disclosure."

[0209] The display panel, electronic device, device for manufacturing the same, or any other related device or component according to the embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of the device can be formed on an integrated circuit (IC) chip or on separate IC chips. In addition, the various components of the device can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. In addition, the various components of the device can be processes or threads running on one or more processors, in one or more computing devices, executing computer program instructions and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in a memory, which can be implemented in a computing device using a standard storage device (e.g., random access memory (RAM)). The computer program instructions can also be stored in other non-transitory computer-readable media (e.g., compact disc read-only memory (CD-ROM), flash drive, etc.). In addition, those skilled in the art should recognize that, without departing from the scope of the embodiments of the present disclosure, the functions of the various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed on one or more other computing devices.

[0210] In view of the overall disclosure, those skilled in the art will understand that, unless otherwise stated or implied, each suitable feature of the various embodiments of the present disclosure may be partially or completely combined or coupled with each other and may be technically related and operated with each other in various suitable manners, and each embodiment may be implemented independently of each other or in combination with each other in any suitable manner.

[0211] It will be understood that, unless otherwise described, the description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Therefore, it will be apparent to those skilled in the art that, unless specifically stated otherwise, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. In addition, it should be understood that the foregoing is illustrative of various example embodiments and should not be construed as limiting the specific embodiments disclosed herein, and that various modifications to the disclosed embodiments and other example embodiments are intended to be included within the spirit and scope of the present disclosure as defined in the appended claims and their equivalents.

Claims

1. A display panel, wherein: The display panel includes: a circuit component layer, including transistors; a common electrode on the circuit element layer; a conductive barrier wall on the common electrode and defining an outer barrier wall opening and an inner barrier wall opening; a blocking insulating layer on the conductive blocking wall; a first electrode on the blocking insulating layer and in the inner barrier wall opening and electrically connected to the transistor; a light emitting pattern on the first electrode and covering a portion of the conductive barrier wall and the blocking insulating layer; and A second electrode covers the light emitting pattern and is electrically connected to the conductive barrier wall, wherein the inner barrier wall opening of the conductive barrier wall overlaps with a center of the light emitting pattern.

2. The display panel according to claim 1, wherein The inner barrier wall opening has a polygonal shape.

3. The display panel according to claim 1, wherein: The inner barrier wall opening has a circular shape.

4. The display panel according to claim 1, wherein: The conductive barrier wall comprises: a first barrier wall layer on the common electrode; and The second barrier wall layer is on the first barrier wall layer.

5. The display panel according to claim 4, wherein: The first barrier wall layer includes a first inner side surface, the second barrier wall layer includes a second inner side surface, and the first inner side surface and the second inner side surface define the inner barrier wall opening and are aligned with each other. The display panel according to claim 4 , wherein: The outer barrier wall opening comprises: a first region defined by a first outer side surface of the first barrier wall layer; and The second region is defined by the second outer side surface of the second barrier wall layer, the length of the first region in the first direction is greater than the length of the second region in the first direction, and the first direction is perpendicular to the thickness direction of the circuit element layer.

7. The display panel according to claim 6, wherein: The light emitting pattern covers at least a portion of the second outer side surface of the second barrier wall layer.

8. The display panel according to claim 6, wherein: The display panel further includes an auxiliary electrode covering the second electrode and directly contacting the conductive barrier wall.

9. The display panel according to claim 8, wherein: The auxiliary electrode covers a lower surface of the second barrier wall layer.

10. The display panel according to claim 8, wherein: The auxiliary electrode contacts the first outer surface of the first barrier wall layer.

11. The display panel according to claim 8, wherein: The auxiliary electrode is electrically connected to the conductive barrier wall and the second electrode.

12. The display panel according to claim 8, wherein: The display panel further includes a lower encapsulation inorganic pattern covering the auxiliary electrode, wherein the lower encapsulation inorganic pattern is spaced apart from the common electrode when viewed in a cross-section.

13. The display panel according to claim 1, wherein: The display panel further includes a pixel defining layer on the blocking insulating layer and defining a light emitting opening passing through the pixel defining layer to expose at least a portion of the first electrode, wherein the light emitting opening overlaps the inner barrier wall opening.

14. A method for manufacturing a display panel, wherein: The method comprises: forming a circuit element layer including a transistor and a common electrode on the base layer; forming a preliminary conductive barrier wall on the common electrode; forming an inner barrier wall opening through the preliminary conductive barrier wall; forming a blocking insulating layer on the preliminary conductive barrier wall and in the inner barrier wall opening; forming a first electrode electrically connected to the transistor on the blocking insulating layer and in the inner barrier wall opening; forming a pixel defining layer covering the first electrode and on the blocking insulating layer; etching the preliminary conductive barrier wall to form a conductive barrier wall defining an outer barrier wall opening; forming a light emitting pattern covering a portion of the first electrode and the conductive barrier wall; and A second electrode electrically connected to the conductive barrier wall is formed on the light emitting pattern.

15. The method according to claim 14, wherein The forming the inner barrier wall opening through the preliminary conductive barrier wall includes etching the preliminary conductive barrier wall to define the inner barrier wall opening to have a polygonal shape or a circular shape.

16. The method according to claim 14, wherein The forming of the preliminary conductive barrier wall on the common electrode comprises: forming a first preliminary barrier wall layer on the common electrode; and forming a second preliminary barrier wall layer on the first preliminary barrier wall layer, and The forming of the inner barrier wall opening through the preliminary conductive barrier wall includes etching the preliminary conductive barrier wall so that a first inner side surface of the first preliminary barrier wall layer is aligned with a second inner side surface of the second preliminary barrier wall layer.

17. The method according to claim 16, wherein The etching of the preliminary conductive barrier wall to form the conductive barrier wall defining the outer barrier wall opening comprises: performing a first etching on the first preliminary barrier wall layer and the second preliminary barrier wall layer; and The first preliminary barrier wall layer is subjected to a second etching process to form a first barrier wall layer and a second barrier wall layer.

18. The method according to claim 14, wherein The method further includes forming an auxiliary electrode, the auxiliary electrode covering the second electrode, the auxiliary electrode directly contacting the conductive barrier wall, and electrically connecting the conductive barrier wall and the second electrode.

19. The method according to claim 18, wherein The method further includes forming a lower encapsulation inorganic pattern covering the auxiliary electrode and spaced apart from the common electrode when viewed in a cross section.

20. An electronic device, wherein: The electronic device comprises: a circuit component layer, including transistors; a common electrode on the circuit element layer; a conductive barrier wall comprising a first barrier wall layer on the common electrode and a second barrier wall layer on the first barrier wall layer, and defining an outer barrier wall opening and an inner barrier wall opening passing through the conductive barrier wall; a first electrode on the conductive barrier wall and in the inner barrier wall opening, and electrically connected to the transistor through the inner barrier wall opening; a light emitting pattern on the first electrode and covering a portion of the second barrier wall layer; a second electrode covering the light-emitting pattern; and an auxiliary electrode covering the second electrode and contacting a lower surface of the second barrier wall layer and a first outer side surface of the first barrier wall layer, wherein, when viewed in a plan view, the outer barrier wall opening surrounds the inner barrier wall opening, and the auxiliary electrode is electrically connected to the conductive barrier wall and the second electrode.

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