In-situ random synaptic transistor and preparation method thereof
By designing in-situ random synaptic transistors and using the doped double layer to form random conductive channels under the action of an electric field, the problem that traditional devices cannot support random computing is solved, and efficient random computing and high generalization capabilities are achieved.
Patent Information
- Application Number
- CN202510648002.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-20
- Publication Date
- 2025-09-16
AI Technical Summary
Traditional storage and computing integrated devices are limited by the deterministic dependence of the carrier transport process on the applied bias electric field and cannot support random computing, resulting in increased circuit scale and reduced energy efficiency.
An in-situ random synaptic transistor is designed with a bottom-gate top-contact structure. A random conductive channel is formed under the action of an electric field through the doped double layer. The capacitive coupling effect is combined to achieve carrier regulation to meet the needs of random computing.
It implements random number generation and in-memory computation in a single device, reducing hardware overhead, and provides threshold switching functionality with a large dynamic range of turn-on voltages, supporting efficient training of random neural networks and demonstrating high generalization capabilities.
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Figure CN120659528A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of electronic materials and devices, and particularly relates to an in-situ random synapse transistor and a preparation method thereof. Background Art
[0002] Stochastic computing that simulates the complexity and uncertainty of the real world has unique advantages such as strong adaptability, high learning efficiency, and excellent fault tolerance. It has become one of the important technical means to improve the efficiency and generalization of hardware devices. However, traditional storage and computing devices are limited by the deterministic dependence of the carrier transport process on the external bias electric field. Their output current shows a monotonically increasing / decreasing response characteristic with the external bias electric field, and can only be used for deterministic data processing. This inherent deterministic feature makes the device unable to support the probabilistic operations required for stochastic computing. It often requires the introduction of additional random number generator modules and complex peripheral circuits, which not only significantly increases the circuit scale and design complexity, but also introduces additional signal transmission overhead, resulting in reduced system energy efficiency and increased data transmission delay. Therefore, breaking through the deterministic limitations of carrier transport within traditional storage and computing devices and realizing mixed regulation of carrier transport by introducing a controllable random screening mechanism in carrier transport is a key scientific issue in in-situ stochastic computing. Summary of the Invention
[0003] The purpose of the present invention is to overcome the defects in the prior art and provide an in-situ random synaptic transistor and a preparation method thereof.
[0004] To achieve the above objectives, the technical solution of the present invention is: an in-situ random synaptic transistor, which has a bottom-gate top-contact structure and is composed of a substrate gate, an insulating layer, a doped double layer, an active layer, and a source and drain electrode stacked from bottom to top. The doped double layer can form a double layer under the action of an electric field, and the carriers stored in the active layer are gate-controlled by the capacitive coupling effect. At the same time, the doped active metal will randomly form a volatile conductive channel in the stacked dual-threshold switch layer under the action of the electric field, and the formation probability of the conductive channel can be controlled by the amplitude of the voltage. The randomly formed conductive channel can shield the capacitance of the double layer and leak the carriers accumulated in the channel, thereby realizing in-situ random calculation with the channel conductance randomly set to zero, meeting the requirement of random neural networks to introduce switching randomness in the reading process of synaptic conductance, and the probability of random calculation can be controlled by the amplitude of the gate programming voltage.
[0005] Furthermore, the in-situ random calculation is specifically implemented as follows:
[0006] Process 1: Random number generation stage: The active metal doped in the doped double layer will randomly form volatile conductive channels in the stacked dual-threshold switching layer under the action of the electric field. The probability of the conductive channel formation can be controlled by the voltage amplitude;
[0007] Process 2, weight storage stage: The doped double layer can form a double layer under the action of the electric field. The carriers in the active layer are affected by the capacitive coupling effect and accumulate in the channel, storing the channel conductance, which is the weight;
[0008] Process 3, efficient calculation: By applying positive and negative gate voltages, the capacitance of the double layer can be controlled, thereby regulating the number of carriers in the channel and changing the channel conductance. At the same time, the randomly formed conductive channels inside the device can shield the capacitance of the double layer and leak the accumulated carriers in the channel, thereby achieving in-situ random calculation with the channel conductance randomly set to zero.
[0009] Furthermore, the insulating layer is made of a metal oxide material or a polymer material having both insulating layer and threshold switch functions, and has a thickness of 50 to 150 nm.
[0010] Furthermore, the doped electric double layer is a double layer doped with active metal.
[0011] Furthermore, the doped double electric layer is made of a metal oxide material or a polymer material having both double electric layer function and threshold switching layer function, and has a thickness of 100 to 600 nm.
[0012] Furthermore, the active layer is an organic or inorganic semiconductor thin film with a thickness of 100 to 300 nm.
[0013] Furthermore, the top source and drain are made of inert metal materials such as gold, with a thickness of 30 to 100 nm.
[0014] The present invention also provides a method for preparing an in-situ random synaptic transistor based on any of the above, comprising the following steps:
[0015] S1. Clean the substrate, i.e., the substrate on which the highly conductive material is grown, with acetone, isopropyl alcohol, and deionized water in sequence, and blow dry with nitrogen gas;
[0016] S2. Depositing an insulating layer on the substrate obtained in step S1;
[0017] S3, depositing a doped double electric layer on the insulating layer obtained in step S2;
[0018] S4, depositing an active layer on the doped double electric layer obtained in step S3;
[0019] S5. Depositing a source electrode and a drain electrode on the active layer obtained in step S4. The semiconductor region between the source and drain electrodes serves as a channel.
[0020] Compared with the prior art, the present invention has the following beneficial effects:
[0021] (1) The random number generation and in-memory computation of the present invention are both implemented in a single device, so the random computation can be implemented in a crossbar array architecture for in-memory computation, thereby reducing the hardware overhead of the neural network.
[0022] (2) The in-situ random synaptic transistor of the present invention has a threshold switching function with a large dynamic range of turn-on voltage, which makes it easy to adjust the probability of random calculation from 0 to 1.
[0023] (3) The in-situ random synaptic transistor of the present invention utilizes the influence of random conductive channels on the electrostatic coupling effect to realize an in-situ random calculation strategy of randomly setting the channel conductance to zero, which can meet the demand of introducing switching randomness in the reading process of synaptic conductance, and the probability of random calculation can be controlled by the amplitude of the gate programming voltage.
[0024] (4) The in-situ random synaptic transistor of the present invention can be used to construct a random neural network. The overfitting problem can be suppressed through random calculation, so that the network model shows a high generalization ability for unknown test samples. It achieves a high accuracy image classification task of 92.7% on the MNIST database with limited training samples, and the difference in accuracy between the test set and the training set is less than 3%. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 This is a schematic structural diagram of an in-situ random synaptic transistor prepared in Example 1 of the present invention.
[0026] Figure 1 100 is a gate electrode, 110 is an insulating layer, 120 is a doped double layer, 130 is an active layer, and 140 is a source electrode and a drain electrode.
[0027] Figure 2 is a bidirectional scanning transfer characteristic curve of a three-terminal synaptic transistor according to an embodiment of the present invention (I DS -V GS ).
[0028] Figure 3 is a bidirectional scanning output curve (I GS -V GS ).
[0029] Figure 4 is the I corresponding to the conductance modulation process of the in situ random synaptic transistor under the conditions of conductive channel formation and non-formation.DS and I GS response.
[0030] Figure 5 This is a graph showing changes in accuracy obtained by performing pattern recognition on the National Institute of Standards and Technology Hybrid Handwriting Database (MNIST) in an embodiment of the present invention. DETAILED DESCRIPTION
[0031] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings.
[0032] The present invention provides an in-situ random synaptic transistor, which has a bottom-gate top-contact structure and is composed of a substrate gate, an insulating layer, a doped double electric layer, an active layer, a source electrode and a drain electrode stacked from bottom to top.
[0033] The present invention also provides a method for preparing an in-situ random synaptic transistor based on any of the above, comprising the following steps:
[0034] S1. Clean the substrate, i.e., the substrate on which the highly conductive material is grown, with acetone, isopropyl alcohol, and deionized water in sequence, and blow dry with nitrogen gas;
[0035] S2. Depositing an insulating layer on the substrate obtained in step S1;
[0036] S3, depositing a doped double electric layer on the insulating layer obtained in step S2;
[0037] S4, depositing an active layer on the doped double electric layer obtained in step S3;
[0038] S5. Depositing a source electrode and a drain electrode on the active layer obtained in step S4. The semiconductor region between the source and drain electrodes serves as a channel.
[0039] The following is a specific implementation process of the present invention.
[0040] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present application belongs.
[0041] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.
[0042] like Figure 1As shown, the present invention provides an in-situ random synaptic transistor, which includes a substrate gate, an insulating layer, a doped double electric layer, an active layer, and a source and drain electrode in a stacked design from bottom to top; the substrate gate 100 is a silicon wafer, which serves as both a substrate and a gate, the insulating layer 110 is tantalum oxide, the doped double electric layer 120 is polyvinyl alcohol doped with silver nanowires, the active layer 130 is a semiconductor polymer material PDVT-10, and the source and drain electrodes 140 are gold.
[0043] Example 1:
[0044] S1. Clean a 1.5 cm x 1.5 cm silicon wafer with acetone, isopropyl alcohol, and deionized water, and blow dry with nitrogen.
[0045] S2. Using magnetron sputtering, a tantalum oxide insulating layer with a thickness of about 120 nm is sputtered on the substrate with an argon to oxygen ratio of 20:4.5 and a sputtering pressure of 0.5 Pa;
[0046] S3. Dissolve polyvinyl alcohol at a ratio of 100 mg / mL in deionized water, blend with a silver nanowire solution at a weight ratio of 3:20, fully heat and stir to obtain a silver nanowire-doped polyvinyl alcohol solution, and use this solution as a spin coating to prepare a doped double electric layer on the tantalum oxide insulating layer. The spin coating speed is 1200 rpm / min for 60 seconds, followed by annealing at 120°C in air for 30 minutes. The thickness of the prepared doped double electric layer is approximately 540 nm.
[0047] S4. Dissolve the semiconducting polymer material PDVT-10 in chlorobenzene at a ratio of 5 mg / mL. Spin-coat this solution onto the resulting doped double layer to form an active layer with a thickness of approximately 240 nm. Spin-coat at a speed of 1000 rpm / min for 60 seconds, followed by annealing in air at 120°C for 30 minutes. The resulting active layer is approximately 240 nm thick.
[0048] S5: A 50 nm thick top gold electrode layer with a channel length of 30 μm and a width of 1000 μm is evaporated on the active layer using a dedicated mask by vacuum evaporation deposition.
[0049] Example 2:
[0050] S1. Clean a 1.5 cm x 1.5 cm silicon wafer with acetone, isopropyl alcohol, and deionized water, and blow dry with nitrogen.
[0051] S2. Using magnetron sputtering, a tantalum oxide insulating layer with a thickness of about 120 nm is sputtered on the substrate with an argon to oxygen ratio of 20:4.5 and a sputtering pressure of 0.5 Pa;
[0052] S3. Dissolve polyvinyl alcohol at a ratio of 100 mg / mL in deionized water, blend with a silver nanowire solution at a weight ratio of 3:20, fully heat and stir to obtain a silver nanowire-doped polyvinyl alcohol solution, and use this solution as a spin coating to prepare a doped double electric layer on the tantalum oxide insulating layer. The spin coating speed is 1200 rpm / min for 60 seconds, followed by annealing at 120°C in air for 30 minutes. The thickness of the prepared doped double electric layer is approximately 540 nm.
[0053] S4. Dissolve the semiconductor polymer material IDTBT in chlorobenzene at a ratio of 5 mg / mL. Spin-coat this solution onto the resulting doped double layer to form an active layer. Spin-coat at a speed of 1000 rpm / min for 60 seconds, then anneal in air at 120°C for 30 minutes. The resulting active layer has a thickness of approximately 240 nm.
[0054] S5. Vacuum evaporation is used to deposit a 50 nm thick top gold electrode layer with a channel length of 30 μm and a width of 1000 μm on the active layer using a dedicated mask.
[0055] The structural diagram of Example 1 is as follows Figure 1 As shown in the figure, the bidirectional scanning transfer curve of the three-terminal synaptic transistor of the prepared in-situ random synaptic transistor is shown in the figure. Figure 2 The bidirectional scanning output curve of the two-terminal threshold switch device in the in-situ random synaptic transistor is shown in Figure 3 The corresponding I per pulse number of the long-term potentiation and long-term depression phases when the internal threshold switching device is not activated is shown in Figure 2. DS and I GS Response such as Figure 4 The corresponding I per pulse number during the long-term potentiation and long-term depression phases when the internal threshold switching device is activated is shown in Figures 4a and 4b. DS and I GS Response such as Figure 4 Finally, the training set accuracy and test set accuracy obtained by pattern recognition of the MNIST handwritten digit library change with the learning cycle as shown in Figure 4c and 4d. Figure 5 After 200 learning cycles, the accuracy on the test set is as high as 92.7%, and the difference between the training accuracy and the test accuracy is less than 3%, demonstrating high generalization ability.
[0056] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be considered as equivalent replacement methods and are included in the scope of protection of the present invention.
Claims
1. An in-situ random synaptic transistor, characterized in that The in-situ random synaptic transistor has a bottom-gate top-contact structure and is composed of a substrate gate (100), an insulating layer (110), a doped double electric layer (120), an active layer (130), and a source and a drain (140) stacked from bottom to top.
2. The in-situ random synaptic transistor according to claim 1, characterized in that: The "random charge screening effect" and "field effect" are introduced to hybridly regulate the carrier transport process within the in-situ random synaptic transistor device, so that a single in-situ random synaptic transistor device has in-situ random computing functions that integrate random number generation, weight storage and efficient computing.
3. The in-situ random synaptic transistor according to claim 1 or 2, characterized in that: An in-situ random computing strategy is adopted to achieve random approximate zeroing of channel conductance by utilizing the influence of random conductive channels inside the device on the electrostatic coupling effect. This meets the requirement of introducing switching randomness in the reading process of synaptic conductance in random neural networks, and the probability of random computing can be controlled by the amplitude of the gate programming voltage.
4. The in-situ random synaptic transistor according to claim 3, characterized in that: The in-situ random calculation is specifically implemented as follows: Process 1: Random number generation stage: The active metal doped in the doped double layer will randomly form volatile conductive channels in the stacked dual-threshold switching layer under the action of the electric field. The probability of the conductive channel formation can be controlled by the voltage amplitude; Process 2, weight storage stage: The doped double layer can form a double layer under the action of the electric field. The carriers in the active layer are affected by the capacitive coupling effect and accumulate in the channel, storing the channel conductance, which is the weight; Process 3, efficient calculation: By applying positive and negative gate voltages, the capacitance of the double layer can be controlled, thereby regulating the number of carriers in the channel and changing the channel conductance. At the same time, the randomly formed conductive channels inside the device can shield the capacitance of the double layer and leak the accumulated carriers in the channel, thereby achieving in-situ random calculation with the channel conductance randomly set to zero.
5. The in-situ random synaptic transistor according to claim 1, characterized in that: The insulating layer is made of a metal oxide material or a polymer material having both insulating layer and threshold switch functions, and has a thickness of 50 to 150 nm.
6. The in-situ random synaptic transistor according to claim 1, characterized in that: The doped double electric layer is a double electric layer doped with active metal.
7. The in-situ random synaptic transistor according to claim 1 or 6, characterized in that: The doped double electric layer is made of a metal oxide material or a polymer material having both double electric layer functions and threshold switching layer functions, and has a thickness of 100 to 600 nm.
8. The in-situ random synaptic transistor according to claim 1, characterized in that: The active layer is an organic or inorganic semiconductor thin film with a thickness of 100 to 300 nm.
9. The in-situ random synaptic transistor according to claim 1, characterized in that: The top source and drain are made of inert metal materials including gold, and have a thickness of 30 to 100 nm.
10. A method for preparing an in-situ random synaptic transistor according to any one of claims 1 to 9, characterized in that: The steps include: S1. Clean the substrate, i.e., the substrate on which the highly conductive material is grown, with acetone, isopropyl alcohol, and deionized water in sequence, and blow dry with nitrogen gas; S2. Depositing an insulating layer on the substrate obtained in step S1; S3, depositing a doped double electric layer on the insulating layer obtained in step S2; S4, depositing an active layer on the doped double electric layer obtained in step S3; S5. Depositing a source electrode and a drain electrode on the active layer obtained in step S4. The semiconductor region between the source and drain electrodes serves as a channel.