Analog circuit with reconfiguration mechanism for stress and / or iddq testing and related methods

Abstract

The invention relates to an analog circuit (1) based on MOS, BCMOS or CMOS. The analog circuit (1) is designed to implement a predetermined circuit function in a normal state of the analog circuit (1). The analog circuit (1) has an analog input or output signal, or has an analog signal inside the analog circuit (1). The analog circuit (1) is connected to the test logic (38). The test logic (38) is designed to place the analog circuit (1) in a normal state and at least a first test state. The analog circuit (1) comprises a first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) which is designed to perform a function of the analog circuit (1) according to a predetermined circuit function during normal operation. According to the invention, the analog circuit (1) further comprises second means (S1 to S9; g1 to G9) which are designed to enable the test logic (38) to set the switching state of the first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) in at least a first test state of the analog circuit (1).

Description

Technical Field

[0001] The present invention relates to an analog circuit capable of performing an IDDQ test and / or a stress test. Background Art

[0002] High quality and low defect rates are key requirements for the use of microelectronic circuits in automotive applications. Therefore, when manufacturing mixed-signal CMOS circuits for the automotive industry, it is essential to ensure adequate test coverage of the microelectronic circuits after fabrication. For example, IDDQ testing can be used for digital circuit components in such automotive microelectronic circuits.

[0003] IDDQ testing is a method used to test CMOS integrated circuits for manufacturing defects. This method is based on measuring the supply current (Idd) in a quiescent state (when the circuit is not switching and the inputs are held at static values). The supply current consumed in this state is often referred to as IDDQ quiescent current, or IDD quiescent current. The power supply line is often referred to as the VDD line, and the associated supply current is called IDD current, hence the name.

[0004] IDDQ testing is based on the following principle: in a normally operating digital CMOS circuit in a static state, no static current path exists between the positive and negative voltage supply lines. At the end of microelectronic circuit manufacturing, fully automated test equipment tests the fabricated microelectronic circuits. Typically, the digital circuit portion of a microelectronic circuit is driven by a clock. With each clock edge, circuit nodes within the digital portion of the microelectronic circuit change their logic state. The logic state of these circuit nodes is associated with their voltage level relative to a reference node at a reference potential. Because circuit nodes always have parasitic node capacitance, when the logic state, and therefore the potential, changes, this capacitance must charge to the new potential. Consequently, charging current flows due to the clocking of the digital circuit components of the microelectronic circuit. When the clock stops, circuit nodes in standard CMOS circuits typically maintain their potential, and thus their logic level, because each potential current path in the digital portion of the microelectronic circuit typically includes at least one P-channel transistor and one N-channel transistor, one of which is always in the off state, while the other is in the on state in a complementary manner. Therefore, except for leakage current after the clock of the digital part of the microelectronic circuit is stopped, no current can flow from the positive power supply voltage line of the microelectronic circuit through the digital part to the negative power supply voltage line of the microelectronic circuit. After the clock is turned off, the state of the digital part of the microelectronic circuit is the aforementioned static state of the digital part of the microelectronic circuit.

[0005] However, in practice, when the clock of the digital part stops, a small leakage current will flow from the positive power supply voltage line of the microelectronic circuit through the digital part to the negative power supply voltage line of the microelectronic circuit. Usually, this leakage current is very small and can be basically ignored.

[0006] If a digital transistor in the digital part is defective, this usually leads to an increase in its leakage current. The leakage current is particularly easy to measure if the transistor should actually be in the off state due to its control. In order to test the transistor, the test device controls the microelectronic circuit using a specific signal sequence, the so-called pattern. The transistor under test is located in one or more current paths between the positive supply voltage line and the negative supply voltage line. The test vectors that the test system applies to the microelectronic circuit during the test are designed so that when the test system stops the clock, firstly, the transistor under test is in the off state at at least one time position in the test vector; secondly, at this time position, in at least one current path where the transistor under test is located, all other transistors in this current path are switched to the on state.

[0007] If the leakage current of the transistor under test increases, the increased leakage current flows between the positive power supply voltage line and the negative power supply voltage line through the current path. The test system detects the current in one of the two power supply voltage lines. The test performed by the test system can use this current value and determine that one or more transistors are defective when the current value is too high (in particular, exceeds a threshold value). In the presence of a defect, the leakage current value flowing through the transistor under test will generally increase by several orders of magnitude compared to the current value in the absence of defects. Thus, such defects can be detected in the power supply current. Another advantage of IDDQ testing is that the test system only needs to perform a few measurements to check whether there are a relatively large number of transistor defects in the microelectronic circuit. In addition, the test system can also detect transistor defects that cannot be found using traditional static defect test vectors (patterns).

[0008] IDDQ test

[0009] IDDQ testing is slightly more complex than simply measuring supply current. For example, if a line is shorted to the positive supply voltage, the logic circuit generating the signal will not draw any additional current, even if it attempts to pull it high. However, if the logic circuit attempts to pull the signal low, the leakage current increases dramatically. If the leakage current exceeds a current threshold in magnitude, this indicates a defective component. The test system rejects such defective components. Importantly, the IDDQ test inputs require only controllability of the logic states of the digital section nodes, not observability of these nodes in the sense of logical observability. Observability of the defect's effects is achieved by observing and evaluating the current consumption of the circuit's supply voltage terminals using leakage current.

[0010] However, the controllability of the control signal states of transistors in analog circuits is precisely the reason why conventional IDDQ testing is not suitable for the analog portion of mixed-signal circuits. For this reason, mixed-signal circuits typically have separate positive analog power supply voltage lines (for the analog portion) and positive digital power supply voltage lines (for the digital portion). Additional circuitry can disconnect the analog circuit portion from the digital circuit portion.

[0011] This specification explains this problem using a simple differential amplifier stage shown here as an example of analog circuit application. Figure 1 An example of such an analog circuit 1 is shown. However, the principles described here and presented below may be applied to other analog circuits.

[0012] Voltage source 2 provides power to exemplary analog circuit 1. Current source 4 draws power from supply voltage line 3 and feeds reference current 5 to first node 6. First transistor 7, connected as a MOS diode, draws reference current 5 from first node 6, serving as a reference node, and transfers it to reference potential line 8. First transistor 7, connected as a MOS diode, converts reference current 5 into reference voltage 27. Reference voltage 27 is applied between first node 6 and reference potential line 8. Second transistor 9, together with first transistor 7, connected as a MOS diode, forms a current mirror. Thus, second transistor 9 acts as a current source for the differential stage consisting of third transistor 10, fourth transistor 11, fifth transistor 12, and sixth transistor 13. Control electrode 28 of third transistor 10 and control electrode 29 of fourth transistor 11 form the differential inputs of the exemplary differential amplifier. Fifth transistor 12, connected as a MOS diode, acts as an operating resistor for the left amplifier branch consisting of third transistor 10 and fifth transistor 12. The sixth transistor 13 is connected as a current source of a current mirror formed by the sixth transistor 13 and the MOS diode 12 and acts as an operating resistor for the right amplifier branch formed by the fourth transistor 11 and the sixth transistor 13 .

[0013] The seventh transistor 15 receives the signal at the second node 14 between the fourth transistor 11 and the sixth transistor 13 and performs power amplification as part of a source follower circuit formed by the seventh transistor 15 and the eighth transistor 16. The eighth transistor 16 acts as a current source transistor and, therefore, also acts as an operating resistor for the source follower circuit. The eighth transistor 16 is part of a current mirror formed by the eighth transistor 16 and the first transistor 7 connected as a MOS diode.

[0014] The inverter 17 generates an inverted digital transmission clock 19 according to the digital transmission clock 18 for use by subsequent transmission gates.

[0015] exist Figure 1In the example shown in FIG, when the digital transmission clock 18 is at a high level, the first transmission gate formed by the ninth transistor 20 and the tenth transistor 21 can charge the intermediate node 25 to the potential of the output terminal 26 of the source follower. At this time, the inverted digital transmission clock 19 is at a low level. If the digital transmission clock 18 is at a low level, and thus the inverted digital transmission clock is at a high level, the first transmission gate formed by the ninth transistor 20 and the tenth transistor 21 is turned off. In this case, the intermediate node 25 substantially maintains its voltage level due to the parasitic capacitance.

[0016] exist Figure 1 In the example shown in FIG, when the digital transmission clock 18 is at a high level, the second transmission gate formed by the eleventh transistor 22 and the twelfth transistor 23 can charge the input node 24 of the subsequent analog circuit to the potential of the intermediate node 25. At this time, the inverted digital transmission clock 19 is at a low level. If the digital transmission clock 18 is at a low level, and therefore the inverted digital transmission clock 19 is at a high level, the second transmission gate formed by the eleventh transistor 22 and the twelfth transistor 23 is turned off. In this case, the input node 24 substantially maintains its voltage level due to parasitic capacitance.

[0017] The thirteenth transistor 30 may connect the intermediate node 25 to the reference potential 8 .

[0018] The first problem that now arises is that the reference voltage source formed by the current source 4 and the first transistor 7 has a permanent quiescent current due to the MOS diode connection of the first transistor 7. The current value of this current is much higher than the leakage current of the first transistor 7 when it is turned off. Figure 1 In the circuit, the first transistor 7 cannot perform the IDDQ test.

[0019] The second problem is that the control input of the second transistor 9 (its gate) always has a reference voltage, so that it operates as a current source and therefore has a continuous quiescent current. The current value of this current is much higher than the leakage current of the second transistor 9 when it is turned off. Therefore, in Figure 1 In the circuit shown, the second transistor 9 cannot be subjected to the IDDQ test.

[0020] The third problem is that the control input terminal (gate) of the eighth transistor 16 always has a reference voltage, so that it operates as a current source and therefore also has a continuous quiescent current. The current value of this current is much higher than the leakage current of the eighth transistor 16 when it is turned off. Figure 1 In the circuit shown, the eighth transistor 16 cannot be subjected to the IDDQ test.

[0021] The fourth problem is that when the third transistor 10 is turned on, the reference voltage source formed by the second transistor 9 and the fifth transistor 12 has a constant quiescent current due to the MOS diode connection of the fifth transistor 12. The current value of this current is usually much higher than the leakage current of the cut-off fifth transistor 12. Figure 1 In the circuit shown, the fifth transistor 12 cannot be subjected to the IDDQ test.

[0022] The fifth problem is that the control input terminal (gate) of the sixth transistor 13 always has a reference voltage, so that it operates as a current source and thus has a continuous quiescent current. The current value of this current is much higher than the leakage current of the cut-off sixth transistor 13. Therefore, in Figure 1 In the circuit shown, the sixth transistor 13 cannot be subjected to the IDDQ test.

[0023] The sixth problem is that the control input terminal (gate) of the seventh transistor 15 always has a certain voltage, so that it is not without quiescent current. Therefore, it also has a continuous quiescent current. The current value of this current is much higher than the leakage current of the cut-off seventh transistor 15. Therefore, in Figure 1 In the circuit shown, the seventh transistor 15 cannot be subjected to the IDDQ test.

[0024] Due to the current source function of the second transistor 9, a quiescent current flows through the third transistor 10 and the fourth transistor 11. Although one of the transistors can be turned off via the input, the other amplifier branch still generates a quiescent current in the supply lines 3 and 8, which is much higher than the leakage current of the off transistor. Figure 1 In the circuit of FIG, the third transistor 10 and the fourth transistor 11 cannot be tested for IDDQ. For the same reason, Figure 1 In the circuit, the fifth transistor 12 and the sixth transistor 11 cannot perform the IDDQ test either.

[0025] Due to the current source function of the eighth transistor 16, the static current flows through the eighth transistor 16 and the seventh transistor 15. Figure 1 In the circuit, the seventh transistor 15 and the eighth transistor 16 cannot perform the IDDQ test.

[0026] In contrast, a transmission gate does not necessarily have leakage current flowing through it. If the output terminal 26 of the source follower and the intermediate node 25 are at the same or substantially the same potential, no leakage current will flow through the ninth transistor 20 and the tenth transistor 21. Therefore, the IDDQ test of the ninth transistor 20 and the tenth transistor 21 lacks simulation of the leakage current in these transistors. The same is true for the eleventh transistor 22 and the twelfth transistor 23. Therefore, the IDDQ test of the eleventh transistor 22 and the twelfth transistor 23 lacks simulation of the leakage current in these transistors.

[0027] However, in order to improve functional safety, it is desirable to stress test all transistors of a mixed-signal circuit using an increased operating voltage during IDDQ testing, so that imperfectly manufactured transistors and circuit elements can be detected and, if necessary, defects that have not yet manifested can be activated by stress voltage.

[0028] Therefore, there are currently problems in generating test vectors for analog portions and adapting IDDQ testing to transistors in the analog portion of mixed-signal circuits. Due to the aforementioned reasons, functional test vectors for large digital control buses in the analog portion of mixed-signal circuits typically have very limited test coverage.

[0029] Furthermore, unlike digital circuits, designers cannot fully automatically generate test vectors for analog circuits. Fully automatic test vector generation (ATPG) for analog circuits is crucial for achieving optimal test coverage. The control signals used by the digital circuits to control the analog circuits (hereinafter referred to as D2A control signals) are typically not arbitrarily changed to avoid short circuits, damage, and other issues.

[0030] The quiescent current consumption of the analog part and its deviations are significantly higher than the expected leakage current of the transistor in the event of a defect. Therefore, specifying a test threshold for the quiescent current is difficult, if not impossible.

[0031] Experience has shown that applying an increased voltage between the positive supply voltage line 3 and the reference potential line 8 (VDDA) of the analog portion of a mixed-signal circuit causes virtually no load on any of the analog portion's transistors. Experiments and studies conducted during the development of the technical concept described herein have shown that the load level on the analog portion's transistors is only 2%. This value can be classified as "untestable."

[0032] The implementation of bus systems from the digital to the analog portion of mixed-signal circuits often requires a large number of memory cells (latches). These memory cells can contain a large number of transistors in the 5V range and have a significant control electrode area. To achieve a zero-defect strategy, voltage stress testing should be performed on such a large control electrode area.

[0033] US 2005 / 0024075 A1 discloses a device that uses a "defect injection transistor" to generate a defect state in an analog circuit, thereby enabling detection of the defect state. However, the technical concept of US 2005 / 0024075 A1 does not disclose a method or related device that can perform IDDQ testing similar to the method allowed by digital circuits.

[0034] The technical concept of US 2005 / 0024075 A1 discloses a method of injecting a defect node potential through a "defect injection transistor." In this way, US 2005 / 0024075 A1 improves the excitability of the analog circuit being tested.

[0035] However, the technical concept of US 2005 / 0024075 A1 does not address the lack of IDDQ testability for analog circuits. None of the circuit examples cited in US 2005 / 0024075 A1 achieves full IDDQ testability. "Full" refers to IDDQ testing of all analog transistors. Therefore, the technical concept of US 2005 / 0024075 A1 addresses a completely different problem.

[0036] The technical concept of US 2005 / 0024075 A1 proposes inserting a test block (referred to as a BICS in US 2005 / 0024075 A1) into the ground terminal of an analog CMOS circuit block (referred to as a CUT in US 2005 / 0024075 A1) and using this test block to monitor the operating current of the analog circuit block CUT. However, this is not an IDDQ test as understood in testing technology.

[0037] At this point, this article quotes the following from Wikipedia (source: https: / / en.wikipedia.org / wiki / Iddq_testing):

[0038] “Iddq testing is a method for testing CMOS integrated circuits for the presence of manufacturing faults. It relies on measuring the supplycurrent (Idd) in the quiescent state (when the circuit is not switching and inputs are held at static values). The current consumed in the state iscommonly called Iddq for Idd (quiescent) and hence the name.

[0039] Iddq testing uses the principle that in a correctly operatingquiescent CMOS digital circuit, there is no static current path between thepower supply and ground, except for a small amount of leakage. Many commonsemiconductor manufacturing faults will cause the current to increase byorders of magnitude, which can be easily detected. This has the advantage ofchecking the chip for many possible faults with one measurement. Anotheradvantage is that it may catch faults that are not found by conventionalstuck-at fault test vectors.

[0040] Iddq testing is somewhat more complex than just measuring the supplycurrent. If a line is shorted to Vdd, for example, it will still draw noextra current if the gate driving the signal is attempting to set it to '1'.However, a different input that attempts to set the signal to 0 will show alarge increase in quiescent current, signaling a bad part. Typical Iddq testsmay use 20 or so inputs. Note that Iddq- -test inputs require onlycontrollability, not observability. This is because observability is achieved through the shared power supply connection".

[0041] The translation is as follows: "The Iddq test is a method for testing CMOS integrated circuits for manufacturing defects. It relies on measuring the supply current (Idd) in a quiescent state (when the circuit is not switching and the inputs are held at static values). Therefore, the current consumed in this state is often referred to as Iddq, or Idd (quiescent).

[0042] Iddq testing exploits the principle that in a normally operating CMOS digital circuit in a static state, there is no static current path between the power supply and ground, leaving only a small amount of leakage current. Many common semiconductor manufacturing defects can cause current increases by orders of magnitude, and these defects are easily detected. The advantage of this is that a single measurement can check for many possible defects in the chip. Another benefit is that it can capture defects that traditional fixed-defect test patterns cannot reveal.

[0043] Iddq testing is more complex than simply measuring supply current. For example, if a line is shorted to Vdd, the gate driving the signal will still draw no additional current when attempting to set it to "1." However, if a different input attempts to set the signal to 0, this will result in a significant increase in quiescent current, indicating a defective device. A typical Iddq test may require around 20 inputs. Note that the Iddq test inputs must only be controllable, not observable. This is because observability is achieved through the shared power supply terminals.

[0044] However, the technical concept of US 2005 / 0024075 A1 still indicates the existence of a static current path between the positive and negative power supply voltages. The "IDDQ current" mentioned in paragraph

[0042] of US 2005 / 0024075 A1 is not the leakage current of the digital circuit in the static switching state, but the static current of the analog circuit derived from the static current path.

[0045] The technical concept of US 2005 / 0024075 A1 does not allow for fully automated generation of IDDQ test vectors, making it difficult to demonstrate adequate test coverage in circuit designs that comply with ISO 26262 functional safety requirements.

[0046] The technical concept of US 2005 / 0024075 A1 also does not teach any suggestions on how to handle feedback branches in analog circuits.

[0047] In US 2005 / 0024075 A1 Figure 4 In the circuit shown, even in the test state, there is always an operating current, not just the leakage current of the off transistor. Therefore, US 2005 / 0024075 A1 does not disclose any circuit that can perform IDDQ testing in any state (as described in the present invention or within the meaning defined by Wikipedia).

[0048] JP 2003-156545 A discloses a semiconductor chip integrating analog and digital circuits. This semiconductor chip is assembled according to the technical concept of JP 2003-156545 A. According to the technical concept of JP 2003-156545 A, a common power supply terminal of the semiconductor chip is used to test a semiconductor device that supplies power supply voltage to the analog and digital circuits, thereby detecting leakage current in the digital circuit. The method of JP 2003-156545 A includes interrupting the power line from the power supply terminal to the digital circuit during testing, thereby placing the digital circuit in a test mode. Summary of the Invention

[0049] Purpose

[0050] The object of the present invention is therefore to create a solution which does not have the above-mentioned disadvantages of the prior art and has further advantages.

[0051] This object is achieved by the technical concept of the independent claim. If necessary, other embodiments can be the subject of the dependent claims.

[0052] Solution

[0053] The basic idea of ​​the technical concept proposed here is to use additional switching transistors to switch the transistors of the analog part of the mixed-signal circuit in the test state of the analog circuit 1, thereby essentially obtaining a CMOS logic circuit that can be stimulated with test vectors like an ordinary CMOS logic circuit, and for which IDDQ test vectors can be generated fully automatically by the ATPG program.

[0054] To this end, the technical concept proposed by the present invention proposes providing at least one IDDQ test state for the exemplary analog circuit 1. Furthermore, the technical concept proposed by the present invention proposes inserting additional switches in the circuit of the analog circuit element, wherein these switches have at least one switching state during normal operation of the exemplary analog circuit 1 and have at least one IDDQ switching state.

[0055] The present invention therefore relates to an analog circuit 1 based on MOS, BiCMOS or CMOS, wherein the analog circuit 1 is designed to realize a predetermined circuit purpose in the normal state of the analog circuit 1. The analog circuit 1 has one or more input signals and / or one or more output signals. The analog circuit 1 generally contains one or more analog signals inside the analog circuit 1. According to the proposal, the analog circuit (1) is connected to a test logic 38, which is designed to set the analog circuit 1 to a normal state and to set the analog circuit 1 to at least a first test state and / or to other test states as necessary, based on the control of the test logic 38 by an external measurement system. The analog circuit 1 includes first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30), which, in the normal state of the analog circuit 1, perform the functions of the analog circuit 1 according to the predetermined circuit purpose of the analog circuit 1. Therefore, these first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) represent the actual analog circuit 1 or at least a basic part of the analog circuit 1. These first components are preferably MOS transistors or bipolar transistors. Such first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) generally each have a control electrode, and the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) can also be operated as switches via the control electrode. When operating as switches, the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) can be in an open state and a closed state, respectively, as the respective switch states. For the purposes of this document, the first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) is fully connected in the on state, i.e., it conducts electricity. Fully connected means that the on-resistance (R) of the first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) (i.e., the transistor) is ON Resistance) corresponds to the minimum on-resistance of these first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30), and the deviation is less than 25%. The first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) are usually completely turned off in the off state, that is, cut off. Completely turned off means that the on-resistance (R) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) (i.e., transistors) is OFFThe analog circuit (1) preferably includes a second component (S1 to S9; G1 to G9). The test logic 38 sets the switch state of one or more first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) through the second component (S1 to S9; G1 to G9) in the first test state of the analog circuit 1. A control electrode (33, 34, 36, 37) of at least one of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) is not directly connected to an input signal or an output signal. Such an IDDQ test of an analog circuit 1 has not been described in the prior art. In a first test state, a test logic 38 disconnects the control electrode (33, 34, 36, 37) of the first component (7, 9, 12, 16) of the first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) from the rest of the analog circuit (1) via at least one switch (S1, S2, S3, S4). Therefore, the control electrodes (33, 34, 36, 37, 39) of the first components (7, 9, 12, 16) in the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) are left floating. Therefore, these control electrodes are easily affected. However, their potentials are not fixed. Therefore, the switching states of the first components (7, 9, 12, 16) in the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) are also not fixed. To set the switch state, the test logic 38 switches on the control electrodes (33, 34, 36, 37, 39) of the first components (7, 9, 12, 16) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) through the first devices (G1, G2, G5, G6) to enter the on state or switches them off to enter the off state. In a normal state, the test logic 38 controls the first devices (G1, G2, G5, G6) so that the first devices (G1, G2, G5, G6) do not affect the control electrodes (33, 34, 36, 37, 39) of the first components (7, 9, 12, 16) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) in the normal state of the analog circuit 1.Preferably, the first devices (G1, G2, G5, G6) are tri-state drivers, and the first test logic 38 switches their outputs to a tri-state state with a high-ohmic output resistance in a normal state and to a low-ohmic low-level or high-level state in a first test state. The output terminals of the respective tri-state drivers are connected to the respective control electrodes (33, 34, 36, 37, 39) of the respective first components (7, 9, 12, 16) among the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30).

[0056] In a normal state, the test logic 38 connects the control electrodes (33, 34, 36, 37, 39) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) to the nodes of the rest of the analog circuit (1) through switches (S1, S2, S3, S4), thereby ensuring the normal function of the analog circuit 1 in a normal state.

[0057] The exemplary analog circuit 1 preferably has at least a normal state, a first IDDQ test state, and a second IDDQ test state. In the normal state, the exemplary analog circuit 1 performs its intended normal operation. In the first IDDQ test state, all P-channel transistors of the exemplary analog circuit 1 are preferably fully turned on, and all N-channel transistors of the exemplary analog circuit 1 are preferably fully turned off. In the second IDDQ test state, all P-channel transistors of the exemplary analog circuit 1 are preferably fully turned off, and all N-channel transistors of the exemplary analog circuit 1 are preferably fully turned on.

[0058] To achieve this, the technical concept proposed herein proposes that, in the first IDDQ test state and the second IDDQ test state, all feedback branches are disconnected by a feedback switch.

[0059] The present invention comprises an improved analog circuit that can be fabricated using, for example, MOS, BiCMOS, or CMOS semiconductor technologies. For the purposes of this document, semiconductor technologies that are functionally equivalent to such MOS, BiCMOS, or CMOS semiconductor technologies are encompassed by the term "MOS, BiCMOS, or CMOS." A semiconductor technology is functionally equivalent if it provides a semiconductor switch having a first terminal, a second terminal, and a control terminal, and the semiconductor switch opens or closes the electrical connection between the first and second terminals based on the potential of the control terminal or an input current. This definition does not take into account any leakage current.

[0060] The technical concept proposed by the present invention is intended to generally relate to analog circuits. The analog circuit is preferably part of a microintegrated circuit. Such an analog circuit generally realizes a predetermined circuit purpose during the expected operation of the circuit using the analog circuit. The predetermined circuit purpose can be, for example, an amplifier, a differential amplifier, a current source, a voltage source, an analog multiplier, an analog multiplexer, an analog filter, an oscillator, a delay line, a phase shifter, an analog phase-locked loop (PLL), a reset circuit, an electronic fuse, an analog adder, an analog subtractor, an analog differentiator, an analog integrator, etc. and their interconnections, but the technical concept proposed by the present invention is not limited thereto. The present invention, for example, refers to the following books:

[0061] Dietmar Ehrhardt, “Integrated Analog Circuit Technology: Technology, Design, Simulation, and Layout,” Vieweg Publishing, June 28, 2000, 2000 edition, ISBN-10: 3528038608, ISBN-13: 978-352803860;

[0062] Phillip E. Allen (author) and Douglas R. Holberg, “CMOS Analog Circuit Design,” Oxford University Press, 3rd edition, International Edition, July 13, 2012, ISBN-10: 0199937427, ISBN-13: 978-0199937424;

[0063] Saggio, Giovanni, and Tor Vergata, “Principles of Analog Electronics,” Taylor & Francis Inc., January 29, 2014, ASIN: 1466582014, ISBN-10: 9781466582019, ISBN-13: 978-1466582019;

[0064] “Halbleiter-Schaltungstechnik (Semiconductor Circuit Technology)” by Ulrich Tietze and Christoph Schenk, 5 July 2019, Springer-Verlag (SpringerVieweg), 16th edition, expanded and updated, 2019 edition, ISBN-10: 3662485532, ISBN-13: ‎978-3662485538.

[0065] To be considered an analog circuit within the meaning of the present invention, an analog circuit must have at least one analog input signal, one analog output signal, or an analog signal within the analog circuit. When evaluating whether a circuit is an analog circuit, the supply voltage line should be explicitly considered.

[0066] Regarding the definition of analog signals, the present invention is explained using the prior art on the following Internet website as an example: https: / / www.elektronik-kompendium.de / sites / kom / 2405151.htm.

[0067] “An analog signal is a physical quantity that varies continuously both in magnitude (amplitude) and in value over time.

[0068] A digital signal (from the Latin word "digitus" meaning finger) is a physical quantity that can only take on specific discrete values. These values ​​correspond to a predetermined number of states. If there are two predetermined states, the signal is called a binary (digital) signal.

[0069] To be considered an analog circuit in the sense of this invention, an analog circuit must have at least one input signal, one output signal, or a signal within the analog circuit, and these signals must exhibit continuous values ​​in both magnitude (amplitude) and time. Amplitude is typically the potential of the line carrying the signal relative to the potential of a reference node of the analog circuit, or the value of the current in the line carrying the signal.

[0070] In particular, the proposed simulation circuit is connected with the test logic (see Figure 2 As mentioned above, the test logic is preferably a test logic based on IEEE Standard 1149 and its sub-versions. However, it can also be a scan path activated by a test terminal external to the microintegrated circuit.

[0071] In particular, the test logic is a digital circuit. In particular, the test logic is designed to place the analog circuit into a normal state and at least a first test state.

[0072] Preferably, the test logic can place the analog circuit in a normal state and multiple test states. Different test states are used for different test purposes and / or to activate defects in specific parts of the analog circuit during load testing (such as voltage stress testing).

[0073] In this regard, the present invention refers to “Integrated Circuit Test Engineering: Modern Techniques” by Ian A. Grout, Springer London, published on June 2, 2010 (2006 edition), ISBN-10: 1846280230, ISBN-13: 978-1846280238.

[0074] In particular, the analog circuit according to the present invention includes first components that, during normal operation, perform the functions of the analog circuit, depending on the intended use of the circuit. In the normal state of the analog circuit, the interconnections of these first components generally correspond, at least in part, to circuits known in the prior art. It is contemplated that the principles proposed by the present invention may also be applied to analog circuits not previously known in the prior art after the disclosure of the technical concept of the present invention.

[0075] In particular, to improve testability and / or stress resistance, the analog circuit according to the present invention includes, in addition to the first components, second components that enable the test logic to set the switch state of the first components when the analog circuit is in at least a first test state. Preferably, the test logic controls the additional second components.

[0076] In one embodiment, an analog circuit according to the present invention includes an N-channel transistor and a P-channel transistor.

[0077] In particular, the second component of the test logic is capable of setting the switch state of the first component in at least a first test state of the analog circuit so that in the first test state all N-channel transistors are turned off and all P-channel transistors are turned on, or alternatively, all N-channel transistors are turned on and all P-channel transistors are turned off.

[0078] Similarly, the analog circuit may have a second test state settable by test logic in which all N-channel transistors are on and all P-channel transistors are off, or alternatively, all N-channel transistors are off and all P-channel transistors are on.

[0079] Therefore, the second test state is preferably complementary to the first test state with respect to the switching states of the N-channel transistor and the P-channel transistor.

[0080] In another embodiment, the analog circuit 1 according to the present invention includes a positive power supply voltage line and a negative power supply voltage line. As before, the test logic preferably can place the analog circuit in a normal state and at least a first test state. Preferably, in this alternative scenario, the analog circuit also has multiple test states. The above description also applies here.

[0081] In particular, again, the analog circuit 1 comprises first components that, in normal operation, perform the intended function of the analog circuit.

[0082] In particular, in addition to the first components, the analog circuit 1 also includes second components, which enable the test logic to set the switching state of the first components in at least the first test state of the analog circuit. As a result, the measuring device can control the test logic of the exemplary analog circuit of the exemplary microintegrated circuit, put the first analog circuit into the test state, and thereby control the switching state of the first component. In this case, the measuring device can preferably also control the switching state of the second component. Therefore, the behavior of the analog circuit in this test state is similar to that of a digital circuit. Therefore, in this test state, the analog circuit can be applied to the test method of the digital circuit. Therefore, the method for planning the test of the digital circuit (such as fully automatic test pattern generation and / or IDDQ test method) can also be applied to the analog circuit in this test state.

[0083] In particular, the analog circuit according to the present invention has multiple potential current paths from the positive power supply voltage line to the negative power supply voltage line. These current paths from the positive power supply voltage line to the negative power supply voltage line of the analog circuit generally include components in the first component and / or the second component. The analog circuit is preferably designed so that substantially all of the first component and / or the second component (S1 to S9; G1 to G9) are part of at least one such current path. Therefore, these current paths generally and preferably pass through these first components and / or these second components.

[0084] The second component enables the test logic to set the switch state of the first component while simulating at least a first test state of the circuit. The test logic preferably sets the switch state of the first component so that in every possible current path from the positive power supply voltage line to the negative power supply voltage line, at least one first component and / or at least one second component is blocked.

[0085] If the measuring device now applies an increased supply voltage to the analog circuit between the positive supply voltage line and the negative supply voltage line, the increased voltage is applied to the first component that is cut off and / or the second component that is cut off. As a result, these cut-off components will be subjected to a greater voltage load, which may cause stress to potentially damaged components and generally lead to an increase in leakage current between the positive supply voltage line and the negative supply voltage line. The measuring device can then detect this leakage current as needed and compare it with an allowed leakage current threshold. If the leakage current value detected by the measuring device is higher than the leakage current threshold, the measuring device can infer that there is a defect, deviation, quality problem or the like in the analog circuit and can discard the related microelectronic circuit containing the analog circuit. For the sake of clarity, the present invention refers to defects, deviations, quality problems, etc. in analog circuits as defects.

[0086] In a further refinement of the above embodiment, a second component of the test logic is capable of setting the switching state of the first component in at least a first test state of the analog circuit, wherein the test logic performs setting of the switching state of the first component such that, in at least one current path between the positive power supply voltage line and the negative power supply voltage line of the analog circuit, exactly one first component and / or exactly one second component is turned off. The present invention refers to this current path as a target current path. Consequently, multiple components in other current paths between the positive power supply voltage line and the negative power supply voltage line of the analog circuit (these paths are not the target current path) can be turned off. At least one component of the analog circuit is also turned off in other current paths between the positive power supply voltage line and the negative power supply voltage line of the analog circuit (these paths are not the target current path). As a result, only leakage current flows between the positive power supply voltage line and the negative power supply voltage line of the analog circuit. Consequently, other components in the target current path are not turned off. Hereinafter, the present invention refers to this turned-off component in the target current path as an IDDQ component.

[0087] By limiting component cutoff to the IDDQ components in the target current path and switching the other components in the relevant current path to a conductive state, the measurement device can apply a voltage between the positive and negative supply voltage lines of the analog circuit, which then falls completely across the IDDQ component. If the measurement device increases the voltage between the positive and negative supply voltage lines to the maximum allowable value, this ensures that the measurement device applies the maximum load to the IDDQ component through the applied voltage. This maximizes the degradation of the IDDQ component. Experience has shown that this load does not accumulate over the expected service life of the IDDQ component. Experience has shown that if the parameters of this stress test (such as the applied supply voltage value) are selected appropriately, properly manufactured IDDQ components will not suffer any prior damage.

[0088] In this way, the measurement device can apply specific loads to individual components of the analog circuit. Preferably, the test patterns generated by the test logic are selected so that each test pattern converts multiple components of the analog circuit into IDDQ components. A test pattern is a vector that typically contains the switching states of the first and second components. By setting the test states, the test logic generates a specific test pattern, whereby the components of the analog circuit are in the switching state corresponding to the test pattern. The present invention clarifies that this applies to the entire solution proposed by the present invention.

[0089] By simultaneously setting multiple components of the analog circuit as IDDQ components of corresponding current paths, the number of test states required to fully test all or most components of the analog circuit is reduced. DETAILED DESCRIPTION

[0090] Further explanation based on the accompanying drawings

[0091] The present invention is exemplary Figures 2 to 7 The present invention is further explained.

[0092] For example, taking the exemplary analog circuit 1 as an example, the technical concept proposed by the present invention is to disconnect the MOS diode circuit of the first transistor 7 by opening the first switch S1 in the first IDDQ test state and the second IDDQ test state. In the normal state, the first switch S1 is closed, thereby forming the MOS diode circuit of the first transistor 7. Therefore, the first switch S1 is a feedback switch, which is closed in the normal operation state and opened in the two test states (i.e., the first IDDQ test state and the second IDDQ test state). The first switch S1 is preferably a MOS transistor, which is preferably opened or closed by the test logic of the microintegrated circuit, and the exemplary analog circuit 1 is usually a part of the microintegrated circuit. For example, the test device can set the normal operation, the first IDDQ test state, or the second IDDQ test state through the test logic. For example, the test logic can be a JTAG test interface or a similar device.

[0093] Description of the example

[0094] ===============================================

[0095] The present invention utilizes Figure 2 An example is shown to explain the scenario. Figure 2 The exemplary analog circuit 1 shown may clearly have more than two test states. For the sake of clarity, the present invention initially describes only the first IDDQ test state and the second IDDQ test state, but this does not constitute a limitation to the technical concept proposed by the present invention.

[0096] Test Logic

[0097] ===============================================

[0098] As an example, Figure 2 The analog circuit 1 preferably has a test logic 38. The test logic 38 may be, for example, a test interface that complies with the JTAG boundary scan standard. The present invention references, for example, the JTAG standard IEEE 1149. More information about this standard can be found at the following website: https: / / de.wikipedia.org / wiki / Boundary_Scan_Test (Non-Patent Document 1).

[0099] A good overview is provided by LY Ungar, H. Bleeker, JE McDermid, and H. Hulvershorn, “IEEE-1149.x standards: achievements vs. expectations,” in Proceedings of the 2001 IEEE Autotestcon (IEEE System Readiness Technology Conference) (No. 01CH37237), 2001, pp. 188–205, DOI: 10.1109 / AUTEST.2001.948964 (Non-Patent Document 2).

[0100] IEEE Standard 1149 consists of several substandards:

[0101] “IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks,” IEEE Std 1149.6-2015 (revised from IEEE Std 1149.6-2003), pp. 1-230, March 18, 2016, DOI: 10.1109 / IEEESTD.2016.7436703 (Non-Patent Document 3).

[0102] “IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture,” IEEE Std 1149.7-2009, pp. 1-985, February 10, 2010, DOI: 10.1109 / IEEESTD.2010.5412866 (Non-Patent Document 4).

[0103] “IEEE Standard for Test Access Port and Boundary-Scan Architecture – Redline,” IEEE Std 1149.1-2013 (revised from IEEE Std 1149.1-2001), Redline, pp. 1-899, May 13, 2013 (Non-Patent Document 5).

[0104] “IEEE Standard for Test Access Port and Boundary-Scan Architecture,” IEEE Std 1149.1-2013 (revised from IEEE Std 1149.1-2001), pp. 1-444, May 13, 2013, DOI: 10.1109 / IEEESTD.2013.6515989 (Non-Patent Document 6).

[0105] “IEEE Standard for a Mixed-Signal Test Bus,” IEEE Std 1149.4-2010 (revised from IEEE Std 1149.4-1999), pp. 1-116, March 18, 2011, DOI: 10.1109 / IEEE STD.2011.5738198 (Non-Patent Document 7).

[0106] “IEEE Standard for Boundary-Scan-Based Stimulus of Interconnections to Passive and / or Active Components,” IEEE Std 1149.8.1-2012, pp. 1-95, August 9, 2012, DOI: 10.1109 / IEEESTD.2012.6259815 (Non-Patent Document 8).

[0107] “IEEE Standard for High-Speed ​​Test Access Port and On-Chip Distribution Architecture,” IEEE Std 1149.10-2017, pp. 1-96, July 28, 2017, DOI: 10.1109 / IEEESTD.2017.7995164 (Non-Patent Document 9).

[0108] “IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks- Redlin,” IEEE Std 1149.6-2015 (revised from IEEE Std 1149.6-2003), Redlin, pp. 1-441, March 18, 2016 (Non-Patent Document 10).

[0109] “IEEE Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device,” IEEE Std 1687-2014, pp. 1-283, December 5, 2014, DOI: 10.1109 / IEEESTD.2014.6974961 (Non-Patent Document 11).

[0110] “IEEE Draft Standard for Reduced-Pin and Enhanced-Functionality TestAccess Port and Boundary-Scan Architecture,” IEEE P1149.7 / D6, July 2020, pp. 1-1043, November 3, 2020 (Non-Patent Document 12).

[0111] “IEEE Draft Standard for a Mixed-Signal Test Bus,” IEEE P1149.4 / D2, September 2010, pp. 1-113, October 7, 2010 (Non-Patent Document 14).

[0112] “IEEE Approved Draft Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits,” IEEE P1838_D3.00, September 2019, pp. 1-63, November 7, 2019 (Non-Patent Document 15).

[0113] For the sake of completeness, the present invention also cites the following documents.

[0114] G. O.D. Acevedo and J. Ramírez-Angulo, “VDDQ: a built-in self-test scheme for analog on-chip diagnosis, compliant with the IEEE 1149.4 mixed-signal test bus standard,” in Proceedings of the 4th IEEE International Caracas Conference on Devices, Circuits, and Systems (No. 02TH8611), 2002, pp. I026–I026, DOI: 10.1109 / ICCDCS.2002.1004083 (Non-Patent Literature 13).

[0115] For clarity, Figure 2Not shown are control lines between the test logic 38 and tri-state gates ( G1 to G9 ) explained below, switches ( S1 to S9 ) also explained below, and other test control lines also explained below.

[0116] However, the control lines between the test logic 38 and the tri-state gates (G1 to G9) explained below, the switches (S1 to S9) also explained below, and other test control lines also explained below are necessary for the functioning of the technical principles disclosed in the present invention. Therefore, the drawings are only schematic and simplified.

[0117] Changes in interconnection of the first transistor 7

[0118] ===============================================

[0119] The technical concept proposed by the present invention further provides, using the exemplary analog circuit 1 as an example, that the MOS diode circuit of the fifth transistor 12 is disconnected by the second switch S2 in the first IDDQ test state and by opening the second switch S2 in the second IDDQ test state. Thus, the second switch S2 disconnects the control electrode 33 of the first transistor 7 from the first node 6. Therefore, after the second switch S2 is opened, the potential of the control electrode 33 of the first transistor 7 is undefined. However, to perform a sequenced test, it is necessary to establish a clear potential of the control electrode 33 of the first transistor 7 relative to the reference potential of the reference potential line 8. In the normal state, the second switch S2 is closed, thereby closing the MOS diode circuit of the fifth transistor 12 and generating a unique potential on the control electrode 33 of the first transistor 7. Therefore, the second switch S2 is a feedback switch that is closed during normal operation and open in two test states (i.e., the first IDDQ test state and the second IDDQ test state). The second switch S2 is preferably a MOS transistor, and its opening or closing is preferably implemented by the test logic of the microintegrated circuit.

[0120] General handling of feedback and characteristics of tri-state gates

[0121] ===============================================

[0122] During normal operation, the feedback determines the potential of the control electrodes of certain transistors in the analog circuit 1. However, by opening the feedback switches, the potential of the control electrodes of these transistors is no longer defined.

[0123] Therefore, the present invention proposes to preferably connect these control electrodes to a device that sets the potential of the target control electrode to a defined potential in the case of the first IDDQ test state or the second IDDQ test state, while not affecting it in the case of the normal state.

[0124] The present invention proposes setting each control electrode (which is in a floating state due to the opening of the feedback switch, i.e., its potential is undefined) to a defined potential by means of a tri-state gate (usually additional). To simplify the explanation, for example, it is assumed that the tri-state gate includes a first tri-state gate transistor, which pulls the output of the tri-state gate to the positive power supply potential when closed and does not affect the output of the tri-state gate when opened. To simplify the explanation, it is further assumed that the tri-state gate includes a second tri-state gate transistor, which pulls the output of the tri-state gate to the negative power supply potential when closed and does not affect the output of the tri-state gate when opened. The control logic ensures that the first tri-state gate transistor and the second tri-state gate transistor are never closed at the same time. The output of the tri-state gate has three states.

[0125] In the first state, the output of the tri-state gate is in a high-impedance state. In this high-impedance state of the tri-state gate, in this example, both the first tri-state gate transistor and the second tri-state gate transistor are turned on. Therefore, in the first state, the tri-state gate does not affect the node at its output.

[0126] In the second state, the output of the tri-state gate is connected to the negative supply voltage line. In this high impedance state of the tri-state gate, the first tri-state gate transistor is open and the second tri-state gate transistor is closed.

[0127] In the third state, the output of the tri-state gate is connected to the positive supply voltage line. In this high impedance state of the tri-state gate, the first tri-state gate transistor is closed and the second tri-state gate transistor is open.

[0128] Implementation of Exemplary Analog Circuit 1

[0129] ===============================================

[0130] Therefore, the present invention proposes to insert a first switch S1 in the reference voltage line of the first node 6. The test logic 38 controls the first switch S1. For the sake of clarity, the exemplary Figure 2 The control line from the test logic 38 to the first switch S1 is not shown. If the exemplary analog circuit 1 is in the normal state, the test logic 38 closes the first switch S1. If the exemplary analog circuit 1 is in the first IDDQ test state or the second IDDQ test state, the test logic 38 opens the first switch S1, thereby disconnecting the feedback from the first transistor 7 to itself.

[0131] The present invention further proposes to connect the control electrode 33 of the first transistor 7 to the output terminal of the first tri-state gate G1. The test logic 38 controls the first tri-state gate G1. For the sake of clarity, the exemplary Figure 2 The control line from test logic 38 to first tri-state gate G1 is not shown. Therefore, when exemplary analog circuit 1 is in the first or second IDDQ test state and first switch S1 is open, test logic 38 can apply a defined logic level to control electrode 33 of first transistor 7 via first tri-state gate G1. If exemplary analog circuit 1 is in a normal state, test logic 1 switches first tri-state gate G1 to high impedance. Ideally, if exemplary analog circuit 1 is in a normal state, first tri-state gate G1 behaves as if it is not present and does not interfere with the analog circuit functions of exemplary analog circuit 1.

[0132] If the exemplary analog circuit 1 is in the first IDDQ test state or the second IDDQ test state, the first tri-state gate G1 ideally sets the potential at the control electrode 33 of the first transistor 7. If the exemplary analog circuit 1 is in the first IDDQ test state or the second IDDQ test state, the first tri-state gate G1 ideally sets the switching state of the first transistor 7.

[0133] Therefore, the present invention further proposes connecting the control electrode 36 of the fifth transistor 12 to the output of the second tri-state gate G2. Test logic 38 controls the second tri-state gate G2. For clarity, the exemplary figures do not show the control line from the test logic 38 to the second tri-state gate G2. Therefore, when the exemplary analog circuit 1 is in the first IDDQ test state or the second IDDQ test state and the second switch S2 is open, the test logic 38 can apply a defined logic level to the control electrode of the fifth transistor 12.

[0134] exist Figure 1 In the example shown, the control electrode 28 of the third transistor 10 should serve as an external input of the exemplary analog circuit 1 .

[0135] exist Figure 1 In the example shown, the control electrode 29 of the fourth transistor 11 should serve as an external input of the exemplary analog circuit 1 .

[0136] Therefore, the present invention proposes to connect the control electrode 28 of the third transistor 10 to the output terminal of the third tri-state gate G3. The test logic 38 preferably controls the third tri-state gate G3. For the sake of clarity, the exemplary Figure 2These control lines from test logic 38 to third tri-state gate G3 are not shown. Therefore, when exemplary analog circuit 1 is in the first or second IDDQ test state, test logic 38 can apply a defined logic level to control electrode 28 of third transistor 10. Preferably, a seventh switch S7 is inserted in the circuitry connected to control electrode 28 of third transistor 10. When exemplary analog circuit 1 is in the first or second IDDQ test state, this switch disconnects control electrode 28 of third transistor 10 and the feed point of third tri-state gate G3, located on one side of seventh switch S7, from third node 31, located on the other side of seventh switch S7. In this state, seventh switch S7 is preferably open. In a normal state, seventh switch S7 is preferably closed and preferably connects third node 31 to control electrode 28 of third transistor 10. Therefore, it is possible to consider inserting the seventh switch S7 into the circuit of the control electrode 28 of the third transistor 10. When the exemplary analog circuit 1 is in the first IDDQ test state or the second IDDQ test state, the switch S7 disconnects the input of the third node 31 from the feed point of the third tri-state gate G3 and the control electrode 28 of the third transistor 10. When the exemplary analog circuit 1 is in the normal state, the switch S7 connects the input of the third node 31 to the feed point of the third tri-state gate G3 and the control electrode 28 of the third transistor 10. The test logic 38 preferably controls the additional seventh switch S7.

[0137] The present invention further proposes to connect the control electrode 29 of the fourth transistor 11 to the output terminal of the fourth tri-state gate G4. The test logic 38 controls the fourth tri-state gate G4. For the sake of clarity, the exemplary Figure 2These control lines from test logic 38 to fourth tri-state gate G4 are not shown. Therefore, when exemplary analog circuit 1 is in the first or second IDDQ test state, test logic 38 can apply a defined logic level to control electrode 29 of fourth transistor 11. Preferably, an eighth switch S8 is inserted in the circuitry connected to control electrode 29 of fourth transistor 11. When exemplary analog circuit 1 is in the first or second IDDQ test state, eighth switch S8 disconnects control electrode 29 of fourth transistor 11 and the feed point of fourth tri-state gate G4, located on one side of eighth switch S8, from fourth node 32, located on the other side of eighth switch S8. In this state, eighth switch S8 is preferably open. In a normal state, eighth switch S8 is preferably closed and preferably connects fourth node 32 to control electrode 29 of fourth transistor 11. Therefore, it is possible to consider inserting an eighth switch S8 in the circuit of the control electrode 29 of the fourth transistor 11. When the exemplary analog circuit 1 is in the first IDDQ test state or the second IDDQ test state, the switch S8 disconnects the input of the fourth node 32 from the feed point of the fourth tri-state gate G4 and the control electrode 29 of the fourth transistor 11. When the exemplary analog circuit 1 is in the normal state, the switch S8 connects the input of the fourth node 32 to the feed point of the fourth tri-state gate G4 and the control electrode 29 of the fourth transistor 11. The test logic preferably controls this additional switch.

[0138] Disconnection of circuit nodes electrically connected to each other

[0139] ================================================

[0140] The present invention further proposes that when the exemplary analog circuit is in an IDDQ test state, particularly in a first IDDQ test state or a second IDDQ test state, the electrically connected control electrodes of the exemplary analog circuit 1 are disconnected from each other by an additional switch.

[0141] exist Figure 1 In the example, the control electrode of the first transistor 7, the control electrode of the second transistor 9, and the control electrode 37 of the eighth transistor 16 are connected to each other through the first node 6 as a reference voltage line.

[0142] Figure 2 Modifications proposed in this respect of the invention are shown by way of example.

[0143] For example, the present invention proposes that when the exemplary analog circuit 1 is in the first IDDQ test state or the second IDDQ test state, the test logic 38 preferably disconnects the control electrode 34 of the second transistor 9 from the first node 6 through the third switch S3; when the exemplary analog circuit 1 is in the normal state, the test logic 38 preferably connects the control electrode 34 of the second transistor 9 to the first node 6 through the third switch S3. Therefore, when the exemplary analog circuit 1 is in the normal state, the test logic 38 preferably closes the third switch S3; when the exemplary analog circuit is in the first IDDQ test state or the second IDDQ test state, the test logic 38 preferably opens the third switch S3. The test logic 38 preferably controls the third switch S3. For clarity, the exemplary analog circuit 1 Figure 2 These control lines from the test logic 38 to the third switch S3 are not shown.

[0144] For example, the present invention proposes that when the exemplary analog circuit 1 is in the first IDDQ test state or the second IDDQ test state, the test logic 38 preferably disconnects the control electrode 37 of the eighth transistor 16 from the first node 6 through the fourth switch S4; when the exemplary analog circuit 1 is in the normal state, the test logic 38 preferably connects the control electrode 37 of the eighth transistor 16 to the first node 6 through the fourth switch S4. Therefore, when the exemplary analog circuit 1 is in the normal state, the test logic 38 preferably closes the fourth switch S4; when the exemplary analog circuit is in the first IDDQ test state or the second IDDQ test state, the test logic 38 preferably opens the fourth switch S4. The test logic 38 preferably controls the fourth switch S4. For clarity, the exemplary analog circuit 1 Figure 2 These control lines from the test logic 38 to the fourth switch S4 are not shown.

[0145] To ensure that control electrode 37 of second transistor 9 does not have an undefined potential in either the first or second IDDQ test state, the present invention proposes connecting control electrode 37 of second transistor 9 to the output of fifth tri-state gate G5. Test logic 38 preferably controls fifth tri-state gate G5. Thus, when exemplary analog circuit 1 is in either the first or second IDDQ test state, and third switch S3, first switch S1, and fourth switch S4 are therefore open, test logic 38 is generally capable of applying a defined logic level to control electrode 37 of second transistor 9.

[0146] Indirect control of switch state

[0147] Since the test logic 38 can generally control the switching states of the second transistor 9, the third transistor 10, the fourth transistor 11, and the fifth transistor 12 in the first IDDQ test state or the second IDDQ test state of the exemplary analog circuit 1, the test logic 38 can also control the switching state of the sixth transistor 13 in the first IDDQ test state or the second IDDQ test state. This is because the test logic 38 can generally set the potential of the control electrode 28 of the sixth transistor 13 by setting the switching states of the second transistor 9, the third transistor 10, the fourth transistor 11, and the fifth transistor 12. Therefore, the test logic 38 can generally set the switching state of the sixth transistor 13 by setting the switching states of the second transistor 9, the third transistor 10, the fourth transistor 11, and the fifth transistor 12.

[0148] Since the test logic 38 can control the switching states of the sixth transistor 13 and the fourth transistor 11 in the first IDDQ test state or the second IDDQ test state, the test logic 38 can generally also control the switching state of the seventh transistor 15 in the first IDDQ test state or the second IDDQ test state. This is because the test logic 38 can generally control the switching states of the sixth transistor 13 and the fourth transistor 11 in the first IDDQ test state or the second IDDQ test state, and therefore the test logic 38 can generally also control the potential of the second node 14 in the first IDDQ test state or the second IDDQ test state, and thus can generally also control the potential of the control electrode 39 of the seventh transistor 15 in the first IDDQ test state or the second IDDQ test state.

[0149] Since the test logic 38 can control the switching state of the seventh transistor 15 and the eighth transistor 16 in the first IDDQ test state or the second IDDQ test state, the test logic 38 can also control the potential of the output end of the source follower 26 composed of the seventh transistor 15 and the eighth transistor 16 in the first IDDQ test state or the second IDDQ test state.

[0150] Processing of intermediate nodes

[0151] Analog circuits also typically include switches that are intended to pull nodes, such as intermediate node 25, to the supply voltage potential or similar under certain conditions during normal operation. Figure 1 In the case of the exemplary analog circuit 1, the thirteenth transistor 30 is such a transistor.

[0152] One side of such a transistor is connected to a supply voltage line of a first polarity and the other side is connected to a node of an exemplary electrical side. The invention also proposes providing an additional switch for connecting the respective node to another supply voltage line.

[0153] The present invention proposes designing the control of such transistors and additional switches so that, in the normal state of the exemplary analog circuit, the additional switches are in an open state, and the transistors operate normally according to other control signals 40 of the entire circuit, as if no changes have occurred. However, in the first IDDQ test state or the second IDDQ test state of the exemplary analog circuit 1, the additional switches and transistors operate as tri-state gates, allowing the test logic to control the voltage level of the node.

[0154] The exemplary thirteenth transistor 30 is such a transistor. One side of the thirteenth transistor 30 of the exemplary analog circuit 1 is connected to the power supply voltage line 8 of the first polarity, and the other side is connected to the intermediate node 25 of the exemplary analog circuit 1. The present invention also proposes to provide an additional fifth switch S5 that can connect the corresponding intermediate node 25 to another power supply voltage line.

[0155] The present invention proposes to design the control of the thirteenth transistor 30 and the additional fifth switch S5 by the test logic 38 so that in the normal state of the exemplary analog circuit 1, the additional fifth switch S5 is in the open state, and the thirteenth transistor 30 operates normally according to other control signals of the entire circuit, as if nothing has changed.

[0156] In particular, this can mean, for example, that in Figure 2 In the example of FIG, the digital transmission clock 18 is an input signal of the test logic 38, and in the normal state of the exemplary analog circuit 1, the digital transmission clock 18 is equal to the modified digital transmission clock 41, and in the first IDDQ test state or in the second IDDQ test state, the test logic 38 generally generates the modified digital transmission clock 41 in a manner independent of the digital transmission clock 18. In addition, this can mean, for example, that in Figure 2 In the example, the inverted digital transmission clock 19 is an input signal of the test logic 38, and in the normal state of the exemplary analog circuit 1, the inverted digital transmission clock 19 is equal to the deformed inverted digital transmission clock 42, and in the first IDDQ test state or in the second IDDQ test state, the test logic 38 generally generates the deformed inverted digital transmission clock 42 in a manner independent of the inverted digital transmission clock 19.

[0157] However, in the first IDDQ test state or the second IDDQ test state of the exemplary analog circuit 1, the additional fifth switch S5 and the thirteenth transistor 30 operate together as the eighth tri-state gate G8, so that the test logic 38 can preferably control the voltage level of the intermediate node 25. To this end, the test logic 38 preferably controls the potential of the control electrode 43 of the thirteenth transistor 30. This means that the test logic preferably controls the switching state of the thirteenth transistor 30. Preferably, in Figure 2In the example shown in FIG1 , in a normal state of the exemplary analog circuit 1, the signal at the control electrode 43 of the thirteenth transistor 30 is equal to the inverted digital transmission clock 19. In the first IDDQ test state and the second IDDQ test state, the test logic 38 generally generates the signal 19 at the control electrode 43 of the thirteenth transistor 30 in a manner independent of the inverted digital transmission clock.

[0158] exist Figure 2 In the exemplary analog circuit 1 of FIG. 1 , the ninth transistor 20 and the tenth transistor 21 form a so-called transmission gate, which connects the intermediate node 25 to the output 26 of the source follower formed by the seventh transistor 15 and the eighth transistor 16 when the control electrodes of the ninth transistor 20 and the tenth transistor 21 are appropriately controlled. Figure 2 In the example, the test logic 38 generates a modified digital transmission clock 41 such that when the exemplary analog circuit 1 is in a normal state, the modified digital transmission clock 41 is equal to the digital transmission clock 18, and when the exemplary analog circuit 1 is in the first IDDQ test state or the second IDDQ test state, the test logic 38 generates the modified digital transmission clock 41 in a manner independent of the digital transmission clock 18.

[0159] Preferably, the test logic 38 then controls the control electrodes of the ninth transistor 21, the tenth transistor 21, the twelfth transistor 23, the eleventh transistor 22, and the thirteenth transistor 30 in a manner independent of each other, wherein the test logic 38 prevents and locks out uncontrolled lateral current. In the first IDDQ test state or the second IDDQ test state of the exemplary analog circuit 1, the test logic 38 can generally control the switching states of the seventh transistor 15, the eighth transistor 16, the thirteenth transistor 30, the ninth transistor 20, the tenth transistor 21, and the fifth switch S5 so that no lateral current occurs at these locations.

[0160] Figure 3 Basically with Figure 2 Correspondingly, the difference is that the ninth switch S9 can disconnect the second node 14 from the control electrode 39 of the seventh transistor 15 .

[0161] For example, the present invention proposes that when the exemplary analog circuit 1 is in the first IDDQ test state or the second IDDQ test state, the test logic 38 preferably disconnects the control electrode 39 of the seventh transistor 15 from the second node 14 by adding the ninth switch S9, and when the exemplary analog circuit 1 is in the normal state, the test logic 38 preferably connects the control electrode 39 of the seventh transistor 15 to the fourth node 6 through the ninth switch S9. Therefore, when the exemplary analog circuit 1 is in the normal state, the test logic 38 preferably closes the ninth switch S9, and when the exemplary analog circuit is in the first IDDQ test state or the second IDDQ test state, the test logic 38 preferably opens the ninth switch S9. The test logic 38 preferably controls the ninth switch S9. For clarity, the exemplary analog circuit 1 is Figure 3 These control lines from the test logic 38 to the ninth switch S9 are not shown.

[0162] To ensure that the control electrode 39 of the seventh transistor 15 does not have an undefined potential in the first or second IDDQ test state, the present invention preferably connects the control electrode 39 of the seventh transistor 15 to the output of the ninth tri-state gate G9. Test logic 38 preferably controls the ninth tri-state gate G9. Thus, when the exemplary analog circuit 1 is in the first or second IDDQ test state and the ninth switch S9 is open, the test logic 38 is generally capable of applying a defined logic level to the control electrode 39 of the seventh transistor 15. Thus, when the exemplary analog circuit 1 is in the first or second IDDQ test state and the ninth switch S9 is open, the test logic 38 is generally capable of controlling the switching state of the seventh transistor 15.

[0163] This simplifies test pattern generation because test logic 38 no longer needs to generate and set a pattern sequence based on a plurality of predetermined pattern time sequences. This simplifies the test pattern generation process for generating the pattern sequence required to be set by test logic 38. This shortens the test time of the measurement device, which represents an economic advantage.

[0164] In a transmission gate having a first transmission gate terminal and a second transmission gate terminal, the test logic 38 may also preferably control the potentials at the first transmission gate terminal and the second transmission gate terminal in the first IDDQ test state or the second IDDQ test state via at least one additional switch (here, the fifth switch S5). In this context, "control" preferably means that the test logic 38 may apply a voltage equal to the operating voltage to the transmission gate by controlling the transmission gate and the transistors and switches used to determine the potentials at the first transmission gate terminal and the second transmission gate terminal, wherein the direction of the voltage across the transmission gate may preferably be specified by the test logic.

[0165] Figure 2The example of the analog circuit 1 in FIG. 1 is now configured as follows: the test logic 38 can also connect the analog output 24 of the exemplary analog circuit 1 to the positive power supply voltage or the negative power supply voltage through the seventh tri-state gate G7 in the first IDDQ test state or the second IDDQ test state. Figure 2 In the normal state of the exemplary analog circuit 1 in FIG. 1 , the output terminal of the seventh tri-state gate G7 is preferably in a high impedance state because the switch of the seventh tri-state gate G7 is usually in an open state.

[0166] Voltage stress load used to activate previously damaged components

[0167] In a first exemplary embodiment of the present invention, maximum voltage stress is applied to the transistors of exemplary analog circuit 1 prior to actual IDDQ testing to uncover potential defects in the transistors. Typically, such potential defects would not have caused previous functional test failures because the transistors functioned normally. However, voltage stresses that perfectly manufactured transistors could withstand without damage can further damage these previously damaged transistors, causing the stress test to amplify the effects of damage already amplified during manufacturing testing to the point where it can be detected by the measurement equipment used to measure exemplary analog circuit 1.

[0168] In this first exemplary embodiment, the present invention proposes that, for example, in a first test step, a measuring device uses test logic 38 to switch all P-channel transistors of exemplary analog circuit 1 to an on state and all N-channel transistors to an off state in a first IDDQ test state of exemplary analog circuit 1. The measuring device increases the power supply voltage to a maximum allowable level and maintains this level for a maximum allowable time. This causes previously damaged transistors in exemplary analog circuit 1 to be damaged. However, this does not damage previously undamaged transistors in exemplary analog circuit 1. The maximum allowable time for this stress load depends on the semiconductor or CMOS technology used. The maximum allowable time is preferably determined during the development of the semiconductor or CMOS technology, or during component qualification of the technical concept disclosed in the present invention, by performing stress tests on a sufficient number of components, preferably with typical control of manufacturing parameters during production testing and stress testing.

[0169] In this first exemplary embodiment, the present invention proposes that, for example, in a second test step, the measurement device uses test logic 38 to switch all N-channel transistors of exemplary analog circuit 1 to an on state and all P-channel transistors to an off state in a second IDDQ test state of exemplary analog circuit 1. The measurement device increases the power supply voltage to a maximum allowable level and for a maximum allowable time. This may cause previously damaged transistors in exemplary analog circuit 1 to damage. However, this does not damage previously undamaged transistors in exemplary analog circuit 1.

[0170] If it is not possible to put all P-channel transistors and / or all N-channel transistors into the expected switching states, additional switches or tri-state gates are inserted into the design to isolate the control nodes of these transistors from other nodes in the first IDDQ test state and the second IDDQ test state and enable them to be controlled according to the above example.

[0171] In the context of the present invention, for example, a measuring device and / or a testing process of the analog circuit 1 may perform the first step and the second step individually or consecutively in any order.

[0172] Leakage current measurement of individual transistors

[0173] In a second exemplary embodiment of the present invention, a measuring device applies a generally increased power supply voltage to the exemplary analog circuit 1. The measuring device then uses test logic 38 to sequentially place the exemplary analog circuit 1 in different test states. Under each test state of the exemplary analog circuit 1, the test logic 38 typically sets the switch states of the transistors, switches, and tri-state gates of the exemplary analog circuit 1 in different ways. Hereinafter, the switch state vectors of these elements of the exemplary analog circuit 1 (i.e., the transistors, switches, and tri-state gates of the exemplary analog circuit 1) are referred to as modes. Therefore, the difference between two different modes only relates to the switch states of a single transistor, a single switch, or a single tri-state gate in the exemplary analog circuit 1 between the two modes. However, typically, for two different modes, at least two switch states of at least two of these elements are different between the two modes. Developers manufacturing the test typically select modes so that only leakage current flows under each of these test states. To this end, developers design the control signals for the measurement device so that the test logic generates a pattern for controlling transistors, switches, and tri-state gates and controls them so that in all potential current paths between the positive and negative power supply voltages, at least one transistor or switch is off, and no transverse current flows from the positive to the negative power supply voltage line in the exemplary analog circuit 1. Therefore, in the context of the present invention, transverse current is typically a short-circuit current flowing from the positive power supply voltage line 3 to the negative power supply voltage line 8 of the exemplary analog circuit 1, or a fault current having the same effect. Preferably, in each of these test states, the test logic 38 controls the transistors, switches, and tri-state gates so that in at least one current path between the positive and negative power supply voltage lines (or their functional equivalents), exactly one transistor or one switch is off, and the other transistors and switches in that current path are on. In all other potential current paths between the positive and negative power supply voltage lines (or their functional equivalents), at least one switch is open, or at least one transistor is off, so that current cannot flow through that path. These switches can also be explicitly referred to as switches within the tri-state gates. The present invention refers to this transistor in the off state or the switch in the off state as the "IDDQ test transistor" in this test state. The measuring device then uses the test logic 38 to set each test state in chronological order. In this process, the test logic 38 preferably sets a mode specific to the test state for each test state. The measuring device preferably determines the leakage current in each test state. The leakage current is generally the current consumption of the exemplary analog circuit 1, preferably the current consumption through the power supply voltage line. The measuring device compares the leakage current value detected in each test state with a set value. The set value can be global, specific to a test state group, or specific to each test state.A mixture of test states is also conceivable. The current consumption of the exemplary analog circuit 1 is typically the leakage current of the transistor being tested by IDDQ in each test state. Preferably, the measuring device changes the test state in the form of a pattern generated by the test logic 38 until all transistors and switches of the exemplary analog circuit 1 have been tested by IDDQ at least once. In a preferred embodiment, the measuring device can control the test logic 38, for example, via a JTAG test bus interface. The advantage of using this method in combination with the switches and tri-state gates in the exemplary analog circuit 1 is that, firstly, the leakage current of each transistor can be measured; secondly, when the measuring device measures the leakage current of the transistor, a maximum voltage stress can be applied to each transistor. In addition, the test pattern for generating the control signal for setting the test mode of the test logic 38 can be generated using an ATPG method. The test logic 38 should be reliably protected against lateral currents.

[0174] The test procedure preferably includes an initial stress test that utilizes the first embodiment of the invention to maximize the acceleration of activation of latent defects by applying the maximum supply voltage, and is optionally followed by a systematic measurement of the leakage current of all transistors by one or more IDDQ measurements (possibly using different modes).

[0175] Furthermore, practice has shown that in many cases, it is sufficient to perform stress testing using the method in the first embodiment of the present invention and then measure the current consumption of the exemplary analog circuit 1 during normal operation. However, this measurement method has low accuracy.

[0176] The present invention proposes combining the testing of the exemplary analog circuit 1 with the digital testing of the measuring device. To achieve this, the present invention proposes integrating digital flip-flops (storage cells) into the scan path of the test logic 38 during one, several, or all test states. These digital flip-flops thus block signals to and from the analog circuit 1 during these test states. Simply put, the "gates" of the exemplary analog circuit are thus closed and controlled by the test logic 38, which can control these digital flip-flops or they can be part of the test logic 38.

[0177] The measurement device sets the test state and mode via the scan path of the test logic 38 and controls the test logic 38 accordingly.

[0178] When measured in a clock-stopped test state, the supply current of the exemplary analog circuit should generally be close to zero in different states with different modes. Actual tests conducted during the development of the method of the present invention showed that very good results can be achieved by using an automatically generated IDDQ test pattern (containing approximately 20 IDDD measurement points).

[0179] The development of the present invention has shown that voltage stress (typically an increased gate voltage lasting 20ms) can damage weaker transistors. Subsequently, a significant increase in leakage current can be measured. The level and duration of these voltage overshoots depend largely on the specific semiconductor technology or CMOS technology used to implement the analog circuit 1.

[0180] In order to solve the above problem, the present invention further proposes a method for performing IDDQ testing on an analog circuit 1 . Figure 4 The method is shown in simplified schematic form. Assume that the analog circuit 1 is, for example, Figure 3 The embodiment shown corresponds to an analog circuit 1 .

[0181] The method proposed here consists of multiple steps.

[0182] If no measuring device is available, the method starts with step 400 of providing a measuring device.

[0183] In a subsequent step, power is supplied to the simulation circuit 1 ( 401 ), preferably via a measuring device.

[0184] In a subsequent step, the analog circuit 1 is switched to a first test state ( 402 ), wherein the measuring device preferably performs this switching via the test logic 38 , for example via a JTAG test bus interface.

[0185] In a subsequent step, the current consumption of the analog circuit 1 in this first test state is detected (403) and a current consumption value is determined, in particular by a measuring device which preferably detects the current value of one of the supply voltage lines 3, 8 fed to the analog circuit 1.

[0186] In a subsequent step, the detected current consumption value is compared with a set value ( 404 ), wherein the comparison is preferably performed by the measuring device.

[0187] In a subsequent step, if the current consumption value is greater than a set value, a defect is inferred (405), wherein the measuring device preferably performs this inference and preferably, in the event of such a defect, discards the possibly defective analog circuit 1 (406).

[0188] In the event that the measuring device does not conclude that analog circuit 1 is defective in the previous step 405, analog circuit 1 can be used as intended with a higher probability (407) if it is not discarded for other reasons in further, subsequent or previous tests.

[0189] In order to solve the above problem, the present invention further proposes a method for performing IDDQ testing on an analog circuit 1 . Figure 5The method is shown in simplified schematic form. Assume that the analog circuit 1 is, for example, Figure 3 The illustrated embodiment corresponds to an analog circuit 1 .

[0190] For example, with Figure 3 In contrast to the exemplary embodiment shown, analog circuit 1 is now intended to have one or more further test states in addition to the first test state.

[0191] The present invention collectively refers to these other test states and the first test state as "test states".

[0192] The test states should preferably be distinguished such that at least one IDDQ component of one test state is different from all other IDDQ components of all other test states. Thus, the IDDQ component of the test state is different from any other IDDQ component of the other test states.

[0193] The method proposed here consists of multiple steps.

[0194] If no measuring device is available, the method starts with step 500 of providing a measuring device.

[0195] In a subsequent step, the simulation circuit 1 is powered (501), preferably by a measuring device.

[0196] In a subsequent step, the analog circuit 1 is switched to one of the test states by setting and adopting this test state (502), wherein the measuring device preferably performs this switching and setting via the test logic 38 (for example via the JTAG test bus interface), and the analog circuit 1 subsequently adopts this test state.

[0197] In a subsequent step a), the current consumption of the analog circuit 1 in this test state is detected (503) and the current consumption value is determined, in particular by a measuring device, which preferably detects the current value of one of the supply voltage lines 3, 8 fed to the analog circuit 1.

[0198] In a subsequent step b), the detected current consumption value is compared with a set value ( 504 ), which can be specific to the set test conditions, wherein the comparison is preferably performed by the measuring device.

[0199] In a subsequent step c), the analog circuit 1 is switched to another of the test states by setting and adopting the other test state (508), wherein the other test state is different from the previously adopted test state, and wherein in particular the switching 508 and the setting are performed by a measuring device, and the method is continued with step a) until all test states or a predetermined subset of test states have been adopted;

[0200] Therefore, a check is performed (509) to determine whether all test states or all test states specified to be adopted have been adopted. If all test states to be adopted have been adopted, the method ends and (if necessary) analog circuit 1 is used as intended (507). If not all test states to be adopted have been adopted, the method continues with step a) and the current consumption of analog circuit 1 is detected (503).

[0201] Naturally, the use of the analog circuit 1 (507) is intended on the assumption that no defects in the sense of the present invention are or have not been discovered during any previous and / or subsequent testing and / or during operation of the analog circuit.

[0202] In step d) after comparing the current consumption value with a preset value (504), if the amount of the current consumption value is greater than the set value, a defect is inferred (505), wherein preferably the measuring device performs this inference and then preferably, in the case of inferring such a defect (506), the possibly defective analog circuit 1 is discarded.

[0203] The inference 506 about the presence of a defect can be interchanged with the transition 508 of the analog circuit 1 to another of the test states.

[0204] The check 509 of whether all test states or all test states designated to be adopted have been adopted can be interchanged with the transition 508 of the analog circuit 1 to another of the test states.

[0205] In this respect, the numbering of the steps from a) to d) in the description and claims does not imply any chronological order.

[0206] The present invention also proposes a method for performing IDDQ testing on the analog circuit 1 . Figure 6 The method is shown in simplified schematic form. Assume that the analog circuit 1 is, for example, Figure 2 The illustrated embodiment corresponds to an analog circuit 1 .

[0207] The method proposed here consists of multiple steps.

[0208] If no measuring device is available, the method starts with step 600 of providing a measuring device.

[0209] In a subsequent step, the simulation circuit 1 is powered ( 601 ), preferably by a measuring device.

[0210] In a subsequent step, the analog circuit 1 is switched to a first test state ( 602 ), wherein the measuring device preferably executes and preferably controls this switching via the test logic 38 (eg via a JTAG test bus interface).

[0211] In a subsequent step, the current consumption of the analog circuit 1 in this first test state is detected (503) and the current consumption value is determined, in particular by a measuring device which preferably detects the current value of one of the supply voltage lines 3, 8 fed to the analog circuit 1.

[0212] In a subsequent step, the determined current consumption value is compared with a setpoint value ( 604 ), wherein the comparison is preferably performed by the measuring device.

[0213] In a subsequent step, if the current consumption value is greater than a set value, a defect is inferred (605), wherein the measuring device preferably performs this inference and then preferably, in the event of such a defect, discards the possibly defective analog circuit 1 (606).

[0214] In the event that the measuring device does not conclude that analog circuit 1 is defective in the previous step 605, analog circuit 1 can be used as intended with a higher probability (607) if analog circuit 1 is not discarded for other reasons in further, subsequent or previous tests.

[0215] In order to solve the above problem, the present invention further proposes a method for performing stress testing on the analog circuit 1 . Figure 7 The method is schematically shown in a simplified manner. Assume that the analog circuit 1 is, for example, Figure 2 The analog circuit corresponding to the embodiment shown.

[0216] The method proposed here consists of multiple steps.

[0217] If no measuring device is available, the method starts with step 700 of providing a measuring device.

[0218] In a subsequent step, the simulation circuit 1 is powered ( 701 ), preferably by a measuring device.

[0219] In a subsequent step, the analog circuit 1 is switched to a first test state ( 702 ), wherein the measuring device preferably performs this switching via the test logic 38 , for example via a JTAG test bus interface.

[0220] In a subsequent step, the supply voltage is increased by a predetermined stress voltage value within a predetermined time period ( 708 ), wherein the measuring device preferably performs this increase 708 ;

[0221] Undoing the increase 708 ( 709 ) of the supply voltage, wherein this undoing of the increase ( 709 ) is preferably performed by a measuring device;

[0222] In a subsequent step, the current consumption of the analog circuit 1 in this first test state is detected (703) and the current consumption value is determined, in particular by a measuring device which preferably detects the current value of one of the supply voltage lines 3, 8 fed to the analog circuit 1.

[0223] In a subsequent step, the detected current consumption value is compared with a predetermined value ( 704 ), wherein the comparison is preferably performed by the measuring device.

[0224] In a subsequent step, if the current consumption value is greater than a set value, a defect is inferred (705), wherein the measuring device preferably performs this inference and then preferably, in the presence of such a defect, discards the possibly defective analog circuit 1 (706).

[0225] In the event that no defect is inferred in the previous step 705, if the analog circuit 1 is not discarded for other reasons in further, subsequent or previous tests, the analog circuit 1 can be used as intended with a higher probability (707).

[0226] advantage

[0227] By using the proposed switches and tri-state gates to set specific test states, meaningful IDDQ testing can be achieved for the exemplary analog circuit 1. This increases the testability of the exemplary analog circuit 1, thereby improving the delivery quality.

[0228] Compared to the technical concept of US 2005 / 0024075 A1, the technical concept proposed in the present invention solves the IDDQ testability issue for analog circuits. Compared to the example in US 2005 / 0024075 A1, the technical concept proposed in the present invention discloses a solution for fully IDDQ testability. "Fully" refers to IDDQ testing of all analog transistors in the example of the present invention.

[0229] Compared with the technical concept of US 2005 / 0024075 A1, the technical concept of the present invention does not have any static current path between the positive power supply voltage and the negative power supply voltage in the test state.

[0230] Compared to the technical concept of US 2005 / 0024075 A1, the present invention proposes reconfiguring the analog circuit under test into a digital circuit. Compared to the technical concept of US 2005 / 0024075 A1, the technical concept of the present invention can fully automatically generate IDDQ test vectors. Therefore, by using the technical concept of the present invention, it is possible to generate certification documents that comply with ISO 26262 requirements.

[0231] Compared with the technical concept of US 2005 / 0024075 A1, the present invention proposes disconnection of the feedback branch.

[0232] Compared with the technical concept of US 2005 / 0024075 A1, the present invention proposes a complete disconnection of the control node. Figure 2 In the example shown, this is achieved in particular by means of exemplary switches S6, S7, S8, S1, S2, S3 and S4. In contrast, the technical concept of US 2005 / 0024075 A1 does not provide such additional transmission gates for testing purposes.

[0233] Compared with US 2005 / 0024075 A1, the present invention discloses a circuit that can be tested in an IDDQ test state, and further discloses its principle that can be transferred to other analog circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0234] Figure 1 An exemplary analog circuit 1 is shown.

[0235] Figure 2 The proposed exemplary analog circuit 1 is shown, which can be reconfigured in a test state by the test logic 38 by appropriately setting the switch states of additional components (S1 to S9, G1 to G9) through control via a JTAG test bus interface, so that it is suitable for IDDQ testing and / or voltage stress testing in this reconfigured test state.

[0236] Figure 3 Corresponding to Figure 2 , wherein the test logic 38 can now also directly control the switching state of the seventh transistor 15 .

[0237] Figure 4 Shown according to Figure 3 A method for performing IDDQ testing on analog circuits.

[0238] Figure 5 Shown according to Figure 3 Another approach to IDDQ testing of analog circuits.

[0239] Figure 6 Shown according to Figure 2 A method for performing IDDQ testing on analog circuits.

[0240] Figure 7 Shown according to Figure 2 A method for stress testing analog circuits.

[0241] Reference Signs List

[0242] 1. Example analog circuit;

[0243] 2 voltage source;

[0244] 3 power supply voltage lines;

[0245] 4 current sources;

[0246] 5. Reference current;

[0247] 6 first node;

[0248] 7 first transistor;

[0249] 8 reference potential line;

[0250] 9 second transistor;

[0251] 10 third transistor;

[0252] 11 fourth transistor;

[0253] 12 fifth transistor;

[0254] 13 sixth transistor;

[0255] 14 second node;

[0256] 15 seventh transistor;

[0257] 16 eighth transistor;

[0258] 17 Inverter;

[0259] 18 digital transmission clock;

[0260] 19 Inverted digital transmission clock;

[0261] 20 ninth transistor;

[0262] 21 tenth transistor;

[0263] 22 eleventh transistor;

[0264] 23 12th transistor;

[0265] 24 analog output and input nodes for subsequent circuits;

[0266] 25 intermediate nodes;

[0267] 26 an output terminal of a source follower composed of the seventh transistor 15 and the eighth transistor 16;

[0268] 27 reference voltage between the first node 6 and the reference potential line 8;

[0269] 28 a control electrode of the third transistor 10;

[0270] 29 a control electrode of the fourth transistor 11;

[0271] 30 13th transistor;

[0272] 31 third node;

[0273] 32 fourth node;

[0274] 33 control electrode 33 of the first transistor 7;

[0275] 34 a control electrode of the second transistor 9;

[0276] 36 a control electrode of the fifth transistor 12;

[0277] 37 a control electrode of the eighth transistor 16;

[0278] 38 test logic;

[0279] 39 a control electrode of the sixth transistor 13;

[0280] 40 other control signals of the overall circuit to which the exemplary analog circuit 1 belongs;

[0281] 41 Variant Digital Transmission Clock;

[0282] 42 Variant inverted digital transmission clock;

[0283] 43 a control electrode of the thirteenth transistor 30;

[0284] 400 provides measuring devices;

[0285] 401 supplies power to analog circuit 1;

[0286] 402: Switch the analog circuit 1 to a first test state;

[0287] 403 Detecting the current consumption of the analog circuit 1 in the test state, in particular by means of a measuring device, and determining a current consumption value;

[0288] 404 compares the current consumption value with the set value,

[0289] 405 inferred that there was a flaw;

[0290] 406 Discard the defective analog circuit 1;

[0291] 407 The method terminates and it is expected that analog circuit 1 will be used if necessary;

[0292] 500 provides measuring devices;

[0293] 501 provides power to the analog circuit 1;

[0294] 502 , by setting and adopting one of the test states, causing the analog circuit 1 to switch to the test state;

[0295] 503 Detecting the current consumption of the analog circuit 1 in the test state, in particular by means of a measuring device, and determining a current consumption value;

[0296] 504 compares the current consumption value with the set value,

[0297] 505 inferred that there was a defect;

[0298] 506 Discard defective analog circuit 1;

[0299] 507 The method terminates and, if necessary, it is expected that the analog circuit 1 will be used;

[0300] 508 by setting and adopting another test state in the test states, so that the analog circuit 1 switches to the other test state;

[0301] 509 Checks whether all test states or all test states specified to be adopted have been adopted;

[0302] 600 provides measuring devices;

[0303] 601 provides power to analog circuit 1;

[0304] 602: Switch the analog circuit 1 to a first test state;

[0305] 603 Detecting the current consumption of the analog circuit 1 in the test state, in particular by means of a measuring device, and determining a current consumption value;

[0306] 604 compares the current consumption value with the set value,

[0307] 605 inferred that there was a defect;

[0308] 606 Discard defective analog circuit 1;

[0309] 607 The method terminates and, if necessary, it is expected that the analog circuit 1 will be used;

[0310] 700 provides measuring devices;

[0311] 701 supplies power to analog circuit 1;

[0312] 702 : switching 402 the analog circuit 1 to a first test state;

[0313] 703 Detecting the current consumption of the analog circuit 1 in the test state, in particular by means of a measuring device, and determining a current consumption value;

[0314] 704 compares the sixth consumption value with the set value,

[0315] 705 infers the existence of circumstances;

[0316] 706 Discard defective analog circuit 1;

[0317] 707 The method terminates and, if necessary, it is expected that the analog circuit 1 will be used;

[0318] 708 Increase the supply voltage;

[0319] 709 cancelling the supply voltage increase, which can be done in whole or in part;

[0320] G1 first three-state gate;

[0321] G2 second three-state gate;

[0322] G3 third three-state gate;

[0323] G4 fourth three-state gate;

[0324] G5 fifth three-state gate;

[0325] G6 sixth three-state gate;

[0326] G7 seventh three-state gate;

[0327] G8 eighth tri-state gate;

[0328] G9 ninth tri-state gate;

[0329] S1 first switch;

[0330] S2 second switch;

[0331] S3 third switch;

[0332] S4 fourth switch;

[0333] S5 fifth switch;

[0334] S6 sixth switch;

[0335] S7 seventh switch;

[0336] S8 eighth switch;

[0337] S9 ninth switch;

[0338] Idd is the power supply current entering analog circuit 1;

[0339] List of citations

[0340] If an intellectual property application claiming priority of the present invention is filed in a country that allows the technical concept of the cited documents for protection to be combined with the technical concept of the present invention as part of the present disclosure, the combination of the following documents with the present invention explicitly constitutes a part of the present invention.

[0341] Patent Literature

[0342] US 2005 / 0024075 A1

[0343] Non-patent literature

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[0348] Non-Patent Document 5: “IEEE Standard for Test Access Port and Boundary-Scan Architecture – Redline,” IEEE Std 1149.1-2013 (revised from IEEE Std 1149.1-2001), Redline Edition, pp. 1-899, May 13, 2013

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Claims

1. An analog circuit based on MOS, BiCMOS or CMOS (1), in, The analog circuit (1) is designed to realize a predetermined circuit purpose in a normal state of the analog circuit (1), and The analog circuit (1) has one or more input signals and / or one or more output signals, and The analog circuit (1) has at least one analog signal inside the analog circuit (1), and wherein the analog circuit (1) is connected to a test logic (38), and wherein the test logic (38) is designed to set the analog circuit (1) to the normal state and at least a first test state, and The analog circuit (1) includes a first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30), and wherein the first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) is designed to perform the function of the analog circuit (1) according to the predetermined circuit purpose of the analog circuit (1) in the normal state of the analog circuit (1), and wherein each of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) has a control electrode, and wherein the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) are designed to also be operable as switches via their respective control electrodes, and wherein the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) have an on state and an off state as their respective switch states in their respective operations as switches, and wherein the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) are fully connected in the open state, and wherein the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) are completely shut down in the off state, and The analog circuit (1) includes second components (S1 to S9; G1 to G9), and wherein the test logic (38) is designed to use the second components (S1 to S9; G1 to G9) to set the switch state of at least one first component (7, 9, 12, 16) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) in the first test state of the analog circuit (1), and wherein the control electrode (33, 34, 36, 37) of the first component (7, 9, 12, 16) of the first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) is not directly connected to the input signal or not directly connected to the output signal, and wherein the test logic (38) is designed to disconnect, in the first test state, the control electrode (33, 34, 36, 37) of the first component (7, 9, 12, 16) of the first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) from the rest of the analog circuit (1) via at least one switch (S1, S2, S3, S4), and wherein the test logic (38) is designed to connect, in the normal state, at least via the switches (S1, S2, S3, S4) the control electrodes (33, 34, 36, 37) of the first components (7, 9, 12, 16) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) to nodes of the rest of the analog circuit (1), and The test logic (38) is designed to, in the first test state, connect the control electrodes (33, 34, 36, 37, 39) of the first components (7, 9, 12, 16) in the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) to the on state or to disconnect them to the off state through the first device (G1, G2, G5, G6), and The test logic (38) is designed to control the first device (G1, G2, G5, G6) in the normal state so that the first device (G1, G2, G5, G6) does not affect the control electrode (33, 34, 36, 37, 39) of the first component (7, 9, 12, 16) in the normal state of the analog circuit (1).

2. The analog circuit (1) according to claim 1, characterized in that The analog circuit (1) includes N-channel transistors (7, 9, 16, 30, 10, 11, 20, 22) and P-channel transistors (12, 13, 15, 21, 23), and The second components (S1 to S9; G1 to G9) are designed to enable the test logic (38) to set the switch states of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) so that In the first test state of the analog circuit (1), all N-channel transistors (7, 9, 16, 30, 10, 11, 20, 22) of the analog circuit (1) are turned off, and all P-channel transistors (12, 13, 15, 21, 23) of the analog circuit (1) are turned on, or In the first test state of the analog circuit (1), all N-channel transistors (7, 9, 16, 30, 10, 11, 20, 22) of the analog circuit (1) are turned on, and all P-channel transistors (12, 13, 15, 21, 23) of the analog circuit (1) are turned off.

3. The analog circuit (1) according to claim 1, characterized in that , The analog circuit (1) has a positive supply voltage line (3), and The analog circuit (1) has a negative supply voltage line (8), and The analog circuit (1) has a plurality of potential current paths from the positive power supply voltage line (3) through at least one of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) and / or the second components (S1 to S9; G1 to G9) to the negative power supply voltage line (8), The second components (S1 to S9; G1 to G9) are designed to enable the test logic (38) to set the switch states of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) so that In each of the potential current paths, at least one first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) and / or at least one second component (S1 to S9; G1 to G9) is blocked.

4. The analog circuit (1) according to claim 3, characterized in that In at least one of the potential current paths, referred to below as the target current path, in the first test state exactly one first component or exactly one second component is blocked, and The exactly one turned-off first component or the exactly one turned-off second component in the target current path corresponds to an IDDQ component, and In the first test state, other components in the target current path except the IDDQ component are not turned off.

5. A method for performing an IDDQ test on an analog circuit (1) according to claim 4, comprising the following steps: Providing measuring devices; Supplying power to the analog circuit (1); Switching the analog circuit (1) to the first test state; By means of the measuring device, the current consumption of the analog circuit (1) in the first test state is detected, and a current consumption value is determined; comparing the current consumption value with a set value; If the current consumption value is higher than the set value, a defect is inferred.

6. A method for performing an IDDQ test on an analog circuit (1) according to claim 4, in, In addition to the first test state, the analog circuit (1) also has one or more other test states, The other test states and the first test state are collectively referred to as test states hereinafter. wherein the test states are different from one another in that an IDDQ component of one of the test states is different from another IDDQ component of another of the test states, and The method comprises the following steps: Providing measuring devices; Supplying power to the analog circuit (1); By using the measuring device, the analog circuit (1) is switched to one of the test states by setting and adopting the test state; Step a): detecting the current consumption of the analog circuit (1) in the set test state by means of the measuring device, and determining the current consumption value; Step b): comparing the determined current consumption value with a set value, which can be specific to the set test state; Step c): switching the analog circuit (1) to another test state of the test states by setting and adopting the other test state, wherein the set other test state is different from a previously adopted test state of the test states, and wherein the switching is performed by the measuring device, and step a) is continued until all test states or a predetermined subset of test states of the test states are adopted; Step d): If the determined current consumption value is higher than the set value, inferring the presence of a defect, wherein step d) can also be performed between step b) and step c) and the measuring device can also perform the inference of the presence of a defect.

7. A method for performing an IDDQ test on an analog circuit (1) according to claim 2 or 4, comprising the following steps: Providing measuring devices; supplying power to the analog circuit (1), wherein the measuring device is also capable of supplying power; Switching the analog circuit (1) to the first test state, wherein the measuring device can also control the switching; detecting the current consumption of the analog circuit (1) in the first test state and determining a current consumption value, wherein the measuring device is also capable of performing the detection; comparing the detected current consumption value with a set value, wherein the measuring device is also capable of performing the comparison; If the detected current consumption value is higher than the set value, a defect is inferred, wherein the measuring device can also perform the inference of the presence of a defect.

8. A method for performing a stress test on an analog circuit (1) according to claim 2 or 4, comprising the following steps: Providing measuring devices; Supplying power to the analog circuit (1); causing the analog circuit (1) to switch to a first test state; increasing the power supply voltage by a predetermined stress voltage value and continuing for a predetermined period of time; canceling the increase in the power supply voltage; By means of the measuring device, the current consumption of the analog circuit (1) in the first test state is detected, and a current consumption value is determined; comparing the current consumption value with a set value; If the current consumption value is higher than the set value, an error is inferred.

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