MEMS device and manufacturing method thereof

Abstract

The invention provides an MEMS device and a manufacturing method thereof. The MEMS device comprises a substrate; the conductive layer is formed on a part of the substrate; the sacrificial layer is formed on the conductive layer and the substrate, a cavity is formed in the sacrificial layer, and the cavity exposes part of the top surface of the conductive layer; the semiconductor layer is formed on the sacrificial layer, the semiconductor layer is electrically connected with the conductive layer, a release hole is formed in the semiconductor layer, and the release hole is communicated with the cavity; wherein the top surface of the conductive layer and / or the bottom surface of the semiconductor layer are / is provided with a plurality of bulges, and the longitudinal section contour of each bulge is arc-shaped. According to the technical scheme, the performance of the MEMS device is improved, and meanwhile, the MEMS device can meet the reliability test requirement proposed for coping with a severe environment.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a MEMS device and a manufacturing method thereof. Background Art

[0002] The performance requirements for MEMS (Micro-Electro-Mechanical System) devices, such as capacitive sensors, accelerometers, and gyroscopes, are becoming increasingly demanding. For example, in capacitive sensors, increasing the area of ​​the top plate (i.e., the proof mass) can improve sensitivity, reduce stray capacitance, and enhance the signal-to-noise ratio. However, a larger top plate can easily cause adhesion between the top and bottom plates in applications.

[0003] Currently, methods for improving the adhesion between the upper and lower plates include: (1) providing two downwardly protruding stoppers on the bottom surface of the upper plate; (2) optimizing the deposition process to provide a certain degree of roughness on the top surface of the lower plate, and providing a hydrophobic film on the top surface of the lower plate. However, the above methods can only be effective in ordinary working environments and cannot cope with harsh working environments. In other words, they cannot meet the reliability testing requirements (such as pull-in testing) proposed for harsh environments.

[0004] Therefore, there is a need to improve the method of improving the adhesion between the upper plate and the lower plate. Summary of the Invention

[0005] An object of the present invention is to provide a MEMS device and a method for manufacturing the same, so that while improving the performance of the MEMS device, the MEMS device can also meet the reliability testing requirements proposed for coping with harsh environments.

[0006] To achieve the above object, the present invention provides a MEMS device, comprising:

[0007] substrate;

[0008] a conductive layer formed on a portion of the substrate;

[0009] a sacrificial layer formed on the conductive layer and the substrate, wherein a cavity is formed in the sacrificial layer, and the cavity exposes a portion of the top surface of the conductive layer;

[0010] a semiconductor layer formed on the sacrificial layer, the semiconductor layer being electrically connected to the conductive layer, and a release hole being formed in the semiconductor layer, the release hole being in communication with the cavity;

[0011] The top surface of the conductive layer and / or the bottom surface of the semiconductor layer has a plurality of protrusions, and the longitudinal section profile of the protrusions is arc-shaped.

[0012] Optionally, the base includes a substrate and an insulating dielectric layer formed on the substrate, and the conductive layer penetrates the insulating dielectric layer to be electrically connected to the substrate.

[0013] Optionally, the multiple protrusions are connected in a grid shape, or the multiple protrusions are arranged in an array.

[0014] Optionally, an angle between a bottom tangent line of the longitudinal section profile of the protrusion and the top surface of the base directly below the protrusion is 15° to 30°.

[0015] Optionally, the center distance between adjacent protrusions is 1.5 μm to 2 μm.

[0016] Optionally, the height of the protrusion is

[0017] The present invention also provides a method for manufacturing a MEMS device, comprising:

[0018] providing a substrate;

[0019] forming a conductive layer on the substrate;

[0020] Etching the conductive layer to expose a portion of the top surface of the substrate;

[0021] forming a sacrificial layer on the etched conductive layer and the exposed substrate;

[0022] forming a semiconductor layer on the sacrificial layer, wherein the semiconductor layer penetrates the sacrificial layer to be electrically connected to the conductive layer;

[0023] Etching the semiconductor layer to form a release hole exposing a portion of the sacrificial layer;

[0024] releasing a portion of the sacrificial layer through the release hole to form a cavity, wherein the cavity exposes a portion of the top surface of the conductive layer;

[0025] Before etching the conductive layer, the top surface of the conductive layer is patterned so that the top surface of the conductive layer has a plurality of protrusions; and / or before forming the semiconductor layer on the sacrificial layer, the top surface of the sacrificial layer is patterned so that the top surface of the sacrificial layer has a plurality of protrusions; the longitudinal cross-sectional profile of the protrusion is arc-shaped.

[0026] Optionally, the base includes a substrate and an insulating dielectric layer formed on the substrate, and the conductive layer penetrates the insulating dielectric layer to be electrically connected to the substrate.

[0027] Optionally, the multiple protrusions are connected in a grid shape, or the multiple protrusions are arranged in an array.

[0028] Optionally, an angle between a bottom tangent line of the longitudinal section profile of the protrusion and the top surface of the base directly below the protrusion is 15° to 30°.

[0029] Optionally, the center distance between adjacent protrusions is 1.5 μm to 2 μm.

[0030] Optionally, the height of the protrusion is

[0031] Optionally, the step of patterning the top surface of the conductive layer and / or patterning the top surface of the sacrificial layer includes:

[0032] forming a patterned photoresist layer on the top surface of the conductive layer and / or the sacrificial layer, wherein the longitudinal cross-sectional profile of the patterned photoresist layer is an arc shape;

[0033] The conductive layer and / or the sacrificial layer are partially etched using the patterned photoresist layer as a mask, so that a top surface of the conductive layer has a plurality of protrusions, and / or a top surface of the sacrificial layer has a plurality of protrusions.

[0034] Optionally, an angle between a bottom tangent line of a longitudinal cross-sectional profile of the patterned photoresist layer and a top surface of the substrate directly below the patterned photoresist layer is 40° to 60°.

[0035] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0036] 1. The MEMS device of the present invention comprises: a substrate; a conductive layer formed on a portion of the substrate; a sacrificial layer formed on the conductive layer and the substrate, the sacrificial layer having a cavity formed therein, the cavity exposing a portion of the top surface of the conductive layer; a semiconductor layer formed on the sacrificial layer, the semiconductor layer being electrically connected to the conductive layer, the semiconductor layer having a release hole formed therein, the release hole communicating with the cavity; wherein the top surface of the conductive layer and / or the bottom surface of the semiconductor layer have a plurality of protrusions, the longitudinal cross-sectional profile of the protrusions being arc-shaped. This improves the performance of the MEMS device while enabling the MEMS device to meet the reliability testing requirements for harsh environments.

[0037] 2. The method for manufacturing a MEMS device of the present invention comprises: providing a substrate; forming a conductive layer on the substrate; etching the conductive layer to expose a portion of the top surface of the substrate; forming a sacrificial layer on the etched conductive layer and the exposed substrate; forming a semiconductor layer on the sacrificial layer, the semiconductor layer penetrating the sacrificial layer to be electrically connected to the conductive layer; etching the semiconductor layer to form a release hole exposing a portion of the sacrificial layer; releasing a portion of the sacrificial layer through the release hole to form a cavity, the cavity exposing a portion of the top surface of the conductive layer; wherein, before etching the conductive layer, the top surface of the conductive layer is patterned to have a plurality of protrusions; and / or, before forming the semiconductor layer on the sacrificial layer, the top surface of the sacrificial layer is patterned to have a plurality of protrusions; the longitudinal cross-sectional profile of the protrusions is arc-shaped. This improves the performance of the MEMS device while enabling the MEMS device to meet the reliability testing requirements for harsh environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a cross-sectional schematic diagram of a MEMS device according to an embodiment of the present invention;

[0039] Figure 2 is a cross-sectional schematic diagram of a MEMS device according to another embodiment of the present invention;

[0040] Figure 3 is a flow chart of a method for manufacturing a MEMS device according to an embodiment of the present invention;

[0041] Figure 4a to Figure 4k yes Figure 3 A schematic cross-sectional view of a device in an embodiment of a method for manufacturing a MEMS device is shown;

[0042] Figure 5a to Figure 5d yes Figure 3 FIG2 is a schematic cross-sectional view of a device according to another embodiment of a method for manufacturing a MEMS device.

[0043] Among them, Figure 1 to Figure 5d The reference numerals are described as follows:

[0044] 111 - substrate; 112 - first insulating dielectric layer; 1121 - opening; 113 - second insulating dielectric layer; 12 - conductive layer; 121 - first protrusion; 13 - first patterned photoresist layer; 14 - sacrificial layer; 141 - contact hole; 142 - cavity; 143 - second protrusion; 15 - semiconductor layer; 151 - release hole; 152 - third protrusion; 16 - bonding ring. DETAILED DESCRIPTION

[0045] To make the objectives, advantages, and features of the present invention more apparent, the MEMS device and its manufacturing method proposed in the present invention are further described in detail below. It should be noted that the accompanying drawings are all in a very simplified form and are not to exact scale, and are only used to facilitate and clearly illustrate the purpose of the embodiments of the present invention.

[0046] One embodiment of the present invention provides a MEMS device, comprising: a substrate; a conductive layer formed on a portion of the substrate; a sacrificial layer formed on the conductive layer and the substrate, a cavity formed in the sacrificial layer, the cavity exposing a portion of the top surface of the conductive layer; a semiconductor layer formed on the sacrificial layer, the semiconductor layer being electrically connected to the conductive layer, a release hole formed in the semiconductor layer, the release hole being connected to the cavity; wherein the top surface of the conductive layer and / or the bottom surface of the semiconductor layer have a plurality of protrusions, and the longitudinal cross-sectional profile of the protrusions is arc-shaped.

[0047] See below Figure 1 and Figure 2 The MEMS device of this embodiment is described in more detail. Figure 1 and Figure 2 It is a schematic diagram of the longitudinal cross-section of a MEMS device.

[0048] In one embodiment, the base includes a substrate 111 and an insulating dielectric layer (ie, Figure 1 and Figure 2 The first insulating dielectric layer 112 in the embodiment of the present invention.

[0049] The substrate 111 may be a semiconductor substrate or a wafer including a semiconductor substrate, etc. Device structures such as transistors may be formed in the substrate 111 as needed.

[0050] In one embodiment, the base further includes a second insulating dielectric layer 113 . The second insulating dielectric layer 113 is formed on the bottom surface of the substrate 111 to insulate the bottom surface of the substrate 111 from other structures.

[0051] The first insulating dielectric layer 112 and the second insulating dielectric layer 113 may be made of insulating materials such as silicon oxide and silicon oxynitride.

[0052] A conductive layer 12 is formed on a portion of the substrate.

[0053] In one embodiment, the conductive layer 12 penetrates the first insulating dielectric layer 112 to be electrically connected to the substrate 111 .

[0054] In one embodiment, the conductive layer 12 is made of polysilicon. In other embodiments, the conductive layer 12 may be made of a metal material.

[0055] The sacrificial layer 14 is formed on the conductive layer 12 and the substrate. A cavity 142 is formed in the sacrificial layer 14 . The cavity 142 exposes a portion of the top surface of the conductive layer 12 .

[0056] exist Figure 1 and Figure 2 In the illustrated embodiment, the sacrificial layer 14 is formed on a portion of the conductive layer 12 and the first insulating dielectric layer 112 .

[0057] The material of the sacrificial layer 14 includes but is not limited to silicon oxide.

[0058] A semiconductor layer 15 is formed on the sacrificial layer 14 . The semiconductor layer 15 is electrically connected to the conductive layer 12 . A release hole 151 is formed in the semiconductor layer 15 . The release hole 151 is connected to the cavity 142 .

[0059] The cavity 142 also exposes a portion of the bottom surface of the semiconductor layer 15 .

[0060] The semiconductor layer 15 includes a comb-tooth structure and mass blocks. Release holes 151 are formed in the comb-tooth structure, between the mass blocks and the comb-tooth structure, and between the mass blocks.

[0061] The cavity 142 is used to provide a vibration space for the comb structure and the mass block.

[0062] The material of the semiconductor layer 15 includes but is not limited to semiconductor materials such as silicon, germanium, silicon germanium, and silicon carbide.

[0063] A bonding ring 16 is formed on a portion of the top surface of the semiconductor layer 15 so that the semiconductor layer 15 can be bonded to another substrate through the bonding ring 16 .

[0064] The bonding ring 16 may be made of metal materials such as germanium, aluminum, copper, nickel or gold.

[0065] The top surface of the conductive layer 12 and / or the bottom surface of the semiconductor layer 15 has a plurality of protrusions, and the longitudinal cross-sectional profile of the protrusions is arc-shaped.

[0066] exist Figure 1 In the embodiment shown, the top surface of the conductive layer 12 has a plurality of first protrusions 121; Figure 2 In the illustrated embodiment, the top surface of the conductive layer 12 has a plurality of first protrusions 121 , and the bottom surface of the semiconductor layer 15 has a plurality of third protrusions 152 .

[0067] In one embodiment, the longitudinal cross-sectional profile of the groove between adjacent protrusions is also arc-shaped, that is, the longitudinal cross-sectional profile of the top surface of the conductive layer 12 and / or the bottom surface of the semiconductor layer 15 is wavy.

[0068] In one embodiment, the plurality of protrusions are connected in a grid pattern, or the plurality of protrusions are arranged in an array. In other embodiments, the plurality of protrusions are arranged irregularly.

[0069] The angle between the bottom tangent line of the longitudinal section of the protrusion and the top surface of the base directly below the protrusion is 15° to 30°. Figure 4f The included angle β between the bottom tangent line of the longitudinal cross-section of the first protrusion 121 and the top surface of the base directly below the first protrusion 121 is 15° to 30°. It should be noted that, in order to facilitate the illustration of β, Figure 4f In the embodiment, a surface parallel to the top surface of the base is used to replace the top surface of the base.

[0070] Preferably, the center distance between adjacent protrusions is 1.5 μm to 2 μm. It should be noted that when the plurality of protrusions are connected in a grid shape, the adjacent protrusions refer to the opposite sides of a single grid.

[0071] Preferably, the height of the protrusion is

[0072] In one embodiment, the bottom surface of the semiconductor layer 15 in the cavity 142 further has a limiting structure (not shown) to limit the range of the mass block's upward and downward movement to prevent the mass block from vibrating excessively and breaking.

[0073] The number of the limiting structures is much smaller than the number of the protrusions, and the number of the limiting structures is, for example, two; the number of the protrusions is large, and all of the protrusions can be distributed on the entire top surface of the conductive layer 12 and / or the entire bottom surface of the semiconductor layer 15.

[0074] The width and height of the limiting structure are correspondingly much larger than the width and height of the protrusion. For example, the width and height of the limiting structure are correspondingly larger than 10 times the width and height of the protrusion.

[0075] In one embodiment, the MEMS device is a capacitive sensor, and the semiconductor layer 15 and the conductive layer 12 are both electrode plates, wherein the semiconductor layer 15 is an upper electrode plate, and the conductive layer 12 is a lower electrode plate.

[0076] As can be seen from the above, in the MEMS device of the present invention, since the top surface of the conductive layer 12 and / or the bottom surface of the semiconductor layer 15 have a plurality of protrusions, the longitudinal cross-sectional profile of the protrusions is arc-shaped, so that during the operation of the MEMS device, when the mass block in the semiconductor layer 15 moves up and down and the bottom surface of the mass block contacts the top surface of the conductive layer 12, the bottom surface of the mass block and the top surface of the conductive layer 12 are in point contact (that is, the top of the protrusion on the bottom surface of the mass block is in point contact with the top surface of the conductive layer 12, or the bottom surface of the mass block and the top surface of the conductive layer 12 are in point contact). The top of the protrusion is in point contact, or the top of the protrusion on the bottom surface of the mass block is in point contact with the top of the protrusion on the top surface of the conductive layer 12), that is, the contact area between the two is very small, so that even if the area of ​​the mass block is increased, the bottom surface of the mass block and the top surface of the conductive layer 12 can be prevented from adhering to each other, and the mass block can return to its original position, thereby improving the performance of the MEMS device (for example, improving sensitivity, reducing stray capacitance and improving signal-to-noise ratio) while also enabling the MEMS device to meet the reliability test requirements (for example, pull-in test, etc.) proposed in harsh environments.

[0077] Although stress accumulates in the grooves between adjacent protrusions, the protrusions can release stress in the protruding direction. Therefore, the formation of the protrusions has little effect on the warping of the conductive layer 12 and / or the semiconductor layer 15 .

[0078] Since the height of the limiting structure is relatively large, the capacitance value corresponding to the position where the limiting structure is located is greatly different from the capacitance value corresponding to the position outside the limiting structure. If too many limiting structures are set, it will lead to a large stray capacitance; and the height of the protrusion is very small, so that the difference between the spacing between the protrusion on one electrode plate and the other electrode plate opposite to it and the spacing between the groove outside the protrusion on one electrode plate and the other electrode plate opposite to it is reduced, and since the longitudinal cross-sectional profile of the protrusion is arc-shaped, the height difference between the part outside the top of the protrusion and the groove outside the protrusion is reduced, further reducing the difference between the spacing between the part outside the top of the protrusion on one electrode plate and the other electrode plate opposite to it and the spacing between the groove outside the protrusion on one electrode plate and the other electrode plate opposite to it, thereby reducing the difference between the capacitance value corresponding to the position where the protrusion is located and the capacitance value corresponding to the position outside the protrusion, so that even if a large number of the protrusions are set, the generated stray capacitance is very small. Therefore, in the present invention, by providing a small number of the limiting structures in combination with a large number of the protrusions, it is possible to avoid the generation of large stray capacitance, thereby having little impact on the output of the capacitance signal.

[0079] When the center distance between adjacent protrusions is 1.5μm to 2μm, it can avoid the spacing between adjacent protrusions being too large, which causes the area between adjacent protrusions on one electrode plate to adhere to another electrode plate, and avoid the spacing between adjacent protrusions being too small, which causes the total contact area of ​​all the protrusions on one electrode plate to be too large and adhere to another electrode plate.

[0080] When the height of the protrusion is When the height of the protrusion is too small to play the role of anti-adhesion, the height of the protrusion can be avoided from being too large to cause a large stray capacitance.

[0081] An embodiment of the present invention provides a method for manufacturing a MEMS device. Figure 3 , Figure 3 1 is a flow chart of a method for manufacturing a MEMS device according to an embodiment of the present invention, wherein the method for manufacturing a MEMS device comprises:

[0082] Step S1, providing a substrate;

[0083] Step S2, forming a conductive layer on the substrate;

[0084] Step S3, etching the conductive layer to expose a portion of the top surface of the substrate;

[0085] Step S4, forming a sacrificial layer on the etched conductive layer and the exposed substrate;

[0086] Step S5, forming a semiconductor layer on the sacrificial layer, wherein the semiconductor layer penetrates the sacrificial layer to be electrically connected to the conductive layer;

[0087] Step S6, etching the semiconductor layer to form a release hole exposing a portion of the sacrificial layer;

[0088] Step S7, releasing a portion of the sacrificial layer through the release hole to form a cavity, wherein the cavity exposes a portion of the top surface of the conductive layer;

[0089] Before etching the conductive layer, the top surface of the conductive layer is patterned so that the top surface of the conductive layer has a plurality of protrusions; and / or before forming the semiconductor layer on the sacrificial layer, the top surface of the sacrificial layer is patterned so that the top surface of the sacrificial layer has a plurality of protrusions; the longitudinal cross-sectional profile of the protrusion is arc-shaped.

[0090] See below Figure 4a to Figure 4k and Figure 5a to Figure 5d The manufacturing method of the MEMS device provided in this embodiment is described in more detail. Figure 4a to Figure 4k and Figure 5a to Figure 5d It is also a longitudinal cross-sectional diagram. Figure 4dyes Figure 4c An enlarged schematic diagram of area A1 in FIG. Figure 4f yes Figure 4e An enlarged schematic diagram of area A1 in FIG.

[0091] Follow step S1, refer to Figure 4a , providing a substrate.

[0092] In one embodiment, the base includes a substrate 111 and an insulating dielectric layer (ie, Figure 4a The first insulating dielectric layer 112 in the embodiment of the present invention.

[0093] The substrate 111 may be a semiconductor substrate or a wafer including a semiconductor substrate, etc. Device structures such as transistors may be formed in the substrate 111 as needed.

[0094] In one embodiment, the base further includes a second insulating dielectric layer 113 . The second insulating dielectric layer 113 is formed on the bottom surface of the substrate 111 to insulate the bottom surface of the substrate 111 from other structures.

[0095] The first insulating dielectric layer 112 and the second insulating dielectric layer 113 may be formed by a thermal oxidation process or a deposition process.

[0096] The first insulating dielectric layer 112 and the second insulating dielectric layer 113 may be made of insulating materials such as silicon oxide and silicon oxynitride.

[0097] Follow step S2, refer to Figure 4b , forming a conductive layer 12 on the substrate.

[0098] In one embodiment, if Figure 4a As shown, by performing a photolithography process and an etching process, an opening 1121 exposing a portion of the top surface of the substrate 111 is formed in the first insulating dielectric layer 112; then, as shown in FIG. Figure 4b As shown, a conductive layer 12 is formed on the first insulating dielectric layer 112 , and the conductive layer 12 fills the opening 1121 , so that the conductive layer 12 passes through the first insulating dielectric layer 112 to be electrically connected to the substrate 111 .

[0099] In one embodiment, the conductive layer 12 is made of polysilicon. In other embodiments, the conductive layer 12 may be made of a metal material.

[0100] Follow step S3, refer to Figure 4g , etching the conductive layer 12 to expose a portion of the top surface of the substrate.

[0101] exist Figure 4gIn the illustrated embodiment, after etching the conductive layer 12 , a portion of the top surface of the first insulating dielectric layer 112 is exposed.

[0102] In one embodiment, before etching the conductive layer 12 to expose a portion of the top surface of the substrate, the top surface of the conductive layer 12 is patterned so that the top surface of the conductive layer 12 has a plurality of protrusions (ie, Figure 4e and Figure 4f The first protrusion 121 in the figure) has a longitudinal cross-sectional profile that is arc-shaped.

[0103] In one embodiment, the longitudinal cross-sectional profile of the groove between adjacent first protrusions 121 is also arc-shaped, that is, the longitudinal cross-sectional profile of the top surface of the conductive layer 12 after the patterning process is wavy.

[0104] The step of patterning the top surface of the conductive layer 12 may include:

[0105] like Figure 4c and Figure 4d As shown, a first patterned photoresist layer 13 is formed on the top surface of the conductive layer 12, wherein the first patterned photoresist layer 13 exposes a portion of the top surface of the conductive layer 12, and the longitudinal cross-sectional profile of the first patterned photoresist layer 13 is an arc shape;

[0106] like Figure 4e and Figure 4f As shown, the first patterned photoresist layer 13 is used as a mask to etch a portion of the conductive layer 12 so that a top surface of the conductive layer 12 has a plurality of first protrusions 121 .

[0107] In one embodiment, the step of forming the first patterned photoresist layer 13 may include: forming a photoresist layer on the top surface of the conductive layer 12; then, performing exposure and development processes on the photoresist layer to preliminarily pattern the photoresist layer. At this time, the side wall of the photoresist layer will be rough or perpendicular to the top surface of the conductive layer 12; then, heating and reflowing the preliminarily patterned photoresist layer to soften the photoresist and cause surface tension-driven flow, thereby transforming the side wall of the photoresist layer into a smooth arc shape; then, cooling and solidifying the heated and reflowed photoresist layer to form the first patterned photoresist layer 13.

[0108] Taking the conductive layer 12 as an example of polysilicon, the step of etching a partial thickness of the conductive layer 12 using the first patterned photoresist layer 13 as a mask may include: using an etching gas to etch the first patterned photoresist layer 13 and the entire top surface of the conductive layer 12, the etching gas may include argon and oxygen, oxygen is used to etch the first patterned photoresist layer 13, and argon is used to bombard and etch the entire top surface of the conductive layer 12, the conductive layer 12 covered by the first patterned photoresist layer 13 is etched away less, and the conductive layer 12 not covered by the first patterned photoresist layer 13 is etched away more, so that when the etching is completed, the first patterned photoresist layer 13 is completely etched away, and at the same time, the top of the conductive layer 12 below the first patterned photoresist layer 13 is formed as a first protrusion 121, and the top of the conductive layer 12 not covered by the first patterned photoresist layer 13 is formed as a groove. In other embodiments, the etching gas may include only argon, and parameters such as the bombardment angle and etching rate of the etching gas may be adjusted to achieve the first protrusion 121 on the top surface of the conductive layer 12. In this case, when the etching is completed, the first patterned photoresist layer 13 may be partially or completely etched away. It should be noted that a suitable etching gas can be selected according to the material of the conductive layer 12.

[0109] Preferably, the angle α between the bottom tangent line of the longitudinal cross-sectional profile of the first patterned photoresist layer 13 and the top surface of the substrate directly below the first patterned photoresist layer 13 is 40° to 60°, and α is also the angle between the bottom tangent line of the longitudinal cross-sectional profile of the first patterned photoresist layer 13 and the top surface of the conductive layer 12 covered by the first patterned photoresist layer 13, so that the angle β between the bottom tangent line of the longitudinal cross-sectional profile of the first protrusion 121 and the top surface of the substrate directly below the first protrusion 121 is 15° to 30°. It should be noted that, in order to facilitate the illustration of β, Figure 4f In the embodiment, a surface parallel to the top surface of the base is used to replace the top surface of the base.

[0110] In one embodiment, the first patterned photoresist layer 13 is in a grid shape, or the first patterned photoresist layer 13 is arranged in an array on the conductive layer 12, so that the plurality of first protrusions 121 are connected in a grid shape, or the plurality of first protrusions 121 are arranged in an array. In other embodiments, the first patterned photoresist layer 13 may be arranged irregularly on the conductive layer 12, so that the plurality of first protrusions 121 are arranged irregularly.

[0111] Preferably, the center distance L between adjacent first protrusions 121 is 1.5 μm to 2 μm. It should be noted that when the plurality of first protrusions 121 are connected in a grid shape, adjacent first protrusions 121 refer to opposite sides of a single grid.

[0112] Preferably, the height H of the first protrusion 121 is

[0113] Follow step S4, refer to Figure 4h , forming a sacrificial layer 14 on the etched conductive layer 12 and the exposed substrate.

[0114] exist Figure 4h In the illustrated embodiment, the sacrificial layer 14 covers the etched conductive layer 12 and the exposed first insulating dielectric layer 112 .

[0115] In one embodiment, before subsequently forming the semiconductor layer 15 on the sacrificial layer 14, Figure 5a As shown, the top surface of the sacrificial layer 14 is patterned so that the top surface of the sacrificial layer 14 has a plurality of protrusions (ie Figure 5a The second protrusion 143 in the drawing has a longitudinal section profile that is arc-shaped.

[0116] In one embodiment, the longitudinal cross-sectional profile of the groove between adjacent second protrusions 143 is also arc-shaped, that is, the longitudinal cross-sectional profile of the top surface of the sacrificial layer 14 after patterning is wavy.

[0117] The step of patterning the top surface of the sacrificial layer 14 includes:

[0118] forming a second patterned photoresist layer (not shown) on the top surface of the sacrificial layer 14 , wherein the second patterned photoresist layer exposes a portion of the top surface of the sacrificial layer 14 , and the longitudinal cross-sectional profile of the second patterned photoresist layer is arc-shaped;

[0119] The sacrificial layer 14 is partially etched using the second patterned photoresist layer as a mask, so that a plurality of second protrusions 143 are formed on the top surface of the sacrificial layer 14 .

[0120] The step of forming the second patterned photoresist layer refers to the step of forming the first patterned photoresist layer 13 mentioned above; the step of using the second patterned photoresist layer as a mask to etch a portion of the thickness of the sacrificial layer 14 to form the second protrusion 143 refers to the step of using the first patterned photoresist layer 13 as a mask to etch a portion of the thickness of the conductive layer 12 to form the first protrusion 121, and the argon gas in the etching gas is replaced with a fluorine-containing gas (such as CF4, CHF4, C4F8, etc.); it will not be repeated here.

[0121] Preferably, the angle between the bottom tangent line of the longitudinal cross-sectional profile of the second patterned photoresist layer and the top surface of the substrate directly below the second patterned photoresist layer can also be 40° to 60°, so that the angle between the bottom tangent line of the longitudinal cross-sectional profile of the second protrusion 143 and the top surface of the substrate directly below the second protrusion 143 is 15° to 30°.

[0122] In one embodiment, the second patterned photoresist layer is in a grid pattern, or the second patterned photoresist layer is arranged in an array on the sacrificial layer 14, so that the plurality of second protrusions 143 are connected in a grid pattern, or the plurality of second protrusions 143 are arranged in an array. In other embodiments, the second patterned photoresist layer can be arranged irregularly on the sacrificial layer 14, so that the plurality of second protrusions 143 are arranged irregularly.

[0123] Preferably, the center distance between adjacent second protrusions 143 is 1.5 μm to 2 μm. It should be noted that when the plurality of second protrusions 143 are connected in a grid shape, adjacent second protrusions 143 refer to opposite sides of a single grid.

[0124] Preferably, the height of the second protrusion 143 is

[0125] In other embodiments, the top surface of the conductive layer 12 may be patterned to have a plurality of first protrusions 121 , and the top surface of the sacrificial layer 14 may be patterned to have a plurality of second protrusions 143 .

[0126] According to step S5, refer to Figure 4j and Figure 5c , a semiconductor layer 15 is formed on the sacrificial layer 14 , and the semiconductor layer 15 penetrates the sacrificial layer 14 to be electrically connected to the conductive layer 12 .

[0127] In one embodiment, the step of forming the semiconductor layer 15 may include: Figure 4i and Figure 5b As shown, the sacrificial layer 14 is etched to form a contact hole 141 exposing a portion of the top surface of the conductive layer 12; then, as shown Figure 4j and Figure 5c As shown, a semiconductor layer 15 is formed on the sacrificial layer 14 , and the semiconductor layer 15 fills the contact hole 141 , so that the semiconductor layer 15 is electrically connected to the conductive layer 12 .

[0128] The etching rates of the sacrificial layer 14, the semiconductor layer 15 and the conductive layer 12 are all greatly different. For example, the etching selectivity ratios of the sacrificial layer 14, the semiconductor layer 15 and the conductive layer 12 are all greater than 10, so that when the sacrificial layer 14 is subsequently released, the semiconductor layer 15 and the conductive layer 12 are avoided from being etched, or only a small amount of etching is performed on the semiconductor layer 15 and the conductive layer 12.

[0129] The material of the sacrificial layer 14 includes but is not limited to silicon oxide.

[0130] The material of the semiconductor layer 15 includes but is not limited to semiconductor materials such as silicon, germanium, silicon germanium, and silicon carbide.

[0131] In one embodiment, after the semiconductor layer 15 is formed, a bonding ring 16 is further formed on a portion of the top surface of the semiconductor layer 15 , so that the bonding ring 16 can be used to bond to other substrates later.

[0132] The bonding ring 16 may be made of metal materials such as germanium, aluminum, copper, nickel or gold.

[0133] According to step S6, refer to Figure 4k and Figure 5d , the semiconductor layer 15 is etched to form a release hole 151 exposing a portion of the sacrificial layer 14 .

[0134] The comb-tooth structure and the mass blocks are formed by etching the semiconductor layer 15 , and release holes 151 are formed in the comb-tooth structure, between the mass blocks and the comb-tooth structure, and between the mass blocks.

[0135] Follow step S7 and continue to Figure 4k and Figure 5d A portion of the sacrificial layer 14 is released through the release hole 151 to form a cavity 142 . The cavity 142 exposes a portion of the top surface of the conductive layer 12 .

[0136] The cavity 142 also exposes a portion of the bottom surface of the semiconductor layer 15 .

[0137] The release hole 151 is communicated with the cavity 142 , and the cavity 142 is used to provide a vibration space for the comb structure and the mass block.

[0138] When the top surface of the sacrificial layer 14 has a plurality of second protrusions 143, in step S5, a groove is formed in the area where the bottom surface of the semiconductor layer 15 contacts the second protrusions 143, and a bulge is formed downward in the area where the bottom surface of the semiconductor layer 15 contacts the grooves between adjacent second protrusions 143, so that after step S7, the bottom surface of the semiconductor layer 15 exposed by the cavity 142 has a plurality of third protrusions 152, and the longitudinal cross-sectional profile of the third protrusions 152 is arc-shaped.

[0139] In one embodiment, the third protrusions 152 and the second protrusions 143 may have the same shape, arrangement, and size.

[0140] Therefore, the top surface of the conductive layer 12 has a plurality of first protrusions 121 , and / or the bottom surface of the semiconductor layer 15 has a plurality of third protrusions 152 .

[0141] In one embodiment, after the sacrificial layer 14 is formed (if the top surface of the sacrificial layer 14 has a plurality of second protrusions 143, then after the second protrusions 143 are formed), the sacrificial layer 14 is partially etched to form a groove (not shown) in the sacrificial layer 14; and, the semiconductor layer 15 fills the groove, so that after a portion of the sacrificial layer 14 is released through the release hole 151 to form the cavity 142, the bottom surface of the semiconductor layer 15 located in the cavity 142 forms a limiting structure (not shown).

[0142] The limiting structure is used to limit the range of the upward and downward movement of the mass block, so as to avoid problems such as breakage of the mass block due to excessive vibration.

[0143] The number of the limiting structures is much smaller than the number of the first protrusions 121 and the third protrusions 152. For example, the number of the limiting structures is two. All the first protrusions 121 can be distributed on the entire top surface of the conductive layer 12, and all the third protrusions 152 can be distributed on the entire bottom surface of the semiconductor layer 15.

[0144] The width and height of the limiting structure are correspondingly much larger than the width and height of the first protrusion 121 and the third protrusion 152 . For example, the width and height of the limiting structure are correspondingly larger than 10 times the width and height of the first protrusion 121 and the third protrusion 152 .

[0145] In one embodiment, the MEMS device is a capacitive sensor, and the semiconductor layer 15 and the conductive layer 12 are both electrode plates, wherein the semiconductor layer 15 is an upper electrode plate, and the conductive layer 12 is a lower electrode plate.

[0146] As can be seen from the above, in the method for manufacturing a MEMS device of the present invention, before etching the conductive layer 12 to expose a portion of the top surface of the substrate, the top surface of the conductive layer 12 is patterned so that the top surface of the conductive layer 12 has a plurality of protrusions (i.e., first protrusions 121); and / or, before forming the semiconductor layer 15 on the sacrificial layer 14, the top surface of the sacrificial layer 14 is patterned so that the top surface of the sacrificial layer 14 has a plurality of protrusions (i.e., second protrusions 143), thereby causing the bottom surface of the semiconductor layer 15 to have a plurality of protrusions (i.e., third protrusions 152); and the longitudinal cross-sectional profile of the protrusions is arc-shaped, so that during the operation of the MEMS device, the mass block formed by etching the semiconductor layer 15 moves up and down so that the bottom surface of the mass block is aligned with the conductive layer 15. 2, the bottom surface of the proof block is in point contact with the top surface of the conductive layer 12 (i.e., the top of the protrusion on the bottom surface of the proof block is in point contact with the top surface of the conductive layer 12, or, the bottom surface of the proof block is in point contact with the top of the protrusion on the top surface of the conductive layer 12, or, the top of the protrusion on the bottom surface of the proof block is in point contact with the top of the protrusion on the top surface of the conductive layer 12), that is, the contact area between the two is very small, so that even if the area of ​​the proof block is increased, the bottom surface of the proof block can be prevented from adhering to the top surface of the conductive layer 12, and the proof block can return to its original position, thereby improving the performance of the MEMS device (for example, improving sensitivity, reducing stray capacitance, and improving signal-to-noise ratio) while also enabling the MEMS device to meet reliability testing requirements (for example, pull-in test, etc.) proposed for coping with harsh environments.

[0147] Since the top surface of the conductive layer 12 and / or the bottom surface of the semiconductor layer 15 are not subjected to complex process treatments, the warping of the conductive layer 12 and / or the semiconductor layer 15 is less affected; and although there is stress accumulation in the grooves between adjacent protrusions, the protrusions can release stress in the protruding direction. Therefore, the formation of the protrusions has little effect on the warping of the conductive layer 12 and / or the semiconductor layer 15.

[0148] Since the height of the limiting structure is relatively large, the capacitance value corresponding to the position where the limiting structure is located is greatly different from the capacitance value corresponding to the position outside the limiting structure. If too many limiting structures are set, it will lead to a large stray capacitance; and the height of the protrusion is very small, so that the difference between the spacing between the protrusion on one electrode plate and the other electrode plate opposite to it and the spacing between the groove outside the protrusion on one electrode plate and the other electrode plate opposite to it is reduced, and since the longitudinal cross-sectional profile of the protrusion is arc-shaped, the height difference between the part outside the top of the protrusion and the groove outside the protrusion is reduced, further reducing the difference between the spacing between the part outside the top of the protrusion on one electrode plate and the other electrode plate opposite to it and the spacing between the groove outside the protrusion on one electrode plate and the other electrode plate opposite to it, thereby reducing the difference between the capacitance value corresponding to the position where the protrusion is located and the capacitance value corresponding to the position outside the protrusion, so that even if a large number of the protrusions are set, the generated stray capacitance is very small. Therefore, in the present invention, by providing a small number of the limiting structures in combination with a large number of the protrusions, it is possible to avoid the generation of large stray capacitance, thereby having little impact on the output of the capacitance signal.

[0149] When the center distance between adjacent protrusions is 1.5μm to 2μm, it can avoid the spacing between adjacent protrusions being too large, which causes the area between adjacent protrusions on one electrode plate to adhere to another electrode plate, and avoid the spacing between adjacent protrusions being too small, which causes the total contact area of ​​all the protrusions on one electrode plate to be too large and adhere to another electrode plate.

[0150] When the height of the protrusion is When the height of the protrusion is too small to play the role of anti-adhesion, the height of the protrusion can be avoided from being too large to cause a large stray capacitance.

[0151] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A MEMS device, characterized in that: include: substrate; a conductive layer formed on a portion of the substrate; a sacrificial layer formed on the conductive layer and the substrate, wherein a cavity is formed in the sacrificial layer, and the cavity exposes a portion of the top surface of the conductive layer; a semiconductor layer formed on the sacrificial layer, the semiconductor layer being electrically connected to the conductive layer, and a release hole being formed in the semiconductor layer, the release hole being in communication with the cavity; The top surface of the conductive layer and / or the bottom surface of the semiconductor layer has a plurality of protrusions, and the longitudinal section profile of the protrusions is arc-shaped.

2. The MEMS device according to claim 1, wherein: The base includes a substrate and an insulating dielectric layer formed on the substrate, and the conductive layer penetrates the insulating dielectric layer to be electrically connected to the substrate.

3. The MEMS device according to claim 1, wherein: The multiple protrusions are connected in a grid shape, or the multiple protrusions are arranged in an array.

4. The MEMS device according to claim 1, wherein: The angle between the bottom tangent line of the longitudinal section profile of the protrusion and the top surface of the base directly below the protrusion is 15° to 30°.

5. The MEMS device according to claim 1, wherein: The center distance between adjacent protrusions is 1.5 μm to 2 μm.

6. The MEMS device according to claim 1, wherein: The height of the protrusion is 7. A method for manufacturing a MEMS device, characterized in that: include: providing a substrate; forming a conductive layer on the substrate; Etching the conductive layer to expose a portion of the top surface of the substrate; forming a sacrificial layer on the etched conductive layer and the exposed substrate; forming a semiconductor layer on the sacrificial layer, wherein the semiconductor layer penetrates the sacrificial layer to be electrically connected to the conductive layer; Etching the semiconductor layer to form a release hole exposing a portion of the sacrificial layer; releasing a portion of the sacrificial layer through the release hole to form a cavity, wherein the cavity exposes a portion of the top surface of the conductive layer; Before etching the conductive layer, the top surface of the conductive layer is patterned so that the top surface of the conductive layer has a plurality of protrusions; and / or before forming the semiconductor layer on the sacrificial layer, the top surface of the sacrificial layer is patterned so that the top surface of the sacrificial layer has a plurality of protrusions; the longitudinal cross-sectional profile of the protrusion is arc-shaped.

8. The method for manufacturing a MEMS device according to claim 7, wherein: The base includes a substrate and an insulating dielectric layer formed on the substrate, and the conductive layer penetrates the insulating dielectric layer to be electrically connected to the substrate.

9. The method for manufacturing a MEMS device according to claim 7, wherein: The multiple protrusions are connected in a grid shape, or the multiple protrusions are arranged in an array.

10. The method for manufacturing a MEMS device according to claim 7, wherein: The angle between the bottom tangent line of the longitudinal section profile of the protrusion and the top surface of the base directly below the protrusion is 15° to 30°.

11. The method for manufacturing a MEMS device according to claim 7, wherein: The center distance between adjacent protrusions is 1.5 μm to 2 μm.

12. The method for manufacturing a MEMS device according to claim 7, wherein: The height of the protrusion is 13. The method for manufacturing a MEMS device according to claim 7, wherein: The step of patterning the top surface of the conductive layer and / or patterning the top surface of the sacrificial layer includes: forming a patterned photoresist layer on the top surface of the conductive layer and / or the sacrificial layer, wherein the longitudinal cross-sectional profile of the patterned photoresist layer is an arc shape; The conductive layer and / or the sacrificial layer are partially etched using the patterned photoresist layer as a mask, so that a top surface of the conductive layer has a plurality of protrusions, and / or a top surface of the sacrificial layer has a plurality of protrusions.

14. The method for manufacturing a MEMS device according to claim 13, wherein: An angle between a bottom tangent line of a longitudinal cross-sectional profile of the patterned photoresist layer and a top surface of the substrate directly below the patterned photoresist layer is 40° to 60°.

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