Method of manufacturing a mask assembly

Abstract

The invention relates to a method of manufacturing a mask assembly. A method of manufacturing a mask assembly includes: fixing a mask sheet to a mask frame, where the mask sheet includes a sheet frame and a plurality of first deposition holes through the sheet frame; and laser-processing, by a laser processing apparatus, the plurality of first deposition holes into a plurality of mask deposition holes passing through the sheet frame, respectively, in which each of the plurality of first deposition holes includes: a (1-1) th deposition hole in the first surface of the sheet frame; and a 1-2 deposition hole in a second surface of the sheet frame opposite to the first surface and communicating with the 1-1 deposition hole, in which a width of each of the plurality of mask deposition holes gradually decreases from the first surface of the sheet frame toward the second surface of the sheet frame.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0037395 filed on March 18, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments are directed to a method, and more particularly, to a method of manufacturing a mask assembly. Background Art

[0004] Mobile electronic devices have become widely used. In addition to small electronic devices such as mobile phones, tablet personal computers (PCs) have recently been widely used as mobile electronic devices.

[0005] To support various functions, these mobile electronic devices include display devices for providing visual information (such as images and / or videos) to users. Recently, as other components for driving the display devices have become smaller, the proportion of display devices in electronic devices has gradually increased, and structures that can be bent from a flat state to a specific angle have also been developed. Summary of the Invention

[0006] One or more embodiments of the present disclosure provide a method for manufacturing a mask assembly for reducing a shadow phenomenon in a deposition process.

[0007] Furthermore, one or more embodiments of the present disclosure provide a method for manufacturing a mask assembly to reduce a phenomenon in which unnecessary deformation of the mask assembly occurs during a process of manufacturing the mask assembly.

[0008] However, the present disclosure is not limited thereto.

[0009] Aspects and features of embodiments of the disclosure will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of one or more embodiments of the disclosure.

[0010] According to one or more embodiments, a method for manufacturing a mask assembly includes: fixing a mask sheet to a mask frame, wherein the mask sheet includes a sheet frame and a plurality of first deposition holes passing through the sheet frame; and laser processing the plurality of first deposition holes into a plurality of mask deposition holes passing through the sheet frame by a laser processing device, wherein each of the plurality of first deposition holes includes: a 1-1th deposition hole in a first surface of the sheet frame; and a 1-2th deposition hole in a second surface of the sheet frame opposite to the first surface and connected to the 1-1th deposition hole, wherein the width of each of the plurality of mask deposition holes gradually decreases from the first surface of the sheet frame toward the second surface of the sheet frame.

[0011] A thickness of each of the plurality of mask deposition holes may be the same as a thickness of the sheet frame.

[0012] Each of the plurality of mask deposition holes may be recessed from the first surface toward the second surface.

[0013] The width of the 1-1th deposition hole may gradually decrease from the first surface toward the second surface of the sheet frame, and the width of the 1-2th deposition hole may gradually decrease from the second surface toward the first surface of the sheet frame.

[0014] The sum of the thickness of the 1-1th deposition hole and the thickness of the 1-2th deposition hole may be equal to the thickness of the sheet frame.

[0015] The 1-1th deposition hole may be recessed from the first surface toward the second surface, and the 1-2th deposition hole may be recessed from the second surface toward the first surface.

[0016] When fixing the mask sheet to the mask frame, the sheet frame may include a protrusion protruding toward a central axis of the first deposition hole at a boundary between the 1-1th deposition hole and the 1-2th deposition hole.

[0017] The 1-1 th deposition hole may be thicker than the 1-2 th deposition hole.

[0018] The laser processing may include: placing the mask sheet on a stage so that the second surface faces the stage; and emitting a laser beam through a light source, the laser beam passing through an optical unit and being incident on the first surface.

[0019] The light source may include at least one of a tuner, a beam splitter, a beam limiter, a scanner, and a telecentric F-theta lens.

[0020] According to one or more embodiments, a method for manufacturing a mask assembly includes: fixing a mask sheet to a mask frame, wherein the mask sheet includes a sheet frame and a plurality of first deposition holes passing through the sheet frame; and laser processing the plurality of first deposition holes into a plurality of mask deposition holes passing through the sheet frame by a laser processing device, wherein each of the plurality of first deposition holes includes: a 1-1 deposition hole in a first surface of the sheet frame; and a 1-2 deposition hole in a second surface of the sheet frame opposite to the first surface and connected to the 1-1 deposition hole, wherein a width of the 1-1 deposition hole gradually decreases from the first surface of the sheet frame toward the second surface, and a width of the 1-2 deposition hole gradually decreases from the second surface of the sheet frame toward the first surface.

[0021] The sum of the thickness of the 1-1th deposition hole and the thickness of the 1-2th deposition hole may be equal to the thickness of the sheet frame.

[0022] The 1-1th deposition hole may be recessed from the first surface toward the second surface, and the 1-2th deposition hole may be recessed from the second surface toward the first surface.

[0023] When fixing the mask sheet to the mask frame, the sheet frame may include a protrusion protruding toward a central axis of the first deposition hole at a boundary between the 1-1th deposition hole and the 1-2th deposition hole.

[0024] A width of each of the plurality of mask deposition holes may gradually decrease from the first surface toward the second surface of the sheet frame.

[0025] A thickness of each of the plurality of mask deposition holes may be the same as a thickness of the sheet frame.

[0026] Each of the plurality of mask deposition holes may be recessed from the first surface toward the second surface.

[0027] The 1-1 th deposition hole may be thicker than the 1-2 th deposition hole.

[0028] The laser processing may include: placing the mask sheet on a stage so that the second surface faces the stage; and emitting a laser beam through a light source, the laser beam passing through an optical unit and being incident on the first surface.

[0029] The light source may include at least one of a tuner, a beam splitter, a beam limiter, a scanner, and a telecentric F-theta lens. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which: Figure 1 is a cross-sectional view of an apparatus for manufacturing a display device according to one or more embodiments; Figure 2is a schematic flow chart of a method of manufacturing a mask assembly according to one or more embodiments; Figure 3 is a schematic perspective view of a sheet frame according to one or more embodiments; Figure 4 is a schematic perspective view of a mask sheet according to one or more embodiments; Figure 5 is a schematic cross-sectional view of a mask sheet according to one or more embodiments; Figure 6 is an exploded perspective view of a mask assembly according to one or more embodiments; Figure 7 is a perspective view of a mask assembly according to one or more embodiments; Figure 8 is a schematic cross-sectional view of a mask sheet according to one or more embodiments; Figure 9 is a schematic perspective view of a laser processing apparatus according to one or more embodiments; Figure 10 is a schematic block diagram of an optical unit according to one or more embodiments; Figure 11 is a schematic plan view of a mask sheet according to one or more embodiments; Figure 12 is a schematic cross-sectional view of a mask sheet according to one or more embodiments; Figure 13 is a schematic cross-sectional view of a mask sheet according to one or more embodiments; Figure 14 is a schematic plan view of a display device according to one or more embodiments; Figure 15 is a schematic cross-sectional view of a display device according to one or more embodiments; and Figure 16 is an equivalent circuit diagram of a pixel according to one or more embodiments. DETAILED DESCRIPTION

[0031] Reference will now be made in detail to the embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals always represent the same elements. In this regard, one or more embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Therefore, the embodiments will be described below solely with reference to the accompanying drawings to explain the aspects and features of the embodiments of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. As used herein, "A and / or B" means A, B, or A and B. In addition, "at least one of A and B" means A, B, or A and B. Throughout this disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0032] Since the present disclosure allows for various variations and numerous embodiments, specific embodiments will be shown in the drawings and described in the written description. From the following detailed description of one or more embodiments in conjunction with the drawings, the effects, aspects, and features of one or more embodiments and methods for achieving them will become apparent. However, one or more embodiments may have different forms and should not be construed as being limited to the description set forth herein.

[0033] One or more embodiments will be described in more detail below with reference to the accompanying drawings. Regardless of the figure numbers, those elements that are identical or corresponding to each other are given the same reference numerals, and their redundant descriptions are omitted.

[0034] Although terms such as "first" and "second" may be used to describe various elements, such elements may not be limited to the above terms. The above terms are only used to distinguish one element from another.

[0035] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0036] It will be understood that the terms “comprising,” “including,” and “having” as used herein specify the presence of stated features or elements, but do not preclude the addition of one or more other features and / or elements.

[0037] It will be further understood that when a layer, region or element is referred to as being on another layer, region or element, it can be directly or indirectly on the other layer, region and / or element. That is, for example, intervening layers, regions and / or elements may be present.

[0038] For the convenience of explanation, the size of the elements in the drawings may be exaggerated or reduced. For example, since the size and thickness of the elements in the drawings are arbitrarily shown for the convenience of description, the following embodiments are not limited thereto.

[0039] The x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0040] When the embodiments can be implemented differently, the specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously and / or in a reverse order to the described order.

[0041] Considering the entirety of the present disclosure, one of ordinary skill in the art will understand that each suitable feature of the various embodiments of the present disclosure may be partially or completely combined or combined with each other, and may be technically interlocked and operated in various suitable ways, and each embodiment may be implemented independently of each other or in combination with each other in any suitable manner, unless otherwise stated or implied.

[0042] Figure 1 is a cross-sectional view of an apparatus 1 for manufacturing a display device according to one or more embodiments.

[0043] The apparatus 1 may include a chamber 10 , a first support 20 , a second support 30 , a mask assembly 40 , a deposition source 50 , a magnetic unit 60 , a vision unit 70 , and a pressure controller 80 .

[0044] The chamber 10 may include a space therein and may accommodate the display substrate DS and the mask assembly 40. In this regard, a portion of the chamber 10 may be open, and the gate valve 11 may be installed in the open portion of the chamber 10. In this case, the open portion of the chamber 10 may be opened or closed according to the operation of the gate valve 11.

[0045] In this regard, the display substrate DS may refer to a display substrate DS in a process of manufacturing a display device, in which at least one of an organic layer, an inorganic layer, and a metal layer is deposited on a substrate 100 (refer to FIG. Figure 15 Alternatively, the display substrate DS may be a substrate 100 on which no organic layer, inorganic layer, and metal layer have been deposited (eg, see Figure 15 ).

[0046] The first support 20 may support the display substrate DS. In this regard, the first support 20 may be in the form of a plate fixed to the interior of the chamber 10. In another embodiment, the first support 20 may have the display substrate DS positioned thereon and may be in the form of a shuttle that is linearly movable in the chamber 10. In another embodiment, the first support 20 may include an electrostatic chuck or an adhesive chuck disposed in the chamber 10 to be fixed to or moved in the chamber 10.

[0047] The second support 30 may support the mask assembly 40. In this regard, the second support 30 may be disposed inside the chamber 10. The second support 30 may fine-tune the position of the mask assembly 40. In this regard, the second support 30 may include a separate driver and / or alignment unit for moving the mask assembly 40 in different directions.

[0048] In another embodiment, the second support 30 may be in the form of a shuttle. In this case, the second support 30 may have the mask assembly 40 positioned thereon and may transport the mask assembly 40. That is, the second support 30 may be moved out of the chamber 10 to seat the mask assembly 40 thereon, and then may be brought into the chamber 10 from outside the chamber 10.

[0049] In the above case, the first support 20 and the second support 30 may be formed integrally with each other. In this case, the first support 20 and the second support 30 may include movable shuttles. In this regard, the first support 20 and the second support 30 may include structures for fixing the mask assembly 40 and the display substrate DS so that the display substrate DS is located on the mask assembly 40 and the display substrate DS and the mask assembly 40 can be linearly moved in parallel (e.g., simultaneously).

[0050] However, for convenience, a form in which the first and second supports 20 and 30 are different from each other and arranged at different positions and a form in which the first and second supports 20 and 30 are arranged inside the chamber 10 will be mainly described below.

[0051] The mask assembly 40 may be disposed inside the chamber 10 to face the display substrate DS. The deposition material M may pass through the mask assembly 40 and may be deposited on the display substrate DS.

[0052] The deposition source 50 may face the mask assembly 40 and may provide the deposition material M so that the deposition material M passes through the deposition region of the mask assembly 40 and is deposited on the display substrate DS. In this regard, the deposition source 50 may evaporate and / or sublime the deposition material M by applying heat to the deposition material M. The deposition source 50 may be fixed inside the chamber 10 and / or may be arranged inside the chamber 10 so as to be able to move linearly in one direction.

[0053] The magnetic unit 60 may be arranged inside the chamber 10 so as to face the display substrate DS and / or the mask assembly 40. In this regard, the magnetic unit 60 may apply a magnetic force to the mask assembly 40, thereby pressing the mask assembly 40 toward the display substrate DS. Specifically, the magnetic unit 60 may prevent or protect the mask assembly 40 from sagging downward, and may also position the mask assembly 40 adjacent to the display substrate DS. Furthermore, the magnetic unit 60 may maintain a uniform spacing between the mask assembly 40 and the display substrate DS.

[0054] The vision unit 70 may be arranged in the chamber 10 and may capture an image of the positions of the display substrate DS and the mask assembly 40. In this regard, the vision unit 70 may include a camera for capturing an image of the display substrate DS and the mask assembly 40. Based on the image captured by the vision unit 70, the positions of the display substrate DS and the mask assembly 40 may be identified, and deformation of the mask assembly 40 may be checked. Furthermore, based on the image, the position of the display substrate DS may be fine-tuned by the first support 20, and / or the position of the mask assembly 40 may be fine-tuned by the second support 30. However, the following will mainly describe a case where the second support 30 fine-tunes the position of the mask assembly 40 so that the positions of the display substrate DS and the mask assembly 40 are aligned with each other.

[0055] The pressure controller 80 may be connected to the chamber 10 to control the internal pressure of the chamber 10. For example, the pressure controller 80 may adjust the internal pressure of the chamber 10 to a level that is the same as or similar to that of atmospheric pressure. In addition, the pressure controller 80 may adjust the internal pressure of the chamber 10 to a level that is the same as or similar to that of a vacuum state.

[0056] The pressure controller 80 may include a connection pipe 81 connected to the chamber 10 and a pump 82 installed at the connection pipe 81. In this regard, depending on the operation of the pump 82, external air may flow in through the connection pipe 81, or the gas inside the chamber 10 may be guided to the outside through the connection pipe 81.

[0057] According to the method of manufacturing a display device by using the above-described apparatus 1 , a display substrate DS may be first prepared.

[0058] The pressure controller 80 may maintain the internal pressure of the chamber 10 at a level that is the same as or similar to that of the atmospheric pressure, and the gate valve 11 may operate to open an opening portion of the chamber 10 .

[0059] Afterwards, the display substrate DS can be loaded into the chamber 10 from outside the chamber 10. In this regard, the display substrate DS can be loaded into the chamber 10 in various ways. For example, the display substrate DS can be loaded into the chamber 10 from outside the chamber 10 by a robotic arm or the like disposed outside the chamber 10. In another embodiment, when the first support 20 is in the form of a shuttle, the first support 20 can be taken out of the chamber 10 from inside the chamber 10, and then the display substrate DS can be placed on the first support 20 by a separate robotic arm or the like disposed outside the chamber 10, and the first support 20 can be loaded into the chamber 10 from outside the chamber 10.

[0060] As described above, the mask assembly 40 may be disposed inside the chamber 10. In another embodiment, the mask assembly 40 may be loaded into the chamber 10 from outside the chamber 10 in the same or similar manner as the display substrate DS.

[0061] When the display substrate DS is loaded into the chamber 10, the display substrate DS may be placed on the first support 20. In this regard, the vision unit 70 may capture an image of the positions of the display substrate DS and the mask assembly 40. The positions of the display substrate DS and the mask assembly 40 may be recognized based on the image captured by the vision unit 70. In this regard, the apparatus 1 may include a separate controller to recognize the positions of the display substrate DS and the mask assembly 40.

[0062] Once the positions of the display substrate DS and the mask assembly 40 are identified, the second support 30 may finely adjust the position of the mask assembly 40 .

[0063] Thereafter, the deposition source 50 may be operated to supply the deposition material M toward the mask assembly 40, and the deposition material M having passed through the plurality of patterned holes in the mask assembly 40 may be deposited on the display substrate DS. In this regard, the deposition source 50 may be moved parallel to the display substrate DS and the mask assembly 40, or the display substrate DS and the mask assembly 40 may be moved parallel to the deposition source 50. That is, the deposition source 50 may be moved relative to the display substrate DS and the mask assembly 40. In this regard, the pump 82 may suck gas from the interior of the chamber 10 and discharge the gas to the outside, thereby maintaining the internal pressure of the chamber 10 at a level that is the same as or similar to that of a vacuum state.

[0064] As described above, the deposition material M provided from the deposition source 50 may pass through the mask assembly 40 and may be deposited on the display substrate DS, and thus, a stacked substrate 100 (refer to FIG. 1 ) described below may be formed. Figure 15 ) on multiple layers, for example, at least one of an organic layer, an inorganic layer and a metal layer.

[0065] Figure 2is a schematic flow chart of a method 2 of manufacturing a mask assembly 40 according to one or more embodiments.

[0066] refer to Figures 2 to 13 , the method 2 of manufacturing the mask assembly 40 may include an operation of fixing the mask sheet 42 to the mask frame 41 (in operation S1 ) and a laser processing operation (in operation S2 ).

[0067] Reference below Figures 3 to 13 A detailed description is given of the method 2 of manufacturing the mask assembly 40 .

[0068] Figure 3 is a schematic perspective view of a sheet frame 421 according to one or more embodiments. Figure 4 is a schematic perspective view of a mask sheet 42 according to one or more embodiments. Figure 5 is a schematic cross-sectional view of a mask sheet 42 according to one or more embodiments. Figure 6 is an exploded perspective view of a mask assembly 40 according to one or more embodiments. Figure 7 is a perspective view of a mask assembly 40 according to one or more embodiments. Figure 8 is a schematic cross-sectional view of a mask sheet 42 according to one or more embodiments.

[0069] More specifically, Figure 5 Can correspond to Figure 4 The line V-V', and Figure 8 Can correspond to Figure 7 Line VIII-VIII'.

[0070] refer to Figures 2 to 8 , the method 2 of manufacturing the mask assembly 40 may include an operation of fixing the mask sheet 42 to the mask frame 41 (operation S1 ).

[0071] refer to Figure 2 and Figure 3 The sheet frame 421 may include a plurality of sheet frames 421, and the plurality of sheet frames 421 may be arranged along a first direction (e.g., direction x). Each of the plurality of sheet frames 421 may extend in a second direction (e.g., direction y) that intersects the first direction (e.g., direction x). For example, the sheet frames 421 may include an Invar material.

[0072] refer to Figure 2 、 Figure 4 and Figure 5 , the sheet frame 421 may include a plurality of first deposition holes H422. That is, the mask sheet 42 may include the sheet frame 421 and the plurality of first deposition holes H422.

[0073] The sheet frame 421 may include a first surface 421S1 and a second surface 421S2 opposite the first surface 421S1. Each of the plurality of first deposition holes H422 may include a 1-1th deposition hole H4221 arranged in the first surface 421S1 of the sheet frame 421 and a 1-2th deposition hole H4222 arranged in the second surface 421S2. The first deposition holes H422 may be symmetrical about the central axis CL. Each of the 1-1th deposition hole H4221 and the 1-2nd deposition hole H4222 may be symmetrical about the central axis CL.

[0074] The 1-1st deposition hole H4221 and the 1-2nd deposition hole H4222 may communicate with each other, and the sum of the thickness D4221 of the 1-1st deposition hole H4221 and the thickness D4222 of the 1-2nd deposition hole H4222 may be equal to the thickness D421 of the sheet frame 421 .

[0075] Each of the 1-1st deposition hole H4221 and the 1-2nd deposition hole H4222 may be formed by a photolithography process. For example, each of the 1-1st deposition hole H4221 and the 1-2nd deposition hole H4222 may be formed by dry etching and / or wet etching.

[0076] When etching the sheet frame 421 from the first surface 421S1 toward the second surface 421S2, a 1-1 deposition hole H4221 may be formed. Therefore, the width W4221 of the 1-1 deposition hole H4221 may gradually decrease from the first surface 421S1 toward the second surface 421S2. For example, the 1-1 deposition hole H4221 may be recessed from the first surface 421S1 toward the second surface 421S2.

[0077] When etching the sheet frame 421 from the second surface 421S2 toward the first surface 421S1, a 1-2 deposition hole H4222 may be formed. Therefore, the width W4222 of the 1-2 deposition hole H4222 may gradually decrease from the second surface 421S2 toward the first surface 421S1. For example, the 1-2 deposition hole H4222 may be recessed from the second surface 421S2 toward the first surface 421S1.

[0078] Therefore, during the operation of securing the mask sheet 42 to the mask frame 41 (operation S1), the sheet frame 421 may include a protrusion 4211 that protrudes toward the center axis CL of the first deposition hole H422. The protrusion 4211 may be arranged at the boundary between the 1-1 deposition hole H4221 and the 1-2 deposition hole H4222. With the protrusion 4211 as the boundary, the width W4221 of the 1-1 deposition hole H4221 may gradually increase in a direction toward the first surface 421S1, and the width W4222 of the 1-2 deposition hole H4222 may gradually increase in a direction toward the second surface 421S2.

[0079] The thickness D4221 of the 1-1 deposition hole H4221 may be greater than the thickness D4222 of the 1-2 deposition hole H4222. The maximum width of the 1-1 deposition hole H4221 may be greater than the maximum width of the 1-2 deposition hole H4222. That is, the 1-1 deposition hole H4221 in contact with the first surface 421S1 may be wider than the 1-2 deposition hole H4222 in contact with the second surface 421S2.

[0080] refer to Figure 2 as well as Figures 6 to 8 , the mask sheet 42 may be fixed to the mask frame 41 . That is, the mask assembly 40 may include the mask frame 41 and the mask sheet 42 .

[0081] The mask frame 41 can support the mask sheet 42 and may include a frame opening OP41 therein. The mask frame 41 may be in the form of an image frame with the frame opening OP41 arranged in the center. The length of one side (or long side) of the mask frame 41 may be greater than the length of the other side (or short side). However, this is an example, and the shape of the mask frame 41 is not limited thereto.

[0082] The mask sheet 42 may be fixed to the mask frame 41 such that a first surface 421S1 of the sheet frame 421 faces the mask frame 41. The first surface 421S1 of the sheet frame 421 may be in contact with the mask frame 41.

[0083] Therefore, when the mask assembly 40 is as Figure 1 The arrangement shown in the chamber 10 (refer to Figure 1 ), the first surface 421S1 of the sheet frame 421 may face the deposition source 50 (refer to Figure 1 ), and the second surface 421S2 of the sheet frame 421 may face the display substrate DS (refer to Figure 1 ). Therefore, the deposited material M (ref. Figure 1 ) may sequentially pass through the frame opening OP41, the 1-1th deposition hole H4221, and the 1-2nd deposition hole H4222, and may be deposited on the display substrate DS (refer to Figure 1 However, due to the protrusion 4211 arranged at the boundary between the 1-1 deposition hole H4221 and the 1-2 deposition hole H4222, it is possible to Figure 1 The shadow phenomenon occurs during the described deposition process. Therefore, it is possible to additionally perform Figures 9 to 13 The laser processing operation (operation S2) is described.

[0084] Figure 9 is a schematic perspective view of a laser processing device 3 according to one or more embodiments. Figure 10is a schematic block diagram of an optical unit 33 according to one or more embodiments. Figure 11 is a schematic plan view of a mask sheet 42 according to one or more embodiments. Figure 12 is a schematic cross-sectional view of a mask sheet 42 according to one or more embodiments. Figure 13 is a schematic cross-sectional view of a mask sheet 42 according to one or more embodiments.

[0085] More specifically, Figure 12 and Figure 13 Can correspond to Figure 11 Line XII-XII'.

[0086] refer to Figure 2 as well as Figures 9 to 13 , the method 2 of manufacturing the mask assembly 40 may include an operation of laser processing each of the plurality of first deposition holes H422 into a mask deposition hole H42 by the laser processing device 3 (in operation S2 ).

[0087] refer to Figure 9 The laser processing device 3 may include a stage 31 , a light source 32 and an optical unit 33 .

[0088] The stage 31 may support the mask assembly 40. For example, the stage 31 may include an electrostatic chuck (ESC). Therefore, the sheet frame 421 including an Invar material may be stably placed on the stage 31. However, this is an example, and the structure of the stage 31 is not limited thereto.

[0089] The light source 32 may emit a laser beam. That is, the light source 32 may emit a femto laser beam. However, this is merely an example, and the laser beam emitted by the light source 32 is not limited thereto.

[0090] The optical unit 33 may adjust the laser beam emitted from the light source 32 to meet the optical conditions of the laser processing. The optical unit 33 may include at least one of a tuner 331, a beam splitter 332, a beam limiter 333, a scanner 334, and a telecentric F-θ lens 335. For example, the optical unit 33 may include all of the tuner 331, the beam splitter 332, the beam limiter 333, the scanner 334, and the telecentric F-θ lens 335. The laser beam emitted from the light source 32 may sequentially pass through the tuner 331, the beam splitter 332, the beam limiter 333, the scanner 334, and the telecentric F-θ lens 335, and may be irradiated onto the mask assembly 40 disposed on the stage 31.

[0091] Tuner 331 can finely adjust the position, power, and number of irradiation times of the laser beam. For example, tuner 331 may include an acousto-optic deflector. Because the laser beam passes through tuner 331 before beam splitter 332, the laser beam emitted from light source 32 can be finely adjusted, and the laser beams obtained by splitting through beam splitter 332 can all be moved according to the laser beam finely adjusted by tuner 331.

[0092] The beam splitter 332 can split the laser beam emitted from the light source 32 into a plurality of laser beams. Therefore, instead of a single laser beam, a plurality of laser beams can be irradiated in parallel (e.g., simultaneously) onto the mask assembly 40. Therefore, a plurality of first deposition holes H422 can be laser-processed in parallel (e.g., simultaneously).

[0093] The beam limiter 333 may selectively block some of the plurality of laser beams obtained by being separated through the beam splitter 332 and adjust the number of laser beams to be used.

[0094] The scanner 334 may scan the plurality of laser beams in one direction onto the mask assembly 40. For example, the scanner 334 may include a galvanometer scanner or a polygon scanner.

[0095] The telecentric F-θ lens 335 may adjust the incident angles of the plurality of laser beams to allow the laser beams to be vertically (eg, substantially vertically) incident on the mask assembly 40 .

[0096] refer to Figure 2 as well as Figures 9 to 13 The laser processing operation (in operation S2) may include an operation of placing the mask sheet 42 on the stage 31 (in operation S21), an operation of emitting a laser beam through the light source 32 (in operation S22), and an operation of passing the laser beam through the optical unit 33 to be incident toward the first surface 421S1 of the sheet frame 421 (in operation S23).

[0097] In the operation of seating the mask sheet 42 on the stage 31 (operation S21), the second surface 421S2 of the sheet frame 421 may face the stage 31. Therefore, the second surface 421S2 of the sheet frame 421 and the stage 31 may contact each other.

[0098] like Figure 11 and Figure 12 As shown in FIG, in the operation of incidenting the laser beam toward the first surface 421 S1 of the sheet frame 421 by passing the laser beam through the optical unit 33 (operation S23 ), the region of the sheet frame 421 to which the laser beam reaches is referred to as a laser region ERL.

[0099] The laser region ERL may correspond to each of the plurality of first deposition holes H422. In a plan view, the size of the laser region ERL may be larger than that of the first deposition holes H422. More specifically, the laser region ERL may overlap with the protrusion 4211 of the sheet frame 421. Although Figure 11 A plurality of laser regions ERL are shown as being spaced apart from each other (eg, spaced apart), but this is merely an example, and the plurality of laser regions ERL may overlap with each other. Alternatively, one laser region ERL may overlap with the plurality of first deposition holes H422.

[0100] like Figure 12 and Figure 13 As shown in FIG, when the laser beam is incident on the sheet frame 421, at least a portion of the sheet frame 421 may be removed. That is, the first deposition hole H422 may be processed into the mask deposition hole H42. Therefore, as a result, the mask sheet 42 may include the sheet frame 421 and a plurality of mask deposition holes H42.

[0101] The plurality of mask deposition holes H42 may pass through the sheet frame 421. That is, the thickness D42 of the plurality of mask deposition holes H42 may be the same as the thickness D421 of the sheet frame 421. The width W42 of each of the plurality of mask deposition holes H42 may gradually decrease from the first surface 421S1 toward the second surface 421S2 of the sheet frame 421. For example, each of the plurality of mask deposition holes H42 may be recessed from the first surface 421S1 toward the second surface 421S2.

[0102] When the first deposition hole H422 is processed into the mask deposition hole H42, the protrusion 4211 of the sheet frame 421 may be removed. Therefore, the above reference Figure 1 Furthermore, since the laser processing operation (operation S2) is performed with the mask sheet 42 fixed to the mask frame 41, a phenomenon in which unnecessary deformation occurs in the mask sheet 42 during the laser processing operation (operation S2) can be reduced.

[0103] Figure 14 is a schematic plan view of a display device 4 according to one or more embodiments.

[0104] refer to Figure 14 The display device 4 according to one or more embodiments may include a display area DA and a peripheral area PA located outside the display area DA along an edge or periphery of the display area DA. The display device 4 may provide an image by an array of a plurality of pixels PX arranged two-dimensionally in the display area DA (e.g., along rows and columns of a matrix).

[0105] The peripheral area PA is an area that does not provide an image and may be completely or partially around the display area DA (e.g., surrounding the display area DA). A driver for providing electrical signals or power to the pixel circuit corresponding to each of the pixels PX may be arranged in the peripheral area PA. Pads, which are areas to which electronic components or a printed circuit board (PCB) can be electrically connected, may be arranged in the peripheral area PA.

[0106] In the following, it is assumed that the display device 4 includes an organic light-emitting diode (OLED) as a light-emitting element, but the display device 4 described herein is not limited thereto. In another embodiment, the display device 4 may be a light-emitting display device including an inorganic light-emitting diode, that is, an inorganic light-emitting display. The inorganic light-emitting diode may include a PN junction diode, which includes an inorganic semiconductor-based material. When voltage is applied to the PN junction diode in the forward direction, holes and electrons are injected, and by converting the energy generated by the recombination of holes and electrons into light energy, light of a specific color can be emitted. The above-mentioned inorganic light-emitting diode can have a width of several microns to hundreds of microns, and in some embodiments, the inorganic light-emitting diode can be referred to as a micro-LED. In another embodiment, the display device 4 may be a quantum dot light-emitting display.

[0107] The display device 4 can be used not only as a display screen for portable electronic devices (such as mobile phones, smartphones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs)), but also as a display screen for various products (such as televisions, notebook computers, monitors, billboards, and Internet of Things (IoT) devices). Furthermore, the display device 4 according to one or more embodiments can be used in wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs). Furthermore, the display device 4 according to one or more embodiments can be used as a dashboard in an automobile, a central information display (CID) placed on the center instrument panel or instrument panel of an automobile, an interior mirror display that replaces the automobile's side mirrors, or a display screen placed on the back of the front seats as a rear-seat entertainment system in an automobile.

[0108] Figure 15 is a schematic cross-sectional view of a display device 4 according to one or more embodiments, and may correspond to a cross-sectional view taken along Figure 14 A cross section of the display device 4 taken along line XV-XV'.

[0109] refer to Figure 15 The display device 4 may include a stacked structure of a substrate 100, a pixel circuit layer PCL, a display element layer DEL, and an encapsulation layer 300. The display substrate DS (refer to Figure 1) may be a substrate in a process of manufacturing the display device 4 , for example, a substrate in which at least one of the pixel circuit layer PCL, the display element layer DEL, and the encapsulation layer 300 is stacked on the substrate 100 .

[0110] The substrate 100 may have a multilayer structure including a base layer and an inorganic layer, the base layer including a polymer resin. For example, the substrate 100 may include a base layer including a polymer resin and a barrier layer including an inorganic insulating layer. For example, the substrate 100 may include a first base layer 101, a first barrier layer 102, a second base layer 103, and a second barrier layer 104 stacked sequentially. The first base layer 101 and the second base layer 103 may include polyimide (PI), polyethersulfone (PES), polyarylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polycarbonate, cellulose triacetate (TAC), and / or cellulose acetate propionate (CAP). The first barrier layer 102 and the second barrier layer 104 may include an inorganic insulating material such as silicon oxide, silicon oxynitride, and / or silicon nitride. The substrate 100 may be flexible.

[0111] The pixel circuit layer PCL is disposed on the substrate 100 . Figure 15 A pixel circuit layer PCL including a thin film transistor TFT and a buffer layer 111, a first gate insulating layer 112, a second gate insulating layer 113, an interlayer insulating layer 114, a first planarization insulating layer 115, and a second planarization insulating layer 116 is shown.

[0112] The buffer layer 111 may reduce or prevent penetration of foreign matter, moisture, and / or external air from below the substrate 100, and may provide a flat surface on the substrate 100. The buffer layer 111 may include an inorganic insulating material such as silicon oxide, silicon oxynitride, and / or silicon nitride, and may have a single-layer or multi-layer structure including the above materials.

[0113] The thin film transistor TFT on the buffer layer 111 may include a semiconductor layer Act, and the semiconductor layer Act may include polycrystalline silicon. Alternatively, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor, and / or an organic semiconductor. The semiconductor layer Act may include a channel region C and a drain region D and a source region S respectively arranged on either side of the channel region C. The gate electrode GE may overlap with the channel region C in the thickness direction of the substrate 100.

[0114] The gate electrode GE may include a low-resistance metal material, a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a multi-layer or single-layer structure including the above materials.

[0115] The first gate insulating layer 112 between the semiconductor layer Act and the gate electrode GE may include an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO x Zinc oxide (ZnO x ) can be zinc oxide (ZnO) and / or zinc peroxide (ZnO2).

[0116] The second gate insulating layer 113 may cover the gate electrode GE and may be disposed on the first gate insulating layer 112. Similar to the first gate insulating layer 112, the second gate insulating layer 113 may include an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) and / or zinc oxide (ZnO x Zinc oxide (ZnO x ) can be zinc oxide (ZnO) and / or zinc peroxide (ZnO2).

[0117] The upper electrode Cst2 of the storage capacitor Cst can be disposed on the second gate insulating layer 113. The upper electrode Cst2 can overlap with the underlying gate electrode GE in the thickness direction of the substrate 100. In this regard, the gate electrode GE and the upper electrode Cst2 overlapping each other with the second gate insulating layer 113 therebetween can constitute the storage capacitor Cst. That is, the gate electrode GE can function as the lower electrode Cst1 of the storage capacitor Cst.

[0118] As described above, the storage capacitor Cst and the thin film transistor TFT may overlap each other in the thickness direction of the substrate 100. In one or more embodiments, the storage capacitor Cst may not overlap with the thin film transistor TFT.

[0119] The upper electrode Cst2 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and may have a single-layer or multi-layer structure including the above materials.

[0120] The interlayer insulating layer 114 may cover the upper electrode Cst2 and may be disposed on the second gate insulating layer 113. The interlayer insulating layer 114 may include silicon oxide (SiO2), silicon nitride (SiNx ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) and / or zinc oxide (ZnO x Zinc oxide (ZnO x ) may be zinc oxide (ZnO) and / or zinc peroxide (ZnO 2 ). The interlayer insulating layer 114 may have a single-layer or multi-layer structure including the above-mentioned inorganic insulating material.

[0121] Each of the drain electrode DE and the source electrode SE may be on the interlayer insulating layer 114. The drain electrode DE and the source electrode SE may be connected to the drain region D and the source region S, respectively, through contact holes defined in the underlying insulating layers (e.g., the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 114). The drain electrode DE and the source electrode SE may include highly conductive materials. The drain electrode DE and the source electrode SE may include conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may have a multilayer or single-layer structure including these materials. In one or more embodiments, the drain electrode DE and the source electrode SE may have a multilayer structure of titanium (Ti) / aluminum (Al) / titanium (Ti).

[0122] The first planarization insulating layer 115 may cover the drain electrode DE and the source electrode SE and may be disposed on the interlayer insulating layer 114. The first planarization insulating layer 115 may include an organic insulating material, such as a general commercial polymer (such as polymethyl methacrylate (PMMA) or polystyrene (PS)), a polymer derivative having a phenol group, an acrylic acid-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, and / or a blend thereof.

[0123] The second planarization insulating layer 116 may be provided on the first planarization insulating layer 115. The second planarization insulating layer 116 may include the same material as that of the first planarization insulating layer 115, and may include an organic insulating material such as a general commercial polymer (such as PMMA or PS), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a p-xylene polymer, a vinyl alcohol polymer, and / or a blend thereof.

[0124] The display element layer DEL may be disposed on the pixel circuit layer PCL having the above-described structure. The display element layer DEL may include an organic light-emitting diode (OLED) as a display element (i.e., a light-emitting element), and the organic light-emitting diode OLED may include a stacked structure of a pixel electrode 210, an intermediate layer 220, and a common electrode 230. The organic light-emitting diode OLED may emit, for example, red, green, or blue light, or may emit red, green, blue, or white light. The organic light-emitting diode OLED may emit light through an emission region, and the emission region may be defined as a pixel PX.

[0125] The pixel electrode 210 of the organic light emitting diode OLED may be on the second planarization insulating layer 116 and electrically connected to the thin film transistor TFT through a contact hole defined in the second planarization insulating layer 116 and the first planarization insulating layer 115 and a contact metal CM disposed on the first planarization insulating layer 115 .

[0126] The pixel electrode 210 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and / or aluminum zinc oxide (AZO). In another embodiment, the pixel electrode 210 may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and / or compounds thereof. In another embodiment, the pixel electrode 210 may further include a layer formed of ITO, IZO, ZnO, and / or In2O3 on / below the reflective layer.

[0127] A pixel defining layer 117 including an opening 117OP exposing a central portion of the pixel electrode 210 may be disposed on the pixel electrode 210. The pixel defining layer 117 may include an organic insulating material and / or an inorganic insulating material. The opening 117OP may define an emission region for light emitted from the organic light emitting diode OLED. For example, the size / width of the opening 117OP may correspond to the size / width of the emission region. Thus, the size and / or width of the pixel PX may depend on the size and / or width of the corresponding opening 117OP of the pixel defining layer 117.

[0128] The intermediate layer 220 may include an emission layer 222 corresponding to the pixel electrode 210. The emission layer 222 may include a polymer organic material and / or a low molecular weight organic material that emits light of a specific color. Alternatively, the emission layer 222 may include an inorganic light emitting material and / or quantum dots.

[0129] In one or more embodiments, the intermediate layer 220 may include a first functional layer 221 and a second functional layer 223, respectively disposed below and above the emission layer 222. The first functional layer 221 may include, for example, a hole transport layer (HTL) or an HTL and a hole injection layer (HIL). The second functional layer 223 is disposed above the emission layer 222 and may include an electron transport layer (ETL) and / or an electron injection layer (EIL). Similar to the common electrode 230 described below, the first functional layer 221 and / or the second functional layer 223 may be common layers that completely cover the substrate 100.

[0130] The common electrode 230 may be disposed above the pixel electrode 210 and may overlap with the pixel electrode 210 in the thickness direction of the substrate 100. The common electrode 230 may include a conductive material with a low work function. For example, the common electrode 230 may include a (semi-)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), and / or alloys thereof. Alternatively, the common electrode 230 may include a layer such as ITO, IZO, ZnO, and / or In2O3 on the (semi-)transparent layer including the above materials. The common electrode 230 may be a single electrode that completely covers the substrate 100.

[0131] The encapsulation layer 300 may be disposed on the display element layer DEL and may cover the display element layer DEL. The encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer, and as an example embodiment, Figure 15 An encapsulation layer 300 including a first inorganic encapsulation layer 310 , an organic encapsulation layer 320 , and a second inorganic encapsulation layer 330 sequentially stacked on one another is shown.

[0132] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include one or more inorganic materials selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 320 may include a polymer-based material. Examples of polymer-based materials may include acrylic resins, epoxy resins, polyimide, and polyethylene. In one or more embodiments, the organic encapsulation layer 320 may include acrylate. The organic encapsulation layer 320 may be formed by curing a monomer or coating with a polymer. The organic encapsulation layer 320 may have transparency.

[0133] In one or more embodiments, a touch sensor layer may be disposed on the encapsulation layer 300, and an optical functional layer may be disposed on the touch sensor layer. The touch sensor layer may obtain coordinate information based on external input (e.g., a touch event). The optical functional layer may reduce the reflectivity of light (external light) incident from the outside toward the display device 4 and / or may improve the color purity of the light emitted from the display device 4. In one or more embodiments, the optical functional layer may include a phase retarder and / or a polarizer. The phase retarder may be a film type or a liquid crystal coating type, and may include a λ / 2 phase retarder and / or a λ / 4 phase retarder. The polarizer may also be a film type or a liquid crystal coating type. The film type may include a long synthetic resin film, and the liquid crystal coating type may include liquid crystals arranged in a specific arrangement. The phase retarder and the polarizer may also include a protective film.

[0134] An adhesive member may be provided between the touch sensor layer and the optically functional layer. The adhesive member may be any commonly used adhesive member known in the art (e.g., any suitable adhesive member known to those skilled in the art) without limitation. The adhesive member may be a pressure-sensitive adhesive (PSA).

[0135] refer to Figures 1 to 13 The deposited material M described can form a reference Figure 15 The intermediate layer 220 is described. For example, the deposition material M (refer to Figure 1 ) can form an emission layer 222.

[0136] Figure 16 is an equivalent circuit diagram of a pixel PX according to one or more embodiments.

[0137] refer to Figure 16 , the pixel circuit PC may include first to seventh transistors T1 to T7, and depending on the type of the transistor (p-type or n-type) and / or operating conditions, the first terminal of each of the first to seventh transistors T1 to T7 may be a source terminal or a drain terminal, and the second terminal thereof may be a terminal different from the first terminal. For example, when the first terminal is a source terminal, the second terminal may be a drain terminal.

[0138] The pixel circuit PC can be connected to a first scan line SL, a second scan line SL-1, a third scan line SL+1, an emission control line EL, a data line DL, a driving voltage line PL and an initialization voltage line VL. The first scan line SL is configured to transmit a first scan signal Sn, the second scan line SL-1 is configured to transmit a second scan signal Sn-1, the third scan line SL+1 is configured to transmit a third scan signal Sn+1, the emission control line EL is configured to transmit an emission control signal En, the data line DL is configured to transmit a data signal DATA, the driving voltage line PL is configured to transmit a driving voltage ELVDD, and the initialization voltage line VL is configured to transmit an initialization voltage Vint.

[0139] The first transistor T1 includes a gate terminal connected to the second node N2, a first terminal connected to the first node N1, and a second terminal connected to the third node N3. The first transistor T1 functions as a driving transistor and is configured to receive a data signal DATA and provide a driving current to the light emitting element according to a switching operation of the second transistor T2. The light emitting element may be an organic light emitting diode (OLED).

[0140] The second transistor T2 (e.g., a switching transistor) includes a gate terminal connected to the first scan line SL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1 (or the first terminal of the first transistor T1). The second transistor T2 can be turned on in response to a first scan signal Sn received through the first scan line SL to perform a switching operation for transmitting a data signal DATA transmitted to the data line DL to the first node N1.

[0141] The third transistor T3 (e.g., a compensation transistor) includes a gate terminal connected to the first scan line SL, a first terminal connected to the second node N2 (or the gate terminal of the first transistor T1), and a second terminal connected to the third node N3 (or the second terminal of the first transistor T1). The third transistor T3 can be turned on in response to the first scan signal Sn received via the first scan line SL, thereby forming a diode connection with the first transistor T1. The third transistor T3 can have a structure in which two or more transistors are connected in series.

[0142] The fourth transistor T4 (e.g., a first initialization transistor) includes a gate terminal connected to the second scan line SL-1, a first terminal connected to the initialization voltage line VL, and a second terminal connected to the second node N2. The fourth transistor T4 can be turned on in response to the second scan signal Sn-1 received via the second scan line SL-1 to transmit the initialization voltage Vint to the gate terminal of the first transistor T1 and initialize the gate voltage of the first transistor T1. The fourth transistor T4 can have a structure in which two or more transistors are connected in series.

[0143] The fifth transistor T5 (e.g., a first emission control transistor) includes a gate terminal connected to the emission control line EL, a first terminal connected to the driving voltage line PL, and a second terminal connected to the first node N1. The sixth transistor T6 (e.g., a second emission control transistor) includes a gate terminal connected to the emission control line EL, a first terminal connected to the third node N3, and a second terminal connected to the pixel electrode of the organic light emitting diode OLED. The fifth and sixth transistors T5 and T6 are turned on in parallel (e.g., simultaneously) in response to an emission control signal En received via the emission control line EL, thereby allowing current to flow through the organic light emitting diode OLED.

[0144] The seventh transistor T7 (e.g., a second initialization transistor) includes a gate terminal connected to the third scan line SL+1, a first terminal connected to the second terminal of the sixth transistor T6 and the pixel electrode of the organic light emitting diode OLED, and a second terminal connected to the initialization voltage line VL. The seventh transistor T7 can be turned on in response to the third scan signal Sn+1 received via the third scan line SL+1 to transmit the initialization voltage Vint to the pixel electrode of the organic light emitting diode OLED and initialize the voltage of the pixel electrode of the organic light emitting diode OLED. The seventh transistor T7 may be omitted.

[0145] The storage capacitor Cst includes a first electrode connected to the second node N2 and a second electrode connected to the driving voltage line PL.

[0146] The organic light emitting diode (OLED) may include a pixel electrode and an opposing electrode facing the pixel electrode, and the opposing electrode may receive a common voltage ELVSS. The organic light emitting diode (OLED) may receive a driving current from the first transistor T1 and may emit light of a specific color, thereby displaying an image. The opposing electrode may be common to multiple pixels PX, that is, provided as a single electrode for multiple pixels PX.

[0147] According to one or more of the above embodiments, deposition quality may be improved in a deposition process for depositing a deposition material on a display substrate.

[0148] The effects of one or more embodiments are not limited thereto, and other unmentioned effects will be apparent to those of ordinary skill in the art from the appended claims and their equivalents.

[0149] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a mask assembly, the method comprising: fixing a mask sheet to a mask frame, wherein the mask sheet includes a sheet frame and a plurality of first deposition holes passing through the sheet frame; and The plurality of first deposition holes are laser-processed into a plurality of mask deposition holes passing through the sheet frame by a laser processing device, Wherein, each of the plurality of first deposition holes comprises: A 1-1th deposition hole in the first surface of the sheet frame; and a 1-2 deposition hole in a second surface of the sheet frame opposite to the first surface and communicating with the 1-1 deposition hole, The width of each of the plurality of mask deposition holes gradually decreases from the first surface of the sheet frame toward the second surface of the sheet frame.

2. The method according to claim 1, wherein A thickness of each of the plurality of mask deposition holes is the same as a thickness of the sheet frame.

3. The method according to claim 1, wherein Each of the plurality of mask deposition holes is recessed from the first surface toward the second surface.

4. The method according to claim 1, wherein A width of the 1-1th deposition hole gradually decreases from the first surface toward the second surface of the sheet frame, and a width of the 1-2th deposition hole gradually decreases from the second surface toward the first surface of the sheet frame.

5. The method according to claim 4, wherein The sum of the thickness of the 1-1th deposition hole and the thickness of the 1-2th deposition hole is equal to the thickness of the sheet frame.

6. The method according to claim 4, wherein: The 1-1th deposition hole is recessed from the first surface toward the second surface, and the 1-2th deposition hole is recessed from the second surface toward the first surface.

7. The method according to claim 4, wherein: When the mask sheet is fixed to the mask frame, the sheet frame includes a protrusion protruding toward a central axis of the first deposition hole at a boundary between the 1-1th deposition hole and the 1-2th deposition hole.

8. The method according to claim 1, wherein The 1-1 deposition hole is thicker than the 1-2 deposition hole.

9. The method according to claim 1, wherein The laser treatment includes: placing the mask sheet on a stage so that the second surface faces the stage; and A laser beam is emitted by a light source, passes through an optical unit, and is incident on the first surface.

10. The method according to claim 9, wherein: The light source includes at least one of a tuner, a beam splitter, a beam limiter, a scanner, and a telecentric F-theta lens.

11. A method of manufacturing a mask assembly, the method comprising: fixing a mask sheet to a mask frame, wherein the mask sheet includes a sheet frame and a plurality of first deposition holes passing through the sheet frame; and The plurality of first deposition holes are laser-processed into a plurality of mask deposition holes passing through the sheet frame by a laser processing device, Wherein, each of the plurality of first deposition holes comprises: A 1-1th deposition hole in the first surface of the sheet frame; and a 1-2 deposition hole in a second surface of the sheet frame opposite to the first surface and communicating with the 1-1 deposition hole, The width of the 1-1th deposition hole gradually decreases from the first surface toward the second surface of the sheet frame, and the width of the 1-2th deposition hole gradually decreases from the second surface toward the first surface of the sheet frame.

12. The method according to claim 11, wherein The sum of the thickness of the 1-1th deposition hole and the thickness of the 1-2th deposition hole is equal to the thickness of the sheet frame.

13. The method according to claim 11, wherein The 1-1th deposition hole is recessed from the first surface toward the second surface, and the 1-2th deposition hole is recessed from the second surface toward the first surface.

14. The method according to claim 11, wherein When the mask sheet is fixed to the mask frame, the sheet frame includes a protrusion protruding toward a central axis of the first deposition hole at a boundary between the 1-1th deposition hole and the 1-2th deposition hole.

15. The method according to claim 11, wherein A width of each of the plurality of mask deposition holes gradually decreases from the first surface toward the second surface of the sheet frame.

16. The method according to claim 15, wherein A thickness of each of the plurality of mask deposition holes is the same as a thickness of the sheet frame.

17. The method according to claim 15, wherein: Each of the plurality of mask deposition holes is recessed from the first surface toward the second surface.

18. The method according to claim 11, wherein The 1-1 deposition hole is thicker than the 1-2 deposition hole.

19. The method according to claim 11, wherein The laser treatment includes: placing the mask sheet on a stage so that the second surface faces the stage; and A laser beam is emitted by a light source, passes through an optical unit, and is incident on the first surface.

20. The method according to claim 19, wherein The light source includes at least one of a tuner, a beam splitter, a beam limiter, a scanner, and a telecentric F-theta lens.

Images