Encoder error code identification circuit and method and encoder system

Abstract

The embodiment of the invention provides an encoder error code identification circuit, an encoder error code identification method and an encoder system. The circuit comprises a signal input unit, a circle counting unit, an error code identification unit and a main control chip, the first end of the signal input unit is connected with the encoder, and the second end of the signal input unit is connected with the first end of the circle counting unit, the first end of the error code recognition unit and the main control chip; the second end of the circle counting unit and the second end of the error code recognition unit are connected with the main control chip; the signal input unit is used for receiving a magnetic switch signal output by a magnetic switch in the encoder; wherein the magnetic switch signal is a Gray code; the circle counting unit is used for outputting a wake-up signal based on the magnetic switch signal; the wake-up signal is used for waking up the main control chip; and the error code recognition unit is used for outputting a recognition signal based on the magnetic switch signal. The main control chip determines the abnormal condition of the magnetic switch based on the identification signal of the error code identification unit, and counts according to the wake-up signal when the magnetic switch is normal, thereby preventing the magnetic switch from being damaged to cause the error calculation of the number of turns.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to an encoder error recognition circuit, method, and encoder system. Background Art

[0002] An encoder is a device that converts physical quantities into electrical signals, and magnetic multi-turn technology is a key technology within encoders. Magnetic multi-turn encoders primarily use changes in the magnetic field to measure rotation angle and number of turns. They typically consist of a permanent magnet, a magnetic sensor (such as a Hall effect element), and electronic circuitry. The permanent magnet is mounted on the rotating shaft, and the magnetic sensor detects changes in the magnetic field, thereby obtaining information about the shaft's angular position and number of turns.

[0003] Existing magnetic multi-turn technology uses two magnetic switches, forming four Gray code groups (00-01-11-10) to detect signal changes. Each time the magnetic switch signal changes, the main control chip wakes up and counts the number of turns. Therefore, the main control chip typically wakes up four times for each encoder rotation. However, this technology has wiring issues. If the magnetic switch is damaged, the encoder will only wake up once per rotation, making it impossible to detect the damage. This can lead to incorrect turn counts and affect the overall operating accuracy of the system. Summary of the Invention

[0004] The embodiments of the present application provide an encoder error recognition circuit, method, and encoder system, which are used to identify magnetic switch damage under low power consumption conditions and avoid errors in the calculation of the number of turns.

[0005] In a first aspect, an embodiment of the present application provides an encoder error recognition circuit, comprising: a signal input unit, a circle counting unit, an error recognition unit, and a main control chip; a first end of the signal input unit is connected to the encoder, a second end of the signal input unit is connected to the first end of the circle counting unit, the first end of the error recognition unit, and the main control chip; a second end of the circle counting unit and a second end of the error recognition unit are connected to the main chip;

[0006] The signal input unit is used to receive the magnetic switch signal output by the magnetic switch in the encoder; wherein the magnetic switch signal is Gray code;

[0007] The lap counting unit is used to output a wake-up signal based on the magnetic switch signal; the wake-up signal is used to wake up the main control chip;

[0008] The error recognition unit is used to output an identification signal based on the magnetic switch signal as a basis for identifying magnetic switch abnormalities and send it to the main control chip to prompt the main control chip of the abnormality of the magnetic switch signal;

[0009] The main control chip is used to determine whether there is an abnormality in the magnetic switch based on the identification signal output by the error code identification unit, and to count based on the magnetic switch signal when the magnetic switch signal is normal.

[0010] In one embodiment, the error recognition unit includes: a first recognition subunit and a second recognition subunit;

[0011] The first end of the first identification subunit is connected to the signal input unit, and the second end of the first identification subunit is connected to the main control chip; the first identification subunit is used to output a first identification signal according to the magnetic switch signal;

[0012] The first end of the second identification subunit is connected to the signal input unit, and the second end of the second identification subunit is connected to the main control chip; the second identification subunit is used to output a second identification signal according to the magnetic switch signal;

[0013] The main control chip is used to determine the abnormality of the magnetic switch according to the first identification signal or the second identification signal.

[0014] In one embodiment, the main control chip is used to determine that the magnetic switch is abnormal when the first identification signal or the second identification signal is at a first level.

[0015] In one embodiment, the magnetic switch signal includes: a first magnetic switch signal, a second magnetic switch signal, and a third magnetic switch signal; the first identification subunit includes a first NOT gate, a second NOT gate, a third NOT gate, a first AND gate, a second AND gate, and a first diode;

[0016] The first end of the first NOT gate is used to receive the first magnetic switch signal, and the second end of the first NOT gate is connected to the first end of the first AND gate;

[0017] The first end of the second NOT gate is used to receive the second magnetic switch signal, the second end of the second NOT gate is connected to the second end of the first AND gate; the third end of the first AND gate is connected to the first end of the second AND gate;

[0018] The first end of the third NOT gate is used to receive the third magnetic switch signal, and the second end of the third NOT gate is connected to the second end of the second AND gate;

[0019] The third end of the second AND gate is connected to the main control chip, the third end of the second AND gate is connected to the wake-up pin of the main control chip through the first diode, and the third end of the second AND gate is used to output the first identification signal.

[0020] In one embodiment, the second identification subunit includes a third AND gate, a fourth AND gate, and a second diode;

[0021] The first end of the third AND gate is used to receive the first magnetic switch signal, the second end of the third AND gate is used to receive the second magnetic switch signal, and the third end of the third AND gate is connected to the first end of the fourth AND gate;

[0022] The second end of the fourth AND gate is used to access the third magnetic switch signal, the third end of the fourth AND gate is connected to the main control chip, the third end of the fourth AND gate is connected to the wake-up pin of the main control chip through the second diode, and the third end of the fourth AND gate is used to output the second identification signal.

[0023] In one embodiment, the magnetic switch signal includes: a first magnetic switch signal, a second magnetic switch signal, and a third magnetic switch signal, and the circle counting unit includes a fifth AND gate, a fourth NOT gate, a sixth AND gate, an XOR gate, and a third diode;

[0024] The first end of the fifth AND gate is used to access the first magnetic switch signal, the second end of the fifth AND gate is used to access the second magnetic switch signal through the fourth NOT gate, and the third end of the fifth AND gate is connected to the first end of the sixth AND gate;

[0025] The first end of the XOR gate is used to access the third magnetic switch signal, and the third end of the XOR gate is connected to the second end of the sixth AND gate;

[0026] The third end of the sixth AND gate is connected to the wake-up pin of the main control chip through the third diode, and the third end of the sixth AND gate is used to output the wake-up signal.

[0027] In one embodiment, the lap counting unit further includes a delay unit, a first end of the delay unit is used to receive the third magnetic switch signal, and a second end of the delay unit is connected to the second end of the XOR gate.

[0028] In one embodiment, the delay unit includes a first resistor and a first capacitor;

[0029] The first end of the first resistor is used to receive the third magnetic switch signal, and the second end of the first resistor is connected to the first end of the first capacitor and the second end of the XOR gate;

[0030] The second terminal of the first capacitor is grounded.

[0031] In a second aspect, an embodiment of the present application provides a method for identifying encoder bit errors, the method comprising:

[0032] acquiring an identification signal, and determining an abnormality of the magnetic switch based on the identification signal;

[0033] If the magnetic switch is normal, counting is performed based on the magnetic switch signal.

[0034] In one embodiment, the identification signal includes a first identification signal and a second identification signal, and obtaining the identification signal and determining an abnormality of the magnetic switch based on the identification signal specifically includes:

[0035] If the first identification signal is at the first level, it is determined that the magnetic switch is abnormal;

[0036] If the first identification signal is at the second level, then continue to determine whether the second identification signal is at the first level;

[0037] If the second identification signal is at the first level, it is determined that the magnetic switch is abnormal.

[0038] In a third aspect, an embodiment of the present application provides an encoder system, comprising an encoder and any of the above-mentioned encoder error recognition circuits;

[0039] The encoder is connected to the encoder error recognition circuit.

[0040] In one embodiment, the encoder includes a rotating shaft, an encoder code disk rotating along the axis of the rotating shaft, a magnetic member disposed on the rotating shaft, and three magnetic switches located within the magnetic field range of the magnetic member;

[0041] The magnetic switch is connected to the encoder error recognition circuit and is used to output a magnetic switch signal.

[0042] In one embodiment, the angle formed by the axis directions of two adjacent magnetic switches ranges from 60° to 120°.

[0043] In one embodiment, the angle formed by the axis directions of two adjacent magnetic switches is 120°.

[0044] The present application provides an encoder error recognition circuit, method, and encoder system, the circuit comprising: a signal input unit, a revolution counting unit, an error recognition unit, and a main control chip; the first end of the signal input unit is connected to the encoder, the second end of the signal input unit is connected to the first end of the revolution counting unit, the first end of the error recognition unit, and the main control chip; the second end of the revolution counting unit and the second end of the error recognition unit are connected to the main control chip; the signal input unit is used to receive a magnetic switch signal output by a magnetic switch in the encoder; wherein the magnetic switch signal is a Gray code; the revolution counting unit is used to output a wake-up signal based on the magnetic switch signal; the wake-up signal is used to wake up the main control chip; the error recognition unit is used to output an identification signal based on the magnetic switch signal; the main control chip is used to determine an abnormality of the magnetic switch based on the identification signal, and count based on the magnetic switch signal when the magnetic switch is normal. By adding the error recognition unit, the main control chip determines whether the magnetic switch is damaged based on the identification signal output by the error recognition unit, and counts based on the wake-up signal when the magnetic switch is normal, thereby avoiding errors in the number of revolutions caused by a damaged magnetic switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0046] Figure 1 A schematic structural diagram of a magnetic switch provided in one embodiment of the present application;

[0047] Figure 2 A schematic diagram of the structure of an encoder error recognition circuit provided in one embodiment of the present application;

[0048] Figure 3 A schematic structural diagram of an encoder error recognition circuit provided in another embodiment of the present application;

[0049] Figure 4 This is a signal waveform diagram when the rotating shaft is rotating forward provided in an embodiment of the present application;

[0050] Figure 5 This is a signal waveform diagram when the rotating shaft is reversed according to an embodiment of the present application;

[0051] Figure 6 This is a signal waveform diagram when the magnetic switch T2 provided in one embodiment of the present application is damaged;

[0052] Figure 7 This is a signal waveform diagram when the magnetic switch T2 provided in another embodiment of the present application is damaged;

[0053] Figure 8 This is a flowchart of an encoder error recognition method provided in one embodiment of the present application.

[0054] Reference numerals:

[0055] 210, signal input unit; 220, error code recognition unit; 230, lap counting unit; 240, main control chip; 221, first identification subunit; 222, second identification subunit; V1, first magnetic switch signal; V2, second magnetic switch signal; V3, third magnetic switch signal; U1, first NOT gate; U2, second NOT gate; U3, third NOT gate; U4, first AND gate; U5, second AND gate; U6, third AND gate; U7, fourth AND gate; U8, fourth NOT gate; U9, fifth AND gate; U10, sixth AND gate; U11, XOR gate; D1, first diode; D2, second diode; D3, third diode; R1, first resistor; C1, first capacitor.

[0056] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0057] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0058] First, let’s explain the terms involved in this application:

[0059] Gray code: refers to a special binary encoding method. Its characteristic is that there is only one binary bit difference between two adjacent code words. Due to the cyclic nature of Gray code, there is only one bit difference between the maximum and minimum numbers. Therefore, it is also called cyclic code or reflection code.

[0060] Multi-turn zero point: refers to the reference position that the encoder returns to after rotating multiple turns. This reference position is used to determine the starting position within each turn of the encoder, helping the system to accurately count and identify the corresponding position. In encoder applications, the multi-turn zero point is crucial because it provides a fixed reference point, ensuring a consistent benchmark for each measurement.

[0061] The prior art usually uses two magnetic switches to generate four groups of Gray code combinations (00-01-11-10). When each magnetic switch signal changes, they will wake up the main control chip to count the circles. Therefore, when the encoder rotates one circle, the main control chip will be woken up four times. However, if one of the magnetic switches is damaged, it may cause the main control chip to be woken up only once when the encoder rotates one circle. In this way, it is impossible to accurately judge the damage of the magnetic switch, resulting in errors in the calculation of the number of circles, which in turn affects the accuracy and reliability of the system. The encoder error recognition circuit provided in the present application adds an error recognition unit. The main control chip determines whether the magnetic switch is damaged based on the recognition signal output by the error recognition unit, and counts according to the wake-up signal when the magnetic switch is normal, thereby avoiding errors in the calculation of the number of circles caused by damage to the magnetic switch.

[0062] The following specific embodiments describe in detail the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0063] An embodiment of the present application provides an encoder system, including an encoder and an encoder error recognition circuit; wherein the encoder is connected to the encoder error recognition circuit.

[0064] In one embodiment, the encoder includes a rotating shaft, an encoder code disk rotating along the axis of the rotating shaft, a magnetic part arranged on the rotating shaft, and three magnetic switches located within the magnetic field range of the magnetic part; the magnetic switches are connected to the encoder error recognition circuit for outputting magnetic switch signals.

[0065] Specifically, if a single magnetic switch is used, the encoder can only output two states, 0 and 1, per rotation. If the magnetic switch is damaged, the magnetic switch signal remains high or low, and the system cannot detect a damaged magnetic switch. If two magnetic switches are used, the encoder outputs the combination 00-01-11-10 per rotation. If one of the magnetic switches is damaged and remains high, the encoder outputs the Gray code 10-00 per rotation. Analysis of the Gray code signal indicates no abnormality, and the 10-00 combination also occurs under normal circumstances, making the system unable to detect a damaged magnetic switch. If three magnetic switches are used, the encoder outputs the combination 001-101-100-110-010-011 per rotation. If the first magnetic switch is damaged and remains high, the encoder outputs 101-101-100-110-110-111 per rotation. The 110-111 combination is abnormal, indicating a damaged magnetic switch. The same applies to damaged magnetic switches. Using more than three magnetic switches increases costs and is not the best option. Therefore, this application uses three magnetic switches, which are only awakened once after the encoder rotates one revolution. Secondly, the encoder error detection circuit can use the characteristics of the three-digit Gray code to accurately identify magnetic switch damage.

[0066] In one embodiment, the angle formed by the axis directions of two adjacent magnetic switches ranges from 60° to 120°.

[0067] In one embodiment, the angle formed by the axis directions of two adjacent magnetic switches is 120°.

[0068] Specifically, if the axes of two adjacent magnetic switches form an angle of 120°, each magnetic switch will change state within a specific angular range during rotation (from 0 to 1 or vice versa), with each magnetic switch reaching its next state change position after 120° of rotation. The angular interval between the points where two adjacent magnetic switches change state simultaneously is 60°, and within each 60° angular interval, the Gray code combination remains unchanged. This distribution ensures that the mechanical angle range corresponding to each Gray code is relatively uniform. For example, when an object rotates to a certain position, the corresponding Gray code is 000. As the object rotates, this Gray code remains unchanged for the next 60° of rotation. This ensures that the mechanical angle range corresponding to each Gray code is clear during measurement or encoding, preventing confusion in code group correspondence due to uneven angle distribution. If the angle between the axes of two adjacent magnetic switches is not 120°, or if the angle is less than 120°, for example, less than 60°, the states of the adjacent switches may change rapidly within a very short angular range during rotation, causing some Gray code values ​​to remain constant for less than 60°. If the angle between the axes of two adjacent magnetic switches is greater than 120°, for example, greater than 180°, the angular range between the two magnetic switches may be excessively large, while the angular ranges in other areas may be too small. When the angle between the two magnetic switches is less than 60° or greater than 180°, the Gray code encoding pattern is disrupted, resulting in some Gray code combinations that should not exist or the absence of some Gray code combinations, which is a Gray code error. Therefore, the angle between the axes of two adjacent magnetic switches should be between 60° and 180°. When the angle between the axes of two adjacent magnetic switches is 120°, the accuracy of Gray code encoding and the uniformity of angle measurement can be guaranteed; secondly, the fault tolerance of the encoder is improved, thereby achieving the effect of waking up once the encoder rotates one circle.

[0069] like Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of the magnetic switch provided in one embodiment of the present application. The three magnetic switches in the encoder have an angle of 120° between the axis directions of two adjacent magnetic switches. This design ensures that when the encoder rotates, each switch can produce different states at different angles; secondly, it improves the fault tolerance of the encoder and realizes that the encoder is awakened only once per rotation. Since each magnetic switch has two states, open (high level) and closed (low level), the combination of the three switches can form 2 3= 8 possible states, but only six valid state combinations exist. When the encoder rotates one revolution, the three magnetic switches T1, T2, and T3 output magnetic switch signals of 001-101-100-110-010-011-011 or 001-011-010-110-100-101-001, respectively. This magnetic switch signal is Gray coded, ensuring that only one bit changes between adjacent states during encoder rotation. This reduces the possibility of errors and confusion, improving the encoder's accuracy and reliability.

[0070] If the encoder outputs a magnetic switch signal of 000, this means all magnetic switches are in a low-level state. This typically occurs when the encoder is not rotating or powered on. Therefore, this condition should not occur under normal operation. A state of 111, however, means all magnetic switches are in a high-level state. This condition should also not occur under normal operation, as encoders are designed to maintain state changes during rotation. If this condition occurs, the encoder may be faulty or malfunctioning.

[0071] V1, V2, and V3 represent magnetic switch signals. Which magnetic switch V1, V2, and V3 corresponds to depends on the multi-turn zero point selection. Table 1 shows the relationship between V1, V2, V3, magnetic switches T1, T2, and T3, and the multi-turn zero point. The multi-turn zero point selection is based on the reference position of the encoder for one rotation. For example, if 101-100 is selected as the multi-turn zero point, the number of turns increases by 1 when the Gray code changes from 101 to 100, and decreases by 1 when the Gray code changes from 100 to 101. In this case, V1 corresponds to T1, V2 corresponds to T2, and V3 corresponds to T3.

[0072] Table 1 Relationship between multi-turn zero position selection and magnetic switch and magnetic switch signal

[0073]

[0074] like Figure 2 As shown, Figure 2This is a structural diagram of an encoder error recognition circuit provided in an embodiment of the present application. The encoder error recognition circuit includes: a signal input unit 210, a circle counting unit 230, an error recognition unit 220 and a main control chip 240; the first end of the signal input unit 210 is connected to the encoder, and the second end of the signal input unit 210 is connected to the first end of the circle counting unit 230, the first end of the error recognition unit 220 and the main control chip 240; the second end of the circle counting unit 230 and the second end of the error recognition unit 220 are connected to the main control chip 240; the signal input unit 210 is used to receive a magnetic switch signal output by a magnetic switch in the encoder; wherein the magnetic switch signal is Gray code; the circle counting unit 230 is used to output a wake-up signal based on the magnetic switch signal; the wake-up signal is used to wake up the main control chip 240; the error recognition unit 220 is used to output an identification signal based on the magnetic switch signal; the main control chip 240 is used to determine the abnormality of the magnetic switch based on the identification signal, and count based on the magnetic switch signal when the magnetic switch is normal.

[0075] Specifically, the signal input unit 210 receives the signal output by the magnetic switch from the encoder, and the signal is transmitted in the form of Gray code; the circle counting unit 230 generates a wake-up signal based on the received magnetic switch signal, and the function of the wake-up signal is to activate the main control chip 240 for further processing; the error recognition unit 220 generates an identification signal based on the magnetic switch signal, and the identification signal is used to detect abnormal conditions in the magnetic switch signal, such as error or signal loss. Among them, the use of Gray code helps to reduce errors that may occur during the signal conversion process. The encoder error recognition circuit provided in this application can effectively identify and process error codes in the encoder signal, thereby improving the reliability of the system and avoiding errors in the calculation of the number of circles caused by damage to the magnetic switch.

[0076] In one embodiment, the output of the error recognition unit 220 is also connected to the wake-up pin of the main control chip 240. If the identification signal output by the error recognition unit 220 is high, the main control chip 240 can also be awakened. Because the main control chip 240 is awakened by both the lap counting unit 230 and the error recognition unit 220, after awakening, the main control chip 240 needs to determine whether the magnetic switch is abnormal based on the identification signal. If the magnetic switch is not abnormal, the main control chip 240 continues counting; if the magnetic switch is abnormal, the main control chip 240 stops counting.

[0077] In one embodiment, Figure 3 As shown, Figure 3This is a schematic diagram of the structure of an encoder error recognition circuit provided in another embodiment of the present application. The error recognition unit 220 includes: a first recognition subunit 221 and a second recognition subunit 222; the first end of the first recognition subunit 221 is connected to the signal input unit 210, and the second end of the first recognition subunit 221 is connected to the main control chip 240; the first recognition subunit 221 is used to output a first recognition signal based on the magnetic switch signal; the first end of the second recognition subunit 222 is connected to the signal input unit 210, and the second end of the second recognition subunit 222 is connected to the main control chip 240; the second recognition subunit 222 is used to output a second recognition signal based on the magnetic switch signal; the main control chip 240 is used to determine the abnormality of the magnetic switch based on the first recognition signal or the second recognition signal.

[0078] Specifically, the outputs of the first identification subunit 221 and the second identification subunit 222 are also connected to the wake-up pin of the main control chip 240. If the first identification signal and the second identification signal are at a high level, the main control chip 240 can also be awakened. Because the main control chip 240 is awakened by three sources: the lap counting unit 230, the first identification subunit 221, and the second identification subunit 222, after awakening, the main control chip 240 needs to determine whether the magnetic switch is abnormal based on the first identification signal or the second identification signal. If the magnetic switch is not abnormal, the main control chip 240 continues counting; if the magnetic switch is abnormal, the main control chip 240 stops counting.

[0079] In one embodiment, the main control chip 240 is configured to determine that the magnetic switch is abnormal when the first identification signal or the second identification signal is at a first level.

[0080] In one embodiment, the first level is a high level. After the main control chip 240 is awakened, it determines whether the first identification signal or the second identification signal is a high level. If the first identification signal or the second identification signal is a high level, it is determined that there is an abnormality in the magnetic switch of the encoder. Therefore, if the magnetic switch is abnormal, lap counting cannot be performed based on the wake-up signal received by the main control chip 240, thereby avoiding lap counting errors.

[0081] In one embodiment, see Figure 3The magnetic switch signal includes: a first magnetic switch signal V1, a second magnetic switch signal V2 and a third magnetic switch signal V3. The first identification sub-unit 221 includes a first NOT gate U1, a second NOT gate U2, a third NOT gate U3, a first AND gate U4, a second AND gate U5 and a first diode D1; the first end of the first NOT gate U1 is used to receive the first magnetic switch signal V1, and the second end of the first NOT gate U1 is connected to the first end of the first AND gate U4; the first end of the second NOT gate U2 is used to receive the second magnetic switch signal V2, and the second end of the second NOT gate U2 is connected to the second end of the first AND gate U4; the third end of the first AND gate U4 is connected to the first end of the second AND gate U5; the first end of the third NOT gate U3 is used to receive the third magnetic switch signal V3, and the second end of the third NOT gate U3 is connected to the second end of the second AND gate U5; the third end of the second AND gate U5 is connected to the main control chip 240, and the third end of the second AND gate U5 is connected to the wake-up pin of the main control chip 240 through the first diode D1. The third end of the second AND gate U5 is used to output the first identification signal.

[0082] Specifically, during normal operation of the encoder, assuming that magnetic switches T1, T2, and T3 are all in a normal state, the output signal is 101. In this state, the inputs of the second AND gate U5 are all low, so the output of the second AND gate U5 will also be low, causing the first identification signal to be output at a low level. If one of the magnetic switches fails, for example, the second magnetic switch signal V2 remains at a low level, the encoder state may change to a combination of 101, 100, 001, etc. At this time, the output of the first AND gate U4 will be high, and the second AND gate U5 will output a high level, indicating that there is a possible fault in the detection magnetic switch. The first identification signal will output a high level, and the main control chip 240 will be awakened.

[0083] In one embodiment, see Figure 3 The second identification subunit 222 includes a third AND gate U6, a fourth AND gate U7 and a second diode D2; the first end of the third AND gate U6 is used to access the first magnetic switch signal V1, the second end of the third AND gate U6 is used to access the second magnetic switch signal V2, and the third end of the third AND gate U6 is connected to the first end of the fourth AND gate U7; the second end of the fourth AND gate U7 is used to access the third magnetic switch signal V3, the third end of the fourth AND gate U7 is connected to the main control chip 240, the third end of the fourth AND gate U7 is connected to the wake-up pin of the main control chip 240 through the second diode D2, and the third end of the fourth AND gate U7 is used to output the second identification signal.

[0084] Specifically, when the encoder rotates normally, the Gray code output should not display abnormal states such as 000 or 111. If the system detects 111 or other abnormal combinations, it indicates that a magnetic switch is faulty. When the encoder state reaches 111, both inputs of the fourth AND gate U7 are low, causing the fourth AND gate U7 to output a high level, thereby generating a second identification signal. The second identification signal is input to the wake-up pin of the main control chip 240 through the second diode D2, waking the main control chip 240 and indicating a faulty magnetic switch.

[0085] In one embodiment, see Figure 3 The magnetic switch signal includes: a first magnetic switch signal V1, a second magnetic switch signal V2 and a third magnetic switch signal V3. The circle counting unit 230 includes a fifth AND gate U9, a fourth NOT gate U8, a sixth AND gate U10, an XOR gate U11 and a third diode D3; the first end of the fifth AND gate U9 is used to access the first magnetic switch signal V1, the second end of the fifth AND gate U9 is connected to the second magnetic switch signal V2 through the fourth NOT gate U8, and the third end of the fifth AND gate U9 is connected to the first end of the sixth AND gate U10; the first end of the XOR gate U11 is used to access the third magnetic switch signal V3, and the third end of the XOR gate U11 is connected to the second end of the sixth AND gate U10; the third end of the sixth AND gate U10 is connected to the wake-up pin of the main control chip 240 through the third diode D3, and the third end of the sixth AND gate U10 is used to output a wake-up signal.

[0086] In one embodiment, the lap counting unit 230 further includes a delay unit, a first end of the delay unit is used to receive the third magnetic switch signal V3, and a second end of the delay unit is connected to the second end of the XOR gate U11.

[0087] Specifically, in the circuit, when the third magnetic switch signal V3 transitions from a low level to a high level, this change affects the behavior of the delay unit. The first capacitor C1 begins charging, and the voltage gradually rises. However, due to the characteristics of the delay unit, this voltage rise is not instantaneous but rather occurs over a smooth process. The two inputs of the XOR gate U11 are affected by the first resistor R1 and the first capacitor C1. When the third magnetic switch signal V3 transitions from a low level to a high level, the charging process of the first capacitor C1 causes the input of the XOR gate U11 to briefly experience a combination of low and high levels. This state change is the operating principle of the XOR gate U11: when the two input levels are different, the output is high. Because the input of the XOR gate U11 briefly transitions between low and high levels, the XOR gate U11 outputs a brief high-level pulse. This means that even though the state of the third magnetic switch signal V3 has transitioned to a high level, the output of the XOR gate U11 is still affected by the change in its input state, resulting in a transient output signal. The two inputs of the sixth AND gate U10 receive the high-level pulse from the XOR gate U11. Because both inputs of the sixth AND gate U10 are also high when the XOR gate U11 outputs a high level, the sixth AND gate U10 outputs a brief high-level pulse. This is because the sixth AND gate U10 is an AND gate; when all inputs are high, its output is also high. The high-level pulse output by the sixth AND gate U10 is transmitted to the wake-up pin of the main control chip 240 through the third diode D3.

[0088] Specifically, the delay unit can make the circuit transition smoothly. The delay unit can smooth the changes in the input signal. When the state of the encoder changes, the charging and discharging process of the capacitor prevents the output signal from changing dramatically immediately. This smooth signal change helps reduce false triggering caused by transient noise, thereby improving the stability of the system. Secondly, the delay unit can also generate a pulse signal based on the magnetic switch signal to wake up the main control chip 240. Due to the delay characteristics of the RC delay unit, when the input signal (such as V3) changes from a low level to a high level, the delay unit will generate a short high-level pulse. This pulse signal is then used to wake up the main control chip 240 and put it into normal working state. This pulse generation mechanism ensures that the main control chip 240 is activated at the appropriate time, thereby saving power consumption and improving response efficiency.

[0089] The delay unit can also be used to reduce power consumption. During the rotation of the encoder, the main control chip 240 is only woken up when necessary. The RC delay unit significantly reduces the overall power consumption. In this way, the power consumed by the main control chip 240 in standby mode will be greatly reduced, thereby extending the service life of the battery; secondly, delay unit fault detection. The introduction of the RC delay unit helps to detect faults in a timely manner when the encoder state is abnormal. For example, when a magnetic switch fails and continuously outputs a fixed level, the RC delay unit can help the system identify this change and issue an alarm signal through subsequent logical processing. In other embodiments, the delay unit can also have other structures. In this example, the RC delay unit is used as an example for illustration.

[0090] In one embodiment, the delay unit includes a first resistor R1 and a first capacitor C1; the first end of the first resistor R1 is used to receive the third magnetic switch signal V3, the second end of the first resistor R1 is connected to the first end of the first capacitor C1 and the second end of the XOR gate U11; the second end of the first capacitor C1 is grounded.

[0091] Specifically, the delay unit can provide a certain delay when the input signal changes. The RC delay unit is realized by the charging and discharging process of the first capacitor C1, introducing a time constant This time constant determines the rate of change of the signal. For example, when the input signal changes, the first capacitor C1 does not react immediately, but instead generates a gradually changing voltage based on the resistance of the first resistor R1 and the capacitance of the first capacitor C1.

[0092] like Figure 4 As shown, Figure 4 This is a signal waveform diagram when the rotating shaft is rotating forwardly provided in an embodiment of the present application. Among them, forward rotation refers to counterclockwise rotation of the rotating shaft. When the magnetic switch is normal, the Gray code will not appear as 000 and 111, so the outputs of the second AND gate U5 and the fourth AND gate U7 are both low levels, that is, the first identification signal and the second identification signal are both low levels. When the Gray code changes from 100-110-010-011-001-101, the sixth AND gate U10 always outputs a low level, and the main control chip 240 is not awakened. When the Gray code changes from 101 to 100, the inputs of the fifth AND gate U9 are all high levels, so the fifth AND gate U9 outputs a high level. When the third magnetic switch signal V3 changes from a high level to a low level, due to the delay unit composed of the first resistor R1 and the first capacitor C1, the two inputs of the XOR gate U11 have a short high level and a low level, and the XOR gate U11 outputs a short high level. At this time, both inputs of the sixth AND gate U10 are briefly high, so the sixth AND gate U10 outputs a brief high-level pulse, that is, a wake-up signal. The wake-up signal is input to the wake-up pin of the main control chip 240 through the third diode D3, and the main control chip 240 wakes up.

[0093] like Figure 5 As shown, Figure 5 This is a signal waveform diagram when the rotating shaft is reversed provided in one embodiment of the present application. When the magnetic switch is normal, the Gray code will not appear as 000 and 111, so the outputs of the second AND gate U5 and the fourth AND gate U7 are both low, that is, the first identification signal and the second identification signal are both low. When the Gray code changes from 101-001-011-010-110-100, the sixth AND gate U10 always outputs a low level, and the main control chip 240 is not awakened. When the Gray code changes from 100 to 101, the inputs of the fifth AND gate U9 are all high, so the fifth AND gate U9 outputs a high level. When the third magnetic switch signal V3 changes from a low level to a high level, due to the delay unit composed of the first resistor R1 and the first capacitor C1, the two inputs of the XOR gate U11 have a short low level and a high level, and the XOR gate U11 outputs a short high level. At this time, both inputs of the sixth AND gate U10 are briefly high, so the sixth AND gate U10 outputs a brief high-level pulse, that is, a wake-up signal. The wake-up signal is input to the wake-up pin of the main control chip 240 through the third diode D3, and the main control chip 240 wakes up.

[0094] The above is the logic of the encoder error recognition circuit when the magnetic switch is normal. Next, this application will use two examples to illustrate the logic of the encoder error recognition circuit when the magnetic switch is damaged.

[0095] like Figure 6 As shown, Figure 6 This is a signal waveform diagram when the magnetic switch T2 provided in one embodiment of the present application is damaged. When the second magnetic switch signal V2 remains high, the Gray code change sequence during forward rotation of the encoder is 001-101-100-000-001. In the case of 000, the first AND gate U4 outputs a high level. Both inputs of the second AND gate U5 are high, and the second AND gate U5 outputs a high level, i.e., the first identification signal, which is input to the wake-up pin of the main control chip 240 through the first diode D1, and the main control chip 240 is awakened. The current Gray code sequence is 101 to 100, and the inputs of the fifth AND gate U9 are both high. Therefore, the fifth AND gate U9 outputs a high level. When the third magnetic switch signal V3 changes from a high level to a low level, due to the delay unit composed of the first resistor R1 and the first capacitor C1, the two inputs of the XOR gate U11 have a short period of high and low levels, and the XOR gate U11 outputs a short period of high level. At this time, both inputs of the sixth AND gate U10 are briefly high, so the sixth AND gate U10 outputs a brief high-level pulse, that is, a wake-up signal. The wake-up signal is input to the wake-up pin of the main control chip 240 through the third diode D3, and the main control chip 240 wakes up.

[0096] like Figure 7 As shown, Figure 7 This is a signal waveform diagram when the magnetic switch T2 is damaged, according to another embodiment of the present application. When the second magnetic switch signal V2 remains high, the encoder's Gray code sequence for forward rotation is 011-111-110-010-011. If the number 111 is present, the third AND gate U6 outputs a high level. If both inputs to the fourth AND gate U7 are high, the fourth AND gate U7 outputs a high level, representing the second identification signal. This signal is then fed through the second diode D2 to the wake-up pin of the main control chip 240, waking the main control chip 240.

[0097] like Figure 8 As shown, Figure 8 This is a flowchart of an encoder error recognition method provided in one embodiment of the present application. The encoder error recognition method includes the following steps:

[0098] Step S801: Acquire an identification signal, and determine an abnormality of the magnetic switch based on the identification signal.

[0099] Step S802: If the magnetic switch is normal, count based on the magnetic switch signal.

[0100] Specifically, this application determines whether the magnetic switch is abnormal based on the identification signal. If the magnetic switch is abnormal, no counting is performed; if the magnetic switch is normal, counting is performed based on the magnetic switch signal. If 101-100 is selected as the multi-turn zero point, that is, when the Gray code changes from 101 to 100, the number of turns increases by 1, and when the Gray code changes from 100 to 101, the number of turns decreases by 1. If the multi-turn zero point is selected elsewhere, counting is performed according to the counting logic described above.

[0101] In one embodiment, the identification signal includes a first identification signal and a second identification signal, and obtaining the identification signal and determining an abnormality of the magnetic switch based on the identification signal specifically includes the following steps:

[0102] If the first identification signal is at the first level, it is determined that the magnetic switch is abnormal.

[0103] If the first identification signal is at the second level, it is determined whether the second identification signal is at the first level.

[0104] If the second identification signal is at the first level, it is determined that the magnetic switch is abnormal.

[0105] Specifically, the present application determines the logic of magnetic switch abnormality based on the first identification signal and the second identification signal. Please refer to the above and will not elaborate on it here.

[0106] In one embodiment, the main control chip 240 can be a micro central control chip or system-on-chip chip such as MCU, DSP, MPU, micro CPU, etc. that can process digital signals, analog signals, or perform signal control functions, instruction processing and calculation functions.

[0107] In the above embodiments, it should be understood that the main control chip 240 can be a central processing unit (CPU), or other general-purpose main control chip 240, a digital signal processor (DSP), or an application-specific integrated circuit (ASIC). The general-purpose main control chip 240 can be a micro main control chip 240, or any conventional main control chip 240. The steps of the method disclosed in the present invention can be directly implemented by the hardware main control chip 240, or can be implemented by a combination of hardware and software modules in the main control chip 240.

[0108] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage.

[0109] A bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Buses can be categorized as address buses, data buses, and control buses. For ease of illustration, the buses in the drawings of this application are not limited to just one bus or just one type of bus.

[0110] The readable storage medium may be implemented by any type of volatile or non-volatile memory device, or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium may be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0111] An exemplary readable storage medium is coupled to a processor so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be an integral part of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (ASIC). Of course, the processor and the readable storage medium can also exist in the device as discrete components.

[0112] The division of units is merely a logical functional division; actual implementations may employ alternative divisions, such as combining or integrating multiple units or components into another system, or omitting or disabling certain features. Furthermore, any direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between devices or units, either through an interface, electrical, mechanical, or other means.

[0113] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0114] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0115] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the method of the present invention. The aforementioned storage medium includes various media that can store program code, such as USB flash drives, mobile hard drives, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical disks.

[0116] Those skilled in the art will appreciate that all or part of the steps in the above-described method embodiments can be implemented using hardware associated with program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0117] Finally, it should be noted that those skilled in the art will readily identify other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the present invention and include common knowledge or customary techniques in the art not disclosed herein. The present invention is not limited to the precise structure described above and illustrated in the accompanying drawings, and various modifications and variations may be made without departing from the scope thereof. The scope of the present invention is limited solely by the appended claims.

Claims

1. An encoder error recognition circuit, characterized in that: include: A signal input unit, a lap counting unit, an error code recognition unit, and a main control chip; the first end of the signal input unit is connected to the encoder, the second end of the signal input unit is connected to the first end of the lap counting unit, the first end of the error code recognition unit, and the main control chip; the second end of the lap counting unit and the second end of the error code recognition unit are connected to the main control chip; The signal input unit is used to receive a magnetic switch signal output by a magnetic switch in the encoder; wherein the magnetic switch signal is a Gray code; The lap counting unit is used to output a wake-up signal based on the magnetic switch signal; the wake-up signal is used to wake up the main control chip; The error code identification unit is configured to output an identification signal based on the magnetic switch signal; The main control chip is used to determine the abnormality of the magnetic switch based on the identification signal, and to count based on the magnetic switch signal when the magnetic switch is normal.

2. The circuit according to claim 1, wherein: The error code identification unit includes: a first identification subunit and a second identification subunit; The first end of the first identification subunit is connected to the signal input unit, and the second end of the first identification subunit is connected to the main control chip; the first identification subunit is used to output a first identification signal according to the magnetic switch signal; The first end of the second identification subunit is connected to the signal input unit, and the second end of the second identification subunit is connected to the main control chip; the second identification subunit is used to output a second identification signal according to the magnetic switch signal; The main control chip is used to determine an abnormality of the magnetic switch according to the first identification signal or the second identification signal.

3. The circuit according to claim 2, characterized in that The main control chip is used to determine that the magnetic switch is abnormal when the first identification signal or the second identification signal is at a first level.

4. The circuit according to claim 3, wherein the magnetic switch signal comprises: a first magnetic switch signal, a second magnetic switch signal, and a third magnetic switch signal, wherein the first identification subunit includes a first NOT gate, a second NOT gate, a third NOT gate, a first AND gate, a second AND gate, and a first diode; The first end of the first NOT gate is used to receive the first magnetic switch signal, and the second end of the first NOT gate is connected to the first end of the first AND gate; The first end of the second NOT gate is used to receive the second magnetic switch signal, the second end of the second NOT gate is connected to the second end of the first AND gate; the third end of the first AND gate is connected to the first end of the second AND gate; The first end of the third NOT gate is used to receive the third magnetic switch signal, and the second end of the third NOT gate is connected to the second end of the second AND gate; The third end of the second AND gate is connected to the main control chip, the third end of the second AND gate is connected to the wake-up pin of the main control chip through the first diode, and the third end of the second AND gate is used to output the first identification signal.

5. The circuit according to claim 4, characterized in that The second identification subunit includes a third AND gate, a fourth AND gate and a second diode; The first end of the third AND gate is used to access the first magnetic switch signal, the second end of the third AND gate is used to access the second magnetic switch signal, and the third end of the third AND gate is connected to the first end of the fourth AND gate; The second end of the fourth AND gate is used to access the third magnetic switch signal, the third end of the fourth AND gate is connected to the main control chip, the third end of the fourth AND gate is connected to the wake-up pin of the main control chip through the second diode, and the third end of the fourth AND gate is used to output the second identification signal.

6. The circuit according to claim 1, wherein the magnetic switch signal comprises: a first magnetic switch signal, a second magnetic switch signal, and a third magnetic switch signal, wherein the circle counting unit includes a fifth AND gate, a fourth NOT gate, a sixth AND gate, an XOR gate, and a third diode; The first end of the fifth AND gate is used to receive the first magnetic switch signal, the second end of the fifth AND gate is used to receive the second magnetic switch signal through the fourth NOT gate, and the third end of the fifth AND gate is connected to the first end of the sixth AND gate; The first end of the XOR gate is used to access the third magnetic switch signal, and the third end of the XOR gate is connected to the second end of the sixth AND gate; The third end of the sixth AND gate is connected to the wake-up pin of the main control chip through the third diode, and the third end of the sixth AND gate is used to output the wake-up signal.

7. The circuit according to claim 6, characterized in that The lap counting unit further includes a delay unit, a first end of the delay unit is used to receive the third magnetic switch signal, and a second end of the delay unit is connected to the second end of the XOR gate.

8. The circuit according to claim 7, characterized in that The delay unit includes a first resistor and a first capacitor; The first end of the first resistor is used to receive the third magnetic switch signal, and the second end of the first resistor is connected to the first end of the first capacitor and the second end of the XOR gate; The second terminal of the first capacitor is grounded.

9. A method for identifying code errors, characterized in that: The method comprises: acquiring an identification signal, and determining an abnormality of the magnetic switch based on the identification signal; If the magnetic switch is normal, counting is performed based on the magnetic switch signal.

10. The method according to claim 9, wherein the identification signal comprises a first identification signal and a second identification signal, wherein: The acquiring of the identification signal and determining the abnormality of the magnetic switch based on the identification signal specifically includes: If the first identification signal is at a first level, determining that the magnetic switch is abnormal; If the first identification signal is at the second level, then continue to determine whether the second identification signal is at the first level; If the second identification signal is at the first level, it is determined that the magnetic switch is abnormal.

11. An encoder system, characterized in that comprising an encoder and an encoder error recognition circuit according to any one of claims 1 to 8; Wherein, the encoder is connected to the encoder error recognition circuit.

12. The encoder system according to claim 11, characterized in that The encoder includes a rotating shaft, an encoder code disk rotating along the axis of the rotating shaft, a magnetic member arranged on the rotating shaft, and three magnetic switches located within the magnetic field range of the magnetic member; The magnetic switch is connected to the encoder error recognition circuit and is used to output a magnetic switch signal.

13. The encoder system according to claim 12, characterized in that The angle formed by the axis directions of two adjacent magnetic switches ranges from 60° to 120°.

14. The encoder system according to claim 13, wherein: The angle formed by the axis directions of two adjacent magnetic switches is 120°.

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