High-temperature-resistant piezoresistive pressure sensor chip and processing method

Abstract

The invention relates to the technical field of pressure sensors, in particular to a high-temperature-resistant piezoresistive pressure sensor chip and a processing method.The high-temperature-resistant piezoresistive pressure sensor chip comprises a device layer, a buried oxide layer, a supporting layer and a sealing substrate layer, and the buried oxide layer and the device layer are sequentially arranged on the supporting layer; wherein the device layer comprises a piezoresistor and a wire, the piezoresistor and the wire are arranged on the buried oxide layer, and a metal bonding pad is arranged on the wire; the piezoresistor and the wire are made of a P-type silicon material or an N-type silicon material of which the doping concentration is greater than 1014 cm <-3 >; wherein the sealing substrate layer is connected with the device layer and a reference pressure cavity is formed between the sealing substrate layer and the device layer, or the sealing substrate layer is connected with one side, deviating from the device layer, of the supporting layer and a reference pressure cavity is formed between the sealing substrate layer and the supporting layer. According to the invention, the processing efficiency of the high-temperature-resistant piezoresistive pressure sensor chip is improved, and the electrical stability of the chip in a high-temperature environment is improved at the same time.

Description

Technical Field

[0001] The present invention relates to the technical field of pressure sensors, and in particular to a high-temperature resistant piezoresistive pressure sensor chip and a processing method thereof. Background Art

[0002] High-temperature pressure sensors are devices capable of accurately measuring pressure parameters in environments exceeding 200°C. As industrial technology evolves toward high-temperature, high-precision pressure measurement, these sensors are becoming increasingly important in sectors such as aerospace, energy, chemical engineering, and nuclear power. High-temperature pressure sensors are the "nerve endings" connecting high-temperature environments to digital control systems, and their technological advancements directly impact the reliability, energy efficiency, and safety of industrial equipment.

[0003] Early pressure sensors were primarily based on the silicon-based piezoresistive effect. However, the narrow bandgap of silicon material means that when temperatures exceed 150°C, silicon-based sensors can suffer signal distortion or even failure due to intrinsic carrier excitation. To overcome this limitation, wide-bandgap semiconductor materials such as silicon carbide, sapphire, and aluminum nitride have been used to manufacture high-temperature pressure sensors. However, processing technology and cost constraints have prevented mass production of high-temperature pressure sensor chips. The maturation of silicon-on-insulator technology has further promoted the development of high-temperature pressure sensors.

[0004] However, in the existing ion implantation and thermal diffusion method for fabricating high-temperature pressure sensors, the core ion implantation process includes multiple micromachining processes, such as photolithography, mask overlay, etching, and annealing. This additional processing step, combined with the overlapping of multiple micromachining steps—such as photolithography, etching, ion implantation, and annealing—can introduce process errors at each step. The greater the number of process steps, the lower the overall device yield, leading to lower production efficiency and increased costs. Furthermore, the complex process requires stricter environmental control (such as cleanliness, temperature, and humidity), further increasing production costs and reducing the efficiency of high-temperature pressure sensor fabrication. Furthermore, high-temperature pressure sensor chips fabricated using conventional ion implantation suffer from poor ion distribution uniformity and low activation rates of the doped elements, resulting in poor piezoresistive fabrication consistency. Furthermore, because conventional methods employ a step-by-step ion doping process—for example, phosphorus followed by boron in P-type piezoresistors—donor and acceptor impurities can compensate for each other, leading to unstable carrier concentrations. Especially at high temperatures, the varying degrees of ionization between the two impurities and the carriers they carry can lead to significant resistivity variations. Therefore, the high-temperature pressure-resistant chip prepared by the existing method has poor electrical stability in a high-temperature environment.

[0005] Therefore, it is necessary to provide a high-temperature resistant piezoresistive pressure sensor chip and a processing method to solve the above problems. Summary of the Invention

[0006] The present invention provides a high-temperature resistant piezoresistive pressure sensor chip and a processing method thereof to solve the existing problems.

[0007] A first aspect of the present invention provides a high-temperature resistant piezoresistive pressure sensor chip adopting the following technical solution, including: a support layer, on which a buried oxide layer and a device layer are sequentially arranged; The device layer includes: piezoresistors and wires, with metal pads provided on the wires; the piezoresistors and wires are doped with a concentration greater than 10 14 cm -3 P-type silicon material or N-type silicon material; and a sealing base layer, wherein the sealing base layer is connected to the device layer and a reference pressure cavity is formed therebetween, or the sealing base layer is connected to a side of the support layer away from the device layer and a reference pressure cavity is formed therebetween.

[0008] A further technical solution of the present invention is that the supporting layer includes: a silicon substrate, an annular cavity is provided on the side of the silicon substrate facing away from the buried oxide layer, a boss is formed inside the annular cavity, and a silicon thin film is formed between the inner bottom surface of the annular cavity and the surface of the buried oxide layer connecting to the supporting layer.

[0009] According to a further technical solution of the present invention, the thickness of the silicon film is greater than twice the thickness of the buried oxide layer.

[0010] According to a further technical solution of the present invention, the center line of the piezoresistor of the device layer and the cavity wall of the annular cavity on the support layer are collinear.

[0011] According to a further technical solution of the present invention, the device layer has a thickness of 0.2 μm to 10 μm, the buried oxide layer has a thickness of 0.2 to 5 μm, and the support layer has a thickness of 200 μm to 1000 μm.

[0012] A further technical solution of the present invention is that the sealing base layer includes a glass substrate, a cavity is opened on the glass substrate, the cavity side of the glass substrate is connected to the device layer to form a reference pressure cavity, or the cavity side of the glass substrate is connected to the side of the support layer facing away from the device layer to form a reference pressure cavity, wherein the depth of the cavity on the sealing base layer is greater than 50 μm.

[0013] A second aspect of the present invention provides a method for processing a high-temperature resistant piezoresistive pressure sensor chip, comprising: The in-situ doping method is used to form a P-type silicon wafer or an N-type silicon wafer with a set doping concentration; the set doping concentration is greater than 10 14 cm -3; and using an N-type silicon wafer or a P-type silicon wafer as a wafer corresponding to the device layer; using silicon and silicon oxide to make a wafer corresponding to the support layer; dry-oxidizing the wafer corresponding to the support layer to form a wafer corresponding to the buried oxide layer on the wafer corresponding to the support layer; bonding the side of the wafer corresponding to the buried oxide layer away from the support layer to the wafer corresponding to the device layer to obtain an SOI wafer; Processing piezoresistors and wires on the surface of the wafer corresponding to the device layer in the SOI wafer; A ring-shaped cavity is machined on the surface of the SOI wafer corresponding to the support layer and facing away from the conductive wire to form a boss; sputtering connection metal on the conductive lines of the device layer to form metal pads; A cavity is processed on a glass substrate of a sealing base layer, and the surface where the cavity of the glass substrate is located is bonded to the surface where the annular cavity of the SOI wafer is located to form a pressure sensor chip.

[0014] According to a further technical solution of the present invention, the steps of sputtering connecting metal on the wire to form a metal pad are as follows: Cr, Pt and Au materials are sequentially sputtered on the wire to form a metal pad; Alternatively, Cr, TiN and Au materials are sequentially sputtered on the conductive line to form a metal pad.

[0015] A further technical solution of the present invention is characterized in that piezoresistors and wires are processed on the upper surface of the SOI wafer by dry etching or wet etching, wherein the thickness of the piezoresistors and wires is the thickness of the wafer corresponding to the device layer.

[0016] A third aspect of the present invention provides another method for processing a high-temperature resistant piezoresistive pressure sensor chip, comprising: The in-situ doping method is used to form a P-type silicon wafer or an N-type silicon wafer with a set doping concentration; the set doping concentration is greater than 10 14 cm -3 ; and using an N-type silicon wafer or a P-type silicon wafer as a wafer corresponding to the device layer; using silicon and silicon oxide to make a wafer corresponding to the support layer; dry-oxidizing the wafer corresponding to the support layer to form a wafer corresponding to the buried oxide layer on the wafer corresponding to the support layer; bonding the side of the wafer corresponding to the buried oxide layer away from the support layer to the wafer corresponding to the device layer to obtain an SOI wafer; Processing piezoresistors and wires on the surface of the wafer corresponding to the device layer in the SOI wafer; A ring-shaped cavity is machined on the surface of the SOI wafer corresponding to the support layer and facing away from the conductive wire to form a boss; Processing a cavity on the glass substrate of the sealing base layer, bonding the cavity surface of the glass substrate to the piezoresistor surface of the SOI wafer, and providing a through hole for connecting the wires on the glass substrate; Connecting metal is sputtered on the inner wall of the through hole and the wire to form a metal pad to obtain a pressure sensor chip.

[0017] The beneficial effects of the present invention are: By designing the device layer and using P-type silicon material or N-type silicon material with a set doping concentration, that is, by using in-situ doping technology during silicon growth to improve the lattice integrity, uniformity of doping distribution and low defect state density, the carrier concentration in the piezoresistor is relatively stable at high temperature, thereby significantly improving the electrical stability of the piezoresistor at high temperature.

[0018] Secondly, in the processing method of the high-temperature resistant piezoresistive pressure sensor chip, an in-situ doping method is used to form a P-type silicon wafer or an N-type silicon wafer with a set doping concentration, and the P-type silicon wafer or the N-type silicon wafer is used as the wafer of the device layer, and the piezoresistor and the wire are processed on the wafer of the device layer. The processing method of the present invention only requires two processing steps: preparing the wafer of the device layer by in-situ doping technology and etching the piezoresistor and the wire on the wafer of the device layer. The wires and piezoresistors prepared by the traditional ion implantation and thermal diffusion process are usually phosphorus first and then boron. The donor and acceptor impurities in the piezoresistor will compensate each other, resulting in unstable carrier concentration, especially in a high temperature environment. The ionization degree between the two impurities and the carriers they carry is different, resulting in a large change in resistivity. The in-situ doping method proposed by the present invention only uses a single phosphorus or boron element. In the case of single element doping, there is no such compensation effect. The carrier concentration is mainly determined by the concentration of a single impurity, which improves the lattice integrity, the uniformity of the doping distribution and reduces the low defect state density of the crystal, significantly improving the electrical stability of the piezoresistor at high temperature. In addition, the patent of this invention uses in-situ doping technology and etching technology to replace ion implantation and thermal diffusion technology, avoiding the associated multiple process steps of photolithography, corrosion, ion implantation, and annealing, reducing the cumulative process error, thereby improving the processing efficiency of the high-temperature resistant piezoresistive pressure sensor chip, and at the same time improving the electrical stability of the chip in a high-temperature environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 Schematic diagram of the structure of an SOI wafer of a high-temperature resistant piezoresistive pressure sensor chip in an embodiment of the present invention; Figure 2 For Figure 1Schematic diagram of the structure of the piezoresistor and the wire processed on the SOI wafer; Figure 3 Schematic diagram of the overall structure of a high-temperature resistant piezoresistive pressure sensor chip in an embodiment of the present invention; Figure 4 This is a schematic flow chart of Example 1 of a method for processing a high-temperature resistant piezoresistive pressure sensor chip according to the present invention; Figure 5 This is a schematic flow chart of Example 2 of a method for processing a high-temperature resistant piezoresistive pressure sensor chip according to the present invention; Figure 6 This is a graph showing the bottom noise output of a high-temperature piezoresistive pressure sensor chip manufactured in accordance with an embodiment of the present invention at a high temperature of 200°C; Figure 7 This is a graph showing the bottom noise output of a high-temperature piezoresistive pressure sensor chip prepared using the existing ion implantation process at 200°C.

[0021] In the figure: 1. device layer; 2. buried oxide layer; 3. support layer; 4. wire; 5. piezoresistor; 6. silicon substrate; 7. boss; 8. metal pad; 9. cavity; 10. sealing substrate layer; 11. through hole. DETAILED DESCRIPTION

[0022] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0023] An embodiment of a high temperature resistant piezoresistive pressure sensor chip of the present invention is as follows Figure 1 、 Figure 2 and Figure 3 As shown, the sensor chip includes: a device layer 1, a buried oxide layer 2, a support layer 3 and a sealing base layer 10, and the buried oxide layer 2 and the device layer 1 are sequentially arranged on the support layer 3 to form a Figure 1 wherein a buried oxide layer 2 is provided on the support layer 3 to form a sensitive thin film layer, such as Figure 2 As shown, in this embodiment, the device layer 1 includes: a piezoresistor 5 and a wire 4, the piezoresistor 5 and the wire 4 are arranged on the buried oxide layer 2, and a metal pad 8 is arranged on the wire 4; the piezoresistor 5 and the wire 4 are doped with a concentration greater than or equal to 10 14 cm -3P-type silicon material or N-type silicon material; wherein the sealing base layer 10 and the support layer are connected on the side away from the device layer 1 and a reference pressure cavity is formed between the two, or the sealing base layer 10 and the device layer 1 are connected and a reference pressure cavity is formed between the two, such as Figure 3 As shown, in this embodiment, the sealing base layer 10 is connected to the side of the support layer facing away from the device layer 1, and a reference pressure cavity is formed between the two.

[0024] For example, Figure 2 As shown, in one specific embodiment, the support layer 3 includes a silicon substrate 6, with an annular cavity provided on the side of the silicon substrate 6 facing away from the buried oxide layer 2. A boss 7 is formed inside the annular cavity, and a silicon film is formed between the inner bottom surface of the annular cavity and the surface where the buried oxide layer 2 connects to the support layer 3. The silicon film has a thickness of 1 μm to 100 μm. The center line of the piezoresistor 5 of the device layer 1 is collinear with the cavity wall of the cavity 9 on the support layer 3. The thickness of the silicon film is greater than twice the thickness of the buried oxide layer 2. Specifically, in this embodiment, the thickness of the silicon film is three times the thickness of the buried oxide layer 2.

[0025] For example, in a specific embodiment, the thickness of the device layer 1 is 0.2 μm to 10 μm, the thickness of the buried oxide layer 2 is 0.2 μm to 5 μm, and the thickness of the support layer 3 is 200 μm to 1000 μm; the resistivity of the device layer 1 is less than or equal to 100 Ω·cm, and the resistivity of the support layer 3 is less than or equal to 100 Ω·cm.

[0026] For example, in a specific embodiment, the sealing substrate layer 10 includes a glass substrate, a cavity 9 is formed on the glass substrate, and the cavity side of the glass substrate is connected to the device layer 1 to form a reference pressure cavity, or the cavity side of the glass substrate and the side of the support layer facing away from the device layer 1 are connected to form a reference pressure cavity, wherein the depth of the cavity 9 on the sealing substrate layer 10 is 1 μm~100 μm.

[0027] The present invention provides a method for processing a high-temperature resistant piezoresistive pressure sensor chip according to embodiment 1, as shown in FIG. Figure 4 As shown, the processing method of Example 1 includes: S1, making SOI wafer; Specifically, a P-type silicon wafer or an N-type silicon wafer with a set doping concentration is formed by in-situ doping; the doping concentration is set to be greater than 10 14 cm -3 ; and an N-type silicon wafer or a P-type silicon wafer is used as the wafer corresponding to the device layer 1; silicon and silicon oxide are used to make a wafer corresponding to the support layer 3; the wafer corresponding to the support layer 3 is dry-oxidized to form a wafer corresponding to the buried oxide layer 2 on the wafer of the support layer 3; the side of the wafer corresponding to the buried oxide layer 2 facing away from the support layer 3 is bonded to the wafer corresponding to the device layer 1 to obtain the following Figure 1 The SOI wafer is shown.

[0028] For example, in a specific embodiment, an in-situ doping method is used to form a P-type silicon wafer with a set doping concentration; that is, in this embodiment, boron is used as a dopant to form a P-type silicon wafer.

[0029] For example, in a specific embodiment, the wafer corresponding to the support layer 3 is dry oxidized to form silicon oxide covering the wafer corresponding to the support layer 3, and the silicon oxide on the wafer corresponding to the support layer 3 is removed by a wet etching process, leaving only the silicon oxide on a surface as the wafer corresponding to the buried oxide layer 2.

[0030] For example, in a specific embodiment, the wafer thickness corresponding to the device layer 1 is smaller than the total wafer thickness of the support layer 3 and the buried oxide layer 2 .

[0031] S2, device layer etching; Specifically, piezoresistors and wires are processed on the surface of the wafer corresponding to the device layer.

[0032] For example, in a specific embodiment, the piezoresistor 5 and the wire 4 are processed on the upper surface of the SOI wafer by dry etching or wet etching, wherein the thickness of the piezoresistor 5 and the wire 4 is the wafer thickness corresponding to the device layer 1. Specifically, in this embodiment, dry etching is used to process the piezoresistor 5 and the wire 4 on the upper surface of the SOI wafer.

[0033] S3, supporting layer etching; Specifically, an annular cavity is processed on the surface of the wafer corresponding to the support layer 3 and facing away from the conductive wire 4 to form a boss.

[0034] For example, in a specific embodiment, an annular cavity is processed on the lower surface of the SOI wafer by dry etching or wet etching, a boss 7 is formed inside the annular cavity, and a silicon film is formed between the inner bottom surface of the annular cavity and the connection surface between the buried oxide layer 2 and the support layer 3.

[0035] S4, metal sputtering on the wire; Specifically, a connection metal is sputtered on the conductive line 4 of the device layer to form a metal pad 8 .

[0036] For example, in a specific embodiment, the step of sputtering connection metal on the wire 4 to form the metal pad 8 is: sequentially sputtering Cr, Pt, and Au materials on the wire 4 to form the metal pad 8; or sequentially sputtering Cr, TiN, and Au materials on the wire 4 to form the metal pad 8. In this embodiment, the metal pad 8 is formed by sequentially sputtering Cr, Pt, and Au materials on the wire 4.

[0037] S5, bonding support layer and sealing base layer; Specifically, a cavity 9 is processed on the glass substrate of the sealing base layer 10, and the surface of the glass substrate where the cavity 9 is located and the surface of the SOI wafer where the annular cavity is located are anodically bonded, that is, the cavity 9 of the glass substrate is sealed to realize the preparation of the reference pressure cavity and form a pressure sensor chip.

[0038] The present invention provides a second embodiment of a method for processing a high-temperature resistant piezoresistive pressure sensor chip, as shown in FIG. Figure 5 As shown, the processing method of Example 1 includes: S1, making SOI wafer; Specifically, a P-type silicon wafer or an N-type silicon wafer with a set doping concentration is formed by in-situ doping; the doping concentration is set to be greater than 10 14 cm -3 ; and use an N-type silicon wafer or a P-type silicon wafer as the wafer corresponding to the device layer 1; use silicon and silicon oxide to make a wafer corresponding to the support layer 3; dry-oxidize the wafer corresponding to the support layer 3 to form a wafer corresponding to the buried oxide layer 2 on the wafer of the support layer 3; bond the side of the wafer corresponding to the buried oxide layer 2 away from the support layer 3 to the wafer corresponding to the device layer 1 to obtain an SOI wafer.

[0039] For example, in a specific embodiment, an in-situ doping method is used to form a P-type silicon wafer with a set doping concentration; that is, in this embodiment, boron is used as a dopant to form a P-type silicon wafer.

[0040] For example, in a specific embodiment, the wafer corresponding to the support layer 3 is dry oxidized to form silicon oxide covering the wafer corresponding to the support layer 3, and the silicon oxide on the wafer corresponding to the support layer 3 is removed by a wet etching process, leaving only the silicon oxide on a surface as the wafer corresponding to the buried oxide layer.

[0041] S2, device layer etching; Specifically, piezoresistors and wires are processed on the surface of the wafer corresponding to the device layer.

[0042] For example, in a specific embodiment, the piezoresistor 5 and the wire 4 are processed on the upper surface of the SOI wafer by dry etching or wet etching, wherein the thickness of the piezoresistor 5 and the wire 4 is the wafer thickness corresponding to the device layer 1. Specifically, in this embodiment, dry etching is used to process the piezoresistor 5 and the wire 4 on the upper surface of the SOI wafer.

[0043] S3, supporting layer etching; Specifically, an annular cavity is processed on the surface of the wafer corresponding to the support layer 3 facing away from the conductive wire 4 to form a boss.

[0044] For example, in a specific embodiment, an annular cavity is processed on the lower surface of the SOI wafer by dry etching or wet etching, a boss 7 is formed inside the annular cavity, and a silicon film is formed between the inner bottom surface of the annular cavity and the connection surface between the buried oxide layer 2 and the support layer 3.

[0045] S4, bonding support layer and sealing base layer; Specifically, a cavity 9 is processed on the glass substrate of the sealing base layer 10, and the surface of the glass substrate where the cavity is located and the surface of the SOI wafer where the piezoresistor 5 is located are anodically bonded, that is, the cavity 9 of the glass substrate is sealed to realize the preparation of the reference pressure chamber, and a through hole 11 for connecting the wires is provided on the glass substrate.

[0046] S5, metal sputtering on the wire; Specifically, a connection metal is sputtered on the inner wall of the through hole 11 and the wire 4 to form a metal pad 8 to obtain a pressure sensor chip.

[0047] For example, in a specific embodiment, the steps of sputtering connecting metal on the wire 4 to form the metal pad are: sequentially sputtering Cr, Pt, and Au materials on the wire 4 to form the metal pad 8; or sequentially sputtering Cr, TiN, and Au materials on the wire 4 to form the metal pad 8. In this embodiment, the metal pad 8 is formed by sequentially sputtering Cr, TiN, and Au materials on the wire 4. Specifically, in this embodiment, photoresist protection is first performed on the etched device layer 1, and the position of the wire 4 where the connecting metal needs to be sputtered is developed. Cr, TiN, and Au materials are sequentially sputtered on the exposed area by sputtering or evaporation to form the metal pad 8. Finally, ohmic contact is achieved between the metal pad 8 and the semiconductor silicon wire 4 by a rapid annealing or conventional annealing process.

[0048] It should be noted that, in the process of processing the cavity 9 on the glass substrate of the sealing base layer 10 in step S5 of Example 1 and step S4 of Example 2, a cavity 9 with a depth of 1 to 100 μm is formed on the glass substrate by laser etching, yarn spray etching or wet etching. In the bonding process of step S5 of Example 1 or step S4 of Example 2, this cavity 9 corresponds to the annular cavity of the support layer 3. After standard RCA cleaning and then oxygen cleaning are performed on the etched glass substrate, anode bonding is performed after the cavity 9 is aligned with the annular cavity of the support layer 3.

[0049] Secondly, in step S2 of Example 1 and Example 2, all excess silicon wafers from the wafer of the device layer 1 to the surface of the buried oxide layer 2 are etched away by top-layer etching until the remaining silicon wafer is etched into a resistor with a set resistance value and a wire 4 connecting the resistor. The resistor is directly used as the piezoresistor 5 of the pressure sensor chip to measure pressure, and there is no need to perform ion implantation or ion diffusion process again. At the same time, it also avoids the multi-step auxiliary process of processing, etching and annealing of the shielding layer twice in the prior art.

[0050] Among them, according to the carrier migration theory of solid semiconductors, it can be known that the phonon vibration of the piezoresistor 5 is intensified at high temperatures, and the scattering probability increases, resulting in a decrease in the carrier mobility in the piezoresistor 5. Therefore, the corresponding resistance of the piezoresistor 5 gradually increases with increasing temperature. The existing ion implantation technology introduces lattice defects due to high-energy ion bombardment, and the scattering centers increase. Mutual compensation occurs between the donor and acceptor impurities, resulting in unstable carrier concentration. Especially in a high-temperature environment, the degree of ionization between the two impurities and the carriers they carry is different, resulting in a large change in resistivity. The doping source of in-situ doping is evenly integrated into the lattice during the material growth process, with fewer defects and weaker lattice scattering. The mobility decays more slowly at high temperatures, and there is no mutual compensation between the donor and acceptor impurities, resulting in a more stable carrier concentration, so the resistance change is smaller. Therefore, the piezoresistor prepared by in-situ doping and dry etching methods will have better electrical stability at high temperatures.

[0051] The present invention is further described below with reference to specific simulation data: First, a high-temperature resistant pressure sensor chip was designed. To prepare the high-temperature resistant pressure sensor chip, the silicon-on-insulator device layer 1 was designed to have a thickness of 2 μm, a resistivity of 0.05 Ω·cm, and an in-situ boron doping concentration of 2×10 19 cm -3 The thickness of the intermediate buried oxide layer 2 is 2 μm, the thickness of the support layer 3 is 400 μm, and the resistivity is 10 Ω·cm.

[0052] The device layer 1 is dry-etched to a depth of 2μm down to the buried oxide layer 2, removing excess material from the device layer 1, leaving only the piezoresistor 5 and the conductor 4. The 380μm thick material of the support layer 3 is also dry-etched to form an annular cavity. The thickness of the silicon film between the inner bottom of the annular cavity and the contact surface between the buried oxide layer 2 and the support layer 3 is 20μm. The 20μm silicon film and the 2μm buried oxide layer 2 form a multi-layer composite high-temperature resistant pressure-sensitive film, which is 22μm thick. Subsequently, a multilayer metal sputtering of Cr, Pt, and Aμ is sequentially performed on the conductor 4, with sputtering thicknesses of 20nm, 100nm, and 200nm. After annealing at 400°C, a metal pad 8 is formed to establish an ohmic contact between the semiconductor conductor 4 and the metal pad 8. A 100μm deep cavity 9 is etched on a glass substrate using laser etching technology. After standard RCA cleaning and oxygen cleaning, the edge of the cavity 9 is aligned with the edge of the high-temperature resistant pressure sensitive film, and the support layer 3 and the sealing substrate layer 10 are vacuum anodic bonded to achieve the preparation of a 0kPa reference pressure cavity. The bottom noise results of the high-temperature pressure sensor chip prepared in this embodiment at a high temperature of 200°C are shown in Figure 6; the bottom noise results of the high-temperature pressure sensor chip prepared based on ion implantation at a high temperature of 200°C are shown in Figure 6. Figure 7 As shown, compared Figure 6 and Figure 7 ; The bottom noise output by the ion implantation sensor chip based on the existing technology at a high temperature of 200°C is 27μV, and the bottom noise output by the sensor chip based on in-situ doping at a high temperature of 200°C is 12μV, that is, the bottom noise of the present invention is significantly lower than that of the high-temperature resistant pressure sensor chip prepared by traditional ion implantation technology.

[0053] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A high temperature resistant piezoresistive pressure sensor chip, characterized in that: include: a support layer, on which a buried oxide layer and a device layer are sequentially arranged; The device layer includes: piezoresistors and wires, with metal pads provided on the wires; the piezoresistors and wires are doped with a concentration greater than 10 14 cm -3 P-type silicon material or N-type silicon material; and a sealing base layer, wherein the sealing base layer is connected to the device layer and a reference pressure cavity is formed therebetween, or the sealing base layer is connected to a side of the support layer away from the device layer and a reference pressure cavity is formed therebetween.

2. The high-temperature resistant piezoresistive pressure sensor chip according to claim 1, characterized in that: The support layer includes: The silicon substrate has an annular cavity on the side of the silicon substrate away from the buried oxide layer, a boss is formed inside the annular cavity, and a silicon film is formed between the inner bottom surface of the annular cavity and the surface of the buried oxide layer connected to the support layer.

3. The high temperature resistant piezoresistive pressure sensor chip according to claim 2, characterized in that: The thickness of the silicon film is greater than twice the thickness of the buried oxide layer.

4. The high-temperature resistant piezoresistive pressure sensor chip according to claim 2, characterized in that: The center line of the piezoresistor on the device layer and the cavity wall of the annular cavity on the support layer are collinear.

5. The high temperature resistant piezoresistive pressure sensor chip according to claim 2, characterized in that: The thickness of the device layer is 0.2μm~10μm, the thickness of the buried oxide layer is 0.2~5μm, and the thickness of the support layer is 200μm~1000μm.

6. The high temperature resistant piezoresistive pressure sensor chip according to claim 1, characterized in that: The sealing substrate layer includes a glass substrate with a cavity formed on the glass substrate. The cavity side of the glass substrate is connected to the device layer to form a reference pressure cavity, or the cavity side of the glass substrate is connected to the side of the support layer facing away from the device layer to form a reference pressure cavity. The depth of the cavity on the sealing substrate layer is 1~100μm.

7. A method for processing a high-temperature resistant piezoresistive pressure sensor chip, characterized in that: The steps of preparing the high-temperature resistant piezoresistive pressure sensor chip according to any one of claims 1 to 6 include: The in-situ doping method is used to form a P-type silicon wafer or an N-type silicon wafer with a set doping concentration; the set doping concentration is greater than 10 14 cm -3 ; and using an N-type silicon wafer or a P-type silicon wafer as a wafer corresponding to the device layer; using silicon and silicon oxide to make a wafer corresponding to the support layer; dry-oxidizing the wafer corresponding to the support layer to form a wafer corresponding to the buried oxide layer on the wafer corresponding to the support layer; bonding the side of the wafer corresponding to the buried oxide layer away from the support layer to the wafer corresponding to the device layer to obtain an SOI wafer; Processing piezoresistors and wires on the surface of the wafer corresponding to the device layer in the SOI wafer; A ring-shaped cavity is machined on the surface of the SOI wafer corresponding to the support layer and facing away from the conductive wire to form a boss; sputtering connection metal on the conductive lines of the device layer to form metal pads; A cavity is processed on a glass substrate of a sealing base layer, and the surface where the cavity of the glass substrate is located is bonded to the surface where the annular cavity of the SOI wafer is located to form a pressure sensor chip.

8. The method for processing a high-temperature resistant piezoresistive pressure sensor chip according to claim 7, characterized in that: The steps for sputtering connecting metal on the wire to form a metal pad are: Cr, Pt and Au materials are sequentially sputtered on the wire to form a metal pad; Alternatively, Cr, TiN and Au materials are sequentially sputtered on the conductive line to form a metal pad.

9. The method for processing a high-temperature resistant piezoresistive pressure sensor chip according to claim 7, characterized in that: Piezoresistors and wires are processed on the upper surface of the SOI wafer by dry etching or wet etching, wherein the thickness of the piezoresistors and wires is the thickness of the wafer corresponding to the device layer.

10. A method for processing a high-temperature resistant piezoresistive pressure sensor chip, characterized in that: The steps of preparing the high-temperature resistant piezoresistive pressure sensor chip according to any one of claims 1 to 6 include: The in-situ doping method is used to form a P-type silicon wafer or an N-type silicon wafer with a set doping concentration; the set doping concentration is greater than 10 14 cm -3 ; and using an N-type silicon wafer or a P-type silicon wafer as a wafer corresponding to the device layer; using silicon and silicon oxide to make a wafer corresponding to the support layer; dry-oxidizing the wafer corresponding to the support layer to form a wafer corresponding to the buried oxide layer on the wafer corresponding to the support layer; bonding the side of the wafer corresponding to the buried oxide layer away from the support layer to the wafer corresponding to the device layer to obtain an SOI wafer; Processing piezoresistors and wires on the surface of the wafer corresponding to the device layer in the SOI wafer; A ring-shaped cavity is machined on the surface of the SOI wafer corresponding to the support layer and facing away from the conductive wire to form a boss; Processing a cavity on the glass substrate of the sealing base layer, bonding the cavity surface of the glass substrate to the piezoresistor surface of the SOI wafer, and providing a through hole for connecting the wires on the glass substrate; Connecting metal is sputtered on the inner wall of the through hole and the wire to form a metal pad to obtain a pressure sensor chip.

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