Current detection circuit

Abstract

The invention discloses a current detection circuit for detecting current flowing through a power tube. The current detection circuit comprises a calibration tube, a sampling tube and a voltage regulation circuit. The current detection circuit works in a calibration stage and a sampling stage, in the calibration stage, the output end of the voltage adjusting circuit is coupled to the control end of the sampling tube, and the adjusting signal adjusts the voltage of the first end of the sampling tube to be equal to the voltage of the first end of the calibration tube. In the sampling stage, the output end of the voltage adjusting circuit is coupled to the first end of the sampling tube, and the adjusting signal adjusts the voltage of the first end of the sampling tube to be equal to the voltage of the first end of the power tube. According to the invention, the calibration tube is arranged to realize adaptive adjustment of the on-resistance of the sampling tube, so that the ratio of the on-resistance of the sampling tube to the on-resistance of the power tube is closer to a theoretical value, thereby realizing high-precision sampling of the current of the power tube.

Description

Technical Field

[0001] The present application relates to the technical field of circuit detection, and in particular to a current detection circuit. Background Art

[0002] In high-precision current detection applications, an op amp loop is usually used for current detection. The basic principle is to use an operational amplifier to clamp the drain voltage of the power tube and the sampling tube to the same level, and short-circuit the gate and source of the two. Therefore, the size ratio of the power tube and the sampling tube determines the ratio of the on-resistance between them, thereby controlling the scaling of the detection current and achieving proportional current detection.

[0003] In actual chips, power tubes are generally large in size and are composed of hundreds or even thousands of transistor units (fingers) connected in parallel. In order to reduce power consumption, the size of the sampling tube is generally smaller than the transistor unit of the power tube. Due to process, voltage, temperature and other reasons, the parameters of the transistor units of the power tube and the sampling tube may be inconsistent, especially the fluctuation of the on-resistance may be inconsistent, resulting in a large deviation in the current detection ratio. Simply setting the initial size of the sampling tube will subsequently cause the on-resistance of the power tube and the sampling tube to fluctuate inconsistently, resulting in a deviation in the current detection ratio.

[0004] Therefore, a high-precision current detection circuit is needed to reduce the current sampling error caused by process parameters. Summary of the Invention

[0005] The present application provides a current detection circuit, which aims to solve the problem in the prior art that the on-resistance of a sampling tube of a current detection circuit fluctuates, thereby affecting the current detection accuracy.

[0006] According to a first aspect of the present invention, the present invention provides a current detection circuit for detecting current flowing through a power tube, wherein the power tube includes a plurality of transistor units connected in parallel, and the current detection circuit includes:

[0007] A calibration tube having a first end, a second end and a control end, the calibration tube comprising at least one of the transistor units;

[0008] a sampling tube having a first end, a second end, and a control end; and

[0009] A voltage regulating circuit has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the voltage regulating circuit is coupled to the first terminal of the sampling tube, and the output terminal of the voltage regulating circuit outputs a regulating signal;

[0010] The current detection circuit operates in a calibration phase and a sampling phase. In the calibration phase, the second input terminal of the voltage regulation circuit is coupled to the first terminal of the calibration tube, the output terminal of the voltage regulation circuit is coupled to the control terminal of the sampling tube, and the regulation signal is adjusted so that the voltage of the first terminal of the sampling tube is equal to the voltage of the first terminal of the calibration tube;

[0011] During the sampling phase, the second input end of the voltage regulating circuit is coupled to the first end of the power tube, the output end of the voltage regulating circuit is coupled to the first end of the sampling tube, and the regulating signal regulates the voltage of the first end of the sampling tube to be equal to the voltage of the first end of the power tube.

[0012] The beneficial effect of the present application is as follows: the present application adjusts the voltage of the sampling tube during the calibration phase by setting a calibration tube and a voltage regulation circuit, thereby realizing adaptive adjustment of the on-resistance of the sampling tube, so that the ratio of the on-resistance of the sampling tube to the on-resistance of the power tube is closer to the theoretical value, thereby realizing that the sampling tube can accurately complete the current sampling of the power tube during the sampling phase in different application environments, thereby improving the current detection accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 This is a structural diagram of an existing current detection circuit;

[0015] Figure 2 A structural diagram of a current detection circuit according to an embodiment of the present application is provided;

[0016] Figure 3A The waveform diagrams of the switch control signals, the high-side control signal GH, and the low-side control signal GL in the current detection circuit according to an embodiment of the present application are provided;

[0017] Figure 3B Waveform diagrams of the switch control signals, the high-side control signal GH, and the low-side control signal GL in the current detection circuit according to an embodiment of the present application are provided.

[0018] Figure 4 A schematic diagram of the operation of the current detection circuit in the calibration phase according to an embodiment of the present application is provided;

[0019] Figure 5 A schematic diagram of the operation of the current detection circuit in the sampling phase according to an embodiment of the present application is provided. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "up", "down", "left", and "right", generally refer to the up, down, left, and right of the device in actual use or working state, specifically the drawing direction in the accompanying drawings.

[0021] In this application, unless otherwise specified or limited, terms such as "connected," "coupled to," and "stacked" should be interpreted broadly. For example, they may refer to fixed connections, detachable connections, or integration; they may refer to direct connections or indirect connections through an intermediate medium; they may refer to internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of these terms in this application based on specific circumstances.

[0022] Figure 1 This is a structural diagram of an existing current detection circuit. In the H-bridge low-side current detection circuit, the positive input terminal of the operational amplifier A4 is connected to the drain of the transistor MN3, and the negative input terminal of the operational amplifier A4 is connected to the drain of the transistor MN3. 15 The drain connection of the sampling transistor MN 15 The width-to-length ratio of the transistor MN15 is reduced by a certain multiple compared to that of the transistor MN3, and the current flowing through the transistor MN15 is used to represent the current flowing through the transistor MN3, thereby generating an induced current that is reduced by a certain multiple.

[0023] for Figure 1 The current detection circuit shown in the figure, the power tube MN3 includes multiple transistor units connected in parallel, the transistor MN 15 Determine its size according to the preset multiple. When the transistor MN 15 When the size of the transistor unit is smaller than that of the transistor MN 15 There will be a matching difference between the two transistors MN3, that is, the electrical parameters of the two transistors will be inconsistent due to process, voltage, and temperature, which will cause the current detection ratio to deviate and fail to meet the accuracy requirements of current detection.

[0024] The present application provides a current detection circuit, which is described in detail below. It should be noted that the order in which the following embodiments are described does not limit the preferred order of the embodiments of the present application. In the following embodiments, the description of each embodiment has its own emphasis. For parts not described in detail in one embodiment, please refer to the relevant description of other embodiments.

[0025] Figure 2 A schematic diagram of the structure of a current detection circuit 200 according to an embodiment of the present application is given. The current detection circuit 200 detects the current flowing through the low-side power transistor QL in the switch circuit 10. The current detection circuit 200 includes a calibration transistor MC, a sampling transistor MS, and a voltage regulation circuit 11. The calibration transistor MC has a first terminal, a second terminal, and a control terminal. Figure 2 In the embodiment shown, the control terminal of the calibration transistor MC is coupled to the bias voltage VDD2, and the second terminal of the calibration transistor MC is coupled to the reference ground GND. The sampling transistor MS has a first terminal, a second terminal, and a control terminal, wherein the second terminal is coupled to the reference ground GND. The voltage regulating circuit 11 has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the voltage regulating circuit 11 is coupled to the first terminal of the sampling transistor MS, and the output terminal outputs the regulating signal VR. Figure 2 In the illustrated embodiment, the voltage regulation circuit 11 includes an operational amplifier AMP and a regulating transistor M1. A first input terminal of the operational amplifier AMP is coupled to a first input terminal of the voltage regulation circuit 11. A second input terminal of the operational amplifier AMP is coupled to a second input terminal of the voltage regulation circuit 11. The operational amplifier AMP also has an output terminal. A control terminal of the regulating transistor M1 is coupled to the output terminal of the operational amplifier AMP. A first terminal of the regulating transistor M1 is coupled to a supply voltage VDD1. A second terminal of the regulating transistor M1 serves as an output terminal of the voltage regulation circuit 11. In one embodiment, the first terminal of the regulating transistor M1 can be coupled to the supply voltage VDD1 via, for example, a current mirror circuit. In one embodiment, the supply voltage VDD1 is equal to the bias voltage VDD2.

[0026] exist Figure 2In an embodiment, the power transistor QL includes multiple transistor units connected in parallel, and the calibration transistor MC includes at least one transistor unit, wherein the on-resistance of each transistor unit can maintain extremely high consistency. In one embodiment, the number of transistor units in the power transistor QL is K times the number of transistor units in the calibration transistor MC, that is, the ratio of the size of the power transistor QL to the calibration transistor MC is K:1, where K is a constant greater than 1. In one embodiment, the power transistor QL is composed of K transistor units connected in parallel, and the calibration transistor MC is composed of a single transistor unit. The length of the calibration transistor MC is the same as the length of the power transistor QL, and the width of the power transistor QL is K times the width of the calibration transistor MC. The value of K is determined according to the actual required ratio and ranges from 1 to 100,000. For example, the value of K can be 10, 100, 200, 1000, 2000, 5000, or 10,000.

[0027] exist Figure 2 In the illustrated embodiment, the current detection circuit 200 further includes a calibration capacitor C1 , a first terminal of which is coupled to the gate terminal of the sampling transistor MS and the output terminal of the voltage regulating circuit 11 , and a second terminal of the calibration capacitor C1 is coupled to the reference ground GND.

[0028] exist Figure 2 In the illustrated embodiment, the current detection circuit 200 further includes a first switch S1 and a second switch S2. A first end of the first switch S1 is coupled to a first end of the calibration transistor MC, and a second end of the first switch S1 is coupled to a second input end of the voltage regulator circuit 11. A first end of the second switch S2 is coupled to an output end of the voltage regulator circuit 11, and a second end of the second switch S2 is coupled to a control end of the sampling transistor MS and a first end of the calibration capacitor C1.

[0029] exist Figure 2 In the illustrated embodiment, the current detection circuit 200 further includes a freewheeling circuit 13 . The freewheeling circuit 13 is coupled to the output terminal of the voltage regulating circuit 11 via a fourth switch S4 .

[0030] exist Figure 2 In the illustrated embodiment, the current detection circuit 200 further includes a fifth switch S5 and a sixth switch S6. A first terminal of the fifth switch S5 is coupled to a first terminal of the power transistor QL, and a second terminal of the fifth switch S5 is coupled to a second input terminal of the voltage regulator circuit 11. A first terminal of the sixth switch S6 is coupled to an output terminal of the voltage regulator circuit 11, and a second terminal of the sixth switch S6 is coupled to a first terminal of the sampling transistor MS.

[0031] continue Figure 2As described above, the current detection circuit 200 further includes a current mirror 12, which has a first output terminal and a second output terminal. The first output terminal of the current mirror 12 outputs a first current I1, and the second output terminal of the current mirror 12 outputs a second current I2. The value of the first current I1 and the value of the second current I2 are 1:1 / N, that is, the first current I1 is N times the second current I2. The first output terminal of the current mirror 12 is coupled to the first terminal of the calibration transistor MC via the seventh switch S7, and the second output terminal of the current mirror 12 is coupled to the first terminal of the calibration transistor MC via the third switch S3. In one embodiment, the value of N is determined based on the actual required ratio and ranges from 1 to 1000. For example, the value of N can be 10, 20, 50, 80, or 100.

[0032] In one embodiment, assuming that the current of power transistor QL needs to be sampled at a current sampling ratio of 1:1000, power transistor QL uses 200 parallel transistor units with a channel width of 100 microns, and calibration transistor MC uses two parallel transistor units with a channel width of 100 microns. The size of power transistor QL is 100 times the size of calibration transistor MC. The channel length of sampling transistor MS is the same as that of calibration transistor MC, and the channel width of sampling transistor MS is not limited. In another embodiment, assuming that the current of power transistor QL needs to be sampled at a current sampling ratio of 1:1000, power transistor QL uses 200 parallel transistor units with a channel width of 100 microns, and calibration transistor MC uses two parallel transistor units with a channel width of 100 microns. The size of power transistor QL is 100 times the size of calibration transistor MC, the channel length of sampling transistor MS is the same as that of calibration transistor MC, and the channel width of sampling transistor MS is 1 / 10 of the width of calibration transistor MC.

[0033] continue Figure 2As described above, the current detection circuit 200 operates in a calibration phase and a sampling phase. During the calibration phase, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, and the seventh switch S7 are turned on, and the fifth switch S5 and the sixth switch S6 are turned off. The fourth switch S4 is turned on to couple the first end of the freewheeling circuit 13 to the output end of the voltage regulation circuit 11. The freewheeling circuit 13 provides current so that the regulating transistor M1 can be turned on. More specifically, the regulation signal VR charges the calibration capacitor C1. The freewheeling circuit 13 can provide current to keep the regulating transistor M1 turned on, and the voltage regulation circuit 11 will remain in an operating state. Otherwise, the voltage of the calibration capacitor C1 will continue to rise, causing the source voltage of the regulating transistor M1 to be too high and unable to turn on, thereby causing the voltage regulation circuit 11 to operate abnormally. The third switch S3 and the seventh switch S7 are turned on, and the current mirror 12 provides the first current I1 and the second current I2 to the calibration transistor MC and the sampling transistor MS. When the first switch S1 is turned on, the second input terminal of the voltage regulating circuit 11 is coupled to the first terminal of the calibration transistor MC. When the second switch S2 is turned on, the output terminal of the voltage regulating circuit 11 is coupled to the control terminal of the sampling transistor MS. The output terminal of the voltage regulating circuit 11 outputs a regulating signal VR to the control terminal of the sampling transistor MS to adjust the voltage at the first terminal of the sampling transistor MS to be equal to the voltage at the first terminal of the calibration transistor MC. During the calibration phase, when the operational amplifier AMP adjusts the voltage at the first terminal of the sampling transistor MS to be equal to the voltage at the first terminal of the calibration transistor MC, the on-resistance of the calibration transistor MC is ensured to be N times the on-resistance of the sampling transistor MS. The specific operating principle is as follows:

[0034] According to Ohm's law, in a circuit, the relationship between voltage V, current I, and resistance R satisfies:

[0035] V=IR

[0036] During the calibration phase, the voltage regulator circuit 11 clamps the voltage at the first terminal of the sampling transistor MS to the same voltage as the first terminal of the calibration transistor MC. For example, if the sampling transistor MS and the calibration transistor MC are NMOS transistors, the voltage at the first terminal of the sampling transistor MS is its drain voltage Vsd, and the voltage at the first terminal of the calibration transistor MC is its drain voltage Vcd, so Vsd=Vcd.

[0037] For the calibration tube MC, the current injected into it through the first input terminal of the current mirror 12 is set to I1, and it can be obtained:

[0038] Vcd=I1×Rmc.

[0039] Where Rmc represents the on-resistance of the calibration tube MC;

[0040] For the sampling tube MS, the current injected into it through the second input terminal of the current mirror 12 is set to I2, and it can be obtained:

[0041] Vsd=I2×Rms.

[0042] Where Rms represents the on-resistance of the sampling tube MS;

[0043] The voltage regulating circuit 11 regulates the drain voltage Vsd of the sampling tube MS and the drain voltage of the calibration tube MC to be equal, and the above formula can be obtained:

[0044] I1×Rmc=I2×Rms.

[0045] It can be seen that the ratio of the on-resistance of the calibration tube Mc and the sampling tube Ms is equal to the inverse ratio of the ratio of their injected currents. According to the known current mirror 12 injection current ratio of 1:1 / N, the on-resistance ratio of the calibration tube Mc and the sampling tube Ms is 1:N.

[0046] During the sampling phase, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, and the seventh switch S7 are turned off, and the fifth switch S5 and the sixth switch S6 are turned on. The first switch S1 and the second switch S2 are turned off, and the fifth switch S5 and the sixth switch S6 are turned on, so that the second input terminal of the voltage regulator circuit 11 is coupled to the first terminal of the power transistor QL, and the output terminal of the voltage regulator circuit 11 is coupled to the first terminal of the sampling transistor MS and provides a regulation signal VR to equalize the voltage at the first terminal of the power transistor QL. Specifically, during the calibration phase, the first input terminal of the voltage regulator circuit 11 is coupled to the first terminal of the sampling transistor MS, and the second input terminal of the voltage regulator circuit 11 is connected to the first terminal of the calibration transistor MC. The voltages at the first terminals of the sampling transistor MS and the calibration transistor MC are introduced into the voltage regulator circuit 11. The output terminal of the voltage regulator circuit 11 is connected to the control terminal of the sampling transistor MS. Based on the difference between the two input voltages, a regulation signal VR is generated to adjust the voltage at the first terminal of the sampling transistor MS so that the voltage at the first terminal of the sampling transistor MS is equal to the voltage at the first terminal of the calibration transistor MC.

[0047] The sampling phase operates as follows: During circuit design, the power transistor QL includes multiple transistor units connected in parallel, and the calibration transistor MC includes at least one transistor unit. The on-resistance of each transistor unit is highly consistent. In one embodiment, the number of transistor units in the power transistor QL is K times the number of transistor units in the calibration transistor MC, and the on-resistance of the calibration transistor MC is K times the on-resistance of the power transistor MP. The on-resistance ratio of the calibration transistor MC to the sampling transistor MS is 1:N. Therefore, the on-resistance ratio of the power transistor MP, calibration transistor MC, and sampling transistor MS is a precise 1:K:K*N relationship, achieving high-precision current detection.

[0048] In one embodiment, to further reduce the operating current, the current detection circuit 200 also operates in a hold phase. Specifically, the current detection circuit 200 enters the hold phase after the calibration phase. During the hold phase, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, and the seventh switch S7 are all turned off to reduce the operating current of the current detection circuit 200. The hold phase ends when the power transistor QL turns on.

[0049] exist Figure 2 In the illustrated embodiment, the switching circuit 10 includes an H-bridge circuit, which includes a high-side power transistor QH and a low-side power transistor QL coupled in series between a power supply PVDD and a reference ground GND. It should be noted that the switching circuit 10 is only illustrated herein and is not intended to limit the scope of protection. The high-side power transistor QH and the low-side power transistor QL in the switching circuit 10 are turned on and off under the control of a high-side control signal GH and a low-side control signal GL, respectively.

[0050] Figure 3A The waveform diagram of each switch control signal, high side control signal GH and low side control signal GL in the current detection circuit according to an embodiment of the present application is given. Figure 3A In the embodiment, the current detection circuit 200 operates only in the calibration phase and the sampling phase. When the high-side power transistor QH is turned on and the low-side power transistor QL is turned off, the current detection circuit 200 operates in the calibration phase, the first switch control signal GS1, the second switch control signal GS2, the third switch control signal GS3, the fourth switch control signal GS4, and the seventh switch control signal GS7 are in the first state (e.g., logic high), and the fifth switch control signal GS5 and the sixth switch control signal GS6 are in the second state (e.g., logic low). When the high-side power transistor QH is turned off and the low-side power transistor QL is turned on, the current detection circuit 200 operates in the sampling phase, the first switch control signal GS1, the second switch control signal GS2, the third switch control signal GS3, the fourth switch control signal GS4, and the seventh switch control signal GS7 are in the second state (e.g., logic low), and the fifth switch control signal GS5 and the sixth switch control signal GS6 are in the first state (e.g., logic high).

[0051] Figure 3B The waveform diagrams of the switch control signals, the high-side control signal GH and the low-side control signal GL in the current detection circuit according to an embodiment of the present application are given. Figure 3B The difference between the embodiments is that in Figure 3BIn the current detection circuit 200, the current detection circuit 200 is still operating in the hold phase. When the high-side power transistor QH is turned on and the low-side power transistor QL is turned off, the current detection circuit 200 first operates in the calibration phase. In the calibration phase, the first switch control signal GS1, the second switch control signal GS2, the third switch control signal GS3, the fourth switch control signal GS4, and the seventh switch control signal GS7 are in the first state (e.g., logic high), and the fifth switch control signal GS5 and the sixth switch control signal GS6 are in the second state (e.g., logic low). As the current detection circuit enters the hold phase, the first switch control signal GS1, the second switch control signal GS2, the third switch control signal GS3, the fourth switch control signal GS4, and the seventh switch control signal GS7 jump from the first state to the second state, and the fifth switch control signal GS5 and the sixth switch control signal GS6 remain in the second state (e.g., logic low). When the high-side power tube QH is turned off and the low-side power tube QL is turned on, the current detection circuit 200 enters the sampling stage. In the sampling stage, the first switch control signal GS1, the second switch control signal GS2, the third switch control signal GS3, the fourth switch control signal GS4, and the seventh switch working signal GS7 are in the second state (for example, logic low), and the fifth switch control signal GS5 and the sixth switch control signal GS6 are in the first state (for example, logic high).

[0052] Figure 4 A schematic diagram of the operation of the voltage regulation circuit in the calibration phase according to an embodiment of the present application is provided. During the calibration phase, the first switch S1 is turned on under the control of the first switch control signal GS1, and the first end of the calibration tube MC is connected to the second input end of the voltage regulation circuit 11, transmitting the voltage signal at the first end of the calibration tube MC to the second input end of the operational amplifier AMP in the voltage regulation circuit 11. The second switch S2 is turned on under the control of the second switch signal GS2, and the output end of the voltage regulation circuit 11 is connected to the control end of the sampling tube MS and the first end of the calibration capacitor C1. On the one hand, the regulation signal VR output by the voltage regulation circuit 11 is transmitted to the control end of the sampling tube MS, regulating the working state of the sampling tube MS so that the voltage at the first end of the sampling tube MS is the same as the voltage at the first end of the calibration tube MC. On the other hand, the regulation signal VR also charges the calibration capacitor C1.

[0053] Figure 5 A schematic diagram illustrating the operation of a voltage regulation circuit according to an embodiment of the present application during the sampling phase is provided. During the sampling phase, the fifth switch S5 and the sixth switch S6 are turned on, and the second electrical signal output by the voltage regulation circuit 11 is transmitted to the first terminal of the sampling transistor MS. This adjusts the operating state of the sampling transistor MS so that the voltage at the first terminal of the sampling transistor MS is equal to the voltage at the first terminal of the power transistor QL. The sampling transistor MS then accurately generates the detection current IS, completing the current sampling of the power transistor QL.

[0054] In this application, the on-resistance of the calibration tube MC is designed to be K times the on-resistance of the power tube QL. After calibration, even under different process, voltage, and temperature conditions, the on-resistance ratio of the power tube QL, the calibration tube MC, and the sampling tube MS is a precise 1:K:K*N proportional relationship, achieving high-precision current detection.

[0055] The above is a detailed introduction to a current detection circuit provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A current detection circuit for detecting current flowing through a power transistor, wherein the power transistor includes a plurality of transistor units connected in parallel, and the current detection circuit includes: A calibration tube having a first end, a second end and a control end, the calibration tube comprising at least one of the transistor units; a sampling tube having a first end, a second end, and a control end; as well as A voltage regulating circuit has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the voltage regulating circuit is coupled to the first terminal of the sampling tube, and the output terminal of the voltage regulating circuit outputs a regulating signal; The current detection circuit operates in a calibration phase and a sampling phase. In the calibration phase, the second input terminal of the voltage regulation circuit is coupled to the first terminal of the calibration tube, the output terminal of the voltage regulation circuit is coupled to the control terminal of the sampling tube, and the regulation signal is adjusted so that the voltage of the first terminal of the sampling tube is equal to the voltage of the first terminal of the calibration tube; During the sampling phase, the second input end of the voltage regulating circuit is coupled to the first end of the power tube, the output end of the voltage regulating circuit is coupled to the first end of the sampling tube, and the regulating signal regulates the voltage of the first end of the sampling tube to be equal to the voltage of the first end of the power tube.

2. The current detection circuit according to claim 1 , wherein the voltage regulation circuit comprises: An operational amplifier having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the first input terminal of the voltage regulating circuit, and the second input terminal is coupled to the second input terminal of the voltage regulating circuit; as well as The regulating transistor has a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the supply voltage, the control terminal is coupled to the output terminal of the operational amplifier, and the second terminal is coupled to the output terminal of the voltage regulating circuit. 3 . The current detection circuit according to claim 1 , wherein the number of the plurality of transistor units connected in parallel in the power tube is K times the number of the transistor units in the calibration tube, and K is a constant greater than 1. 4 . The current detection circuit according to claim 1 , further comprising a calibration capacitor coupled between the control terminal of the sampling tube and a reference ground.

5. The current detection circuit according to claim 1 , further comprising: A first switch is coupled between the first terminal of the calibration tube and the second input terminal of the voltage regulating circuit; A second switch is coupled between the output terminal of the voltage regulating circuit and the control terminal of the sampling tube; a fifth switch coupled between the second input terminal of the voltage regulating circuit and the first terminal of the power tube; as well as The sixth switch is coupled between the output terminal of the voltage regulating circuit and the first terminal of the sampling tube.

6. The current detection circuit according to claim 1 further includes a current mirror, the current mirror having a first output terminal and a second output terminal, the first output terminal of the current mirror being coupled to the first terminal of the calibration tube through a seventh switch and providing a first current, the second output terminal of the current mirror being coupled to the first terminal of the sampling tube through a third switch and providing a second current, wherein the first current is N times the second current. 7 . The current detection circuit according to claim 6 , wherein the current detection circuit further operates in a holding phase, wherein the third switch and the seventh switch are turned off during the holding phase, and the third switch and the seventh switch are turned on during the calibration phase. 8 . The current detection circuit according to claim 1 , further comprising a freewheeling power supply, wherein the freewheeling power supply is coupled to the output end of the voltage regulating circuit via a fourth switch. 9 . The current detection circuit according to claim 1 , wherein a control terminal of the calibration tube is coupled to a bias voltage, and a second terminal of the calibration tube is coupled to a reference ground. 10 . The current detection circuit according to claim 1 , wherein in the sampling phase, the power tube is turned on, and in the shut-off phase, the power tube is turned off.

Images