A low-voltage fault early warning method based on chip algorithm

Abstract

The application discloses a low-voltage fault early warning method based on a chip algorithm, which comprises the following steps: S1, collecting operation data in a low-voltage power system, and continuously sampling the operation data through a chip; S2, performing preprocessing on an original input vector sequence and calculating a voltage fluctuation rate index; S3, constructing a sparse connection echo state neural network model; S4, inputting the preprocessed input data set into the echo state neural network model to obtain a state vector after cutting; S5, inputting the state vector after cutting into a sparse output mapping layer to generate a voltage abnormality risk score; S6, comparing the voltage abnormality risk score with a set risk level threshold value, and outputting an early warning level label; and S7, generating an alarm control signal according to the early warning level label, and sending the voltage abnormality risk score and the early warning level label to an upper system or a remote control platform. The application adopts a sparse neural network and a chip algorithm to realize real-time fault early warning of a low-voltage power system.

Description

Technical Field

[0001] This invention relates to the field of intelligent monitoring technology for power systems, and in particular to a low-voltage fault early warning method based on chip algorithms. Background Technology

[0002] In low-voltage power distribution systems, common electrical fault types include voltage fluctuations, voltage drops, and abnormal voltage deviations. If these faults are not detected and addressed promptly, they can lead to equipment malfunctions, degraded power quality, and even partial power outages. Traditional low-voltage fault early warning methods typically rely on static threshold settings, rule-based discrimination models, or feature extraction methods based on human experience. In practical applications, these methods suffer from response lag, low accuracy, and difficulty adapting to varying operating conditions. To improve early warning efficiency, recent research has introduced machine learning algorithms such as neural networks, support vector machines, and decision trees to perform pattern recognition and classification analysis on voltage and current, thereby constructing more flexible fault identification models.

[0003] However, when deployed on resource-constrained embedded terminals or chip platforms, these methods often face significant challenges in terms of model computational load and power consumption. Some models have complex structures and high parameter dimensionality, making them unsuitable for direct application to real-time edge processing tasks. Furthermore, in embedded deployments, once the model structure is fixed, it is difficult to effectively adjust it through online learning, leading to a decline in detection performance with environmental changes. In addition, most current models employ fixed input dimensions and uniform processing strategies, lacking dynamic response mechanisms to voltage fluctuations. This hinders fine-grained perception and tailoring of electrical states, reducing prediction stability under non-stationary power grid operating conditions.

[0004] Existing research has explored the application of Echo State Network (ESN) structures in time series forecasting, but most studies focus on fully connected reservoir architectures, lacking low-dimensional modeling strategies that combine sparse structures with state selection mechanisms. While some methods consider sparse network design, they do not fully integrate grid state indicators for dynamic control, especially in low-voltage power scenarios. A unified solution for transforming the volatility characteristics of actual operating data into a basis for model pruning and response remains unresolved. Furthermore, the chip-level deployment paths of existing ESN algorithms lack detailed design, failing to adequately consider the constraints of connection sparsity and on-chip resources (such as the number of parallel computing channels and storage capacity), limiting the model's real-time performance in embedded devices.

[0005] Therefore, how to provide a low-voltage fault early warning method based on chip algorithms is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] One objective of this invention is to propose a low-voltage fault early warning method based on chip algorithms. This invention makes full use of echo state neural networks, sparse structure modeling and embedded chip resource management technology, and describes in detail a method for realizing real-time perception, state trimming and risk scoring of low-voltage power system operation data under chip resource constraints. It has the advantages of fast response speed, low computational resource consumption and high early warning accuracy.

[0007] A low-voltage fault early warning method based on chip algorithm according to an embodiment of the present invention includes the following steps:

[0008] S1. Collect operating data from the low-voltage power system, continuously sample the operating data through the chip, and generate the original input vector sequence;

[0009] S2. Perform preprocessing operations on the original input vector sequence to generate a preprocessed input dataset and calculate the voltage fluctuation index based on the first-order voltage difference value in the preprocessed input dataset.

[0010] S3. Construct a sparsely connected echo state neural network model, including an input layer, a sparse reservoir structure and a sparse output mapping layer. The connection weights of the sparse reservoir structure are generated and fixed before deployment based on chip resource constraints.

[0011] S4. Input the preprocessed input dataset into the echo state neural network model, update the state vector of the reserve pool, dynamically set the state pruning parameter threshold according to the voltage volatility index and perform the pruning operation to obtain the pruned state vector.

[0012] S5. Input the clipped state vector into the sparse output mapping layer, perform low-dimensional embedding linear projection, and generate a voltage anomaly risk score.

[0013] S6. Compare the voltage anomaly risk score with the set risk level threshold and output the warning level label;

[0014] S7. Generate an alarm control signal based on the warning level label and send the voltage abnormality risk score and warning level label to the upper system or remote control platform through the communication interface.

[0015] Optionally, the original input vector sequence consists of multi-dimensional operational data collected by the target node in the low-voltage power system within a continuous sampling period; the sampling frequency is set to f. s In the continuous time interval T = {t1, t2, ..., t} n Within the system, at each sampling time, operational data including voltage, current, and frequency values ​​are collected; at each time step, an input vector is constructed, and the vectors constructed at each sampling time point are arranged in chronological order to form a complete sequence of original input vectors.

[0016] Optionally, S2 specifically includes:

[0017] S21. Perform a moving average filtering operation on each component of the original input vector sequence at each time step t. i At this point, select the voltage values ​​corresponding to the current time and the previous k-1 sampling times, calculate the arithmetic mean of the k voltage values, and use it as the time step t. i The filtered voltage value;

[0018] S22. Perform normalization processing on each filtered component, and reconstruct the preprocessed input dataset from the normalized vectors.

[0019] S23. Based on the voltage components in the preprocessed input dataset, calculate the voltage change between two adjacent time steps. At each time step t... i At this point, the difference between the current normalized voltage value and the normalized voltage value of the previous time step is the time step t. i The first difference value;

[0020] S24. Based on the continuous first-order difference values ​​within the sliding window, calculate the voltage fluctuation rate index at each time step t. i Select time step t. i The first-order difference values ​​of the previous k consecutive time steps are taken, and the average of the absolute values ​​is used as the average value for time step t. i Voltage fluctuation rate index.

[0021] Optionally, S3 specifically includes:

[0022] S31. Define the structure of a sparsely connected echo state neural network model, including an input layer, a sparse reservoir structure and a sparse output mapping layer, wherein the input layer receives a normalized input vector from a preprocessed input dataset.

[0023] S32. Before deploying the sparsely connected echo state neural network model, a connection matrix W with a sparse reserve pool structure is generated according to the chip computing resource constraints. The connection matrix W satisfies the sparsity constraint. After the connection matrix is ​​generated, it is fixedly stored inside the chip.

[0024] S33. Constructing the input connection matrix W in a sparsely connected echo-state neural network model. in This maps the normalized input vector to neuron nodes in the sparse reservoir structure.

[0025] S34. Construct a sparse output mapping layer in a sparsely connected echo-state neural network model, and let the output mapping matrix be W. outThe sparse output mapping layer performs low-dimensional embedding linear projection only on the subset of indices retained in the clipped state vector of the sparse reservoir structure output.

[0026] S35. In the sparsely connected echo-state neural network model, the connection matrix W and the input connection matrix W... in With output mapping matrix W out It is solidified into the internal storage structure of the chip.

[0027] Optionally, S32 specifically includes:

[0028] S321. Let the state dimension of the sparse reservoir structure be N. Based on the preset connection sparsity ρ of the chip's computing resource constraints, the preset connection sparsity ρ is jointly determined by the number of parallel computing channels that the chip can support and the on-chip storage capacity. It must satisfy that it is not higher than the ratio of the maximum number of parallel computing channels that the chip can support to the state dimension and not higher than the ratio of the available on-chip storage capacity of the chip to the square of the state dimension.

[0029] S322. Randomly generate a sparse reservoir connection matrix W under sparsity constraints, and constrain the number of non-zero elements to ||W||0≤ρ·N. 2 ;

[0030] S323. Perform a spectral radius adjustment operation on the connection matrix W of the sparse reservoir structure, calculate the maximum eigenvalue modulus, and perform a normalization transformation.

[0031] S324. The connection matrix W of the adjusted sparse reservoir structure is fixedly stored inside the chip to construct the sparse reservoir structure of the sparsely connected echo state neural network model.

[0032] Optionally, S35 specifically includes:

[0033] S351. In the sparsely connected echo-state neural network model, the connection matrix W and the input connection matrix W in With the output mapping matrix W out The encoding is a sparse format representation, in which each matrix is ​​compressed and stored using sparse index pairs consisting of non-zero element indices and corresponding weight values.

[0034] S352. Write the three sets of sparse matrices after encoding into the non-volatile memory area inside the chip, and load each matrix into the on-chip cache through the address mapping table during the initialization phase.

[0035] S353. During the operation phase of the echo state neural network model, a sparse matrix calling mechanism based on the instruction mapping table is used to implement sparse multiplication operations between the input vector, state vector and output mapping vector using a preset index structure, ensuring that the sparsely connected echo state neural network model completes the entire calculation process under a fixed structure.

[0036] The parameters of the S354 echo state neural network model are not updated or replaced during operation and are strictly bound to the chip's computing resource budget.

[0037] Optionally, S4 specifically includes:

[0038] S41, at each time step t i At this point, the normalized input vector from the preprocessed input dataset is input into a sparsely connected echo-state neural network model;

[0039] S42, By inputting the connection matrix W in The connection matrix W of the sparse reservoir structure updates the reservoir state vector x(t). i ):

[0040] x(t i )=f(W·x(t i-1 )+W in ·u norm (t i ));

[0041] Where x(t) i At time step t i The state vector of the sparse reservoir structure generated at point t i Let f(·) represent the current sampling time, f(·) be the hyperbolic tangent function, W be the connection matrix of the sparse reservoir structure, and x(t) be the value of x(t). i-1 Previous time step t i-1 The state vector of the reservoir, W in Input connection matrix, u norm (t i At time step t i The normalized input vector obtained at the point;

[0042] S43. Calculate the state trimming parameter threshold θ(t) based on the current time step voltage fluctuation rate index. i The voltage fluctuation rate index is multiplied by a preset proportional coefficient γ, and the product is used as the time step t. i State clipping threshold;

[0043] S44. At the current time step t i For the state vector x(t) i Each component x in ) j (t iPerform an activity check; if |x j (t i )|<θ(t i If a value is found to be inactive, it is considered inactive and removed from the list; all values ​​satisfying |x are retained. j (t i )|≥θ(t i The state components of t constitute the clipped state vector x′(t) i ), and record the state vector x′(t) after clipping. i The subset of indexes retained in ).

[0044] Optionally, the low-dimensional embedded linear projection is derived from the output mapping matrix W. out Extract the column vector subsets corresponding to the retained index subsets to form a sparse output submatrix, and then apply this to the pruned state vector x′(t). i Perform a linear projection operation on the sparse output submatrix, multiplying each column element of the output submatrix by the corresponding state component and summing the results. The weighted sum is used as the time step t. i Voltage anomaly risk score.

[0045] Optionally, S6 specifically includes:

[0046] S61. Set a set of risk level thresholds Where τ1<τ2<τ3 correspond to the risk scoring limits of normal state, attention state and abnormal state, respectively;

[0047] S62, at time step t i At this point, the voltage anomaly risk score y(t) will be applied. i ) and risk level threshold set Perform interval comparison and generate warning level label L(t) according to the rules. i );

[0048] S63, if y(t) i If )≤τ1, then set L(t) i ) = 0 indicates normal operation; if τ1 <y(t i If )≤τ2, then set L(t) i ) = 1 indicates attention, if τ2 <y(t i If )≤τ3, then set L(t) i ) = 2 indicates an early warning; if y(t) i If )>τ3, then set L(t) i =3 indicates a severe warning

[0049] S64, at time step t i At this point, the time step t is adjusted according to the voltage anomaly risk score. i+1 State clipping parameter threshold θ(t) i+1The state pruning threshold of the current time step is multiplied by a scaling factor determined by the risk score, which is equal to the product of the current risk score and a set positive adjustment factor.

[0050] Optionally, S7 specifically includes:

[0051] S71, at time step t i At the location, based on the generated warning level label L(t) i The preset alarm response mapping rules are invoked to map the tag values ​​to the corresponding alarm control commands S. alarm (t i ), where L(t) i When ) = 0, a no-operation instruction is generated, L(t) i When ) = 1, generate a prompting log instruction, L(t) i When ) = 2, a local alarm command is generated, L(t) i When ) = 3, a remote emergency alarm command is generated;

[0052] S72, Construct alarm information communication data packet P(t) i The data packet encapsulates its content using a key-value pair structure, including a timestamp field, a voltage anomaly risk score field, a warning level label field, and an alarm control instruction field.

[0053] S73, transfer the communication data packet P(t) i The data is sent to the designated data receiving node through the communication interface module integrated in the chip. The communication interface includes a serial bus, an Ethernet interface, a CAN bus, or a wireless communication module.

[0054] S74. The receiving node includes a local host system or a remote control platform. After receiving the data, it triggers a status recording, instruction execution, or control strategy update process based on the field content.

[0055] The beneficial effects of this invention are:

[0056] This invention proposes a low-voltage fault early warning method based on chip algorithms, which enables efficient fault identification and early warning control of low-voltage power system operation under conditions of limited chip resources. The method design employs a sparsely connected echo state neural network model and dynamically sets state pruning parameters based on voltage fluctuation rate indices. This achieves real-time filtering and feature compression of the reserve pool state vector, effectively reducing redundant computational load during model operation and improving system response efficiency. The preprocessing stage introduces first-order voltage difference and sliding window fluctuation rate calculation methods, enabling the input data to reflect more sensitive voltage dynamic change trends and enhancing the early identification capability of low-voltage anomalies.

[0057] This invention embeds the sparse connection matrix, input projection matrix, and output mapping matrix into the chip's non-volatile memory in a sparse encoded form. Through a pre-defined address mapping and instruction control mechanism, sparse matrix operations during model inference are implemented, ensuring the matching relationship between the model structure and chip resources, thereby improving the feasibility and operational stability of embedded deployment. Furthermore, a dynamic adjustment mechanism between risk scoring and pruning thresholds is employed, enabling the model to automatically adjust the density of retained information based on the current state during operation. This achieves real-time feedback control of the scoring results on the model's sparsity, enhancing the system's adaptability to scenarios with drastic voltage changes.

[0058] Regarding fault early warning output, early warning level labels can be sent to the upper-level system or remote control platform via a communication interface in the form of structured data packets, realizing a complete data closed-loop link from on-site data acquisition and model processing to alarm issuance and response control. The overall approach can be rapidly deployed without relying on high-performance servers or complex software platforms, and is suitable for intelligent monitoring scenarios of edge devices in low-voltage distribution networks. Attached Figure Description

[0059] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0060] Figure 1 This is a flowchart of a low-voltage fault early warning method based on chip algorithms proposed in this invention;

[0061] Figure 2 This is a schematic diagram of the sparsely connected echo state neural network model structure in a low-voltage fault early warning method based on chip algorithms proposed in this invention.

[0062] Figure 3 This is a schematic diagram of the voltage fluctuation rate index-driven state clipping and scoring feedback mechanism in a low-voltage fault early warning method based on chip algorithms proposed in this invention. Detailed Implementation

[0063] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.

[0064] refer to Figure 1-3 A low-voltage fault early warning method based on chip algorithms includes the following steps:

[0065] S1. Collect operating data from the low-voltage power system, continuously sample the operating data through the chip, and generate the original input vector sequence;

[0066] S2. Perform preprocessing operations on the original input vector sequence to generate a preprocessed input dataset, and calculate the voltage fluctuation index based on the first-order voltage difference value in the preprocessed input dataset.

[0067] S3. Construct a sparsely connected echo state neural network model, the model including an input layer, a sparse reservoir structure and a sparse output mapping layer, wherein the connection weights of the sparse reservoir structure are generated and fixed according to chip resource constraints before deployment;

[0068] S4. Input the preprocessed input dataset into the echo state neural network model, update the state vector of the reserve pool, dynamically set the state pruning parameter threshold according to the voltage volatility index and perform the pruning operation to obtain the pruned state vector.

[0069] S5. Input the clipped state vector into the sparse output mapping layer to generate a voltage anomaly risk score.

[0070] S6. Compare the voltage anomaly risk score with the set risk level threshold, output the warning level label, and adjust the state trimming parameters for the next time step based on the risk score of the current time step.

[0071] S7. Generate an alarm control signal based on the warning level label and send the voltage abnormality risk score and warning level label to the upper system or remote control platform through the communication interface.

[0072] This invention constructs a low-voltage fault early warning method based on chip algorithms. It introduces a sparsely connected echo state neural network model and combines it with a dynamic state pruning mechanism driven by voltage fluctuation rate indicators, achieving efficient identification and fault early warning of low-voltage power system operating states. Compared to traditional fixed threshold methods, this invention can perform real-time scoring and graded responses to minor to severe voltage anomalies, demonstrating excellent performance in accuracy, response speed, and false alarm control. Furthermore, by compressing the sparse matrix and embedding the model structure into an embedded chip, the inference computation load is significantly reduced, improving the model's operating efficiency and stability in resource-constrained environments, and demonstrating good engineering adaptability and field application value.

[0073] In this embodiment, the original input vector sequence consists of multi-dimensional operational data collected by the target node in the low-voltage power system within a continuous sampling period; the sampling frequency is set to f. s In the continuous time interval T = {t1, t2, ..., t} n Within the system, at each sampling time, operational data including voltage, current, and frequency values ​​are collected; at each time step, an input vector is constructed, and the vectors constructed at each sampling time point are arranged in chronological order to form a complete sequence of original input vectors.

[0074] This invention continuously samples the operational data of target nodes in a low-voltage power system at a fixed sampling frequency, extracting multi-dimensional information such as voltage, current, and frequency values ​​over consecutive time periods to construct a temporally ordered sequence of original input vectors. Data collected at each sampling moment is synchronously constructed into an input vector and arranged sequentially according to sampling time, forming a complete set of input data. This method effectively preserves the temporal changes in operational status, providing a coherent, stable, and time-series logical input foundation for subsequent fault detection and risk analysis.

[0075] In this embodiment, S2 specifically includes:

[0076] S21. Perform a moving average filtering operation on each component of the original input vector sequence at each time step t. i At this point, select the voltage values ​​corresponding to the current time and the previous k-1 sampling times, calculate the arithmetic mean of the k voltage values, and use it as the time step t. i The filtered voltage value;

[0077] S22. Perform normalization processing on each filtered component, and reconstruct the preprocessed input dataset from the normalized vectors.

[0078] S23. Based on the voltage components in the preprocessed input dataset, calculate the voltage change between two adjacent time steps. At each time step t... i At this point, the difference between the current normalized voltage value and the normalized voltage value of the previous time step is the time step t. i The first difference value;

[0079] S24. Based on the continuous first-order difference values ​​within the sliding window, calculate the voltage fluctuation rate index at each time step t. i Select time step t. i The first-order difference values ​​of the previous k consecutive time steps are taken, and the average of the absolute values ​​is used as the average value for time step t. i Voltage fluctuation rate index.

[0080] This invention effectively removes high-frequency fluctuation interference from the signal and improves data stability by performing a moving average filter on the voltage component at each sampling time. Subsequently, the filtered voltage values ​​are normalized to enhance the comparability of data with different dimensions. Based on this, the voltage change between the current and previous times is calculated to obtain a first-order difference value reflecting the dynamic trend of voltage change. By averaging the absolute values ​​of multiple consecutive first-order difference values, a voltage volatility index is constructed, which quantifies the intensity of voltage fluctuations and provides a basis for subsequent state trimming and risk scoring. This method enhances the system's sensitivity to voltage change trends and improves the timeliness and accuracy of early warning judgments.

[0081] In this embodiment, S3 specifically includes:

[0082] S31. Define the structure of a sparsely connected echo state neural network model, including an input layer, a sparse reservoir structure and a sparse output mapping layer, wherein the input layer receives a normalized input vector from a preprocessed input dataset.

[0083] S32. Before deploying the sparsely connected echo state neural network model, a connection matrix W with a sparse reserve pool structure is generated according to the chip computing resource constraints. The connection matrix W satisfies the sparsity constraint. After the connection matrix is ​​generated, it is fixedly stored inside the chip.

[0084] S33. Constructing the input connection matrix W in a sparsely connected echo-state neural network model. in This maps the normalized input vector to neuron nodes in the sparse reservoir structure.

[0085] S34. Construct a sparse output mapping layer in a sparsely connected echo-state neural network model, and let the output mapping matrix be W. out The sparse output mapping layer performs low-dimensional embedding linear projection only on the subset of indices retained in the clipped state vector of the sparse reservoir structure output.

[0086] S35. In the sparsely connected echo-state neural network model, the connection matrix W and the input connection matrix W... in With the output mapping matrix W out The structure is embedded in the chip's internal storage structure, maintaining the structural stability of the sparsely connected echo-state neural network model during operation and ensuring that all computational operations are constrained by the chip's resource budget.

[0087] This invention achieves modular deployment of the input layer, sparse reservoir, and sparse output mapping layer by constructing a sparsely connected echo-state neural network structure. The reservoir connection matrix is ​​generated under preset sparsity constraints and stored internally in the chip, ensuring the model's feasibility in resource-constrained environments. The input connection matrix maps the normalized input vector to the reservoir structure, while the output mapping layer only performs linear projections on the state components retained in the reservoir, effectively reducing model dimensionality and improving operational efficiency. This structure achieves sparsity of computational paths, improving the overall system processing speed and chip adaptability.

[0088] In this embodiment, S32 specifically includes:

[0089] S321. Let the state dimension of the sparse reservoir structure be N. Based on the preset connection sparsity ρ of the chip's computing resource constraints, the preset connection sparsity ρ is jointly determined by the number of parallel computing channels that the chip can support and the on-chip storage capacity. It must satisfy that it is not higher than the ratio of the maximum number of parallel computing channels that the chip can support to the state dimension and not higher than the ratio of the available on-chip storage capacity of the chip to the square of the state dimension.

[0090] S322. Randomly generate a sparse reservoir connection matrix W under sparsity constraints, and constrain the number of non-zero elements to ||W||0≤ρ·N. 2 ;

[0091] S323. Perform a spectral radius adjustment operation on the connection matrix W of the sparse reservoir structure, calculate the maximum eigenvalue modulus, and perform a normalization transformation so that the spectral radius of the connection matrix satisfies the echo stability condition of less than 1.

[0092] S324. The connection matrix W of the adjusted sparse reservoir structure is fixedly stored inside the chip to construct the sparse reservoir structure of the sparsely connected echo state neural network model.

[0093] This invention, based on chip computing resource constraints, pre-defines the state dimension and connection sparsity of the sparse reservoir structure to ensure that the generated connection matrix operates within the available computing channels and storage capacity of the chip, improving resource matching. Furthermore, a sparse connection matrix is ​​generated randomly, and the number of non-zero elements is limited to the ratio of the square of the state dimension to ensure matrix sparsity. To guarantee system stability, the spectral radius of the connection matrix is ​​further adjusted, and the eigenvalues ​​are normalized to satisfy the convergence conditions of the echo network. Finally, the adjusted connection matrix is ​​embedded within the chip, achieving low-resource deployment of the sparse structure and improving model operating efficiency and stability.

[0094] In this embodiment, S35 specifically includes:

[0095] S351. In the sparsely connected echo-state neural network model, the connection matrix W and the input connection matrix W in With the output mapping matrix W out The encoding is a sparse format representation, in which each matrix is ​​compressed and stored using sparse index pairs consisting of non-zero element indices and corresponding weight values.

[0096] S352. Write the three sets of sparse matrices after encoding into the non-volatile memory area inside the chip, and load each matrix into the on-chip cache through the address mapping table during the initialization phase.

[0097] S353. During the operation phase of the echo state neural network model, a sparse matrix calling mechanism based on the instruction mapping table is used to implement sparse multiplication operations between the input vector, state vector and output mapping vector using a preset index structure, ensuring that the sparsely connected echo state neural network model completes the entire calculation process under a fixed structure.

[0098] The parameters of the S354 echo state neural network model are not updated or replaced during operation, ensuring that the network structure remains stable within the chip and is strictly bound to the chip's computing resource budget.

[0099] This invention encodes the network connection matrix using a sparse indexing method and stores it in a non-volatile region of the chip. During initialization, it loads the matrix into the runtime cache via an address mapping mechanism, ensuring efficient and stable model loading. During runtime, a pre-defined sparse matrix structure is invoked to perform multiplication calculations between the input vector and the state output, avoiding the resource overhead of full matrix computation. Model parameters are not updated during runtime, ensuring structural stability and strict binding to chip resources, effectively improving the operating efficiency and resource adaptability of neural networks on embedded devices.

[0100] In this embodiment, S4 specifically includes:

[0101] S41, at each time step t i At this point, the normalized input vector from the preprocessed input dataset is input into a sparsely connected echo-state neural network model;

[0102] S42, By inputting the connection matrix W in The connection matrix W of the sparse reservoir structure updates the reservoir state vector x(t). i ):

[0103] x(t i )=f(W·x(t i-1 )+W in ·u norm (t i ));

[0104] Where x(t) i At time step t i The state vector of the sparse reservoir structure generated at point t i Let f(·) represent the current sampling time, f(·) be the hyperbolic tangent function, W be the connection matrix of the sparse reservoir structure, and x(t) be the value of x(t). i-1 Previous time step t i-1 The state vector of the reservoir, W in Input connection matrix, u norm (t i At time step t i The normalized input vector obtained at the point;

[0105] S43. Calculate the state trimming parameter threshold θ(t) based on the current time step voltage fluctuation rate index. i The voltage fluctuation rate index is multiplied by a preset proportional coefficient γ, and the product is used as the time step t. i State clipping threshold;

[0106] S44. At the current time step t i For the state vector x(t) i Each component x in ) j (t i Perform an activity check; if |x j (t i )|<θ(t i If a value is found to be inactive, it is considered inactive and removed from the list; all values ​​satisfying |x are retained. j (t i )|≥θ(t i The state components of t constitute the clipped state vector x′(t) i ), and record the state vector x′(t) after clipping. i The subset of indexes retained in ).

[0107] In the model inference phase, this invention feeds a normalized input vector into a sparsely connected echo-state neural network structure. The state vector at the current time step is updated by combining the input matrix with the reservoir connection matrix, forming a dynamic state representation with temporal correlation. The state vector update process uses an activation function to perform a nonlinear mapping on the weighted sum of the previous state and the current input, improving the modeling ability for nonlinear fluctuations. Based on this, the system calculates a state pruning threshold according to the current voltage fluctuation rate, multiplying the fluctuation intensity by a scaling factor to obtain the effective screening threshold for the current time step. Subsequently, an activity determination is performed on each component of the state vector, eliminating inactive components below the threshold and retaining only high-response state components, forming the pruned sparse state vector. This mechanism effectively reduces the computational burden while preserving key feature information, improving the model's computational efficiency and adaptability to edge devices, and enhancing the system's ability to perceive dynamic anomalies.

[0108] In this embodiment, the low-dimensional embedded linear projection is derived from the output mapping matrix W. out Extract the column vector subsets corresponding to the retained index subsets to form a sparse output submatrix, and then apply this to the pruned state vector x′(t). i Perform a linear projection operation on the sparse output submatrix, multiplying each column element of the output submatrix by the corresponding state component and summing the results. The weighted sum is used as the time step t. i Voltage anomaly risk score.

[0109] This invention constructs a sparse output submatrix by extracting column vectors corresponding to the retained state indices from the output mapping matrix, and performs a linear projection operation with the pruned state vectors to calculate a weighted sum as the voltage anomaly risk score at the current moment, thereby achieving efficient risk assessment after feature compression.

[0110] In this embodiment, S6 specifically includes:

[0111] S61. Set a set of risk level thresholds Where τ1<τ2<τ3 correspond to the risk scoring limits of normal state, attention state and abnormal state, respectively;

[0112] S62, at time step t i At this point, the voltage anomaly risk score y(t) will be applied. i ) and risk level threshold set Perform interval comparison and generate warning level label L(t) according to the rules. i );

[0113] S63, if y(t) i If )≤τ1, then set L(t) i ) = 0 indicates normal operation; if τ1 <y(t i If )≤τ2, then set L(t) i ) = 1 indicates attention, if τ2 <y(t i If )≤τ3, then set L(t) i ) = 2 indicates an early warning; if y(t) i If )>τ3, then set L(t) i =3 indicates a severe warning

[0114] S64, at time step t i At this point, the time step t is adjusted according to the voltage anomaly risk score. i+1 State clipping parameter threshold θ(t) i+1 The state pruning threshold of the current time step is multiplied by a scaling factor determined by the risk score, which is equal to the product of the current risk score and a set positive adjustment factor.

[0115] This invention sets multiple risk level thresholds and compares voltage anomaly risk scores with these thresholds within intervals to generate multi-level early warning labels, achieving fine-grained classification of system states. The scoring results correspond to different response levels, including normal, watchful, warning, and severe warning. Furthermore, the state pruning parameters for the next time step are dynamically adjusted based on the current score value. By calculating the product of the score value and a set adjustment factor, the scaling of the state pruning threshold is controlled, allowing the model to retain more feature information and enhance anomaly response capabilities under high-risk conditions, while further compressing computation under low-risk conditions to improve overall operational efficiency.

[0116] In this embodiment, S7 specifically includes:

[0117] S71, at time step t i At the location, based on the generated warning level label L(t) i The preset alarm response mapping rules are invoked to map the tag values ​​to the corresponding alarm control commands S. alarm (t i ), where L(t) i When ) = 0, a no-operation instruction is generated, L(t) i When ) = 1, generate a prompting log instruction, L(t) i When ) = 2, a local alarm command is generated, L(t) i When ) = 3, a remote emergency alarm command is generated;

[0118] S72, Construct alarm information communication data packet P(t) i The data packet encapsulates its content using a key-value pair structure, including a timestamp field, a voltage anomaly risk score field, a warning level label field, and an alarm control instruction field.

[0119] S73, transfer the communication data packet P(t) i The data is sent to the designated data receiving node through the communication interface module integrated in the chip. The communication interface includes a serial bus, an Ethernet interface, a CAN bus, or a wireless communication module.

[0120] S74. The receiving node includes a local host system or a remote control platform. After receiving the data, it triggers a status recording, instruction execution, or control strategy update process based on the field content, thereby realizing closed-loop reporting and event response of low-voltage fault early warning data.

[0121] This invention, based on voltage anomaly scoring results of different levels, invokes corresponding alarm control commands to generate prompts, records, and local or remote alarm instructions, forming a tiered response mechanism. Simultaneously, it constructs a structured data packet containing a timestamp, voltage anomaly score, level label, and alarm command, and sends it to a designated receiving node via a chip-integrated communication interface module. Interface types include serial port, Ethernet, and CAN bus. The receiving node can be a local host system or a remote control platform, automatically executing alarm commands or updating control strategies based on the data content, achieving real-time reporting and rapid response linkage for low-voltage anomalies.

[0122] Example 1:

[0123] To verify the feasibility of this invention in practice, it was applied to a transformer monitoring terminal in a city's low-voltage power distribution system. By deploying an embedded chip with a sparse echo state neural network model, real-time monitoring and risk warning of voltage anomalies in low-voltage branches of a typical residential area were achieved. This scenario is representative, with a complex system load structure, significant peak-valley variations between morning and evening, and a susceptibility to voltage dips, severe fluctuations, and single-phase imbalances. Traditional monitoring methods often employ fixed-value alarm strategies, which suffer from delayed response and high false alarm rates when facing nonlinear fluctuations and transient interference, hindering proactive defense and rapid response.

[0124] In this deployment, an embedded chip platform with moderate computing resources was selected, featuring a processor clock speed of 150MHz, 512KB of on-chip SRAM, and support for basic neural network inference instruction sets. The sparse echo state neural network model of this invention was embedded and deployed on this chip. Periodic sampling of three types of operational data—voltage, current, and frequency—on the low-voltage input side was performed, with a sampling frequency of 20 times per second and a sliding window length of 25 sample points. The preprocessing module applied moving average filtering and normalization to the data, calculated the voltage fluctuation rate based on the first-order difference of the normalized voltage value, and dynamically set the pruning threshold of the current state vector accordingly. This completed the state filtering and sparse projection process, generating a voltage anomaly risk score in real time and outputting three alarm levels (Attention, Warning, and Severe Warning).

[0125] The field comparative test used data from seven consecutive days for verification, during which a total of eight minor fluctuations, five moderate fluctuations, and two severe voltage drops occurred. The traditional static threshold model (setting upper and lower voltage limits of 205V and 235V) did not respond to seven of the minor fluctuations and had a 2-second delay in responding to one voltage drop event. In contrast, the deployment model of this invention achieved real-time responses to all events, with an average response time of 265 milliseconds for minor fluctuations, 174 milliseconds for moderate fluctuations, and 112 milliseconds for severe drops, significantly outperforming the comparative model. Furthermore, the sparse structure means that each inference step requires only 32KB of memory, with an average inference time of 2.3 milliseconds, and chip resource usage remains within 22% of the rated capacity.

[0126] The test results verify the effectiveness and practicality of the present invention in low-voltage anomaly detection. In particular, it demonstrates stronger adaptability and fault identification accuracy in high-frequency sampling and complex fluctuation scenarios, showing good prospects for engineering deployment.

[0127] The following is a table of key data statistics during the implementation process:

[0128] Table 1. Statistical table of test results comparing the low-voltage fault early warning method of the present invention with the traditional model.

[0129]

[0130] As can be seen from the table above, the present invention has significant advantages over the traditional fixed threshold model in several key performance indicators of low-voltage power system fault early warning. First, in terms of anomaly identification accuracy, the method of the present invention achieves a 100% identification rate for minor fluctuations, moderate fluctuations, and severe voltage drops, while the traditional method has identification rates of 0%, 80%, and 50% for these three types of anomalies, respectively. This shows that the traditional method cannot capture risk signals in time at the initial stage of fluctuations, while the present invention, through dynamic state trimming and risk scoring mechanisms, can achieve full-coverage anomaly identification, especially demonstrating a sensitive early response capability in minor voltage fluctuation scenarios.

[0131] Secondly, regarding response speed, the average response time of this invention is 174 milliseconds, with the shortest response time of 112 milliseconds for severe voltage drops, significantly better than the processing latency of traditional methods, which generally exceeds 800 milliseconds in multiple events. This difference indicates that the sparse echo state neural network structure used in this invention, while ensuring model inference efficiency, has the ability to quickly respond to sudden fluctuations, making it suitable for low-voltage power grid scenarios with high timeliness requirements.

[0132] Furthermore, regarding chip resource adaptability, the neural network model of this invention has a total memory footprint of 112KB after deployment, with an average resource utilization rate controlled at 22% during operation. While traditional methods have slightly lower resource footprints, they lack dynamic model pruning and efficient sparse structures, resulting in no advantage in actual operating efficiency and responsiveness. Particularly in terms of inference computation time, although this invention is slightly longer than traditional methods, the overall processing latency is still far below the communication cycle limit, and the resulting improvement in recognition rate far outweighs the computational cost.

[0133] Finally, regarding false alarm control, this invention maintains a false alarm rate of 2.1% over 7 consecutive days of operation, a significant reduction compared to the 11.4% of traditional methods. This helps avoid false triggering of response measures and improves the reliability of the alarm system. Overall, this invention outperforms existing fixed threshold models in key indicators such as identification accuracy, response timeliness, resource adaptability, and false alarm control, demonstrating promising prospects for practical application and promotion.

[0134] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A low voltage fault early warning method based on chip algorithm, characterized in that, The method comprises the following steps: S1, collecting operation data in a low-voltage power system, continuously sampling the operation data through a chip to generate an original input vector sequence; S2, performing a preprocessing operation on the original input vector sequence to generate a preprocessed input data set and calculating a voltage fluctuation rate index based on a first-order differential value of voltage in the preprocessed input data set; S3, constructing a sparse connection echo state neural network model, including an input layer, a sparse reservoir pool structure, and a sparse output mapping layer, the connection weight of the sparse reservoir pool structure being generated and fixed according to the chip resource constraint before deployment; S4, inputting the preprocessed input data set into the echo state neural network model, updating the reservoir pool state vector, dynamically setting a state clipping parameter threshold value according to the voltage fluctuation rate index and performing a clipping operation to obtain a clipped state vector; S5, inputting the clipped state vector into the sparse output mapping layer, performing low-dimensional embedding linear projection to generate a voltage abnormal risk score; S6, comparing the voltage abnormal risk score with a set risk level threshold value to output an early warning level label; S7, generating an alarm control signal according to the early warning level label and sending the voltage abnormal risk score and the early warning level label to an upper system or a remote control platform through a communication interface.

2. The low-voltage fault early warning method based on chip algorithm according to claim 1, characterized in that, The original input vector sequence is composed of multi-dimensional operation data collected by a target node in a low-voltage power system in consecutive sampling periods; a sampling frequency is set as f s In a continuous time interval T = {t1, t2, …, t n In the continuous time interval T = {t1, t2, …, t}, the system collects operation data including voltage value, current value and frequency value at each sampling time; an input vector is constructed at each time step, and the vectors constructed at various sampling time points are arranged in time sequence to form a complete original input vector sequence.

3. The low-voltage fault early warning method based on chip algorithm according to claim 1, characterized in that, The S2 specifically comprises: S21, performing a sliding average filtering operation on each component in the original input vector sequence, at each time step t i , selecting the voltage values corresponding to the current and the previous k-1 sampling time points, calculating the arithmetic mean of the k voltage values as the filtered voltage value at time step t i ; S22, performing normalization processing on each component after filtering, and reconstituting the normalized vector into a preprocessed input data set; S23, based on the voltage component in the pre-processed input data set, calculate the voltage change value between two adjacent time steps, at each time step t i , subtract the normalized voltage value of the previous time step from the current normalized voltage value, and the resulting difference is the first-order difference value of time step t i . S24, on the basis of the continuous first-order difference values in the sliding window, calculate the voltage fluctuation rate index, at each time step t i , select the first-order difference values of the continuous k time steps before the time step t i , take the absolute values respectively and then average, the average value obtained is the voltage fluctuation rate index of the time step t i .

4. The low-voltage fault early warning method based on chip algorithm according to claim 1, characterized in that, The S3 specifically comprises: S31, defining the structure of the sparse connection echo state neural network model, including an input layer, a sparse reservoir pool structure, and a sparse output mapping layer, the input layer receiving the normalized input vector in the preprocessed input data set; S32, before deploying the sparse connection echo state neural network model, generating a connection matrix W of the sparse reservoir pool structure according to the chip computing resource constraint, the connection matrix W satisfying the sparsity constraint, and the connection matrix being fixed and stored in the chip after being generated; S33, constructing an input connection matrix W in the sparse connection echo state neural network model in mapping the normalized input vector to a neuron node in the sparse reservoir structure; S34. Constructing a sparse output mapping layer in the sparse connection echo state neural network model, setting the output mapping matrix as W out , the sparse output mapping layer only performs low-dimensional embedding linear projection on the reserved index subset in the state vector output by the sparse reservoir structure after pruning. S35, the connection matrix W in the sparsely connected echo state neural network model, the input connection matrix W in and the output mapping matrix W out cured into the chip internal storage structure.

5. The low voltage fault pre-warning method based on chip algorithm according to claim 4, characterized in that, The S32 specifically comprises: S321, setting the state dimension of the sparse reservoir pool structure as N, and determining a preset connection sparsity ρ of the chip computing resource constraint, the preset connection sparsity ρ being determined by the number of parallel computing channels of the chip and the on-chip storage capacity, satisfying that it should not be higher than the ratio of the maximum parallel computing channel number supported by the chip to the state dimension and should not be higher than the ratio of the available on-chip storage capacity of the chip to the square of the state dimension; S322. Randomly generate a sparse reservoir connection matrix W under sparsity constraints, and constrain the number of non-zero elements to ||W||0≤ρ·N. 2 ; S323, performing a spectral radius adjustment operation on the connection matrix W of the sparse reservoir pool structure, calculating the maximum eigenvalue modulus, and performing a normalization transformation; S324, fixing and storing the adjusted connection matrix W of the sparse reservoir pool structure in the chip to construct the sparse reservoir pool structure of the sparse connection echo state neural network model.

6. The low voltage fault pre-warning method based on chip algorithm according to claim 4, characterized in that, The S35 specifically comprises: S351. In the sparsely connected echo-state neural network model, the connection matrix W and the input connection matrix W in With output mapping matrix W out The encoding is a sparse format representation, in which each matrix is ​​compressed and stored using sparse index pairs consisting of non-zero element indices and corresponding weight values. S352, writing the encoded three groups of sparse matrices into the non-volatile memory area in the chip, and loading each matrix into the on-chip running cache through an address mapping table in the initialization stage; S353、in the echo state neural network model running stage, through the sparse matrix calling mechanism based on the instruction mapping table, the preset index structure is used to realize the sparse multiplication operation between the input vector, the state vector and the output mapping vector, and the echo state neural network model with sparse connection is ensured to complete the whole calculation process under the fixed structure; S354、the echo state neural network model parameters are not updated or replaced during the running process, and are strictly bound with the chip calculation resource budget.

7. The low voltage fault pre-warning method based on chip algorithm according to claim 1, characterized in that, The S4 specifically comprises: S41, at each time step t i the pre-processed input data set, a normalized input vector is input to a sparsely connected echo state neural network model; S42, update the reserve pool state vector x(t) by inputting the connection matrix W in and the connection matrix W of the sparse reserve pool structure i ) x(t i ) = f(W · x(t i-1 )+ W in · u norm (t i )); where x(t i ) is the state vector of the sparse reservoir structure generated at time step t i , t i represents the current sampling time, f(·) is the hyperbolic tangent function, W is the connection matrix of the sparse reservoir structure, x(t i-1 ) is the reservoir state vector at the previous time step t i-1 , W in is the input connection matrix, and u norm (t i ) is the normalized input vector obtained at time step t i . S43、According to the voltage fluctuation rate index of the current time step, calculate the state pruning parameter threshold θ(t) i ), multiply the voltage fluctuation rate index by the preset positive proportional coefficient γ, and the product obtained is used as the state pruning threshold of time step t i . S44, at the current time step t i For each component x i (t j ) in the state vector x(t i ), perform an activity determination. If |x j (t i )| < θ(t i ), then consider it as an inactive state and discard it. Keep all the state components that satisfy |x j (t i )| ≥ θ(t i ), and form the pruned state vector x'(t i ). Also, record the index subset of the pruned state vector x'(t i ).

8. The low voltage fault pre-warning method based on chip algorithm according to claim 1, characterized in that, The low-dimensional embedding linear projection extracts a subset of column vectors corresponding to the retained subset of indices from the output mapping matrix W out , resulting in a sparse output submatrix. The linear projection operation is performed on the pruned state vector x'(t i ) and the sparse output submatrix by multiplying each column element in the output submatrix with the state component at the corresponding position and summing the weighted totals to obtain a voltage anomaly risk score at time step t i .

9. The low voltage fault pre-warning method based on chip algorithm according to claim 1, characterized in that, The S6 specifically comprises: S61、set a risk level threshold set wherein τ1<τ2<τ3correspond to risk score boundaries of normal state, attention state and abnormal state respectively. S62、At time step t i , the voltage abnormality risk score y(t i ) is compared with a set of risk level thresholds , and a warning level label L(t i ) is generated according to rules. S63, if y(t i )≤τ1, then set L(t i )=0 to indicate normal, if τ1 i )≤τ2, then set L(t i )=1 to indicate attention, if τ2 i )≤τ3, then set L(t i )=2 to indicate early warning, if y(t i )>τ3, then set L(t i )=3 to indicate severe early warning S64, at time step t i , the state clipping parameter threshold θ(t i+1 ) is adjusted according to the voltage anomaly risk score at time step t i+1 , the state clipping threshold at the current time step is multiplied by a scaling factor determined by the risk score, the scaling factor being equal to one minus the product between the current risk score and a set positive adjustment factor.

10. The low voltage fault pre-warning method based on chip algorithm according to claim 1, characterized in that, The S7 specifically comprises: S71、at time step t i , according to the generated early warning level label L(t i ), a preset alarm response mapping rule is called to map the label value into a corresponding alarm control instruction S alarm (t i ), wherein when L(t i ) = 0, an empty operation instruction is generated, when L(t i ) = 1, a prompt recording instruction is generated, when L(t i ) = 2, a local alarm instruction is generated, and when L(t i ) = 3, a remote emergency alarm instruction is generated. S72, constructing alarm information communication data packet P(t i ), the data packet encapsulates content in a key-value pair structure, including a timestamp field, a voltage anomaly risk score field, a pre-warning level label field, and an alarm control instruction field; S73, sending the communication data packet P(t i ) to a designated data receiving node through a communication interface module integrated with the chip, the communication interface including a serial bus, an Ethernet interface, a CAN bus, or a wireless communication module; S74、the receiving node comprises a local upper system or a remote control platform, and after receiving, the field content triggers the state record, the instruction execution or the control strategy update process.

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