Embedded multimedia card host control system and method

Abstract

The invention discloses an embedded multimedia card host control system and method, and the system comprises a main caching module which is used for carrying out the caching processing of caching information, and the caching information comprises an operation command, to-be-sent data and received data; the command initialization module is used for generating a configuration command, and the configuration command is used for initializing the embedded multimedia card; the command sending and response receiving module is used for preprocessing the to-be-sent command to obtain a target command and sending the target command to the embedded multimedia card; the data receiving and transmitting module is used for carrying out data interaction on the embedded multimedia card, and the data interaction comprises data writing or data reading; and the clock management module is used for adjusting the clock frequency according to the running state of the embedded multimedia card. According to the invention, the host control of the embedded multimedia card is realized, and the efficiency and the transmission rate are improved. The method can be widely applied to the technical field of electronic information.

Description

Technical Field

[0001] The present invention relates to the field of electronic information technology, and in particular to an embedded multimedia card host control system and method. Background Art

[0002] eMMC (embedded MultiMediaCard) is an embedded storage solution widely used in mobile devices, embedded systems, and industrial control. In the aerospace industry, rapid data processing and storage are essential during aircraft operation. Traditionally, eMMC host controllers have been implemented in software. However, due to processor limitations, transmission rates are low, making it difficult to parallelize multiple tasks within the operating system and applications, resulting in low efficiency. Furthermore, data exchange consumes significant CPU resources, consuming significant task execution resources and consuming high power.

[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0004] The embodiment of the present invention provides an embedded multimedia card host control system and method, which effectively improves efficiency and transmission rate.

[0005] In one aspect, an embodiment of the present invention provides an embedded multimedia card host control system, comprising:

[0006] A main cache module, configured to cache cache information, including operation commands, data to be sent, and received data;

[0007] An initialization command module, used for generating a configuration command, wherein the configuration command is used for initializing the embedded multimedia card;

[0008] a command sending and response receiving module, configured to pre-process a command to be sent, obtain a target command, and send the target command to the embedded multimedia card, wherein the command to be sent includes the operation command or the configuration command;

[0009] A data transceiver module, configured to perform data interaction with the embedded multimedia card, wherein the data interaction includes data writing or data reading;

[0010] The clock management module is used to adjust the clock frequency according to the operating status of the embedded multimedia card.

[0011] In some embodiments, the primary cache module includes:

[0012] An operation command cache module, configured to receive and cache the operation command using an operation command cache queue;

[0013] A sending data buffer module is used to receive and buffer the data to be sent using a sending data buffer queue according to the operation command;

[0014] The receiving data caching module is used to receive and cache the received data using the receiving data caching queue according to the operation command.

[0015] In some embodiments, the data transceiver module includes:

[0016] a data sending module, configured to perform control information addition processing on the data to be sent, obtain target data, and send the target data to the embedded multimedia card;

[0017] The data receiving module is used to receive the response data sent by the embedded multimedia card, and perform splicing and verification processing on the response data to obtain the received data.

[0018] In some embodiments, the caching of the cache information includes:

[0019] If the embedded multimedia card host controller is in an idle state, determining whether the operation command buffer queue is empty;

[0020] If the operation command cache queue is not empty, extracting the operation command from the operation command cache queue;

[0021] If the operation command is an embedded multimedia card control command, performing standard format combination processing on the operation command and sending the command sending and response receiving module;

[0022] If the operation command is a data sending command, extracting the data to be sent from the sending data buffer queue and sending it to the data sending module;

[0023] If the operation command is a receive data command, the received data is extracted from the receive data cache queue and sent to the host computer.

[0024] In some embodiments, pre-processing the command to be sent to obtain the target command includes:

[0025] Packaging the command to be sent to obtain a first command;

[0026] Adding a check code to the first command to obtain a second command;

[0027] Perform parallel-to-serial conversion on the second command to obtain the target command.

[0028] The beneficial effects of the present invention are as follows:

[0029] An embodiment of the present invention provides an embedded multimedia card host control system comprising a main cache module, an initialization command module, a command sending and response receiving module, a data transceiver module, and a clock management module. The main cache module caches cache information; the initialization command module generates configuration commands to initialize the embedded multimedia card; the command sending and response receiving module pre-processes the commands to be sent to obtain target commands, which are then sent to the embedded multimedia card; the data transceiver module exchanges data with the embedded multimedia card; and the clock management module adjusts the clock frequency according to the operating status of the embedded multimedia card, thereby achieving embedded multimedia card host control and improving efficiency and transmission rate.

[0030] On the other hand, an embodiment of the present invention provides an embedded multimedia card host control method, comprising the following steps:

[0031] Initializing the embedded multimedia card through the initialization command module;

[0032] After the initialization is completed, obtaining a user instruction, wherein the user instruction includes a write operation instruction, a read operation instruction or an erase operation instruction;

[0033] If the user instruction is the write operation instruction, performing a write operation process on the embedded multimedia card to obtain a write operation result;

[0034] If the user instruction is the read operation instruction, performing a read operation on the embedded multimedia card to obtain the received data;

[0035] If the user instruction is the erase operation instruction, an erase operation process is performed on the embedded multimedia card to obtain an erase operation result.

[0036] In some embodiments, initializing the embedded multimedia card by using the initialization command module includes:

[0037] Sending a first command prompt to the embedded multimedia card to put the embedded multimedia card into an initial state;

[0038] In the initial state, sending a second command prompt to the embedded multimedia card to obtain device information;

[0039] Determining a current device state of the embedded multimedia card according to the device information;

[0040] If the current device state is an idle state, sending a third command prompt to the embedded multimedia card to switch the embedded multimedia card from the idle state to the recognition state;

[0041] sending a fourth command prompt to the embedded multimedia card to perform relative address allocation, so as to switch the embedded multimedia card from the identification state to the standby state;

[0042] In the prepared state, sending a fifth command prompt to the embedded multimedia card to obtain register information;

[0043] sending a sixth command prompt to the embedded multimedia card according to the register information, so as to switch the embedded multimedia card from the preparation state to the transmission state;

[0044] In the transmission state, a seventh command prompt is sent to the embedded multimedia card to modify the working mode.

[0045] In some embodiments, performing a write operation on the embedded multimedia card to obtain a write operation result includes:

[0046] sending an eighth command prompt to the embedded multimedia card through the command sending and response receiving module to determine the number of data blocks;

[0047] Sending a ninth command prompt to the embedded multimedia card to determine a starting address for writing a data block;

[0048] According to the number of data blocks and the starting address of the data block writing, the data to be sent is sent to the embedded multimedia card through the data sending module. The embedded multimedia card is used to verify and store the data to be sent to obtain the write operation result.

[0049] In some embodiments, performing a read operation on the embedded multimedia card to obtain the received data includes:

[0050] sending an eighth command prompt to the embedded multimedia card through the command sending and response receiving module to determine the number of data blocks;

[0051] sending a tenth command prompt to the embedded multimedia card to determine a starting address for reading a data block;

[0052] According to the number of data blocks and the starting address of the data block reading, the response data sent by the embedded multimedia card is received through the data receiving module, and the response data is spliced ​​and verified to obtain the received data.

[0053] In some embodiments, performing an erase operation on the embedded multimedia card to obtain an erase operation result includes:

[0054] Sending an eleventh command prompt to the embedded multimedia card through the command sending and response receiving module to determine a starting address for erasing a data block;

[0055] Sending a twelfth command prompt to the embedded multimedia card to determine an end address of data block erasure;

[0056] According to the starting address and the ending address of the data block erasure, a thirteenth command prompt is sent to the embedded multimedia card, and the embedded multimedia card is used to erase the data to be erased to obtain the erasure operation result.

[0057] The beneficial effects of the present invention are as follows:

[0058] The embodiment of the present invention first initializes the embedded multimedia card through an initialization command module, and then obtains a user instruction. If the user instruction is a write operation instruction, the write operation is performed on the embedded multimedia card to obtain a write operation result; if the user instruction is a read operation instruction, the read operation is performed on the embedded multimedia card to obtain received data; if the user instruction is an erase operation instruction, the erase operation is performed on the embedded multimedia card to obtain an erase operation result, so that the embedded multimedia card host can be controlled by different user instructions, thereby improving efficiency and transmission rate.

[0059] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained through the structures particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0061] Figure 1 This is a schematic structural diagram of an embedded multimedia card host control system according to an embodiment of the present invention;

[0062] Figure 2 This is a data transmission flow chart of an embodiment of the present invention;

[0063] Figure 3 This is a data receiving flow chart of an embodiment of the present invention;

[0064] Figure 4This is a flow chart of caching information according to an embodiment of the present invention;

[0065] Figure 5 This is a schematic diagram of the framework structure of an FPGA-based eMMC host control system according to an embodiment of the present invention;

[0066] Figure 6 This is a flow chart of a method for controlling an embedded multimedia card host according to an embodiment of the present invention;

[0067] Figure 7 This is an overall flow chart of an initialization configuration according to an embodiment of the present invention;

[0068] Figure 8 This is an overall flow chart of a write operation according to an embodiment of the present invention;

[0069] Figure 9 This is an overall flow chart of a read operation according to an embodiment of the present invention;

[0070] Figure 10 This is an overall flow chart of an erase operation according to an embodiment of the present invention. DETAILED DESCRIPTION

[0071] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are merely examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the appended claims.

[0072] It will be understood that the terms "first", "second", etc. used in this application may be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0073] The terms "at least one", "plurality", "each", "any", etc. used in this application include "at least one", "two" or more, "plurality" or "each", "any" or "any one", "each" or "any one" as used herein.

[0074] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0075] Before explaining the embodiments of the present application in detail, some of the nouns and terms involved in the embodiments of the present application are first explained. The nouns and terms involved in the embodiments of the present application are subject to the following explanations.

[0076] Embedded multi-media card (eMMC): is a NAND flash memory-based storage technology widely used in consumer electronics and embedded devices such as smartphones, tablets, digital cameras, and car entertainment systems.

[0077] First-in, first-out (FIFO): is a method of processing program work requests issued from a queue or stack, which allows the oldest request to be processed first.

[0078] Field Programmable Gate Array (FPGA): A new type of high-performance programmable logic device developed based on CPLDs. It generally utilizes an SRAM process, though some specialized devices utilize Flash or anti-fuse processes. FPGAs offer a high level of integration, with device densities ranging from tens of thousands to tens of millions of system gates. They can perform extremely complex sequential and combinational logic circuit functions, making them suitable for high-speed, high-density, high-end digital logic circuit design.

[0079] Cyclic redundancy check (CRC): A commonly used checksum with both error detection and correction capabilities, CRCs were widely used in early communications. They are often used to verify data between external storage devices and computers for synchronous communication.

[0080] CMD (command): refers to the command prompt, which is a working prompt in the operating system that prompts you to enter commands. Expressions such as CMD0, CMD1, CMD2, and CMD18 are standard protocol expressions and refer to the 0th, 1st, 2nd, and 18th commands, respectively.

[0081] In the related art, eMMC is an embedded storage solution widely used in mobile devices, embedded systems, and industrial control. A complete eMMC storage system consists of a host controller (equivalent to the eMMC host controller IP implemented by the FPGA in this application, where the FPGA is the host for the eMMC and the eMMC is the slave for the FPGA) and an eMMC device. The eMMC device contains a NAND flash chip and a flash controller. Compared to independent NAND flash memory, eMMC integrates NAND flash and a controller within the package, eliminating the need for the host to manage the underlying NAND characteristics, thereby simplifying storage management and improving system compatibility and reliability. The interaction between the FPGA host and the eMMC device is achieved through one clock (CLK) signal line, one command (CMD) signal line, and a data line (DATA, which can support 1, 4, or 8 data lines). The FPGA host and the eMMC device implement data transmission through a bus protocol. The host sends commands to the device interface, and the eMMC device returns a response and completes the host's data read and write transmission request. It should be noted that the CLK signal line can only realize one-way transmission from FPGA to eMMC device, while the CMD signal line and DATA signal line can realize bidirectional transmission between the two.

[0082] eMMC integrates the flash controller and NAND flash memory into a single package, simplifying design and integration and reducing space requirements. eMMC supports high-speed interfaces, meeting the requirements of aircraft for rapid data processing and storage. eMMC features a robust built-in error correction code (ECC) mechanism, effectively handling errors in data transmission and improving data storage reliability. The eMMC controller manages wear leveling, extending the lifespan of the flash memory and meeting the long-term stable operation requirements of space missions. eMMC uses standardized interfaces to ensure compatibility and interoperability with various embedded systems, reducing system integration complexity and shortening product development cycles. In the aerospace industry, eMMC is a storage medium that can adapt to the demands of a variety of demanding aerospace applications due to its high integration, superior performance, strong reliability, flexibility, and low power consumption. However, the design and research of eMMC host controllers in China is still limited. Therefore, a high-performance, user-friendly, and versatile eMMC host controller is of great significance.

[0083] Traditional software-implemented eMMC host controllers, due to processor performance limitations, are typically unable to achieve the same transfer rates as hardware-implemented ones, resulting in low transfer rates. Furthermore, due to the multitasking of the operating system and applications, software-implemented eMMC host controllers may not provide sufficient real-time performance, resulting in low efficiency. Furthermore, during data exchange, a large amount of CPU resources will be occupied, potentially affecting the execution efficiency of other tasks. Software power consumption management is inferior to hardware power consumption management, and software-implemented eMMC host controllers may increase the overall power consumption of the system, resulting in high power consumption.

[0084] In view of this, the embodiment of the present application provides an embedded multimedia card host control system. Based on the eMMC5.1 protocol standard, an FPGA eMMC host controller IP (intellectual property) core based on the Verilog language is designed. Compared with the eMMC host controller implemented by software, the eMMC host controller based on FPGA has the advantages of simple interface, convenient operation, high portability and good versatility. The FPGA has a dedicated clock pin that can output a stable high-speed clock for interaction with the eMMC; in addition, because the FPGA has the ability to process in parallel, the eMMC host controller based on FPGA can provide better real-time performance than the eMMC host controller implemented by software; and because the FPGA has the ability to process in parallel, the execution of other functional modules will not be affected during the interaction with the eMMC device, thereby improving the overall execution efficiency of the system; the FPGA can also improve power consumption performance through optimized design, reduce power consumption and improve efficiency. In addition, an embodiment of the present application also provides an embedded multimedia card host control method. The eMMC host controller implemented based on FPGA is easy to use. It only needs to write the starting address and number of data blocks to be read and written, or the starting address and end address of erase to the corresponding register to complete the control of the eMMC. The user does not need to understand the underlying physical protocol for interacting with the eMMC.

[0085] The following is a detailed explanation of the embodiments of the present application with reference to the accompanying drawings:

[0086] like Figure 1 As shown, an embodiment of the present invention provides an embedded multimedia card host control system, comprising:

[0087] The main cache module 101 is used to cache the cache information, including operation commands, data to be sent, and received data;

[0088] Initialization command module 102, used to generate configuration commands, the configuration commands are used to initialize the embedded multimedia card;

[0089] The command sending and response receiving module 103 is used to pre-process the command to be sent, obtain the target command, and send the target command to the embedded multimedia card. The command to be sent includes an operation command or a configuration command;

[0090] The data transceiver module 104 is used to perform data interaction with the embedded multimedia card, where the data interaction includes data writing or data reading;

[0091] The clock management module 105 is configured to adjust the clock frequency according to the operating status of the embedded multimedia card.

[0092] In some embodiments, an embedded multimedia card host control system provided by an embodiment of the present invention includes a main cache module 101, an initialization command module 102, a command sending and response receiving module 103, a data transceiver module 104, and a clock management module 105. The main cache module 101 can cache the cache information to temporarily store information that will not be processed in the future so that it can be retrieved for subsequent use, wherein the cache information includes operation commands, data to be sent, and received data. The initialization command module 102 can generate a configuration command, wherein the configuration command is used to initialize the embedded multimedia card. For example, the initialization command module will be executed first when the FPGA is powered on, and will generate a configuration command to initialize the eMMC. The host configuration may include operating mode configuration, rate mode configuration, data bit width configuration, and data single and double edge mode configuration, etc. These configuration commands can be used to send commands and receive responses through the command sending and response receiving module. After completing the initialization configuration of the eMMC device, the clock frequency output by the clock management module will switch from 400kHz to the actual required operating frequency. The eMMC host controller can then work normally, waiting for the upper-level module (such as the host computer) to initiate commands to send data, read data, or erase data.

[0093] The command to be sent can be pre-processed by the command sending and response receiving module 103 to obtain the target command, and the target command can be sent to the embedded multimedia card, wherein the command to be sent includes an operation command or a configuration command. For example, the eMMC host controller sends commands to the eMMC device and receives responses returned by the eMMC device through a 1-bit wide command signal line (CMD line). A legal command format includes a start bit, a transmission direction, a command index, a command message, a CRC check code, and an end bit. In the process of sending a command, the command sending and response receiving module first packages the pre-processed command data and adds a CRC check code, then converts the command to parallel and serial, and finally transmits it to the eMMC device in a serial manner. After receiving the command, the eMMC device processes it according to the command content. Whether the eMMC device returns a response and the length of the response are determined by the command issued by the eMMC host controller, and different commands have different responses. If the eMMC device returns a response, the response also includes a CRC check code. The host controller should also perform a CRC check when receiving the response to ensure that the data transmission is accurate.

[0094] Data interaction can be performed on the embedded multimedia card through the data transceiver module 104, wherein the data interaction includes data writing or data reading. The clock frequency can be adjusted through the clock management module 105 according to the operating status of the embedded multimedia card. For example, according to the eMMC protocol standard, the clock management module needs to provide a configuration clock of no more than 400kHz during the power-on initialization phase of the eMMC device to ensure the correct execution of the initialization command. During the process of the host controller initializing and configuring the eMMC device, the clock management module can output a 400kHz clock for device configuration. After initialization is completed, the clock management module switches to a higher frequency working clock (the specific clock needs to be confirmed according to actual needs) to increase the data transmission rate and meet the performance requirements in high-speed mode.

[0095] In some embodiments, the primary cache module includes:

[0096] An operation command cache module is used to receive and cache operation commands using an operation command cache queue;

[0097] The sending data buffer module is used to receive and buffer the data to be sent using the sending data buffer queue according to the operation command;

[0098] The receiving data cache module is used to receive and cache received data using the receiving data cache queue according to the operation command.

[0099] In some embodiments, the main cache module includes an operation command cache module, a sending data cache module, and a receiving data cache module. The operation command cache module can be used to receive and cache operation commands using an operation command cache queue. For example, when the eMMC host controller is executing a task, if a new operation command arrives, the operation command cannot be processed immediately because the current host controller is busy. To avoid the loss of operation commands, the operation command cache module will store the operation command in the operation command cache queue FIFO. When the current task is completed, these cached operation commands will be read out and processed in sequence to ensure that all operation commands can be executed in sequence and completely. Furthermore, the operation command pre-processed in a standard format can be sent to the command sending and response receiving module to execute subsequent operations of the task corresponding to the operation command.

[0100] Furthermore, the length of the standard format of the operation command is 48 bits (bits), and the categories of the standard format from high to low include 1-bit start bit, 1-bit transmission direction bit, 6-bit command index bit, 32-bit command message bit, 7-bit check bit and 1-bit end bit. Among them, the 7-bit check code used for the transmitted command is CRC7. It can be understood that CRC is a cyclic redundancy check code, and the "7" here represents the final cyclic redundancy check code of 7 bits. The CRC16 of the subsequent data transmission is expressed as a 16-bit cyclic redundancy check code. The advantages of the cyclic redundancy check code include the ability to detect odd-bit errors, double-bit errors, and all burst errors that are less than or equal to the check bit length. The CMD line and the DATA line are both high when idle, so the start bit is marked by a 1-bit low level; followed by a 1-bit transmission direction bit. When it is a 1-bit high level, it indicates that the current command transmission direction is sent by the host controller to the eMMC device, otherwise, it is returned by the eMMC to the host controller; the 6-bit command index bit is used to mark the command type; the 32-bit command message bit needs to be configured according to the standard protocol; the 7-bit check bit will check the 1-bit start bit, 1-bit transmission direction bit, 6-bit command index bit and 32-bit command message bit; finally, the 1-bit high-level stop bit marks the end of the command, and the transmitted information is 48 bits in total.

[0101] Based on the operation command, the transmit data cache module can use the transmit data cache queue to receive and cache the data to be transmitted. For example, when the eMMC host controller is executing a task and a new transmit data command arrives, the host controller is currently busy and cannot immediately process the transmit data command. To prevent the transmit data command and the data to be transmitted from being lost, the operation command cache module stores the transmit data command in the operation command cache queue FIFO. Similarly, the transmit data cache module stores the data to be transmitted in the transmit data cache queue FIFO. Upon completion of the current task, the cached data will be read out and processed sequentially, ensuring that no data is lost.

[0102] According to the operation command, the received data cache module can use the received data cache queue to receive and cache the received data. For example, the cache mechanism for received data is similar to the cache mechanism for sent data. When the receive data module of the eMMC host controller receives the response data sent by the eMMC device, it will store the response data in the receive data cache queue FIFO, waiting for the host computer to read it through the corresponding interface. This mechanism ensures that even if the host computer is temporarily unable to obtain the data in time, the received data can still be completely cached internally, avoiding data loss and ensuring the reliability and efficient management of data transmission.

[0103] In some embodiments, the data transceiver module includes:

[0104] A data sending module is used to add control information to the data to be sent, obtain target data, and send the target data to the embedded multimedia card;

[0105] The data receiving module is used to receive the response data sent by the embedded multimedia card, and perform splicing and verification processing on the response data to obtain received data.

[0106] In some embodiments, the data transceiver module includes a data sending module and a data receiving module. The data sending module can be used to add control information to the data to be sent, obtain target data, and send the target data to the embedded multimedia card. For example, the data sending process is as follows: Figure 2As shown, when the eMMC host controller successfully sends a data transmission command on the CMD line and receives a correct response from the eMMC device, the data sending module begins to read the data blocks to be transmitted (i.e., the data to be sent) from the send data buffer module of the host controller in sequence. According to the eMMC protocol requirements, each data block needs to add specific control information when transmitting: add a 1-bit start bit before the data block to mark the beginning of the data block; and append a 16-bit CRC16 check bit after the data to implement integrity verification of the start bit and data bit, thereby ensuring the correctness of data transmission; finally, add a 1-bit end bit to indicate the end of the current data block. In addition, eMMC supports three data bus bit widths: 1 bit, 4 bit, and 8 bit. The data transmission methods in different bit width modes are different. In single-edge transmission mode, in 1-bit bit-width mode, data is transmitted serially via a single data line (DATA[0]), with one bit transmitted per clock cycle. In 4-bit bit-width mode, data is transmitted in parallel via four data lines (DATA[3:0]), with 4 bits transmitted per clock cycle. The upper 4 bits of a byte are transmitted first, followed by the lower 4 bits. In 8-bit bit-width mode, data is transmitted in parallel via eight data lines (DATA[7:0]), with 8 bits transmitted per clock cycle. In dual-edge transmission mode, the number of data bits transmitted per clock cycle is doubled. The host controller's data transmission module automatically adjusts the data segmentation method based on the current operating mode of the eMMC device to ensure that data is transmitted at the correct bit width.

[0107] After the data block is preprocessed according to the standard format, the data transmission module will output the data to the eMMC device according to the timing specified by the eMMC protocol. After receiving the data, the eMMC device will perform a CRC check on the data it receives and return a CRC check status signal to the host controller. At the same time, the eMMC device will write the data in the cache to the FLASH and pull DATA[0] to a low level to indicate that the eMMC device is in a busy state. If the CRC check of the data received by the eMMC device passes, the data write operation is successful; if the check fails, the eMMC device will return an error status. The host controller will process the returned CRC check status signal. If the check fails, the data will be retransmitted to ensure that all data blocks are sent and improve the reliability of data transmission.

[0108] The data receiving module can receive the response data sent by the embedded multimedia card, and perform splicing and verification processing on the response data to obtain the received data. For example, the data receiving process is as follows: Figure 3As shown in the figure, when the eMMC host controller successfully sends a data read command on the CMD line and receives a correct response from the eMMC device, the eMMC device returns a specified number of data blocks on the data line. After the transmission is complete, the data receiving module enters the monitoring state and continuously monitors the DATA[0] data line to detect the data start bit and capture the incoming data stream. When the eMMC device begins to transmit data, it first sends a 1-bit start bit on the DATA[0] data line to indicate the start of data transmission. After detecting the start bit, the data receiving module enters the data receiving phase and collects and processes data according to the data bus width currently configured on the eMMC device. eMMC supports three data bus widths: 1 bit, 4 bits, and 8 bits. In single-edge mode, in 1-bit mode, the data receiving module serially reads data from the DATA[0] line, receiving 1 bit of data per clock cycle. In 4-bit mode, the data receiving module reads data from the four data lines DATA[3:0] in parallel, receiving 4 bits of data per clock cycle. In 8-bit mode, the data receiving module reads data from the eight data lines DATA[7:0] in parallel, receiving 8 bits of data per clock cycle. To optimize data storage and subsequent processing, the data receiving module reassembles the received n-bit data into 32-bit data units based on the hardware data bus width n (1-, 4-, or 8-line modes). This data splicing method fully utilizes the FPGA's data path, improves data access efficiency, and optimizes subsequent data transmission and storage operations. After splicing, the data receiving module sends the 32-bit data to the receive data buffer module for storage, awaiting subsequent retrieval by the data processing module or host computer.

[0109] During data block transmission, the eMMC device appends a 16-bit CRC checksum to the end of the data block to verify the integrity of the data transmission. After receiving the complete data block, the data receiving module extracts the CRC checksum and performs a CRC check on the received data to verify its accuracy. If the CRC check passes, the data block is deemed valid and stored in the cache. If the CRC check fails, the host controller deems the data block invalid and stores it in the cache, but reports it as invalid. The data reception process ends when all data blocks have been received. This process enables the eMMC host controller to efficiently and stably complete data reception and adapt to different data bus bit widths, ensuring reliable data storage and subsequent processing.

[0110] In some embodiments, cache processing is performed on the cache information, including:

[0111] If the embedded multimedia card host controller is in an idle state, determining whether the operation command buffer queue is empty;

[0112] If the operation command cache queue is not empty, extract the operation command from the operation command cache queue;

[0113] If the operation command is an embedded multimedia card control command, the operation command is combined and processed in a standard format and sent to the command sending and response receiving module;

[0114] If the operation command is a send data command, the data to be sent is extracted from the send data buffer queue and sent to the data sending module;

[0115] If the operation command is a receive data command, the received data is extracted from the receive data buffer queue and sent to the host computer.

[0116] In some embodiments, the process of caching cache information is as follows: Figure 4 As shown, it is possible to first determine whether the embedded multimedia card is in an idle state. If the embedded multimedia card host controller is in an idle state, it is then determined whether the operation command cache queue is empty. If the operation command cache queue is not empty, the operation command is extracted from the operation command cache queue and the type of the operation command is determined. If the operation command is an embedded multimedia card control command, the operation command is combined and processed in a standard format and sent to the command sending and response receiving module. If the operation command is a send data command, the data to be sent is extracted from the send data cache queue and sent to the data sending module. If the operation command is a receive data command, the received data is extracted from the receive data cache queue and sent to the host computer.

[0117] In some embodiments, preprocessing the command to be sent to obtain the target command includes:

[0118] Packaging the commands to be sent to obtain the first command;

[0119] Add a checksum to the first command to obtain a second command;

[0120] Perform parallel-to-serial conversion on the second command to obtain the target command.

[0121] In some embodiments, the command to be sent can be packaged to obtain a first command, and then a CRC check code can be added to the first command to obtain a second command. The second command can then be converted from parallel to serial to obtain a target command. Finally, the target command can be transmitted to the eMMC device in a serial manner.

[0122] In some embodiments, the framework structure of the FPGA-based eMMC host control system is as follows: Figure 5As shown, the clock management module is connected to the main cache module, the initialization command module, the command sending and response receiving module, the data transceiver module and the eMMC host to provide the clock frequency. The main cache module is connected to the command sending and response receiving module and the data transceiver module, and is used to receive operation commands and send them to the command sending and response receiving module, receive data to be sent and send it to the data sending module, receive response data from the data receiving module and process it into received data and send it to the host computer. The initialization command module is connected to the command sending and response receiving module to send the initialization command to the command sending and response receiving module. The command sending and response receiving module is connected to the eMMC host to send operation commands to the eMMC host via the CMD line. The data transceiver module exchanges data with the eMMC host via the DATA data line.

[0123] The beneficial effects of implementing the embodiments of the present invention include: the embodiments of the present invention provide an embedded multimedia card host control system comprising a main cache module, an initialization command module, a command sending and response receiving module, a data transceiver module, and a clock management module. The main cache module caches cache information; the initialization command module generates a configuration command to initialize the embedded multimedia card; the command sending and response receiving module pre-processes the command to be sent to obtain a target command, and then sends the target command to the embedded multimedia card; the data transceiver module exchanges data with the embedded multimedia card; and the clock management module adjusts the clock frequency according to the operating status of the embedded multimedia card, thereby achieving embedded multimedia card host control and improving efficiency and transmission rate.

[0124] The embodiment of the present application provides an embedded multimedia card host control method, which relates to the field of electronic information technology. The embodiment of the present application provides an embedded multimedia card host control method that can be applied to a terminal, a server, or software running in a terminal or a server. In some embodiments, the terminal can be a smart phone, a tablet computer, a laptop computer, a desktop computer, a smart speaker, a smart watch, and a car terminal, etc., but is not limited to this; the server side can be configured as an independent physical server, or as a server cluster or distributed system composed of multiple physical servers, or as a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms. The server can also be a node server in a blockchain network; the software can be an application that implements an embedded multimedia card host control method, etc., but is not limited to the above forms.

[0125] The present application can be used in many general or special computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, and the like. The present application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, and the like that perform specific tasks or implement specific abstract data types. The present application can also be practiced in distributed computing environments in which tasks are performed by remote processing devices connected via a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media, including storage devices.

[0126] Figure 6 This is an optional flowchart of an embedded multimedia card host control method provided by an embodiment of the present application. Figure 6 The method may include but is not limited to steps S201 to S205.

[0127] Step S201: Initialize the embedded multimedia card through the initialization command module;

[0128] Step S202: After initialization is completed, obtain user instructions, which include write operation instructions, read operation instructions, or erase operation instructions;

[0129] Step S203: If the user instruction is a write operation instruction, perform a write operation on the embedded multimedia card to obtain a write operation result;

[0130] Step S204: If the user instruction is a read operation instruction, perform a read operation on the embedded multimedia card to obtain received data;

[0131] Step S205: If the user instruction is an erase operation instruction, perform an erase operation on the embedded multimedia card to obtain an erase operation result.

[0132] Steps S201 to S205 shown in the embodiment of the present application implement the embedded multimedia card host control, thereby improving efficiency and transmission rate.

[0133] In some embodiments, in step S201, initializing the embedded multimedia card through the initialization command module may include but is not limited to the following steps:

[0134] sending a first command prompt to the embedded multimedia card to put the embedded multimedia card into an initial state;

[0135] In the initial state, a second command prompt is sent to the embedded multimedia card to obtain device information;

[0136] Determine the current device status of the embedded multimedia card according to the device information;

[0137] If the current device state is an idle state, sending a third command prompt to the embedded multimedia card to switch the embedded multimedia card from the idle state to the identification state;

[0138] sending a fourth command prompt to the embedded multimedia card to perform relative address allocation, so as to switch the embedded multimedia card from the identification state to the preparation state;

[0139] In the preparation state, a fifth command prompt is sent to the embedded multimedia card to obtain register information;

[0140] sending a sixth command prompt to the embedded multimedia card according to the register information, so as to switch the embedded multimedia card from a standby state to a transmission state;

[0141] In the transmission state, the seventh command prompt is sent to the embedded multimedia card to modify the working mode.

[0142] In some embodiments, if you want to perform write operations, read operations, and erase operations on the eMMC device, you need to wait until the eMMC host controller completes the initialization of the eMMC device before you can do so. The initialization command module will be executed first when the FPGA is powered on, and will generate configuration commands to initialize the eMMC. It should be noted that the host controller can only perform write operations, read operations, and erase operations after the initialization process is completed. If you need to modify the parameters of the initialization configuration, you only need to modify the file used by the eMMC host controller module to implement the macro definition. For example, to change from a 4-bit data line width mode to an 8-bit data line width mode, you only need to change the parameter to 8 in the macro definition file without modifying the underlying code logic. According to the relevant eMMC protocol requirements, when initializing and configuring the eMMC device, a working clock of no more than 400kHz must be used. Therefore, after all devices are powered on, the host controller will preferentially use a 400kHz working clock to interact with the eMMC device to achieve initialization configuration.

[0143] After power-on is completed, the eMMC device will be in the initial state, waiting for the host controller to initialize and configure it. In order to initialize and configure the eMMC device, the host controller can first send the first command prompt CMD0 to the embedded multimedia card to put the embedded multimedia card in the initial state. For example, the first command prompt CMD0 can carry the parameter 0x0000_0000 to make the eMMC device jump to the initial state. In the initial state, the second command prompt CMD1 is sent to the embedded multimedia card to obtain device information, and the current device status of the embedded multimedia card is determined based on the device information. For example, the second command prompt CMD1 is sent to query the relevant information of the eMMC device (such as operating voltage, capacity mode), the eMMC device will respond, and enter the READY state. The host controller will determine the busy bit of the response information returned by the eMMC device to determine whether the eMMC device is in a busy state. If it is in a busy state, the host controller will continue to send the second command prompt CMD1 to the eMMC device until the eMMC device is in an idle state. If the current device state is idle, the third command prompt CMD2 is sent to the embedded multimedia card to convert the embedded multimedia card from the idle state to the identification state. For example, the third command prompt CMD2 can be sent to make it enter the IDENTIFICATION state (i.e., the identification state). Then the fourth command prompt CMD3 is sent to the embedded multimedia card to perform relative address allocation to convert the embedded multimedia card from the identification state to the standby state. For example, the fourth command prompt CMD3 can be used to allocate a relative address to the eMMC device. After the relative address allocation is completed, the eMMC device will enter the STAND-BY state (i.e., the standby state).

[0144] In the preparation state, the fifth command prompt CMD9 is sent to the embedded multimedia card to obtain register information. For example, the CSD register (Device-SpecificData register device detailed data register) of the eMMC device can be obtained through the fifth command prompt CMD9 to confirm the configuration information of the eMMC device, such as storage capacity, maximum data transfer rate, read and write block size and other information. The basic information of the eMMC device can be obtained through this register. Then, according to the register information, the sixth command prompt CMD7 is sent to the embedded multimedia card to convert the embedded multimedia card from the preparation state to the transmission state. For example, the sixth command prompt CMD7 can be sent to make the eMMC device enter the TRANSFER state (i.e., transmission state). In the transmission state, the seventh command prompt CMD6 is sent to the embedded multimedia card to modify the working mode. For example, the working mode of the eMMC device can be modified by the seventh command prompt CMD6. The items that can be modified include bus mode (1, 4, 8 lines), access mode (default mode, high-speed mode, HS200, HS400), voltage level (1.8V, 3.3V), etc. After completing the above configuration, the host controller completes the initialization configuration process of the eMMC device.

[0145] The overall process of initialization configuration is as follows Figure 7 As shown in the figure, after power-on, the device waits for the initialization command, determines the validity and type of the command, sends the initialization command to the eMMC device, and waits for the response to be received if a response is required. After successfully receiving the response, if the initialization configuration is complete, the clock is switched by the clock management module to complete the initialization.

[0146] In some embodiments, in step S202 , after initialization is completed, a user instruction may be obtained, wherein the user instruction includes a write operation instruction, a read operation instruction, or an erase operation instruction, so that different operations can be performed subsequently according to different user instructions.

[0147] In some embodiments, in step S203, performing a write operation on the embedded multimedia card to obtain a write operation result may include but is not limited to the following steps:

[0148] sending an eighth command prompt to the embedded multimedia card through the command sending and response receiving module to determine the number of data blocks;

[0149] Sending a ninth command prompt to the embedded multimedia card to determine a start address for writing the data block;

[0150] According to the number of data blocks and the starting address of the data block writing, the data to be sent is sent to the embedded multimedia card through the data sending module. The embedded multimedia card is used to verify and store the data to be sent to obtain the write operation result.

[0151] In some embodiments, if the user instruction is a write operation instruction, the embedded multimedia card is processed for a write operation to obtain a write operation result. When performing high-performance data writing on the eMMC device, it is recommended to increase the number of data blocks written by a single command as much as possible (the default is that one data block corresponds to 512B of data). Because it can reduce the overhead of command interaction and reduce the time loss caused by protocol interaction, the larger the total amount of interactive data blocks, the higher the efficiency of a single interaction, and the data throughput can be improved. Therefore, executing a multiple block write (Multiple Block Write) command can optimize the write performance of the eMMC. The multiple block write operation is completed by a combination of CMD23 and CMD25. The eighth command prompt CMD23 can be sent to the embedded multimedia card through the command sending and response receiving module to determine the number of data blocks. For example, the eighth command prompt CMD23 can be sent to specify the number of data blocks to be transferred. Then the ninth command prompt CMD25 is sent to the embedded multimedia card to determine the starting address for the data block write. For example, the ninth command prompt CMD25 can be sent to notify the eMMC device of the starting address for the data block write. Then, based on the number of data blocks and the starting address of the data block write, the data to be sent is sent to the embedded multimedia card through the data sending module. The embedded multimedia card is used to verify and store the data to be sent and obtain the write operation result. For example, after the CMD23 and CMD25 command exchanges are completed, the data sending module sends the data stream to the eMMC device block by block according to the timing specified by the eMMC standard protocol. After each data block is transmitted, the eMMC device performs a CRC check on the received data and feedbacks the check result through the DATA line. The host controller can use this to determine whether the data block has been transmitted correctly. When all host controllers have completed sending the data blocks, the eMMC device enters the internal data storage phase and pulls the lowest bit DATA[0] of the DATA line low, indicating that the eMMC is currently busy. The host controller needs to continuously monitor the data line status and wait for the eMMC device to complete the storage. When DATA[0] is pulled high again to "1", it indicates that the eMMC data storage is complete and the current multi-block write operation has been successfully completed.

[0152] The overall process of the write operation is as follows Figure 8As shown, in response to a valid write command, a write operation command is sent to the eMMC device, and the eMMC device is waited for to respond. If the response times out, the reception fails and a fault is reported. If the response is successfully received, it is determined whether there is a subsequent command. If there is no subsequent command, data is sent to the eMMC device, and after the busy flag of the eMMC device is released, the write command operation is completed and the data writing is completed.

[0153] In some embodiments, in step S204, performing a read operation on the embedded multimedia card to obtain received data may include but is not limited to the following steps:

[0154] sending an eighth command prompt to the embedded multimedia card through the command sending and response receiving module to determine the number of data blocks;

[0155] sending a tenth command prompt to the embedded multimedia card to determine a starting address for reading a data block;

[0156] According to the number of data blocks and the starting address of the data block reading, the data receiving module receives the response data sent by the embedded multimedia card, and performs splicing and verification processing on the response data to obtain the received data.

[0157] In some embodiments, if the user instruction is a read operation, a read operation is performed on the embedded multimedia card to obtain received data. When performing an eMMC read operation, increasing the number of data blocks read in a single operation can effectively improve performance by reducing the frequency of command interactions, lowering protocol overhead, and increasing data throughput. Therefore, using a multi-block read command can optimize eMMC data reading efficiency. The multi-block read operation is performed by combining CMD23 and CMD18. The command sending and response receiving module can first send an eighth command prompt CMD23 to the embedded multimedia card to determine the number of data blocks. For example, the eighth command prompt CMD23 can be sent to specify the number of data blocks to be transferred. Then, a tenth command prompt CMD18 is sent to the embedded multimedia card to determine the starting address for data block reading. For example, the tenth command prompt CMD18 can be sent to notify the eMMC device of the starting address for data block reading. Based on the number of data blocks and the starting address for data block reading, the data receiving module receives response data from the embedded multimedia card and performs concatenation and verification on the response data to obtain received data. For example, the eMMC device returns the data stream (response data) from the DATA line to the host controller module according to the timing specified by the standard protocol. The eMMC device returns data in data blocks, each of which contains a start bit, valid data, a 16-bit CRC check code, and an end bit. During the process of receiving the response data, the data receiving module of the eMMC host controller continuously monitors the DATA line until the lowest bit is DATA[0]. When a valid start bit is detected, it starts receiving data. Since the eMMC device can support 1-bit, 4-bit, and 8-bit bus modes, the host controller needs to splice the n-bit data into 32-bit wide data according to the current data line bit width (n) for storage so that it can be accessed by the upper layer. At the same time, the receiving module will perform a separate CRC check on each data block and send it to the receiving data buffer module to obtain the received data. If a check error is detected, the exception information will be reported immediately to ensure the validity of the data. After transmitting the agreed number of data blocks, the eMMC device will automatically stop sending.

[0158] The overall process of the read operation is as follows Figure 9 As shown, in response to a valid read command, a read operation command is sent to the eMMC device, and the eMMC device waits for a response. If the response times out, the reception fails and a fault is reported. If the response is successfully received, it is determined whether there is a subsequent command. If there is no subsequent command, the response data sent by the eMMC device is received, a CRC check is performed, and the CRC check status is reported. The read command operation ends and the data reading is completed.

[0159] In some embodiments, in step S205, performing an erase operation on the embedded multimedia card to obtain an erase operation result may include but is not limited to the following steps:

[0160] Sending the eleventh command prompt to the embedded multimedia card through the command sending and response receiving module to determine the starting address of the data block erase;

[0161] sending a twelfth command prompt to the embedded multimedia card to determine an end address of data block erasure;

[0162] According to the starting address and the ending address of the data block erasure, the thirteenth command prompt is sent to the embedded multimedia card, and the embedded multimedia card is used to erase the data to be erased and obtain the erasure operation result.

[0163] In some embodiments, if the user instruction is an erase operation instruction, the embedded multimedia card is subjected to an erase operation to obtain an erase operation result. The eleventh command prompt CMD35 can be sent to the embedded multimedia card through the command sending and response receiving module to determine the starting address of the data block erase, and the twelfth command prompt CMD36 can be sent to the embedded multimedia card to determine the ending address of the data block erase. For example, the eleventh command prompt CMD35 can be sent to specify the starting address of the erase area, and the twelfth command prompt CMD36 can be sent to specify the ending address of the erase area. Then, based on the starting address of the data block erase and the ending address of the data block erase, the thirteenth command prompt CMD38 is sent to the embedded multimedia card, and the embedded multimedia card is used to erase the data to be erased to obtain an erase operation result. For example, the host controller sends the thirteenth command prompt CMD38 to notify the eMMC device to start erasing the specified data area. After receiving the CMD38 erase command, the eMMC device will perform the erase operation and pull down the lowest bit DATA[0] of the DATA line to indicate that the device is busy. At this point, the host controller must continuously monitor DATA[0] until it returns to "1" to confirm the completion of the erase operation. Because the eMMC device erase operation involves erasing and managing internal storage cells, the specific execution time depends on the amount of data being erased and the eMMC's internal algorithms. The host controller cannot issue new commands during this waiting period, as doing so may result in conflicts or undefined behavior. Therefore, subsequent read and write tasks can only be continued after the erase operation is complete.

[0164] The overall process of the erase operation is as follows Figure 10As shown, in response to a valid erase command, an erase operation command is sent to the eMMC device, and the eMMC device is waited for to respond. If the response times out, the reception fails and a fault is reported. If the response is successfully received, it is determined whether there is a subsequent command. If there is no subsequent command, the erase command operation ends after the busy flag of the eMMC device is released, and the data erasure is completed.

[0165] In some embodiments, this embodiment allows for configuration of data line width, rate mode, and single-edge and double-edge modes through macro definitions. This embodiment simplifies user operations. For write operations, only the data stream to be written, the write data starting address, and the number of write data blocks need to be provided. Data transmission will be automatically completed by the eMMC host controller module. For read operations, only the read data starting address and the number of read data blocks need to be provided. The eMMC host controller will read the corresponding data from the eMMC device and buffer it in the FPGA's FIFO, awaiting user access. For erase operations, only the erase data starting address and ending address need to be provided. The eMMC host controller will automatically send an erase command to the eMMC device to erase the corresponding area. Furthermore, this embodiment's FPGA-based eMMC host controller improves system efficiency due to the FPGA's inherent parallel processing capabilities. The FPGA has dedicated clock pins that provide a stable output clock and support high-speed data transmission, improving overall performance. Users only need to manipulate registers to operate the eMMC device, without having to understand the underlying protocol.

[0166] In some embodiments, among other alternatives, a software-driven eMMC controller runs on a general-purpose processor. By writing a software driver, the processor communicates with the eMMC device through a standard interface. This approach is common in embedded systems, mobile devices, and consumer electronics. However, due to processor limitations, data transfer rates and real-time performance are poor, CPU resources are consumed, and power consumption is high.

[0167] The beneficial effects of implementing the embodiments of the present invention include: the embodiments of the present invention first initialize the embedded multimedia card through the initialization command module, and then obtain a user instruction. If the user instruction is a write operation instruction, the write operation is performed on the embedded multimedia card to obtain a write operation result; if the user instruction is a read operation instruction, the read operation is performed on the embedded multimedia card to obtain received data; if the user instruction is an erase operation instruction, the erase operation is performed on the embedded multimedia card to obtain an erase operation result, so that the embedded multimedia card host can be controlled through different user instructions, thereby improving efficiency and transmission rate.

[0168] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but are not intended to limit the scope of the present invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and essence of the present invention should be within the scope of the present invention.

Claims

1. An embedded multimedia card host control system, characterized in that: include: A main cache module, configured to cache cache information, including operation commands, data to be sent, and received data; An initialization command module, used for generating a configuration command, wherein the configuration command is used for initializing the embedded multimedia card; a command sending and response receiving module, configured to pre-process a command to be sent, obtain a target command, and send the target command to the embedded multimedia card, wherein the command to be sent includes the operation command or the configuration command; A data transceiver module, configured to perform data interaction with the embedded multimedia card, wherein the data interaction includes data writing or data reading; The clock management module is used to adjust the clock frequency according to the operating status of the embedded multimedia card.

2. The system according to claim 1, wherein: The main cache module includes: An operation command cache module, configured to receive and cache the operation command using an operation command cache queue; A sending data buffer module is used to receive and buffer the data to be sent using a sending data buffer queue according to the operation command; The receiving data caching module is used to receive and cache the received data using the receiving data caching queue according to the operation command.

3. The system according to claim 2, characterized in that The data transceiver module includes: a data sending module, configured to perform control information addition processing on the data to be sent, obtain target data, and send the target data to the embedded multimedia card; The data receiving module is used to receive the response data sent by the embedded multimedia card, and perform splicing and verification processing on the response data to obtain the received data.

4. The system according to claim 3, characterized in that The caching process of the cache information includes: If the embedded multimedia card host controller is in an idle state, determining whether the operation command buffer queue is empty; If the operation command cache queue is not empty, extracting the operation command from the operation command cache queue; If the operation command is an embedded multimedia card control command, performing standard format combination processing on the operation command and sending the command sending and response receiving module; If the operation command is a data sending command, extracting the data to be sent from the sending data buffer queue and sending it to the data sending module; If the operation command is a receive data command, the received data is extracted from the receive data cache queue and sent to the host computer.

5. The system according to claim 1, wherein: The pre-processing of the command to be sent to obtain the target command includes: Packaging the command to be sent to obtain a first command; Adding a check code to the first command to obtain a second command; Perform parallel-to-serial conversion on the second command to obtain the target command.

6. A control method for an embedded multimedia card host control system according to any one of claims 1 to 5, characterized in that: The following steps are involved: Initializing the embedded multimedia card through the initialization command module; After the initialization is completed, obtaining a user instruction, wherein the user instruction includes a write operation instruction, a read operation instruction or an erase operation instruction; If the user instruction is the write operation instruction, performing a write operation process on the embedded multimedia card to obtain a write operation result; If the user instruction is the read operation instruction, performing a read operation on the embedded multimedia card to obtain the received data; If the user instruction is the erase operation instruction, an erase operation process is performed on the embedded multimedia card to obtain an erase operation result.

7. The method according to claim 6, characterized in that Initializing the embedded multimedia card by the initialization command module includes: Sending a first command prompt to the embedded multimedia card to put the embedded multimedia card into an initial state; In the initial state, sending a second command prompt to the embedded multimedia card to obtain device information; Determining a current device state of the embedded multimedia card according to the device information; If the current device state is an idle state, sending a third command prompt to the embedded multimedia card to switch the embedded multimedia card from the idle state to the recognition state; sending a fourth command prompt to the embedded multimedia card to perform relative address allocation, so as to switch the embedded multimedia card from the identification state to the standby state; In the prepared state, sending a fifth command prompt to the embedded multimedia card to obtain register information; sending a sixth command prompt to the embedded multimedia card according to the register information, so as to switch the embedded multimedia card from the preparation state to the transmission state; In the transmission state, a seventh command prompt is sent to the embedded multimedia card to modify the working mode.

8. The method according to claim 6, characterized in that The step of performing a write operation on the embedded multimedia card to obtain a write operation result includes: sending an eighth command prompt to the embedded multimedia card through the command sending and response receiving module to determine the number of data blocks; Sending a ninth command prompt to the embedded multimedia card to determine a starting address for writing a data block; According to the number of data blocks and the starting address of the data block writing, the data to be sent is sent to the embedded multimedia card through the data sending module. The embedded multimedia card is used to verify and store the data to be sent to obtain the write operation result.

9. The method according to claim 6, characterized in that The performing a read operation on the embedded multimedia card to obtain the received data includes: sending an eighth command prompt to the embedded multimedia card through the command sending and response receiving module to determine the number of data blocks; sending a tenth command prompt to the embedded multimedia card to determine a starting address for reading a data block; According to the number of data blocks and the starting address of the data block reading, the response data sent by the embedded multimedia card is received through the data receiving module, and the response data is spliced ​​and verified to obtain the received data.

10. The method according to claim 6, characterized in that The performing an erasing operation on the embedded multimedia card to obtain an erasing operation result includes: Sending an eleventh command prompt to the embedded multimedia card through the command sending and response receiving module to determine a starting address for erasing a data block; Sending a twelfth command prompt to the embedded multimedia card to determine an end address of data block erasure; According to the starting address and the ending address of the data block erasure, a thirteenth command prompt is sent to the embedded multimedia card, and the embedded multimedia card is used to erase the data to be erased to obtain the erasure operation result.

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